clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94275,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94276,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94277,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94278,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94279,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94280,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94281,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94282,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94283,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94284,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94285,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94286,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94287,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94288,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94289,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94290,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94291,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94292,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94293,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94294,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94295,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94296,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94297,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94298,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}},{"rowIdx":94299,"cells":{"content":{"kind":"string","value":"package body badger is\nend package body;\n\npackage body badger2 is\nend package body badger2;\n\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity accumulator is port (\n a: in std_logic_vector(3 downto 0);\n clk, reset: in std_logic;\n accum: out std_logic_vector(3 downto 0)\n );\nend accumulator;\n\narchitecture simple of accumulator is\n\nsignal accumL: unsigned(3 downto 0);\n\nbegin\n\n accumulate: process (clk, reset) begin\n if (reset = '1') then\n accumL <= \"0000\";\n elsif (clk'event and clk= '1') then\n accumL <= accumL + to_unsigned(a);\n end if;\n end process;\n\n accum <= std_logic_vector(accumL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity adder is port (\n a,b : in std_logic_vector (15 downto 0);\n sum: out std_logic_vector (15 downto 0)\n );\nend adder;\n\narchitecture dataflow of adder is\n\nbegin\n\n sum <= a + b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pAdderAttr is\n generic(n : integer := 8);\n port (a : in std_logic_vector(n - 1 downto 0);\n b : in std_logic_vector(n - 1 downto 0);\n cin : in std_logic;\n sum : out std_logic_vector(n - 1 downto 0);\n cout : out std_logic);\nend pAdderAttr;\n\n\narchitecture loopDemo of pAdderAttr is\n\nbegin\n\n process(a, b, cin)\n variable carry: std_logic_vector(sum'length downto 0);\n variable localSum: std_logic_vector(sum'high downto 0);\n\n begin\n\n carry(0) := cin;\n\n for i in sum'reverse_range loop\n localSum(i) := (a(i) xor b(i)) xor carry(i);\n carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));\n end loop;\n\n sum <= localSum;\n cout <= carry(carry'high - 1);\n\n end process;\n\nend loopDemo;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in unsigned(3 downto 0);\n sum: out unsigned(3 downto 0)\n );\nend adder;\n\narchitecture simple of adder is\n\nbegin\n\n sum <= a + b;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity asyncLoad is port (\n loadVal, d: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLoad;\n\narchitecture rtl of asyncLoad is\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n q <= loadVal;\n elsif (clk'event and clk = '1' ) then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity BidirBuf is port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: out std_logic_vector\n );\nend BidirBuf;\n\narchitecture behavioral of BidirBuf is\n\nbegin\n\n bidirBuf: process (OE, input) begin\n if (OE = '1') then\n output <= input;\n else\n output <= (others => 'Z');\n end if;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BidirCnt is port (\n OE: in std_logic;\n CntEnable: in std_logic;\n LdCnt: in std_logic;\n Clk: in std_logic;\n Rst: in std_logic;\n Cnt: inout std_logic_vector(3 downto 0)\n );\nend BidirCnt;\n\narchitecture behavioral of BidirCnt is\n\n component LoadCnt port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\n end component;\n\n component BidirBuf port (\n OE: in std_logic;\n input: in std_logic_vector;\n output: inout std_logic_vector\n );\n end component;\n\nsignal CntVal: std_logic_vector(3 downto 0);\nsignal LoadVal: std_logic_vector(3 downto 0);\n\nbegin\n\n u1: loadcnt port map (CntEn => CntEnable,\n LdCnt => LdCnt,\n LdData => LoadVal,\n Clk => Clk,\n Rst => Rst,\n CntVal => CntVal\n );\n\n u2: bidirbuf port map (OE => oe,\n input => CntVal,\n output => Cnt\n );\n\n LoadVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity bidirbuffer is port (\n input: in std_logic;\n enable: in std_logic;\n feedback: out std_logic;\n output: inout std_logic\n );\nend bidirbuffer;\n\narchitecture structural of bidirbuffer is\n\nbegin\n\n u1: bidir port map (ip => input,\n oe => enable,\n op_fb => feedback,\n op => output\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity clkGen is port (\n clk: in std_logic;\n reset: in std_logic;\n ClkDiv2, ClkDiv4,\n ClkDiv6,ClkDiv8: out std_logic\n );\nend clkGen;\n \narchitecture behav of clkGen is\n\nsubtype numClks is std_logic_vector(1 to 4);\nsubtype numPatterns is integer range 0 to 11;\n\ntype clkTableType is array (numpatterns'low to numPatterns'high) of numClks;\n\nconstant clkTable: clkTableType := clkTableType'(\n-- ClkDiv8______\n-- ClkDiv6_____ |\n-- ClkDiv4____ ||\n-- ClkDiv2 __ |||\n-- ||||\n \"1111\",\n \"0111\",\n \"1011\",\n \"0001\",\n \"1100\",\n \"0100\",\n \"1010\",\n \"0010\",\n \"1111\",\n \"0001\",\n \"1001\",\n \"0101\"); \n\nsignal index: numPatterns;\n \nbegin\n\n lookupTable: process (clk, reset) begin\n if reset = '1' then\n index <= 0;\n elsif (clk'event and clk = '1') then\n if index = numPatterns'high then\n index <= numPatterns'low;\n else\n index <= index + 1;\n end if;\n end if;\n end process;\n\n (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n enable: in std_logic;\n reset: in std_logic;\n count: buffer unsigned(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n count <= \"0000\";\n elsif(clk'event and clk = '1') then\n if enable = '1' then\n count <= count + 1;\n else\n count <= count;\n end if;\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.scaleable.all;\n\nentity count8 is port (\n clk: in std_logic;\n rst: in std_logic;\n count: out std_logic_vector(7 downto 0)\n );\nend count8;\n\narchitecture structural of count8 is\n\nbegin\n\n u1: scaleUpCnt port map (clk => clk,\n reset => rst,\n cnt => count\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 9)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 9);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(3,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(9 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(9 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= to_unsigned(0,10);\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n enable: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n elsif (enable = '1') then\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n load: in std_logic;\n data: in std_logic_vector(3 downto 0);\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n if (load = '1') then\n countL <= to_unsigned(data);\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity Cnt4Term is port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic\n );\nend Cnt4Term;\n\narchitecture behavioral of Cnt4Term is\n\nsignal CntL: unsigned(3 downto 0);\n\nbegin\n\n increment: process begin\n wait until clk = '1';\n CntL <= CntL + 1;\n end process;\n\n Cnt <= to_stdlogicvector(CntL);\n\n TermCnt <= '1' when CntL = \"1111\" else '0';\n\nend behavioral;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity Counter is port (\n clock: in std_logic;\n Count: out std_logic_vector(3 downto 0)\n );\nend Counter;\n\narchitecture structural of Counter is\n\n component Cnt4Term port (\n clk: in std_logic;\n Cnt: out std_logic_vector(3 downto 0);\n TermCnt: out std_logic);\n end component;\n\nbegin\n\n u1: Cnt4Term port map (clk => clock,\n Cnt => Count,\n TermCnt => open\n );\n\nend structural;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if(clk'event and clk = '1') then\n if (reset = '1') then\n countL <= \"0000\";\n else\n countL <= countL + 1;\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity convertArith is port (\n truncate: out unsigned(3 downto 0);\n extend: out unsigned(15 downto 0);\n direction: out unsigned(0 to 7)\n );\nend convertArith;\n\narchitecture simple of convertArith is\n\nconstant Const: unsigned(7 downto 0) := \"00111010\";\n\nbegin\n\n truncate <= resize(Const, truncate'length);\n extend <= resize(Const, extend'length);\n direction <= resize(Const, direction'length);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nconstant THREE: std_logic_vector(1 downto 0) := \"11\";\n\nbegin\n\n y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';\n\nend concurrent;\n-- incorporates Errata 12.1\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity typeConvert is port (\n a: out unsigned(7 downto 0)\n );\nend typeConvert;\n\narchitecture simple of typeConvert is\n\nconstant Const: natural := 43;\n\nbegin\n\n a <= To_unsigned(Const,8);\n\nend simple;\n-- Incorporates Errata 5.4 \n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk) begin\n if (clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n\n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(0 to 3)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(0 to 3);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"0000\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if reset = '1' then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + 1;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity counter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend counter;\n\narchitecture simple of counter is\n\nsignal countL: unsigned(3 downto 0);\n\nbegin\n\n increment: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1001\";\n elsif(clk'event and clk = '1') then\n countL <= countL + \"0001\";\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.decProcs.all;\n\nentity decoder is port (\n decIn: in std_logic_vector(1 downto 0);\n decOut: out std_logic_vector(3 downto 0)\n );\nend decoder;\n\narchitecture simple of decoder is\n\nbegin\n\n DEC2x4(decIn,decOut);\n\nend simple;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n decOut_n: out std_logic_vector(5 downto 0)\n\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n alias sio_dec_n: std_logic is decOut_n(5);\n alias rst_ctrl_rd_n: std_logic is decOut_n(4);\n alias atc_stat_rd_n: std_logic is decOut_n(3);\n alias mgmt_stat_rd_n: std_logic is decOut_n(2);\n alias io_int_stat_rd_n: std_logic is decOut_n(1);\n alias int_ctrl_rd_n: std_logic is decOut_n(0);\n\n alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);\n alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);\n\nbegin\n\n decoder: process (upper, CtrlBits)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case upper is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case CtrlBits is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n\t\t\t\t\t\n end case;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';\n\n int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IntCtrlReg) else '1';\n\n io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = IoIntStatReg) else '1';\n\n rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = RstCtrlReg) else '1';\n\n atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = AtcStatusReg) else '1';\n\n mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)\n and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';\n\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process (dev_adr, cs0_n)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n sio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n int_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n io_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n rst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n atc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n mgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n else\n null;\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n cs0_n: in std_logic;\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\n signal Lsio_dec_n: std_logic;\n signal Lrst_ctrl_rd_n: std_logic;\n signal Latc_stat_rd_n: std_logic;\n signal Lmgmt_stat_rd_n: std_logic;\n signal Lio_int_stat_rd_n: std_logic;\n signal Lint_ctrl_rd_n: std_logic;\n\nbegin\n\n decoder: process (dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n Lsio_dec_n <= '1';\n Lint_ctrl_rd_n <= '1';\n Lio_int_stat_rd_n <= '1';\n Lrst_ctrl_rd_n <= '1';\n Latc_stat_rd_n <= '1';\n Lmgmt_stat_rd_n <= '1';\n\n case dev_adr(19 downto 17) is \n\n when SuperIoRange =>\n Lsio_dec_n <= '0';\n\t\t\n when CtrlRegRange =>\n\n case dev_adr(16 downto 0) is\n\t\t\t\n when IntCtrlReg =>\n Lint_ctrl_rd_n <= '0';\n\n when IoIntStatReg =>\n Lio_int_stat_rd_n <= '0';\n\n when RstCtrlReg =>\n Lrst_ctrl_rd_n <= '0';\n\n when AtcStatusReg =>\n Latc_stat_rd_n <= '0';\n\n when MgmtStatusReg =>\n Lmgmt_stat_rd_n <= '0';\n\n when others =>\n null;\n\t\t\t\t\t\t\t\n end case;\n\n when others =>\n null; \n \n end case;\n\n end process decoder;\n\n qualify: process (cs0_n) begin\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if (cs0_n = '0') then\n sio_dec_n <= Lsio_dec_n;\n int_ctrl_rd_n <= Lint_ctrl_rd_n;\n io_int_stat_rd_n <= Lio_int_stat_rd_n;\n rst_ctrl_rd_n <= Lrst_ctrl_rd_n;\n atc_stat_rd_n <= Latc_stat_rd_n;\n mgmt_stat_rd_n <= Lmgmt_stat_rd_n;\n else\n null;\n end if;\n end process qualify;\n\nend synthesis;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n: out std_logic;\n int_ctrl_rd_n: out std_logic\n);\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n\n decoder: process ( dev_adr)\n begin \n -- Set defaults for outputs - for synthesis reasons.\n\n sio_dec_n <= '1';\n int_ctrl_rd_n <= '1';\n io_int_stat_rd_n <= '1';\n rst_ctrl_rd_n <= '1';\n atc_stat_rd_n <= '1';\n mgmt_stat_rd_n <= '1';\n\n if dev_adr(19 downto 17) = SuperIOrange then\n\n sio_dec_n <= '0';\n\n elsif dev_adr(19 downto 17) = CtrlRegrange then\n\n if dev_adr(16 downto 0) = IntCtrlReg then\n\n int_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0)= IoIntStatReg then\n\n io_int_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = RstCtrlReg then\n\n rst_ctrl_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = AtcStatusReg then\n\n atc_stat_rd_n <= '0';\n\n elsif dev_adr(16 downto 0) = MgmtStatusReg then\n\n mgmt_stat_rd_n <= '0';\n\n else\n\n null;\n\t\t\t\t\t\t\t\n end if;\n\n else\n\n null;\n\n end if;\n\n end process decoder;\n\nend synthesis;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n );\nend decProcs;\n\npackage body decProcs is\n\n procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);\n decode: out std_logic_vector(3 downto 0)\n ) is\n begin\n case inputs is\n when \"11\" =>\n decode := \"1000\";\n when \"10\" =>\n decode := \"0100\";\n when \"01\" =>\n decode := \"0010\";\n when \"00\" =>\n decode := \"0001\";\n when others =>\n decode := \"0001\";\n end case;\n end DEC2x4;\n\nend decProcs;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity isa_dec is port\n(\n dev_adr: in std_logic_vector(19 downto 0);\n\n sio_dec_n: out std_logic;\n rst_ctrl_rd_n: out std_logic;\n atc_stat_rd_n: out std_logic;\n mgmt_stat_rd_n: out std_logic;\n io_int_stat_rd_n:out std_logic;\n int_ctrl_rd_n: out std_logic\n );\nend isa_dec;\n\n\narchitecture synthesis of isa_dec is\n\n constant CtrlRegRange: std_logic_vector(2 downto 0) := \"100\";\n constant SuperIoRange: std_logic_vector(2 downto 0) := \"010\";\n\n constant IntCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000000\";\n constant IoIntStatReg: std_logic_vector(16 downto 0) := \"00000000000000001\";\n constant RstCtrlReg: std_logic_vector(16 downto 0) := \"00000000000000010\";\n constant AtcStatusReg: std_logic_vector(16 downto 0) := \"00000000000000011\";\n constant MgmtStatusReg:std_logic_vector(16 downto 0) := \"00000000000000100\";\n\nbegin\n with dev_adr(19 downto 17) select\n sio_dec_n <= '0' when SuperIORange,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,\n '1' when others;\n\n with dev_adr(19 downto 0) select\n mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,\n '1' when others;\n\n\nend synthesis;\n-- Incorporates Errata 5.1 and 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal delayCnt, pulseCnt: unsigned(7 downto 0);\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nbegin\n\n delayReg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)\n pulseCntVal <= unsigned(data);\n end if;\n end if;\n end process;\n\n pulseDelay: process (clk, reset) begin\n if (reset = '1') then\n delayCnt <= \"11111111\";\n elsif(clk'event and clk = '1') then\n if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)\n delayCnt <= delayCntVal;\n elsif endPulse = '1' then\n delayCnt <= delayCnt - 1;\n end if;\n end if;\n end process;\n\n startPulse <= '1' when delayCnt = \"00000000\" else '0';\n\n pulseLength: process (clk, reset) begin\n if (reset = '1') then\n pulseCnt <= \"11111111\";\n elsif (clk'event and clk = '1') then\n if (loadLength = '1') then\n pulseCnt <= pulseCntVal;\n elsif (startPulse = '1' and endPulse = '1') then\n pulseCnt <= pulseCntVal;\n elsif (endPulse = '1') then\n pulseCnt <= pulseCnt;\n else\n pulseCnt <= pulseCnt - 1;\n end if;\n end if;\n end process;\n\n endPulse <= '1' when pulseCnt = \"00000000\" else '0';\n\n pulseOutput: process (clk, reset) begin\n if (reset = '1') then\n pulse <= '0';\n elsif (clk'event and clk = '1') then\n if (startPulse = '1') then\n pulse <= '1';\n elsif (endPulse = '1') then\n pulse <= '0';\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q: out std_logic;\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, a,b,c) begin\n if ((a = '1' and b = '1') or c = '1') then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n a,b,c : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nsignal localRst: std_logic;\n\nbegin\n\n localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';\n\n process (clk, localRst) begin\n if localRst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n arst: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q <= '0';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n aset : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, aset) begin\n if aset = '1' then\n q <= '1';\n elsif clk'event and clk = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n arst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk, arst) begin\n if arst = '1' then\n q1 <= '0';\n q2 <= '1';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n wait on clk;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n envector: in std_logic_vector(7 downto 0);\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if envector = \"10010111\" then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if en = '1' then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (prst = '1') then\n q <= '1';\n elsif (rst = '1') then\n q <= '0';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity flipFlop is port (\n clock, input: in std_logic;\n ffOut: out std_logic\n );\nend flipFlop;\n\narchitecture simple of flipFlop is\n\n procedure dff (signal clk: in std_logic;\n signal d: in std_logic;\n signal q: out std_logic\n ) is\n begin\n if clk'event and clk = '1' then\n q <= d;\n end if;\n end procedure dff;\n\nbegin\n\n dff(clock, input, ffOut);\n\nend simple;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n end: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1, d2: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q1, q2: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq1 <= '0';\n\tq2 <= '1';\n else\n q1 <= d1;\n q2 <= d2;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe_sr is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n rst,prst: in std_logic;\n q: out std_logic\n );\nend struct_dffe_sr;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe_sr is\n\nbegin\n\n ff: dffe_sr port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n rst => rst,\n prst => prst,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n srst : in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n if clk'event and clk = '1' then\n if srst = '1' then\n\tq <= '0';\n else\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dffe is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dffe;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dffe is\n\nbegin\n\n ff: dffe port map (\n\td => d,\n\tclk => clk,\n\ten => en,\n\tq => q\n );\n\nend instance;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity dffTri is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend dffTri;\n\narchitecture parameterize of dffTri is\n\ntype tribufType is record\n ip: std_logic;\n oe: std_logic;\n op: std_logic;\nend record;\n\ntype tribufArrayType is array (integer range <>) of tribufType;\n\nsignal tri: tribufArrayType(size - 1 downto 0);\n\nbegin\n\n g0: for i in 0 to size - 1 generate\n u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);\n end generate;\n\n g1: for i in 0 to size - 1 generate\n u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);\n tri(i).oe <= op_enable;\n qout(i) <= tri(i).op;\n end generate;\n\nend parameterize;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic bus\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nsignal qLocal: std_logic;\n\nbegin\n\n qLocal <= d when en = '1' else qLocal;\n\n q <= qLocal;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en, d) begin\n if en = '1' then\n q <= d;\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity struct_dlatch is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend struct_dlatch;\n\nuse work.primitive.all;\n\narchitecture instance of struct_dlatch is\n\nbegin\n\n latch: dlatchh port map (\n\td => d,\n\ten => en,\n\tq => q\n );\n\nend instance;\n-- Incorporates Errata 5.4\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity downCounter is port (\n clk: in std_logic;\n reset: in std_logic;\n count: out std_logic_vector(3 downto 0)\n );\nend downCounter;\n\narchitecture simple of downCounter is\n\nsignal countL: unsigned(3 downto 0);\nsignal termCnt: std_logic;\n\nbegin\n\n decrement: process (clk, reset) begin\n if (reset = '1') then\n countL <= \"1011\"; -- Reset to 11\n termCnt <= '1';\n elsif(clk'event and clk = '1') then\n if (termCnt = '1') then\n countL <= \"1011\"; -- Count rolls over to 11\n else\n countL <= countL - 1;\n end if;\n\n if (countL = \"0001\") then -- Terminal count decoded 1 cycle earlier\n termCnt <= '1';\n else\n termCnt <= '0';\n end if;\n end if;\n end process;\n \n count <= std_logic_vector(countL);\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity compareDC is port (\n addressBus: in std_logic_vector(31 downto 0);\n addressHit: out std_logic\n );\nend compareDC;\n\narchitecture wontWork of compareDC is\n\nbegin\n\n compare: process(addressBus) begin\n if (addressBus = \"011110101011--------------------\") then\n addressHit <= '1';\n else\n addressHit <= '0';\n end if;\n end process compare;\n\nend wontWork;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n\n encode: process (invec) begin\n case invec is\n when \"00000001\" =>\n enc_out <= \"000\";\n\n when \"00000010\" =>\n enc_out <= \"001\";\n\n when \"00000100\" =>\n enc_out <= \"010\";\n\n when \"00001000\" =>\n enc_out <= \"011\";\n\n when \"00010000\" =>\n enc_out <= \"100\";\n\n when \"00100000\" =>\n enc_out <= \"101\";\n\n when \"01000000\" =>\n enc_out <= \"110\";\n\n when \"10000000\" =>\n enc_out <= \"111\";\n\n when others =>\n enc_out <= \"000\";\n\n end case;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity encoder is\n port (invec:in std_logic_vector(7 downto 0);\n enc_out:out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\nbegin\n process (invec)\n begin\n if invec(7) = '1' then\n enc_out <= \"111\";\n\n elsif invec(6) = '1' then\n enc_out <= \"110\";\n\n elsif invec(5) = '1' then\n enc_out <= \"101\";\n\n elsif invec(4) = '1' then\n enc_out <= \"100\";\n\n elsif invec(3) = '1' then\n enc_out <= \"011\";\n\n elsif invec(2) = '1' then\n enc_out <= \"010\";\n\n elsif invec(1) = '1' then\n enc_out <= \"001\";\n\n elsif invec(0) = '1' then\n enc_out <= \"000\";\n\n else \n enc_out <= \"000\";\n end if; \n end process;\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nentity encoder is\n port (invec: in std_logic_vector(7 downto 0);\n enc_out: out std_logic_vector(2 downto 0)\n );\nend encoder;\n\narchitecture rtl of encoder is\n\nbegin\n enc_out <= \"111\" when invec(7) = '1' else\n \"110\" when invec(6) = '1' else\n \"101\" when invec(5) = '1' else\n \"100\" when invec(4) = '1' else\n \"011\" when invec(3) = '1' else\n \"010\" when invec(2) = '1' else\n \"001\" when invec(1) = '1' else\n \"000\" when invec(0) = '1' else\n \"000\";\n\nend rtl;\n-- includes Errata 5.2\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all; -- errata 5.2\n\nentity compare is port (\n ina: in std_logic_vector (3 downto 0);\n inb: in std_logic_vector (2 downto 0);\n equal: out std_logic\n );\nend compare;\n\narchitecture simple of compare is\n\nbegin\n\n equalProc: process (ina, inb) begin\n if (ina = inb ) then\n equal <= '1';\n else\n equal <= '0';\n end if;\n end process;\n\nend simple;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture behavioral of LogicFcn is\n\nbegin\n\n fcn: process (A,B,C) begin\n\n if (A = '0' and B = '0') then\n Y <= '1';\n elsif C = '1' then\n Y <= '1';\n else\n Y <= '0';\n end if;\n\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture dataflow of LogicFcn is\n\nbegin\n\n Y <= '1' when (A = '0' AND B = '0') OR\n (C = '1')\n else '0';\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse work.primitive.all;\n\nentity LogicFcn is port (\n A: in std_logic;\n B: in std_logic;\n C: in std_logic;\n Y: out std_logic\n );\nend LogicFcn;\n\narchitecture structural of LogicFcn is\n\nsignal notA, notB, andSignal: std_logic;\n\nbegin\n\n i1: inverter port map (i => A,\n o => notA);\n\n i2: inverter port map (i => B,\n o => notB);\n\n a1: and2 port map (i1 => notA,\n i2 => notB,\n y => andSignal);\n\n o1: or2 port map (i1 => andSignal,\n i2 => C,\n y => Y);\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is port (\n D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nconstant tCQ: time := 8 ns;\nconstant tS: time := 4 ns;\nconstant tH: time := 3 ns;\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process (clk) begin\n wait until clk = '1';\n q <= d;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n q <= d;\n\n wait on clk;\n end process;\n\nend rtl;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for all: AND2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nconfiguration SimpleGatesCfg of FEWGATES is\n\n for structural\n\n for u1: and2\n use entity work.and2(rtl);\n end for;\n\n for u2: and2\n use entity work.and2(rtl);\n end for;\n\n for u3: inverter\n use entity work.inverter(rtl);\n end for;\n\n for u4: or2\n use entity work.or2(rtl);\n end for;\n\n end for;\n\nend SimpleGatesCfg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.and2;\nuse work.or2;\nuse work.inverter;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\n-- Configution specifications\n\nfor all: and2 use entity work.and2(rtl);\nfor u3: inverter use entity work.inverter(rtl);\nfor u4: or2 use entity work.or2(rtl);\n\nbegin\n\n u1: and2 port map (i1 => a, i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c, i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\nuse work.GatesPkg.all;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture concurrent of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n a_and_b <= '1' when a = '1' and b = '1' else '0';\n c_and_d <= '1' when c = '1' and d = '1' else '0';\n\n not_c_and_d <= not c_and_d;\n\n y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage GatesPkg is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nend GatesPkg;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 =>c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (a => c_and_d,\n y => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\n\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity FEWGATES is port (\n a,b,c,d: in std_logic;\n y: out std_logic\n );\nend FEWGATES;\n\narchitecture structural of FEWGATES is\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\nsignal a_and_b, c_and_d, not_c_and_d: std_logic;\n\nbegin\n\n u1: and2 port map (i1 => a ,\n i2 => b,\n y => a_and_b\n );\n\n u2: and2 port map (i1 => c,\n i2 => d,\n y => c_and_d\n );\n\n u3: inverter port map (i => c_and_d,\n o => not_c_and_d);\n\n u4: or2 port map (i1 => a_and_b,\n i2 => not_c_and_d,\n y => y\n );\nend structural;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.simPrimitives.all;\n\nentity simHierarchy is port (\n A, B, Clk: in std_logic;\n Y: out std_logic\n );\nend simHierarchy;\n\narchitecture hierarchical of simHierarchy is\n\nsignal ADly, BDly, OrGateDly, ClkDly: std_logic;\nsignal OrGate, FlopOut: std_logic;\n\nbegin\n\n ADly <= transport A after 2 ns;\n BDly <= transport B after 2 ns;\n OrGateDly <= transport OrGate after 1.5 ns;\n ClkDly <= transport Clk after 1 ns;\n\n u1: OR2 generic map (tPD => 10 ns)\n port map ( I1 => ADly,\n I2 => BDly,\n Y => OrGate\n );\n\n u2: simDFF generic map ( tS => 4 ns,\n tH => 3 ns,\n tCQ => 8 ns\n )\n port map ( D => OrGateDly,\n Clk => ClkDly,\n Q => FlopOut\n );\n\n Y <= transport FlopOut after 2 ns;\n\nend hierarchical;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n--------------------------------------------------------------------------------\n--| File name : $RCSfile: io1164.vhd $\n--| Library : SUPPORT\n--| Revision : $Revision: 1.1 $\n--| Author(s) : Vantage Analysis Systems, Inc; Des Young\n--| Integration : Des Young\n--| Creation : Nov 1995\n--| Status : $State: Exp $\n--|\n--| Purpose : IO routines for std_logic_1164.\n--| Assumptions : Numbers use radixed character set with no prefix.\n--| Limitations : Does not read VHDL pound-radixed numbers.\n--| Known Errors: none\n--|\n--| Description:\n--| This is a modified library. The source is basically that donated by\n--| Vantage to libutil. Des Young removed std_ulogic_vector support (to\n--| conform to synthesizable libraries), and added read_oct/hex to integer.\n--|\n--| =======================================================================\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights\n--| reserved. This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package VHDL source\n--| Package Name: somelib.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types\n--| in manner consistent with TEXTIO package.\n--| * Provides procedures to read and write logic values as\n--| binary, octal, or hexadecimal values ('X' as appropriate).\n--| These should be particularly useful for models\n--| to read in stimulus as 0/1/x or octal or hex.\n--| Subprograms :\n--| Notes : \n--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94\n--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95\n--| (This is because that type is not supported for synthesis).\n--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95\n--|\n--| =======================================================================\n--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.\n--| =======================================================================\n--|\n--------------------------------------------------------------------------------\n\nlibrary ieee;\npackage io1164 is\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- import std_logic package\n use ieee.std_logic_1164.all;\n\n -- import textio package\n use std.textio.all;\n\n --\n -- the READ and WRITE procedures act similarly to the procedures in the\n -- STD.TEXTIO package. for each type, there are two read procedures and\n -- one write procedure for converting between character and internal\n -- representations of values. each value is represented as the string of\n -- characters that you would use in VHDL code. (remember that apostrophes\n -- and quotation marks are not used.) input is case-insensitive. output\n -- is in upper case. see the following LRM sections for more information:\n --\n -- 2.3 - Subprogram Overloading\n -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)\n -- 7.3.6 - Allocators (allocators create access values)\n -- 14.3 - Package TEXTIO\n --\n\n -- Note that the procedures for std_ulogic will match calls with the value\n -- parameter of type std_logic.\n\n --\n -- declare READ procedures to overload like in TEXTIO\n --\n procedure read(l: inout line; value: out std_ulogic ; good: out boolean);\n procedure read(l: inout line; value: out std_ulogic );\n procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);\n procedure read(l: inout line; value: out std_logic_vector );\n\n --\n -- declare WRITE procedures to overload like in TEXTIO\n --\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 );\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 );\n\n --\n -- declare procedures to convert between logic values and octal\n -- or hexadecimal ('X' where appropriate).\n --\n\n -- octal / std_logic_vector\n procedure read_oct (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_oct (l : inout line ;\n value : out std_logic_vector );\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- hexadecimal / std_logic_vector\n procedure read_hex (l : inout line ;\n value : out std_logic_vector ;\n good : out boolean );\n procedure read_hex (l : inout line ;\n value : out std_logic_vector );\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified : in side := right;\n field : in width := 0 );\n\n -- read a number into an integer\n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_oct(l : inout line;\n value : out integer);\n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean);\n procedure read_hex(l : inout line;\n value : out integer);\n\nend io1164;\n\n--------------------------------------------------------------------------------\n--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved\n--| This package is provided by Vantage Analysis Systems.\n--| The package may not be sold without the express written consent of\n--| Vantage Analysis Systems, Inc.\n--|\n--| The VHDL for this package may be copied and/or distributed as long as\n--| this copyright notice is retained in the source and any modifications\n--| are clearly marked in the History: list.\n--|\n--| Title : IO1164 package body VHDL source\n--| Package Name: VANTAGE_LOGIC.IO1164\n--| File Name : io1164.vhdl\n--| Author(s) : dbb\n--| Purpose : source for IO1164 package body\n--| Subprograms :\n--| Notes : see package declaration\n--| History : see package declaration\n--------------------------------------------------------------------------------\n\npackage body io1164 is\n\n\n --$ !VANTAGE_METACOMMENTS_ON\n --$ !VANTAGE_DNA_ON\n\n -- define lowercase conversion of characters for canonical comparison\n type char2char_t is array (character'low to character'high) of character;\n constant lowcase: char2char_t := (\n nul, soh, stx, etx, eot, enq, ack, bel,\n bs, ht, lf, vt, ff, cr, so, si,\n dle, dc1, dc2, dc3, dc4, nak, syn, etb,\n can, em, sub, esc, fsp, gsp, rsp, usp, \n\n ' ', '!', '\"', '#', '$', '%', '&', ''',\n '(', ')', '*', '+', ',', '-', '.', '/',\n '0', '1', '2', '3', '4', '5', '6', '7',\n '8', '9', ':', ';', '<', '=', '>', '?',\n\n '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '[', '\\', ']', '^', '_',\n\n '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',\n 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',\n 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',\n 'x', 'y', 'z', '{', '|', '}', '~', del);\n\n -- define conversions between various types\n\n -- logic -> character\n type f_logic_to_character_t is \n array (std_ulogic'low to std_ulogic'high) of character;\n constant f_logic_to_character : f_logic_to_character_t := \n ( \n 'U' => 'U', \n 'X' => 'X',\n '0' => '0',\n '1' => '1',\n 'Z' => 'Z',\n 'W' => 'W',\n 'L' => 'L',\n 'H' => 'H',\n '-' => '-'\n );\n\n -- character, integer, logic\n\n constant x_charcode : integer := -1;\n constant maxoct_charcode: integer := 7;\n constant maxhex_charcode: integer := 15;\n constant bad_charcode : integer := integer'left;\n\n type digit2int_t is \n array ( character'low to character'high ) of integer;\n constant octdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n constant hexdigit2int: digit2int_t := (\n '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,\n '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, \n 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,\n 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,\n 'X' | 'x' => x_charcode, others => bad_charcode );\n\n constant oct_bits_per_digit: integer := 3;\n constant hex_bits_per_digit: integer := 4;\n\n type int2octdigit_t is \n array ( 0 to maxoct_charcode ) of character;\n constant int2octdigit: int2octdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7' );\n\n type int2hexdigit_t is \n array ( 0 to maxhex_charcode ) of character;\n constant int2hexdigit: int2hexdigit_t :=\n ( 0 => '0', 1 => '1', 2 => '2', 3 => '3',\n 4 => '4', 5 => '5', 6 => '6', 7 => '7',\n 8 => '8', 9 => '9', 10 => 'A', 11 => 'B',\n 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );\n\n type oct_logic_vector_t is\n array(1 to oct_bits_per_digit) of std_ulogic;\n type octint2logic_t is \n array (x_charcode to maxoct_charcode) of oct_logic_vector_t;\n constant octint2logic : octint2logic_t := (\n ( 'X', 'X', 'X' ),\n ( '0', '0', '0' ),\n ( '0', '0', '1' ),\n ( '0', '1', '0' ),\n ( '0', '1', '1' ),\n ( '1', '0', '0' ),\n ( '1', '0', '1' ),\n ( '1', '1', '0' ),\n ( '1', '1', '1' )\n );\n\n type hex_logic_vector_t is\n array(1 to hex_bits_per_digit) of std_ulogic;\n type hexint2logic_t is \n array (x_charcode to maxhex_charcode) of hex_logic_vector_t;\n constant hexint2logic : hexint2logic_t := (\n ( 'X', 'X', 'X', 'X' ),\n ( '0', '0', '0', '0' ),\n ( '0', '0', '0', '1' ),\n ( '0', '0', '1', '0' ),\n ( '0', '0', '1', '1' ),\n ( '0', '1', '0', '0' ),\n ( '0', '1', '0', '1' ),\n ( '0', '1', '1', '0' ),\n ( '0', '1', '1', '1' ),\n ( '1', '0', '0', '0' ),\n ( '1', '0', '0', '1' ),\n ( '1', '0', '1', '0' ),\n ( '1', '0', '1', '1' ),\n ( '1', '1', '0', '0' ),\n ( '1', '1', '0', '1' ),\n ( '1', '1', '1', '0' ),\n ( '1', '1', '1', '1' )\n );\n\n ----------------------------------------------------------------------------\n -- READ procedure bodies\n --\n -- The strategy for duplicating TEXTIO's overloading of procedures\n -- with and without GOOD parameters is to put all the logic in the\n -- version with the GOOD parameter and to have the version without\n -- GOOD approximate a runtime error by use of an assertion.\n --\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is\n\n variable c : character; -- char read while looping\n variable m : line; -- safe copy of L\n variable success: boolean := false; -- readable version of GOOD\n variable done : boolean := false; -- flag to say done reading chars\n\n begin\n\n --\n -- algorithm:\n -- \n -- if there are characters in the line\n -- save a copy of the line\n -- get the next character\n -- if got one\n -- set value\n -- if all ok\n -- free temp copy\n -- else\n -- free passed in line\n -- assign copy back to line\n -- set GOOD\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n \n -- grab the next character\n read( l, c, success );\n\n -- if read ok \n if success then\n\n--\n-- an issue here is whether lower-case values should be accepted or not\n--\n\n -- determine the value \n case c is\n when 'U' | 'u' => value := 'U';\n when 'X' | 'x' => value := 'X';\n when '0' => value := '0';\n when '1' => value := '1';\n when 'Z' | 'z' => value := 'Z';\n when 'W' | 'w' => value := 'W';\n when 'L' | 'l' => value := 'L';\n when 'H' | 'h' => value := 'H';\n when '-' => value := '-';\n when others => success := false;\n end case;\n\n end if;\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n end if; -- non null access, non empty string\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read( l: inout line; value: out std_ulogic ) is\n variable success: boolean; -- internal good flag\n begin\n read( l, value, success ); -- use safe version\n assert success \n report \"IO1164.READ: Unable to read STD_ULOGIC value.\" \n severity error;\n end read;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read(l : inout line ; \n value: out std_logic_vector;\n good : out boolean ) is\n\n variable m : line ; -- saved copy of L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- value for one array element\n variable c : character ; -- read a character\n\n begin\n\n --\n -- algorithm:\n -- \n -- this procedure strips off leading whitespace, and then calls the\n -- READ procedure for each single logic value element in the output\n -- array.\n -- \n\n -- only operate on lines that contain characters\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save a copy of string in case read fails\n m := new string'( l.all );\n\n -- loop for each element in output array\n for i in value'range loop\n\n -- prohibit internal blanks\n if i /= value'left then\n if l.all'length = 0 then\n success := false;\n exit;\n end if;\n c := l.all(l.all'left);\n if c = ' ' or c = ht then\n success := false;\n exit;\n end if;\n end if;\n\n -- read the next logic value\n read( l, logic_value, success );\n\n -- stuff the value in if ok, else bail out\n if success then\n value( i ) := logic_value;\n else\n exit;\n end if;\n\n end loop; -- each element in output array\n\n -- free working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n elsif ( value'length /= 0 ) then\n -- string is empty but the return array has 1+ elements\n success := false;\n end if;\n\n -- set output parameter\n good := success;\n\n end read;\n\n procedure read(l: inout line; value: out std_logic_vector ) is\n variable success: boolean;\n begin\n read( l, value, success );\n assert success \n report \"IO1164.READ: Unable to read T_WLOGIC_VECTOR value.\" \n severity error;\n end read;\n\n ----------------------------------------------------------------------------\n -- WRITE procedure bodies\n ----------------------------------------------------------------------------\n\n --\n -- std_ulogic\n -- note: compatible with std_logic\n --\n\n procedure write(l : inout line ;\n value : in std_ulogic ;\n justified: in side := right;\n field : in width := 0 ) is\n begin\n\n --\n -- algorithm:\n -- \n -- just write out the string associated with the enumerated\n -- value.\n -- \n\n case value is\n when 'U' => write( l, character'('U'), justified, field );\n when 'X' => write( l, character'('X'), justified, field );\n when '0' => write( l, character'('0'), justified, field );\n when '1' => write( l, character'('1'), justified, field );\n when 'Z' => write( l, character'('Z'), justified, field );\n when 'W' => write( l, character'('W'), justified, field );\n when 'L' => write( l, character'('L'), justified, field );\n when 'H' => write( l, character'('H'), justified, field );\n when '-' => write( l, character'('-'), justified, field );\n end case;\n end write;\n\n --\n -- std_logic_vector\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure write(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m: line; -- build up intermediate string\n\n begin\n\n --\n -- algorithm:\n -- \n -- for each value in array\n -- add string representing value to intermediate string\n -- write intermediate string to line parameter\n -- free intermediate string\n -- \n\n -- for each value in array\n for i in value'range loop\n\n -- add string representing value to intermediate string\n write( m, value( i ) );\n\n end loop;\n\n -- write intermediate string to line parameter\n write( l, m.all, justified, field );\n\n -- free intermediate string\n deallocate( m );\n\n end write;\n\n\n--------------------------------------------------------------------------------\n\n ----------------------------------------------------------------------------\n -- procedure bodies for octal and hexadecimal read and write\n ----------------------------------------------------------------------------\n\n --\n -- std_logic_vector/octal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem oct_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := octdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n oct_logic_vector := octint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := oct_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := octdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n oct_logic_vector := octint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_oct;\n\n\n procedure read_oct(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_oct;\n\n procedure write_oct(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / oct_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = oct_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2octdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_oct;\n\n --\n -- std_logic_vector/hexadecimal\n -- note: NOT compatible with std_ulogic_vector\n --\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector; \n good : out boolean ) is\n\n variable m : line ; -- safe L\n variable success : boolean := true; -- readable GOOD\n variable logic_value : std_logic ; -- elem value\n variable c : character ; -- char read\n variable charcode : integer ; -- char->int\n variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit\n variable bitpos : integer ; -- in state vec.\n begin\n\n --\n -- algorithm:\n -- \n -- skip over leading blanks, then read a digit\n -- and do a conversion into a logic value\n -- for each element in array\n -- \n\n -- make sure logic array is right size to read this base\n success := ( ( value'length rem hex_bits_per_digit ) = 0 );\n if success then\n\n -- only operate on non-empty strings\n if ( ( l /= null ) and ( l.all'length /= 0 ) ) then\n\n -- save old copy of string in case read fails\n m := new string'( l.all );\n\n -- pick off leading white space and get first significant char\n c := ' ';\n while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop\n read( l, c, success );\n end loop;\n\n -- turn character into integer\n charcode := hexdigit2int( c );\n\n -- not doing any bits yet\n bitpos := 0;\n\n -- check for bad first character\n if charcode = bad_charcode then\n success := false;\n else\n -- loop through each value in array\n hex_logic_vector := hexint2logic( charcode );\n for i in value'range loop\n \n -- doing the next bit\n bitpos := bitpos + 1;\n \n -- stick the value in\n value( i ) := hex_logic_vector( bitpos );\n \n -- read the next character if we're not at array end\n if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then\n read( l, c, success );\n if not success then\n exit;\n end if;\n -- turn character into integer\n charcode := hexdigit2int( c );\n -- check for bad char\n if charcode = bad_charcode then\n success := false;\n exit;\n end if;\n -- reset bit position\n bitpos := 0;\n -- turn character code into state array \n hex_logic_vector := hexint2logic( charcode );\n end if;\n \n end loop; -- each index in return array\n \n end if; -- if bad first character\n\n -- clean up working storage\n if success then\n deallocate( m );\n else\n deallocate( l );\n l := m;\n end if;\n\n -- no characters to read for return array that isn't null slice\n elsif ( value'length /= 0 ) then\n success := false;\n end if; -- non null access, non empty string\n\n end if;\n\n -- set out parameter of success\n good := success;\n\n end read_hex;\n\n\n procedure read_hex(l : inout line ; \n value : out std_logic_vector) is\n variable success: boolean; -- internal good flag\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value.\" \n severity error;\n end read_hex;\n\n procedure write_hex(l : inout line ;\n value : in std_logic_vector ;\n justified: in side := right;\n field : in width := 0 ) is\n\n variable m : line ; -- safe copy of L\n variable goodlength : boolean ; -- array is ok len for this base\n variable isx : boolean ; -- an X in this digit\n variable integer_value: integer ; -- accumulate integer value\n variable c : character; -- character read\n variable charpos : integer ; -- index string being contructed\n variable bitpos : integer ; -- bit index inside digit\n\n begin\n\n --\n -- algorithm:\n -- \n -- make sure this array can be written in this base\n -- create a string to place intermediate results\n -- initialize counters and flags to beginning of string\n -- for each item in array\n -- note unknown, else accumulate logic into integer\n -- if at this digit's last bit\n -- stuff digit just computed into intermediate result\n -- reset flags and counters except for charpos\n -- write intermediate result into line\n -- free work storage\n -- \n\n -- make sure this array can be written in this base\n goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );\n assert goodlength\n report \"IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4.\"\n severity error;\n if goodlength then\n\n -- create a string to place intermediate results\n m := new string(1 to ( value'length / hex_bits_per_digit ) );\n\n -- initialize counters and flags to beginning of string\n charpos := 0;\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n -- for each item in array\n for i in value'range loop\n\n -- note unknown, else accumulate logic into integer\n case value(i) is\n when '0' | 'L' =>\n integer_value := integer_value * 2;\n when '1' | 'H' =>\n integer_value := ( integer_value * 2 ) + 1;\n when others =>\n isx := true;\n end case;\n\n -- see if we've done this digit's last bit\n bitpos := bitpos + 1;\n if bitpos = hex_bits_per_digit then\n\n -- stuff the digit just computed into the intermediate result\n charpos := charpos + 1;\n if isx then\n m.all(charpos) := 'X';\n else\n m.all(charpos) := int2hexdigit( integer_value );\n end if;\n\n -- reset flags and counters except for location in string being constructed\n bitpos := 0;\n isx := false;\n integer_value := 0;\n\n end if;\n\n end loop;\n\n -- write intermediate result into line\n write( l, m.all, justified, field );\n\n -- free work storage\n deallocate( m );\n\n end if;\n\n end write_hex;\n\n------------------------------------------------------------------------------\n\n ------------------------------------\n -- Read octal/hex numbers to integer\n ------------------------------------\n\n --\n -- Read octal to integer\n --\n \n procedure read_oct(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := octdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := octdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 8) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_oct;\n\n -- simple version\n procedure read_oct(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_oct( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_OCT: Unable to read octal integer value.\" \n severity error;\n end read_oct;\n\n\n --\n -- Read hex to integer\n --\n \n procedure read_hex(l : inout line;\n value : out integer;\n good : out boolean) is\n\n variable pos : integer;\n variable digit : integer;\n variable result : integer := 0;\n variable success : boolean := true;\n variable c : character;\n variable old_l : line := l;\n\n begin\n -- algorithm:\n --\n -- skip leading white space, read digit, convert\n -- into integer\n --\n if (l /= NULL) then\n -- set pos to start of actual number by skipping white space\n pos := l'LEFT;\n c := l(pos);\n while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop\n pos := pos + 1;\n c := l(pos);\n end loop;\n \n -- check for start of valid number\n digit := hexdigit2int(l(pos));\n\n if ((digit = bad_charcode) or (digit = x_charcode)) then\n good := FALSE;\n return;\n else\n -- calculate integer value\n for i in pos to l'RIGHT loop\n digit := hexdigit2int(l(pos));\n exit when (digit = bad_charcode) or (digit = x_charcode);\n result := (result * 16) + digit;\n pos := pos + 1;\n end loop;\n value := result;\n -- shrink line\n if (pos > 1) then\n l := new string'(old_l(pos to old_l'HIGH));\n deallocate(old_l);\n end if;\n good := TRUE;\n return;\n end if;\n else\n good := FALSE;\n end if;\n\n end read_hex;\n\n -- simple version\n procedure read_hex(l : inout line;\n value : out integer) is\n\n variable success: boolean; -- internal good flag\n\n begin \n read_hex( l, value, success ); -- use safe version \n assert success \n report \"IO1164.READ_HEX: Unable to read hex integer value.\" \n severity error;\n end read_hex;\n\nend io1164;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity asyncLdCnt is port (\n loadVal: in std_logic_vector(3 downto 0);\n clk, load: in std_logic;\n q: out std_logic_vector(3 downto 0)\n );\nend asyncLdCnt;\n\narchitecture rtl of asyncLdCnt is\n\nsignal qLocal: unsigned(3 downto 0);\n\nbegin\n\n process (clk, load, loadVal) begin\n if (load = '1') then\n qLocal <= to_unsigned(loadVal);\n elsif (clk'event and clk = '1' ) then\n qLocal <= qLocal + 1;\n end if;\n end process;\n\n q <= to_stdlogicvector(qLocal);\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity LoadCnt is port (\n CntEn: in std_logic;\n LdCnt: in std_logic;\n LdData: in std_logic_vector(3 downto 0);\n Clk: in std_logic;\n Rst: in std_logic;\n CntVal: out std_logic_vector(3 downto 0)\n );\nend LoadCnt;\n\narchitecture behavioral of LoadCnt is\n\nsignal Cnt: std_logic_vector(3 downto 0);\n\nbegin\n\n counter: process (Clk, Rst) begin\n if Rst = '1' then\n Cnt <= (others => '0');\n elsif (Clk'event and Clk = '1') then\n if (LdCnt = '1') then\n Cnt <= LdData;\n elsif (CntEn = '1') then\n Cnt <= Cnt + 1;\n else\n Cnt <= Cnt;\n end if;\n end if;\n end process;\n\n CntVal <= Cnt;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nlibrary UTILS;\nuse UTILS.io1164.all;\nuse std.textio.all;\n\nentity loadCntTB is\nend loadCntTB;\n\narchitecture testbench of loadCntTB is\n\n component loadCnt port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\n end component;\n\nfile vectorFile: text is in \"vectorfile\";\ntype vectorType is record\n data: std_logic_vector(7 downto 0);\n load: std_logic;\n rst: std_logic;\n q: std_logic_vector(7 downto 0);\nend record;\n\nsignal testVector: vectorType;\nsignal TestClk: std_logic := '0';\nsignal Qout: std_logic_vector(7 downto 0);\n\nconstant ClkPeriod: time := 100 ns;\n\nfor all: loadCnt use entity work.loadcnt(rtl);\n\nbegin\n\n-- File reading and stimulus application\n readVec: process\n variable VectorLine: line;\n variable VectorValid: boolean;\n variable vRst: std_logic;\n variable vLoad: std_logic;\n variable vData: std_logic_vector(7 downto 0);\n variable vQ: std_logic_vector(7 downto 0);\n \n begin\n while not endfile (vectorFile) loop\n readline(vectorFile, VectorLine);\n\n read(VectorLine, vRst, good => VectorValid);\n next when not VectorValid;\n read(VectorLine, vLoad);\n read(VectorLine, vData);\n read(VectorLine, vQ);\n\n wait for ClkPeriod/4;\n\n testVector.Rst <= vRst;\n testVector.Load <= vLoad;\n testVector.Data <= vData;\n testVector.Q <= vQ;\n\n wait for (ClkPeriod/4) * 3;\n\n end loop;\n\n assert false\n report \"Simulation complete\"\n severity note;\n\n wait;\n\n end process;\n\n-- Free running test clock\n TestClk <= not TestClk after ClkPeriod/2;\n\n-- Instance of design being tested\n u1: loadCnt port map (Data => testVector.Data,\n load => testVector.Load,\n clk => TestClk,\n rst => testVector.Rst,\n q => Qout\n );\n\n-- Process to verify outputs\n verify: process (TestClk)\n variable ErrorMsg: line;\n begin\n if (TestClk'event and TestClk = '0') then\n if Qout /= testVector.Q then\n write(ErrorMsg, string'(\"Vector failed \"));\n write(ErrorMsg, now);\n writeline(output, ErrorMsg);\n end if;\n end if;\n end process;\n \n\nend testbench;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity loadCnt is port (\n data: in std_logic_vector (7 downto 0);\n load: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n q: out std_logic_vector (7 downto 0)\n );\nend loadCnt;\n\narchitecture rtl of loadCnt is\n\nsignal cnt: std_logic_vector (7 downto 0);\n\nbegin\n\n counter: process (clk, rst) begin\n if (rst = '1') then\n cnt <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (load = '1') then\n cnt <= data;\n else\n cnt <= cnt + 1;\n end if;\n end if;\n end process;\n\n q <= cnt;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity multiplier is port (\n a,b : in std_logic_vector (15 downto 0);\n product: out std_logic_vector (31 downto 0)\n );\nend multiplier;\n\narchitecture dataflow of multiplier is\n\nbegin\n\n product <= a * b;\n\nend dataflow;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity mux is port (\n A, B, Sel: in std_logic;\n Y: out std_logic\n );\nend mux;\n\narchitecture simModel of mux is\n\n-- Delay Constants\nconstant tPD_A: time := 10 ns;\nconstant tPD_B: time := 15 ns;\nconstant tPD_Sel: time := 5 ns;\n\nbegin\n\n DelayMux: process (A, B, Sel)\n\n variable localY: std_logic; -- Zero delay place holder for Y\n\n begin\n\n -- Zero delay model\n case Sel is\n when '0' =>\n localY := A;\n when others =>\n localY := B;\n end case;\n\n -- Delay calculation\n if (B'event) then\n Y <= localY after tPD_B;\n elsif (A'event) then\n Y <= localY after tPD_A;\n else\n Y <= localY after tPD_Sel;\n end if;\n\n end process;\n\n\nend simModel;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n begin\n\n if (a + b = \"10011010\") then\n result <= c;\n elsif (a + b = \"01011001\") then\n result <= d;\n elsif (a + b = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture concurrent of TRIBUF8 is\n\nbegin\n\n op <= ip when oe = '1' else (others => 'Z');\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture concurrent of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend concurrent;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF8 is port (\n ip: in std_logic_vector(7 downto 0);\n oe: in std_logic;\n op: out std_logic_vector(7 downto 0)\n );\nend TRIBUF8;\n\narchitecture sequential of TRIBUF8 is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= (others => 'Z');\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in bit;\n oe: in bit;\n op: out bit\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= null;\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture sequential of TRIBUF is\n\nbegin\n\n enable: process (ip,oe) begin\n if (oe = '1') then\n op <= ip;\n else\n op <= 'Z';\n end if;\n end process;\n\nend sequential;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity tribuffer is port (\n input: in std_logic;\n enable: in std_logic;\n output: out std_logic\n );\nend tribuffer;\n\narchitecture structural of tribuffer is\n\nbegin\n\n u1: tribuf port map (ip => input,\n oe => enable,\n op => output\n );\n\nend structural;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nbegin\n\n genXOR(0) <= '0';\n\n parTree: for i in 1 to ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity oddParityLoop is\n generic ( width : integer := 8 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityLoop ; \n\narchitecture scaleable of oddParityLoop is\nbegin\n\n process (ad) \n variable loopXor: std_logic;\n begin\n loopXor := '0';\n\n for i in 0 to width -1 loop\n loopXor := loopXor xor ad( i ) ;\n end loop ;\n\n oddParity <= loopXor ;\n\n end process;\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\n\nentity OR2 is port (\n I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after 10 ns;\n\nend simple;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity adder is port (\n a,b: in std_logic_vector(3 downto 0);\n sum: out std_logic_vector(3 downto 0);\n overflow: out std_logic\n );\nend adder;\n\narchitecture concat of adder is\n\nsignal localSum: std_logic_vector(4 downto 0);\n\nbegin\n\n localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));\n\n sum <= localSum(3 downto 0);\n overflow <= localSum(4);\n\nend concat;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity paramDFF is\n generic (size: integer := 8);\n port (\n data: in std_logic_vector(size - 1 downto 0);\n clock: in std_logic;\n reset: in std_logic;\n ff_enable: in std_logic;\n op_enable: in std_logic;\n qout: out std_logic_vector(size - 1 downto 0)\n );\nend paramDFF;\n\narchitecture parameterize of paramDFF is\n\nsignal reg: std_logic_vector(size - 1 downto 0);\n\nbegin\n\n u1: pDFFE generic map (n => size)\n port map (d => data,\n clk =>clock,\n rst => reset,\n en => ff_enable,\n q => reg\n );\n u2: pTRIBUF generic map (n => size)\n port map (ip => reg,\n oe => op_enable,\n op => qout\n );\n\nend paramterize;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 );\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal genXor: std_logic_vector(ad'range);\n\nsignal one: std_logic := '1';\n\nbegin\n\n parTree: for i in ad'range generate\n g0: if i = 0 generate\n x0: xor2 port map (i1 => one,\n i2 => one,\n y => genXor(0)\n );\n end generate;\n\n g1: if i > 0 and i <= ad'high generate\n x1: xor2 port map (i1 => genXor(i - 1),\n i2 => ad(i - 1),\n y => genXor(i)\n );\n end generate;\n\n end generate;\n\n oddParity <= genXor(ad'high) ;\n\nend scaleable ;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity oddParityGen is\n generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2\n port (ad: in std_logic_vector (width - 1 downto 0);\n oddParity : out std_logic ) ;\nend oddParityGen; \n\narchitecture scaleable of oddParityGen is\n\nsignal stage0: std_logic_vector(31 downto 0);\nsignal stage1: std_logic_vector(15 downto 0);\nsignal stage2: std_logic_vector(7 downto 0);\nsignal stage3: std_logic_vector(3 downto 0);\nsignal stage4: std_logic_vector(1 downto 0);\n\nbegin\n\n g4: for i in stage4'range generate\n g41: if (ad'length > 2) generate\n x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));\n end generate;\n end generate;\n\n g3: for i in stage3'range generate\n g31: if (ad'length > 4) generate\n x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));\n end generate;\n end generate;\n\n g2: for i in stage2'range generate\n g21: if (ad'length > 8) generate\n x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));\n end generate;\n end generate;\n\n g1: for i in stage1'range generate\n g11: if (ad'length > 16) generate\n x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));\n end generate;\n end generate;\n\n\n s1: for i in ad'range generate\n s14: if (ad'length = 2) generate\n stage4(i) <= ad(i);\n end generate;\n\n s13: if (ad'length = 4) generate\n stage3(i) <= ad(i);\n end generate;\n\n s12: if (ad'length = 8) generate\n stage2(i) <= ad(i);\n end generate;\n\n s11: if (ad'length = 16) generate\n stage1(i) <= ad(i);\n end generate;\n\n s10: if (ad'length = 32) generate\n stage0(i) <= ad(i);\n end generate;\n\n end generate;\n\n\n genPar: xor2 port map (stage4(0), stage4(1), oddParity);\n\nend scaleable ;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in unsigned(3 downto 0);\n power : out unsigned(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nsignal inputValInt: integer range 0 to 15;\nsignal powerL: integer range 0 to 65535;\n \nbegin\n\n inputValInt <= to_integer(inputVal);\n power <= to_unsigned(powerL,16);\n\n process begin\n wait until Clk = '1';\n\n powerL <= Pow(inputValInt,4);\n \n end process;\n\nend behavioral;\npackage PowerPkg is \n component Power port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\n end component;\nend PowerPkg;\n\nuse work.bv_math.all;\nuse work.int_math.all;\nuse work.PowerPkg.all;\n\nentity Power is port(\n Clk : in bit; \n inputVal : in bit_vector(0 to 3);\n power : out bit_vector(0 to 15) );\nend Power;\n\n\n\n\narchitecture funky of Power is\n \n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n Variable i : integer := 0;\n begin\n while( i < Exp ) loop\n Result := Result * N;\n i := i + 1;\n end loop;\n return( Result );\n end Pow;\n \n \n function RollVal( CntlVal : integer ) return integer is\n begin\n return( Pow( 2, CntlVal ) + 2 );\n end RollVal;\n \n \nbegin\n process \n begin\n wait until Clk = '1';\n \n power <= i2bv(Rollval(bv2I(inputVal)),16);\n \n end process;\nend funky;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity priority_encoder is port\n (interrupts : in std_logic_vector(7 downto 0);\n priority : in std_logic_vector(2 downto 0);\n result : out std_logic_vector(2 downto 0)\n );\nend priority_encoder;\n\narchitecture behave of priority_encoder is\nbegin\n\n process (interrupts)\n variable selectIn : integer;\n variable LoopCount : integer;\n begin\n\n LoopCount := 1;\n selectIn := to_integer(to_unsigned(priority));\n \n while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop\n\t\t\n if (selectIn = 0) then\n selectIn := 7;\n else\n selectIn := selectIn - 1;\n end if;\n\t\t\t\n LoopCount := LoopCount + 1;\n \n end loop;\n\t\t\n result <= std_logic_vector(to_unsigned(selectIn,3));\n\n end process;\n \nend behave;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage primitive is\n component DFFE port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\n end component;\n\n component DFFE_SR port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\n end component;\n\n component DLATCHH port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\n end component;\n\n component AND2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component OR2 port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\n end component;\n\n component INVERTER port (\n i: in std_logic;\n o: out std_logic\n );\n end component;\n\n component TRIBUF port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\n end component;\n\n component BIDIR port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\n end component;\n\nend package;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE is port (\n d: in std_logic;\n q: out std_logic;\n en: in std_logic;\n clk: in std_logic\n );\nend DFFE;\n\narchitecture rtl of DFFE is\n\nbegin\n\n process begin\n wait until clk = '1';\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFFE_SR is port (\n d: in std_logic;\n en: in std_logic;\n clk: in std_logic;\n rst: in std_logic;\n prst: in std_logic;\n q: out std_logic\n );\nend DFFE_SR;\n\narchitecture rtl of DFFE_SR is\n\nbegin\n\n process (clk, rst, prst) begin\n if (rst = '1') then\n q <= '0';\n elsif (prst = '1') then\n q <= '1';\n elsif (clk'event and clk = '1') then\n if (en = '1') then\n q <= d;\n end if;\n end if;\n end process;\n\nend rtl;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DLATCHH is port (\n d: in std_logic;\n en: in std_logic;\n q: out std_logic\n );\nend DLATCHH;\n\narchitecture rtl of DLATCHH is\n\nbegin\n\n process (en) begin\n if (en = '1') then\n q <= d;\n end if;\n end process;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity AND2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend AND2;\n\narchitecture rtl of AND2 is\n\nbegin\n\n y <= '1' when i1 = '1' and i2 = '1' else '0';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity OR2 is port (\n i1: in std_logic;\n i2: in std_logic;\n y: out std_logic\n );\nend OR2;\n\narchitecture rtl of OR2 is\n\nbegin\n\n y <= '1' when i1 = '1' or i2 = '1' else '0';\n\nend rtl;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity INVERTER is port (\n i: in std_logic;\n o: out std_logic\n );\nend INVERTER;\n\narchitecture rtl of INVERTER is\n\nbegin\n\n o <= not i;\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity TRIBUF is port (\n ip: in std_logic;\n oe: in std_logic;\n op: out std_logic\n );\nend TRIBUF;\n\narchitecture rtl of TRIBUF is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n\nend rtl;\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity BIDIR is port (\n ip: in std_logic;\n oe: in std_logic;\n op_fb: out std_logic;\n op: inout std_logic\n );\nend BIDIR;\n\narchitecture rtl of BIDIR is\n\nbegin\n\n op <= ip when oe = '1' else 'Z';\n op_fb <= op;\n\nend rtl;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\nsubtype fsmType is std_logic_vector(1 downto 0);\nconstant loadDelayCnt : fsmType := \"00\";\nconstant waitDelayEnd : fsmType := \"10\";\nconstant loadLengthCnt : fsmType := \"11\";\nconstant waitLengthEnd : fsmType := \"01\";\n\nsignal currState, nextState: fsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n\n -- Assign pulse output\n pulse <= currState(0);\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity pulseErr is port\n (a: in std_logic;\n b: out std_logic\n );\nend pulseErr;\n\narchitecture behavior of pulseErr is\n\nsignal c: std_logic;\n\nbegin\n\n pulse: process (a,c) begin\n b <= c XOR a;\n\n c <= a;\n end process;\n\nend behavior;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulse is port (\n clk, reset: in std_logic;\n loadLength,loadDelay: in std_logic;\n data: in std_logic_vector(7 downto 0);\n pulse: out std_logic\n );\nend progPulse;\n\narchitecture rtl of progPulse is\n\nsignal downCnt, downCntData: unsigned(7 downto 0);\nsignal downCntLd, downCntEn: std_logic;\nsignal delayCntVal, pulseCntVal: unsigned(7 downto 0);\nsignal startPulse, endPulse: std_logic;\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n delayreg: process (clk, reset) begin\n if reset = '1' then\n delayCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n delayCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n lengthReg: process (clk, reset) begin\n if reset = '1' then\n pulseCntVal <= \"11111111\";\n elsif clk'event and clk = '1' then\n if loadDelay = '1' then\n pulseCntVal <= to_unsigned(data);\n end if;\n end if;\n end process;\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCnt = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, pulseCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downCntData <= pulseCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downCntData <= pulseCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\n downCntr: process (clk,reset) begin\n if (reset = '1') then\n downCnt <= \"00000000\";\n elsif (clk'event and clk = '1') then\n if (downCntLd = '1') then\n downCnt <= downCntData;\n elsif (downCntEn = '1') then\n downCnt <= downCnt - 1;\n else\n downCnt <= downCnt;\n end if;\n end if;\n end process;\n \n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\ntype stateVec is array (3 downto 0) of std_logic;\ntype stateBits is array (progPulseFsmType) of stateVec;\n\nsignal loadVal: std_logic;\n\nconstant stateTable: stateBits := (\n loadDelayCnt => \"0010\",\n waitDelayEnd => \"0100\",\n loadLengthCnt => \"0011\",\n waitLengthEnd => \"1101\" );\n-- ^^^^\n-- ||||__ loadVal \n-- |||___ downCntLd\n-- ||____ downCntEn\n-- |_____ pulse\n\nsignal currState, nextState: progPulseFsmType;\n\nbegin\n\n nextStProc: process (currState, downCnt, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (to_unsigned(downCnt) = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n pulse <= stateTable(currState)(3);\n downCntEn <= stateTable(currState)(2);\n downCntLd <= stateTable(currState)(1);\n loadVal <= stateTable(currState)(0);\n \n downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;\n\nend fsm;\n-- Incorporates Errata 6.1\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity progPulseFsm is port (\n downCnt: in std_logic_vector(7 downto 0);\n delayCntVal: in std_logic_vector(7 downto 0);\n lengthCntVal: in std_logic_vector(7 downto 0);\n loadLength: in std_logic;\n loadDelay: in std_logic;\n clk: in std_logic;\n reset: in std_logic;\n\n downCntEn: out std_logic;\n downCntLd: out std_logic;\n downtCntData: out std_logic_vector(7 downto 0);\n\n pulse: out std_logic\n );\nend progPulseFsm;\n\narchitecture fsm of progPulseFsm is\n\ntype progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);\nsignal currState, nextState: progPulseFsmType;\nsignal downCntL: unsigned (7 downto 0);\n\nbegin\n\n downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned\n\n nextStProc: process (currState, downCntL, loadDelay, loadLength) begin\n case currState is\n when loadDelayCnt =>\n nextState <= waitDelayEnd;\n\n when waitDelayEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadLengthCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when loadLengthCnt =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n else\n nextState <= waitLengthEnd;\n end if;\n\n when waitLengthEnd =>\n if (loadDelay = '1' or loadLength = '1') then\n nextState <= loadDelayCnt;\n elsif (downCntL = 0) then\n nextState <= loadDelayCnt;\n else\n nextState <= waitDelayEnd;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nextStProc;\n\n currStProc: process (clk, reset) begin\n if (reset = '1') then\n currState <= loadDelayCnt;\n elsif (clk'event and clk = '1') then\n currState <= nextState;\n end if;\n end process currStProc;\n\n outConProc: process (currState, delayCntVal, lengthCntVal) begin\n case currState is\n when loadDelayCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when waitDelayEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n when loadLengthCnt =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when waitLengthEnd =>\n downCntEn <= '1';\n downCntLd <= '0';\n downtCntData <= lengthCntVal;\n pulse <= '1';\n\n when others =>\n downCntEn <= '0';\n downCntLd <= '1';\n downtCntData <= delayCntVal;\n pulse <= '0';\n\n end case;\n end process outConProc;\n\nend fsm;\n-- Incorporates errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nuse work.specialFunctions.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\n-- Incorporate errata 5.4\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity powerOfFour is port(\n clk : in std_logic; \n inputVal : in std_logic_vector(3 downto 0);\n power : out std_logic_vector(15 downto 0)\n );\nend powerOfFour;\n\narchitecture behavioral of powerOfFour is\n\n function Pow( N, Exp : integer ) return integer is\n Variable Result : integer := 1;\n\n begin\n for i in 1 to Exp loop\n Result := Result * N;\n end loop;\n return( Result );\n end Pow;\n\nbegin\n\n process begin\n wait until Clk = '1';\n\n power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);\n \n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity regFile is port (\n clk, rst: in std_logic;\n data: in std_logic_vector(31 downto 0);\n regSel: in std_logic_vector(1 downto 0);\n wrEnable: in std_logic;\n regOut: out std_logic_vector(31 downto 0)\n );\nend regFile;\n\narchitecture behavioral of regFile is\n\nsubtype reg is std_logic_vector(31 downto 0);\ntype regArray is array (integer range <>) of reg;\n\nsignal registerFile: regArray(0 to 3);\n\nbegin\n\n regProc: process (clk, rst) \n variable i: integer;\n\n begin\n i := 0;\n\n if rst = '1' then\n while i <= registerFile'high loop\n registerFile(i) <= (others => '0');\n i := i + 1;\n end loop;\n\n elsif clk'event and clk = '1' then\n if (wrEnable = '1') then\n case regSel is\n when \"00\" =>\n registerFile(0) <= data;\n when \"01\" =>\n registerFile(1) <= data;\n when \"10\" =>\n registerFile(2) <= data;\n when \"11\" =>\n registerFile(3) <= data;\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n outputs: process(regSel, registerFile) begin\n case regSel is\n when \"00\" =>\n regOut <= registerFile(0);\n when \"01\" =>\n regOut <= registerFile(1);\n when \"10\" =>\n regOut <= registerFile(2);\n when \"11\" =>\n regOut <= registerFile(3);\n when others =>\n null;\n end case;\n end process;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity DFF is port (\n d1,d2: in std_logic;\n q1,q2: out std_logic;\n clk: in std_logic;\n rst : in std_logic\n );\nend DFF;\n\narchitecture rtl of DFF is\n\nbegin\n\n resetLatch: process (clk, rst) begin\n if rst = '1' then\n q1 <= '0';\n elsif clk'event and clk = '1' then\n q1 <= d1;\n q2 <= d2;\n end if;\n end process;\n\nend rtl;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity resFcnDemo is port (\n a, b: in std_logic;\n oeA,oeB: in std_logic;\n result: out std_logic\n );\nend resFcnDemo;\n\narchitecture multiDriver of resFcnDemo is\n\nbegin\n\n result <= a when oeA = '1' else 'Z';\n result <= b when oeB = '1' else 'Z';\n\nend multiDriver;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleDFF is port (\n data: in std_logic_vector(7 downto 0);\n clock: in std_logic;\n enable: in std_logic;\n qout: out std_logic_vector(7 downto 0)\n );\nend scaleDFF;\n\narchitecture scalable of scaleDFF is\n\nbegin\n\n u1: sDFFE port map (d => data,\n clk =>clock,\n en => enable,\n q => qout\n );\n\nend scalable;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nsignal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;\nsignal oe: std_logic;\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n la_n <= '1'; lb_n <= '1';\n lc_n <= '1'; ld_n <= '1';\n le_n <= '1'; lf_n <= '1';\n lg_n <= '1';\n\n case bcdInputs is\n when \"0000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n\n when \"0001\" => lb_n <= '0'; lc_n <= '0';\n\n when \"0010\" => la_n <= '0'; lb_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lg_n <= '0';\n\n when \"0011\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lg_n <= '0';\n\n when \"0100\" => lb_n <= '0'; lc_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0101\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"0110\" => la_n <= '0'; lc_n <= '0';\n ld_n <= '0'; le_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n when \"0111\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0';\n\n when \"1000\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n le_n <= '0'; lf_n <= '0';\n lg_n <= '0';\n\n when \"1001\" => la_n <= '0'; lb_n <= '0';\n lc_n <= '0'; ld_n <= '0';\n lf_n <= '0'; lg_n <= '0';\n\n-- All other inputs possibilities are \"don't care\"\n\n when others => la_n <= 'X'; lb_n <= 'X';\n lc_n <= 'X'; ld_n <= 'X';\n le_n <= 'X'; lf_n <= 'X';\n lg_n <= 'X';\n\n end case;\n\n end process bcd2sevSeg;\n\n -- Disable outputs for all invalid input values\n\n oe <= '1' when (bcdInputs < 10) else '0';\n\n a_n <= la_n when oe = '1' else 'Z';\n b_n <= lb_n when oe = '1' else 'Z';\n c_n <= lc_n when oe = '1' else 'Z';\n d_n <= ld_n when oe = '1' else 'Z';\n e_n <= le_n when oe = '1' else 'Z';\n f_n <= lf_n when oe = '1' else 'Z';\n g_n <= lg_n when oe = '1' else 'Z';\n\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nuse std.textio.all;\n\nentity sevenSegmentTB is\nend sevenSegmentTB;\n\narchitecture testbench of sevenSegmentTB is\n\ncomponent sevenSegment port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend component;\n\ntype vector is record\n bcdStimulus: std_logic_vector(3 downto 0);\n sevSegOut: std_logic_vector(6 downto 0);\nend record;\n\nconstant NumVectors: integer:= 17;\nconstant PropDelay: time := 40 ns;\nconstant SimLoopDelay: time := 10 ns;\n\ntype vectorArray is array (0 to NumVectors - 1) of vector;\nconstant vectorTable: vectorArray := (\n (bcdStimulus => \"0000\", sevSegOut => \"0000001\"),\n (bcdStimulus => \"0001\", sevSegOut => \"1001111\"),\n (bcdStimulus => \"0010\", sevSegOut => \"0010010\"),\n (bcdStimulus => \"0011\", sevSegOut => \"0000110\"),\n (bcdStimulus => \"0100\", sevSegOut => \"1001100\"),\n (bcdStimulus => \"0101\", sevSegOut => \"0100100\"),\n (bcdStimulus => \"0110\", sevSegOut => \"0100000\"),\n (bcdStimulus => \"0111\", sevSegOut => \"0001111\"),\n (bcdStimulus => \"1000\", sevSegOut => \"0000000\"),\n (bcdStimulus => \"1001\", sevSegOut => \"0000100\"),\n (bcdStimulus => \"1010\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1011\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1100\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1101\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1110\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"1111\", sevSegOut => \"ZZZZZZZ\"),\n (bcdStimulus => \"0000\", sevSegOut => \"0110110\") -- this vector fails\n );\n\nfor all : sevenSegment use entity work.sevenSegment(behavioral);\n\nsignal StimInputs: std_logic_vector(3 downto 0);\nsignal CaptureOutputs: std_logic_vector(6 downto 0);\n\nbegin\n\n u1: sevenSegment port map (bcdInputs => StimInputs,\n a_n => CaptureOutputs(6),\n b_n => CaptureOutputs(5),\n c_n => CaptureOutputs(4),\n d_n => CaptureOutputs(3),\n e_n => CaptureOutputs(2),\n f_n => CaptureOutputs(1),\n g_n => CaptureOutputs(0));\n\n LoopStim: process\n variable FoundError: boolean := false;\n variable TempVector: vector;\n variable ErrorMsgLine: line;\n begin\n\n for i in vectorTable'range loop\n TempVector := vectorTable(i);\n\n StimInputs <= TempVector.bcdStimulus;\n\n wait for PropDelay;\n\n if CaptureOutputs /= TempVector.sevSegOut then\n write (ErrorMsgLine, string'(\"Vector failed at \"));\n write (ErrorMsgLine, now);\n writeline (output, ErrorMsgLine);\n FoundError := true;\n end if;\n\n wait for SimLoopDelay;\n\n end loop;\n\n assert FoundError\n report \"No errors. All vectors passed.\"\n severity note;\n\n wait;\n\n end process;\n\nend testbench;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity sevenSegment is port (\n bcdInputs: in std_logic_vector (3 downto 0);\n a_n, b_n, c_n, d_n,\n e_n, f_n, g_n: out std_logic\n );\nend sevenSegment;\n\narchitecture behavioral of sevenSegment is\n\nbegin\n\n bcd2sevSeg: process (bcdInputs) begin\n\n -- Assign default to \"off\"\n a_n <= '1'; b_n <= '1';\n c_n <= '1'; d_n <= '1';\n e_n <= '1'; f_n <= '1';\n g_n <= '1';\n\n case bcdInputs is\n when \"0000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n\n when \"0001\" =>\n b_n <= '0'; c_n <= '0';\n\n when \"0010\" =>\n a_n <= '0'; b_n <= '0';\n d_n <= '0'; e_n <= '0';\n g_n <= '0';\n\n when \"0011\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n g_n <= '0';\n\n when \"0100\" =>\n b_n <= '0'; c_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0101\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"0110\" =>\n a_n <= '0'; c_n <= '0';\n d_n <= '0'; e_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when \"0111\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0';\n\n when \"1000\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n e_n <= '0'; f_n <= '0';\n g_n <= '0';\n\n when \"1001\" =>\n a_n <= '0'; b_n <= '0';\n c_n <= '0'; d_n <= '0';\n f_n <= '0'; g_n <= '0';\n\n when others =>\n null;\n\n end case;\n\n end process bcd2sevSeg;\n\nend behavioral;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity ForceShare is port (\n a,b,c,d,e,f: in std_logic_vector (7 downto 0);\n result: out std_logic_vector(7 downto 0)\n );\nend ForceShare;\n\narchitecture behaviour of ForceShare is\n\nbegin\n\n sum: process (a,c,b,d,e,f)\n variable tempSum: std_logic_vector(7 downto 0);\n begin\n\n tempSum := a + b; -- temporary node for sum\n\n if (tempSum = \"10011010\") then\n result <= c;\n elsif (tempSum = \"01011001\") then\n result <= d;\n elsif (tempSum = \"10111011\") then\n result <= e;\n else\n result <= f;\n end if;\n end process;\n\nend behaviour;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity shifter is port (\n clk, rst: in std_logic;\n shiftEn,shiftIn: std_logic;\n q: out std_logic_vector (15 downto 0)\n );\nend shifter;\n\n\narchitecture behav of shifter is\n\nsignal qLocal: std_logic_vector(15 downto 0);\n\nbegin\n\n shift: process (clk, rst) begin\n if (rst = '1') then\n qLocal <= (others => '0');\n elsif (clk'event and clk = '1') then\n if (shiftEn = '1') then\n qLocal <= qLocal(14 downto 0) & shiftIn;\n else\n qLocal <= qLocal;\n end if;\n end if;\n\n q <= qLocal;\n end process;\n\nend behav;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity lastAssignment is port\n (a, b: in std_logic;\n selA, selb: in std_logic;\n result: out std_logic\n );\nend lastAssignment;\n\narchitecture behavioral of lastAssignment is\n\nbegin\n\n demo: process (a,b,selA,selB) begin\n if (selA = '1') then\n result <= a;\n else\n result <= '0';\n end if;\n\n if (selB = '1') then\n result <= b;\n else\n result <= '0';\n end if;\n end process demo;\n\nend behavioral;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '0' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity signalDemo is port (\n a: in std_logic;\n b: out std_logic\n );\nend signalDemo;\n\narchitecture basic of signalDemo is\n\nsignal c: std_logic;\n\nbegin\n\n demo: process (a) begin\n\n c <= a;\n\n if c = '1' then\n b <= a;\n else\n b <= '0';\n end if;\n\n end process;\n\nend basic;\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\npackage simPrimitives is\n\n component OR2\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\n end component;\n\n component SimDFF\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\n end component;\n\n\nend simPrimitives;\n\n\nlibrary IEEE;\nUSE IEEE.std_logic_1164.all;\n\nentity OR2 is\n generic (tPD: time := 1 ns);\n\n port (I1, I2: in std_logic;\n Y: out std_logic\n );\nend OR2;\n\narchitecture simple of OR2 is\n\nbegin\n\n Y <= I1 OR I2 after tPD;\n\nend simple;\n\n\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SimDFF is\n generic(tCQ: time := 1 ns;\n tS : time := 1 ns;\n tH : time := 1 ns\n );\n port (D, Clk: in std_logic;\n Q: out std_logic\n );\nend SimDff;\n\narchitecture SimModel of SimDFF is\n\nbegin\n\n reg: process (Clk, D) begin\n\n -- Assign output tCQ after rising clock edge\n if (Clk'event and Clk = '1') then\n Q <= D after tCQ;\n end if;\n\n -- Check setup time\n if (Clk'event and Clk = '1') then\n assert (D'last_event >= tS)\n report \"Setup time violation\"\n severity Warning;\n end if;\n\n -- Check hold time\n if (D'event and Clk'stable and Clk = '1') then\n assert (D'last_event - Clk'last_event > tH)\n report \"Hold Time Violation\"\n severity Warning;\n end if;\n\n end process;\n\nend simModel;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until rising_edge(clk);\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity SRFF is port (\n s,r: in std_logic;\n clk: in std_logic;\n q: out std_logic\n );\nend SRFF;\n\narchitecture rtl of SRFF is\n\nbegin\n\n process begin\n wait until clk = '1';\n if s = '0' and r = '1' then\n\tq <= '0';\n elsif s = '1' and r = '0' then\n\tq <= '1';\n end if;\n end process;\n\nend rtl;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\npackage scaleable is\n component scaleUpCnt port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: in std_logic_vector\n );\n end component;\nend scaleable;\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nuse work.primitive.all;\n\nentity scaleUpCnt is port (\n clk: in std_logic;\n reset: in std_logic;\n cnt: out std_logic_vector\n );\nend scaleUpCnt;\n\narchitecture scaleable of scaleUpCnt is\n\nsignal one: std_logic := '1';\nsignal cntL: std_logic_vector(cnt'range);\nsignal andTerm: std_logic_vector(cnt'range);\n\nbegin\n\n-- Special case is the least significant bit\n\n lsb: tff port map (t => one,\n reset => reset,\n clk => clk,\n q => cntL(cntL'low)\n );\n\n andTerm(0) <= cntL(cntL'low);\n\n\n-- General case for all other bits\n\n genAnd: for i in 1 to cntL'high generate\n andTerm(i) <= andTerm(i - 1) and cntL(i);\n end generate;\n\n genTFF: for i in 1 to cntL'high generate\n t1: tff port map (t => andTerm(i),\n clk => clk,\n reset => reset,\n q => cntl(i)\n );\n end generate;\n\n cnt <= CntL;\n\nend scaleable;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \t\ttargetFsmType := \"010\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(3 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"0000\";\nconstant B_Busy: \ttargetFsmType := \"0001\";\nconstant Backoff: \ttargetFsmType := \"0011\";\nconstant S_Data: \ttargetFsmType := \"1100\";\nconstant Turn_Ar: \ttargetFsmType := \"1101\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \t\ttargetFsmType := \"101\";\nconstant Backoff: \ttargetFsmType := \"010\";\nconstant S_Data: \t\ttargetFsmType := \"011\";\nconstant Turn_Ar: \ttargetFsmType := \"110\";\nconstant Dont_Care: targetFsmType := \"XXX\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= Dont_Care;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\ntype targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n-- Process to generate next state logic\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n null;\n\n end case;\n\n end process nxtStProc;\n\n\n-- Process to register the current state\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n-- Process to generate outputs\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n-- Assign output ports\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\n-- Incorporates Errata 10.1 and 10.2\n\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(4 downto 0);\n\nconstant Idle: integer := 0;\nconstant B_Busy: integer := 1;\nconstant Backoff: integer := 2;\nconstant S_Data: integer := 3;\nconstant Turn_Ar: integer := 4;\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n\n nextState <= (others => '0');\n\n if currState(Idle) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n if currState(B_Busy) = '1' then\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState(Idle) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState(S_Data) <= '1';\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState(Backoff) <= '1';\n else\n nextState(B_Busy) <= '1';\n end if;\n end if;\n\n if currState(S_Data) = '1' then\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState(Backoff) <= '1';\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState(Turn_Ar) <= '1';\n else\n nextState(S_Data) <= '1';\n end if;\n end if;\n\n\n if currState(Backoff) = '1' then\n if PCI_Frame_n = '1' then\n nextState(Turn_Ar) <= '1';\n else\n nextState(Backoff) <= '1';\n end if;\n end if;\n\n if currState(Turn_Ar) = '1' then\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState(B_Busy) <= '1';\n else\n nextState(Idle) <= '1';\n end if;\n end if;\n\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n\tcurrState <= (others => '0'); -- per Errata 10.2\n currState(Idle) <= '1';\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n OE_Trdy_n <= '0';\tOE_Stop_n <= '0';\tOE_Devsel_n <= '0';\t-- defaults per errata 10.1\n OE_AD <= '0';\t\tLPCI_Trdy_n <= '1';\tLPCI_Stop_n <= '1';\n\t LPCI_Devsel_n <= '1';\n\n if (currState(S_Data) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n\n if (currState(Backoff) = '1') then\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n end if;\n\n\n if (currState(Turn_Ar) = '1') then\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n end if;\n\n if (currState(Idle) = '1' or currState(B_Busy) = '1') then\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n end if;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic;\t-- PCI Frame#\n PCI_Irdy_n: in std_logic;\t\t-- PCI Irdy#\n Hit: in std_logic;\t\t\t-- Hit on address decode\n D_Done: in std_logic;\t\t\t-- Device decode complete\n Term: in std_logic;\t\t\t-- Terminate transaction\n Ready: in std_logic;\t\t\t-- Ready to transfer data\n Cmd_Write: in std_logic;\t\t-- Command is Write\n Cmd_Read: in std_logic;\t\t-- Command is Read\n T_Abort: in std_logic;\t\t-- Target error - abort transaction\n PCI_Clk: in std_logic;\t\t-- PCI Clock\n PCI_Reset_n: in std_logic;\t-- PCI Reset#\n\n PCI_Devsel_n: out std_logic;\t-- PCI Devsel#\n PCI_Trdy_n: out std_logic;\t-- PCI Trdy#\n PCI_Stop_n: out std_logic;\t-- PCI Stop#\n OE_AD: out std_logic;\t\t\t-- PCI AD bus enable\n OE_Trdy_n: out std_logic;\t\t-- PCI Trdy# enable\n OE_Stop_n: out std_logic;\t\t-- PCI Stop# enable\n OE_Devsel_n: out std_logic\t-- PCI Devsel# enable\n\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\nsignal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\nsubtype targetFsmType is std_logic_vector(2 downto 0);\n\nconstant Idle: \t\ttargetFsmType := \"000\";\nconstant B_Busy: \ttargetFsmType := \"001\";\nconstant Backoff: \ttargetFsmType := \"011\";\nconstant S_Data: \ttargetFsmType := \"110\";\nconstant Turn_Ar: \ttargetFsmType := \"100\";\n\nsignal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n\t\t\t LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when IDLE =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when B_BUSY =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= IDLE;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= BACKOFF;\n else\n nextState <= B_BUSY;\n end if;\n\n when S_DATA =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= BACKOFF;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= TURN_AR;\n else\n nextState <= S_DATA;\n end if;\n\n\n when BACKOFF =>\n if PCI_Frame_n = '1' then\n nextState <= TURN_AR;\n else\n nextState <= BACKOFF;\n end if;\n\n when TURN_AR =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_BUSY;\n else\n nextState <= IDLE;\n end if;\n\n when others =>\n\t nextState <= IDLE;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n\n -- Set default output assignments\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n\t\t OE_AD <= '1';\n\t else\n\t\t OE_AD <= '0';\n\t\tend if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n\t when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n\t\tOE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n\nentity pci_target is port (\n PCI_Frame_n: in std_logic; -- PCI Frame#\n PCI_Irdy_n: in std_logic; -- PCI Irdy#\n Hit: in std_logic; -- Hit on address decode\n D_Done: in std_logic; -- Device decode complete\n Term: in std_logic; -- Terminate transaction\n Ready: in std_logic; -- Ready to transfer data\n Cmd_Write: in std_logic; -- Command is Write\n Cmd_Read: in std_logic; -- Command is Read\n T_Abort: in std_logic; -- Target error - abort transaction\n PCI_Clk: in std_logic; -- PCI Clock\n PCI_Reset_n: in std_logic; -- PCI Reset#\n\n PCI_Devsel_n: out std_logic; -- PCI Devsel#\n PCI_Trdy_n: out std_logic; -- PCI Trdy#\n PCI_Stop_n: out std_logic; -- PCI Stop#\n OE_AD: out std_logic; -- PCI AD bus enable\n OE_Trdy_n: out std_logic; -- PCI Trdy# enable\n OE_Stop_n: out std_logic; -- PCI Stop# enable\n OE_Devsel_n: out std_logic -- PCI Devsel# enable\n );\nend pci_target;\n\narchitecture fsm of pci_target is\n\n signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;\n\n subtype targetFsmType is std_logic_vector(2 downto 0);\n\n constant Idle: targetFsmType := \"000\";\n constant B_Busy: targetFsmType := \"001\";\n constant Backoff: targetFsmType := \"011\";\n constant S_Data: targetFsmType := \"110\";\n constant Turn_Ar: targetFsmType := \"100\";\n\n signal currState, nextState: targetFsmType;\n\nbegin\n\n nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,\n LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin\n case currState is\n when Idle =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when B_Busy =>\n if (PCI_Frame_n ='1' and D_Done = '1') or\n\t (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then\n nextState <= Idle;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '0' or (Term = '1' and Ready = '1') ) then\n nextState <= S_Data;\n elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and\n\t\t (Term = '1' and Ready = '0') then\n nextState <= Backoff;\n else\n nextState <= B_Busy;\n end if;\n\n when S_Data =>\n if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and\n (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then\n nextState <= Backoff;\n elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then\n nextState <= Turn_Ar;\n else\n nextState <= S_Data;\n end if;\n\n\n when Backoff =>\n if PCI_Frame_n = '1' then\n nextState <= Turn_Ar;\n else\n nextState <= Backoff;\n end if;\n\n when Turn_Ar =>\n if (PCI_Frame_n = '0' and Hit = '0') then\n nextState <= B_Busy;\n else\n nextState <= Idle;\n end if;\n\n when others =>\n\t null;\n end case;\n end process nxtStProc;\n\n\n curStProc: process (PCI_Clk, PCI_Reset_n) begin\n if (PCI_Reset_n = '0') then\n currState <= Idle;\n elsif (PCI_Clk'event and PCI_Clk = '1') then\n currState <= nextState;\n end if;\n end process curStProc;\n\n\n outConProc: process (currState, Ready, T_Abort, Cmd_Write,\n Cmd_Read, T_Abort, Term) begin\n case currState is\n when S_Data =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then\n LPCI_Trdy_n <= '0';\n else\n LPCI_Trdy_n <= '1';\n end if;\n\n if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then\n LPCI_Stop_n <= '0';\n else\n LPCI_Stop_n <= '1';\n end if;\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when Backoff =>\n if (Cmd_Read = '1') then \n OE_AD <= '1';\n else\n OE_AD <= '0';\n end if;\n\n LPCI_Stop_n <= '0';\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n if (T_Abort = '0') then\n LPCI_Devsel_n <= '0';\n else\n LPCI_Devsel_n <= '1';\n end if;\n\n when Turn_Ar =>\n\n OE_Trdy_n <= '1';\n OE_Stop_n <= '1';\n OE_Devsel_n <= '1';\n\n when others =>\n\n OE_Trdy_n <= '0';\n OE_Stop_n <= '0';\n OE_Devsel_n <= '0';\n OE_AD <= '0';\n LPCI_Trdy_n <= '1';\n LPCI_Stop_n <= '1';\n LPCI_Devsel_n <= '1';\n\n end case;\n\n end process outConProc;\n\n PCI_Devsel_n <= LPCI_Devsel_n;\n PCI_Trdy_n <= LPCI_Trdy_n;\n PCI_Stop_n <= LPCI_Stop_n;\n\nend fsm;\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity test is port (\n a: in std_logic;\n z: out std_logic;\n en: in std_logic\n );\nend test;\n\narchitecture simple of test is\n\nbegin\n\n z <= a when en = '1' else 'z';\n\nend simple;\n"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":942,"numItemsPerPage":100,"numTotalItems":100932,"offset":94200,"length":100}},"jwt":"eyJhbGciOiJFZERTQSJ9.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc3OTQ5NzU3OCwic3ViIjoiL2RhdGFzZXRzL3J0bC1sbG0vdmhkbF9naXRodWIiLCJleHAiOjE3Nzk1MDExNzgsImlzcyI6Imh0dHBzOi8vaHVnZ2luZ2ZhY2UuY28ifQ.AJKibNcBTJ_O2ZYfx_-tf62fKeukW6zdT2hJlCE9vHYaJj-GPxauVK3gAm1t6MQJ_AQyMGrfKG9lByH8d6ICAg","displayUrls":true,"splitSizeSummaries":[{"config":"default","split":"train","numRows":100932,"numBytesParquet":281891788}]},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Generate I2S audio stream and master clock for the PMODI2S.
-- The chip is a Cirrus Logic CS4344 DAC
--
-- Drive with a 100MHz clock for 48,828 samples per se... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RD_Mux is
Port ( RfDest : in STD_LOGIC;
RD : in STD_LOGIC_VECTOR (5 downto 0);
nRD : out STD_LOGIC_VECTOR (5 downto 0));
end RD_Mux;
architecture Behavioral of RD_Mux is
begin
process(RfDest, RD)
begin
if (RfDest = '1') then
nRD <= "0... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Projec... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity compar is
port (
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
so_a : out std_logic;
so_b : out std_logic
);
end entity;
architecture behav of compar is
signal a_b, b_b,a_b1, b_b1,a_b2, b_b2,a_b3, b_b3,... |
----------------------------------------------------------------------------------------------------
-- inverter_maia.vhd ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity BRESENHAMER is
port (
WRITEENABLE : out std_logic;
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(8 downto 0);
X1 : in std_logic_vec... |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Ha... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual clock multiplexer with buffered output.
---------------------------------------------------------------------... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual clock multiplexer with buffered output.
---------------------------------------------------------------------... |
-- tdp_ram_behav.vhd
-- Copyright (C) 2017 VectorBlox Computing, Inc.
--
-- Behavioural implementation of synchronous true dual-port RAM.
-- Can either be read first or write first.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.idram_utils.all;
entity tdp_ram_behav is
... |
---------------------------------------------------------------------------------
-- Title : 1000 BASE X ability match
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : Eth1000BaseXAbilityMatch.vhd
-- Author : Kurt... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.dbgsnap;
entity dbgsnap_testbench is
port(done : out boolean);
end;
architecture structural of dbgsnap_testbench is
signal finished : boolean;
signal clk : boolean;
si... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.dbgsnap;
entity dbgsnap_testbench is
port(done : out boolean);
end;
architecture structural of dbgsnap_testbench is
signal finished : boolean;
signal clk : boolean;
si... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- A simple frequency divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity divider is
-- 1
-- f_out = f_in -----
-- 2 * n
generic (n: natural range 1 to 2147483647);
port (
clk_in : in std_logic;
nrst : in std_logic;
... |
entity tb_func08b is
end tb_func08b;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func08b is
signal v : std_ulogic_vector(3 downto 0);
signal r : integer;
begin
dut: entity work.func08b
port map (v, r);
process
begin
v <= x"0";
wait for 1 ns;
assert r = 4 severity fai... |
entity record_test is
port (
o : out integer
);
end record_test;
architecture rtl of record_test is
type t_record is record
int : integer range 0 to 15;
end record t_record;
constant rec_constant : t_record := (int => 8);
signal int_signal : integer range 0 to rec_constant.int := 4;
begin
o <= i... |
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_core.vhd,v 1.28 2006/06/18 10:47:01 arnim Exp $
--
-- Core Toplevel
--
-- Notes:
-- This core implements a simple VRAM interface which is suitable f... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:00:58 11/19/2013
-- Design Name:
-- Module Name: My_PC_Adder_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
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