content stringlengths 1 1.04M ⌀ |
|---|
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 do... |
entity sigvar is
end entity;
architecture test of sigvar is
procedure proc1(signal x : bit_vector) is
variable y : bit_vector(x'range);
begin
y := x;
end procedure;
procedure proc2(signal x : out bit_vector; signal y : in bit_vector) is
begin
x <= y;
end procedure;
... |
entity sigvar is
end entity;
architecture test of sigvar is
procedure proc1(signal x : bit_vector) is
variable y : bit_vector(x'range);
begin
y := x;
end procedure;
procedure proc2(signal x : out bit_vector; signal y : in bit_vector) is
begin
x <= y;
end procedure;
... |
entity sigvar is
end entity;
architecture test of sigvar is
procedure proc1(signal x : bit_vector) is
variable y : bit_vector(x'range);
begin
y := x;
end procedure;
procedure proc2(signal x : out bit_vector; signal y : in bit_vector) is
begin
x <= y;
end procedure;
... |
entity sigvar is
end entity;
architecture test of sigvar is
procedure proc1(signal x : bit_vector) is
variable y : bit_vector(x'range);
begin
y := x;
end procedure;
procedure proc2(signal x : out bit_vector; signal y : in bit_vector) is
begin
x <= y;
end procedure;
... |
entity sigvar is
end entity;
architecture test of sigvar is
procedure proc1(signal x : bit_vector) is
variable y : bit_vector(x'range);
begin
y := x;
end procedure;
procedure proc2(signal x : out bit_vector; signal y : in bit_vector) is
begin
x <= y;
end procedure;
... |
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type
state_machine is (idle, write, read, done);
type
state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
entity bounds7 is
end entity;
architecture test of bounds7 is
type my_int is range 1 to 10;
begin
process is
variable x : my_int;
variable y : integer;
begin
x := 6;
y := integer(x);
x := 10;
x := x + 1;
wait;
end process;
end architecture;
|
entity bounds7 is
end entity;
architecture test of bounds7 is
type my_int is range 1 to 10;
begin
process is
variable x : my_int;
variable y : integer;
begin
x := 6;
y := integer(x);
x := 10;
x := x + 1;
wait;
end process;
end architecture;
|
entity bounds7 is
end entity;
architecture test of bounds7 is
type my_int is range 1 to 10;
begin
process is
variable x : my_int;
variable y : integer;
begin
x := 6;
y := integer(x);
x := 10;
x := x + 1;
wait;
end process;
end architecture;
|
entity bounds7 is
end entity;
architecture test of bounds7 is
type my_int is range 1 to 10;
begin
process is
variable x : my_int;
variable y : integer;
begin
x := 6;
y := integer(x);
x := 10;
x := x + 1;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: John Bieling ----
---- ... |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... |
--------------------------------------------------------------------------------
-- Title : RX data path
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_get_data.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfel... |
package TestPkg is
generic (
G_TEST : positive := 8
);
end package TestPkg;
package body TestPkg is
procedure TestReport is
begin
report "G_TEST :" & to_string(G_TEST);
end procedure;
end package body;
|
package TestPkg is
generic (
G_TEST : positive := 8
);
end package TestPkg;
package body TestPkg is
procedure TestReport is
begin
report "G_TEST :" & to_string(G_TEST);
end procedure;
end package body;
|
-------------------------------------------------------------------------
-- TEST_BENCH PARA SIMULACAO DA SERIAL
-- Simular por 100 microssegundos
-------------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_uns... |
--------------------------------------------------------------------------------
--
-- Copyright 2015 PMC-Sierra, Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License"); you
-- may not use this file except in compliance with the License. You may
-- obtain a copy of the License at
-- http://www.apache... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when inp... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when inp... |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet.... |
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All r... |
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All r... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY system IS
PORT(rst: IN std_logic; -- system reset, high active
clk: IN std_logic; -- system clock, 50 MHz, rising edge active
btn0: IN std_logic; -- push button, low active
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity top is
port(
rst : in std_logic;
clk : in std_logic;
pc : out std_logic_vector(7 downto 0);
rx : in std_logic;
tx : ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--STEP 1
--This component takes 2 numbers written in scientific notation and returns the same 2 numbers specifying which has the biggest
--exponent and which has the smaller
entity number_swapper is
generic(
TOTAL_BITS : natural := 23;
EXP_BI... |
library ieee;
use ieee.std_logic_1164.all;
-- This package is meant as a stop-gap solution while the boolean_vector type
-- specified in VHDL 2008 is not availabe in the used synthesis tools.
package basic_types_pkg is
type bool_vector is array (natural range <>) of boolean;
function std_logic_vector_... |
-------------------------------------------------------------------------------
-- system_clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_0_v4_03... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
-- so, acc, hold: in STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_l... |
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v8_0 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity tb_cmp02 is
end tb_cmp02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cmp02 is
signal l : std_logic_vector(3 downto 0);
signal r : natural;
signal eq : std_logic;
signal ne : std_logic;
signal lt : std_logic;
signal le : std_logic;
signal ge : std_logic;
signal gt : st... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:50:16 04/30/2015
-- Design Name:
-- Module Name: C:/IRIS/IRIS/IRIS_TB.vhd
-- Project Name: IRIS
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--
-- Definition of a single port ROM for KCPSM3 program defined by programm.psm
--
-- Generated by KCPSM3 Assembler 27Apr2016-08:23:29.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is use... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee ;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity Pipeliner is
port(
clk, rst : in std_logic;
IF_en, ID_en, EX_en, MEM_en, MEM_read, WB_en : out std_logic;
Instruction_done : out std_logic
);
end;
architecture behav of Pipeliner is
begin... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================================... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================================... |
--------------------------------------------------------------------------------
-- MIPS I CPU --
--------------------------------------------------------------------------------
-- ... |
---------------------------------------------------------------------------------
-- Design Name : neighExtractor
-- File Name : neighExtractor.vhd
-- Function : Extracts a generic neighborhood from serial in_data
-- Coder : Kamel Eddine ABDELOUAHAB
-- Institution : Institut Pascal
------... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/12/15 01:59:13 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/12/15 01:59:13 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity repro2 is
generic(
BITS : positive := 4);
port(
min : in bit_vector(BITS - 1 downto 0) := "1010");
end entity;
architecture rtl of repro2 is
begin
process
variable sum : bit_vector(BITS - 2 downto 0);
variable carry : bit;
begin
(carry, sum) := min;
assert carry = '1';
asse... |
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
-- ----------------------------------------------------------------------------
-- Entity for implementation of Clark Strided NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ... |
-- ----------------------------------------------------------------------------
-- Entity for conversion from one hot encoding to binary state encoding
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- AXI Lite IP Interface (IPIF) - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF L... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:55:00 11/18/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_18.11.2013/My_16bitOr_tb_948282.vhd
-- Project Name: Mips32_948282_18.11.2013
-- Target Device:
-- T... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Da... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity koc_signal is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32;
axi_control_offset : integer := 0;
axi_control_signal... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
clock : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return std_logic;
begin
process(A) is
... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_192 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(10 downto 0)
);
end mul_192;
architecture augh of mul_192 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_192 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(10 downto 0)
);
end mul_192;
architecture augh of mul_192 is
signal tmp_res : signed(... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
generic (WIDTH: integer := 8);
port ( I_a, I_b : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
I_op : in STD_LOGIC_VECTOR (2 downto 0);
O_isZero : out STD_LOGIC;
... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ie... |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:01 04/27/2015
-- Design Name:
-- Module Name: UDP_1Gbe_Core - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package float_types is
subtype float is std_logic_vector(31 downto 0);
type float_vector is array( NATURAL range <> ) of float;
type float_alu_mode is ( idle, add, sub, mul, div, exp);
end package float_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCMSID1 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end DCMSID1;
architecture BEHAVIORAL ... |
library ieee;
use ieee.std_logic_1164.all;
use work.graphics_types_pkg.all;
use work.game_state_pkg.all;
use work.npc_pkg.all;
-- "Artifical intelligence" (for lack of a better name) for moving NPCs
-- (non-player characters, such as enemies) around the screen. The "follower"
-- strategy consists in moving the... |
-- $Id: rlinklib.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity memory is
generic(N: integer := 7; M: integer := 32);
port(
clk: in STD_LOGIC := '0';
we: in STD_LOGIC := '0';
adr: in STD_LOGIC_VECTOR(N-1 downto 0) := (others => '0');
din: in STD_LOGIC_VECTOR(M-1 downto 0) := (oth... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 20:15:21 2017
-- Host : GILAMONSTER running 64-bit major rel... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
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