content stringlengths 1 1.04M ⌀ |
|---|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, cre... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
entity sklopI is port (
a,b: in std_logic;
f, test: out std_logic);
end sklopI;
architecture pon of sklopI is
signal pomocni: std_logic;
begin
pomocni <= a and b after 3 s;
f <= pomocni after 100 ms;
test <= pomocni after 2 s;
end pon;
|
-----------------------------------------------------------------------------
--
-- AVR opcode package
--
-- This package defines opcode constants for the complete AVR instruction
-- set. Not all variants of the AVR implement all instructions.
--
-- Revision History
-- 4/27/98 Glen George initial revision
... |
-------- Clock Divisor -----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.processor_functions.all;
----------------------------------------------------------------------------------
ENTITY clock_divisor IS
PORT (clk, nrst : IN STD_LOGIC; -- clock de entrada,... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAM_16_8 is
port( clk : in std_logic;
writeEnable : in std_logic;
address : in std_logic_vector(3 downto 0);
writeData : in std_logic_vector(7 downto 0);
readData : out std_logic_vector(7 downto 0));
end Ram_16_8;
architect... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_118 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end add_118;
architecture augh of add_118 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_118 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end add_118;
architecture augh of add_118 is
signal carry_inA : std_l... |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(
g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
end entity FIFO;
|
-------------------------------------------------------------------------------
-- File : bmp_source.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Outputs a bitmap image as a data stream
-- Target: Simulator
-- Dependencies: ... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_11.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity clk_div is
generic(
div:integer := 8
);
port(
input: in std_logic;
output: out std_logic;
state: out std_logic_vector(log2(div/2)-1 downto 0)
);
end clk_div;... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Rob Mushrall
-- Timothy Doucette Jr
-- Christopher Parks
--
-- Create Date: 15:43:26 03/25/2016
-- Design Name:
-- Module Name: ProjLab01 - Behavioral
-- Project Name:
-- Target Devi... |
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Con... |
-- NEED RESULT: ARCH00408.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00408.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00408.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: tetrisIO.vhd
-- // Date: 12/9/2004
-- // Description: Main Tetris Program
-- // Class: CSE 378
-- =========================================... |
---------------------------------------------------------------------
-- TITLE: DDR SDRAM Interface
-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 7/26/07
-- FILENAME: ddr_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' witho... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity top_level is
port(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector (3 downto 0);
LEDG : out std_logic_vector(7 downto 0) := X"00";
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
-- $Id: ibdlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
-- $Id: ibdlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:53:20 11/25/2016
-- Design Name:
-- Module Name: Z:/Documents/COP/COPproject/project/maintester.vhd
-- Project Name: project
-- Target Device:
-- Tool versions:
-- Descr... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_top is
signal clk : std_logic;
signal addr : std_logic_vector (1 downto 0);
signal data : std_logic_vector (2 downto 0);
begin
dut: entity work.top
port map (clk, addr, data);
process
procedure pulse is... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Elmer Homero
--
-- Create Date: 10:59:30 08/26/2015
-- Design Name:
-- Module Name: Dec_Binary_7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descriptio... |
--------------------------------------------------------------------------------
-- MIPS I CPU - Functions --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Zoom is
Port ( bleft : in STD_LOGIC;
bright : in STD_LOGIC;
bup : in STD_LOGIC;
bdwn : in STD_LOGIC;
bctr : in STD_LOGIC;
clock : in STD_LOGIC;
reset... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:06 2017
-- Host : KLight-PC running 64-bit major relea... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac_serial is
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- cont... |
entity top_entity is
end top_entity;
architecture top_arch of top_entity is
component used_entity
port (
myport1: in sometype;
myport2: inout sometype
);
end component;
signal mysignal1: sometype;
signal mysignal2: sometype;
begin
myinstance1: used_entity
port map (
myport1 => my... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity romram is
generic (
BITS: integer := 32
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_lo... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--========================================================================================================================
-- Copyright (c) 2016 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
fpga_0_clk_1_sys_... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revi... |
-- #################################################################################################
-- # << NEO430 - Processor Top Entity with Avalon-Compatible Master Interface >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool ver... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool ver... |
---------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Alte... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Ta... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Ta... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Ta... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Ta... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 01:50:56 10/03/2009
-- Design Name:
-- Module Name: TestCPU1_OutPins - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- ... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity VOICE_CLOCK is
port(inclk0:in std_logic;
c0,c1:out std_logic);
end entity;
architecture clkx of VOICE_CLOCK is
begin
c0<=inclk0;
c1<=not inclk0;
end clkx;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_c_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
-- $Id: fifo_2c_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram - syn
-- Description: FIFO, ... |
-------------------------------------------------------------------------------
-- file: TOP_EQ.vhd
-- author: Rene Herthel <rene.herthel@haw-hamburg.de>
-- author: Hauke Sondermann <hauke.sondermann@haw-hamburg.de>
-------------------------------------------------------------------------------
library IEEE;
use ... |
architecture rtl of fifo is
begin
x <= a and b or c nand d nor e xor f xnor g;
x <= a and b or c nand d nor e xor f xnor g;
end architecture;
|
--------------------------------------------------------------------------------
-- Entity: connector
-- Date:2018-08-05
-- Author: gideon
--
-- Description: This simple module connects two tristate "TTL" buffers
-- This module does not allow external drivers to the net.
----------------------------... |
entity tb_rotate_testcase is
end tb_rotate_testcase;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_Std.all;
architecture behav of tb_rotate_testcase is
signal in_vec: UNSIGNED(31 downto 0);
signal out_vecl: UNSIGNED(31 downto 0);
signal out_vecr: UNSIGNED(31 downto 0);
begin
dut: entity work.r... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief ... |
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief ... |
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