content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xil... |
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
----------------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
----------------------------------------------------... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:44:51 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ok_2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_o... |
-----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
--
-- Create Date: 09:56:30 07/06/2011
-- Module Name: grp_debouncer - RTL
-- Project Name: basic functions
-- Targe... |
--------------------------------------------------------------------------------
--
-- Title : ctrl_leds.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Cont... |
-- $Id: sys_w11a_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n3 - syn
-- Description: w11a tes... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block2.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
--!
--! Copyright (C) 2012 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief AXI4-Stream buffer that allows to buffer the accept-signal.
--! @author Matthias Alles
--! @date 2012... |
--!
--! Copyright (C) 2012 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief AXI4-Stream buffer that allows to buffer the accept-signal.
--! @author Matthias Alles
--! @date 2012... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity System is
Port(door: IN std_logic_vector(3 downto 0);
ARM, clock : IN std_logic;
ready, delay, SysArm, AlrOn: OUT std_logic);
end System;
Architecture Basic of System is
Type StateName is (sysoff, syson, alr);
signal Prest,NxtSt,s... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:51:25 10/20/2017
-- Design Name:
-- Module Name: MuxRF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:51:25 10/20/2017
-- Design Name:
-- Module Name: MuxRF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--
-- Title : req_ack
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd
-- Generated : Mon Aug 1 15:58:57 ... |
-------------------------------------------------------------------------------
--
-- Title : req_ack
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd
-- Generated : Mon Aug 1 15:58:57 ... |
-------------------------------------------------------------------------------
--
-- Title : req_ack
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd
-- Generated : Mon Aug 1 15:58:57 ... |
library IEEE;
use IEEE.std_logic_1164.all;
entity com1_pkg1_lib2 is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity com1_pkg1_lib2;
architecture RTL of com1_pkg1_lib2 is
begin
data_o <= data_i;
end architecture RTL;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Softw... |
entity \test
\ is end;
|
-- $Id: sys_tst_serloop1_n3.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either v... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library s... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
SIGNAL I_BUFFERED : std_logic_vector(0 TO %%I_MAX);
SIGNAL C_SIG : std_logic_vector(0 TO %%C_MAX);
SIGNAL STATE, NEXTSTATE : std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0); |
SIGNAL I_BUFFERED : std_logic_vector(0 TO %%I_MAX);
SIGNAL C_SIG : std_logic_vector(0 TO %%C_MAX);
SIGNAL STATE, NEXTSTATE : std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0); |
SIGNAL I_BUFFERED : std_logic_vector(0 TO %%I_MAX);
SIGNAL C_SIG : std_logic_vector(0 TO %%C_MAX);
SIGNAL STATE, NEXTSTATE : std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0); |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version :... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity test_typecasts is
end test_typecasts;
architecture behavioural of test_typecasts is
constant natural_value : natural range 255 downto 0 := 164;
constant slv_value : std_logic_vector(7 downto 0) := "10100100";
funct... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity speccy is
Port (
CLK50 : in std_logic;
MCU_READY : in std_logic;
KEYB_CLK : in std_logic;
KEYB_DATA : in std_logic;
SD_MOSI : out ... |
entity tb_cnt01 is
end tb_cnt01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cnt01 is
signal clk : std_logic;
signal rst : std_logic;
signal clr : std_logic;
signal en : std_logic;
signal cnt : std_logic_vector (9 downto 0);
begin
dut: entity work.cnt01
port map (clock => clk, ... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\SinglePortRAM_Inst0.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -----------------------------------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
architecture RTL of BLOCK_EXAMPLE is
begin
-- correct block format
BLK : block is
begin
BLK2 : block is
begin
BLK3 : block is
begin
end block BLK3;
end block BLK2;
BLK4 : block is
begin
BLK5 : block is
begin
BLK6 : block is
... |
-------------------------------------------------------------------------------
-- Title : Onewire Master Testbench - Reset Operation
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
-----------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_393 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_393;
architecture augh of add_393 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_393 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_393;
architecture augh of add_393 is
signal carry_inA : std_l... |
architecture RTL of FIFO is
function func1 return integer is begin END function func1;
function func1 return integer is begin END function func1;
function func1 return integer is begin END function func1;
procedure proc1 is begin End procedure proc1;
begin
end architecture RTL;
|
entity tb_revrng01 is
end tb_revrng01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_revrng01 is
signal a, z : std_logic_vector (7 downto 0);
begin
dut: entity work.revrng01
port map (a, z);
process
begin
a <= x"a1";
wait for 1 ns;
assert z = x"85" severity failure;
... |
library verilog;
use verilog.vl_types.all;
entity dummy_hub is
generic(
sld_node_ir_width: integer := 16
);
port(
jtag_tck : in vl_logic;
jtag_tdi : in vl_logic;
jtag_tms : in vl_logic;
jtag_usr1 : in vl_logic;
jtag_s... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CU is
Port ( OP : in STD_LOGIC_VECTOR (1 downto 0);
OP3 : in STD_LOGIC_VECTOR (5 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
Cond : in STD_LOGIC_VECTOR (3 downto 0);
wren : out STD_LOGIC;
PCs... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:12:44 08/17/2014
-- Design Name:
-- Module Name: vga_tx_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
entity FIFO is
generic (
G_GEN1 : integer;
G_GEN2 : std_logic;
G_GENA : t_user2;
G_GEN3 : std_logic_vector(3 downto 0);
G_GEN4 : signed(15 downto 0);
G_GEN5 : unsigned(7 downto 0);
G_GEN6 : std_ulogic;
G_GEN7 : t_user1
);
end entity FIFO;
-- Violation below
entity FIFO is
ge... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.HammingPack16.all;
use work.PhoenixPackage.all;
entity HAM_ENC is
port
(
data_in : in regflit; -- data input
data_out : out reghamm -- data output
);
end HAM_ENC;
architecture HAM_ENC of HAM_ENC is
signal P : ... |
-------------------------------------------------------------------------------
-- axi_cdma_sg_cntlr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reser... |
-------------------------------------------------------------------------------
-- $Id: cntr_incr_decr_addn_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- cntr_incr_decr_addn_f - entity / architecture pair
------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Top level for the OV7670 camera project.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Lib... |
package pkg1 is
type my_int1 is range 1 to 10;
type my_int2 is range 1 to 10;
type my_int3 is range 1 to 10;
end package;
-------------------------------------------------------------------------------
package pkg2 is
use work.pkg1.my_int2; -- OK
function func return my_int2;
end pack... |
package pkg1 is
type my_int1 is range 1 to 10;
type my_int2 is range 1 to 10;
type my_int3 is range 1 to 10;
end package;
-------------------------------------------------------------------------------
package pkg2 is
use work.pkg1.my_int2; -- OK
function func return my_int2;
end pack... |
package pkg1 is
type my_int1 is range 1 to 10;
type my_int2 is range 1 to 10;
type my_int3 is range 1 to 10;
end package;
-------------------------------------------------------------------------------
package pkg2 is
use work.pkg1.my_int2; -- OK
function func return my_int2;
end pack... |
package pkg1 is
type my_int1 is range 1 to 10;
type my_int2 is range 1 to 10;
type my_int3 is range 1 to 10;
end package;
-------------------------------------------------------------------------------
package pkg2 is
use work.pkg1.my_int2; -- OK
function func return my_int2;
end pack... |
package pkg1 is
type my_int1 is range 1 to 10;
type my_int2 is range 1 to 10;
type my_int3 is range 1 to 10;
end package;
-------------------------------------------------------------------------------
package pkg2 is
use work.pkg1.my_int2; -- OK
function func return my_int2;
end pack... |
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_cmd_demux_001 is
port(
sink_valid : in vl_logic_vector(0 downto 0);
sink_data : in vl_logic_vector(104 downto 0);
sink_channel : in vl_logic_vector(5 downto 0);
sink_startofpack... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.PhoenixPackage.regNport;
use work.HammingPack16.all;
entity FPPM is
port
(
clock : in std_logic;
reset_in : in std_logic; -- reset geral da NoC
rx : in regHamm_Nport; -- rx ... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 14:13:16 11/21/2015
-- Design Name:
-- Module Name: Robot - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: ... |
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your opt... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00226
--
-- AUTHOR:
--
-- A. Wilm... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- x^131 + x^8 + x^3 + x^2 + 1
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ledController IS
PORT(
clk : in std_logic;
rst : in std_logic;
bus_addr : in std_LOGIC_VECTOR(15 downto 0);
bus_dq : in STD_LOGIC_VECTOR(15 DOWNTO 0);
bus_req : in std_LOGIC;... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Twofish_ecb_vt_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any late... |
--*****************************************************************************
-- @Copyright All rights reserved.
-- Module name : frontend
-- Call by :
-- Description :
-- IC :
-- Version : 1.0
-- Note: :
-- Author : QIU Weibao
-- Date : 20... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Instruction memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "test.asm.mem"
entity IRAM is
generic (
RAM_DEPTH : integer := 48;
I_SIZE : integer := 32
... |
package rectype is
type r1 is record
x : integer;
end record;
end package;
entity e is
end entity;
use work.rectype.all;
architecture a of e is
type r2 is record
x : r1;
end record;
signal s : r2;
begin
p1: process is
type r3 is record
x : r2;
e... |
-------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : bcdtime.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-05-0... |
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