content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- Entity: rom
-- Author: Waj
-- Date : 11-May-13, 26-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Program memory for simple von-Neumann MCU with registerd read da... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of vgca
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
lpm_add_sub0_inst : lpm_add_sub0 PORT MAP (
datab => datab_sig,
result => result_sig
);
|
package cond1 is
`if TOOL_NAME = "false" then
`error "Should not be here"
constant d : integer := 1;
`else
constant c : integer := 1;
`end if
`warning "this is a warning"
`if TOOL_NAME = "nvc" then
`warning "Using nvc"
`end if
`if not (TOOL_TYPE = "SIMULATION") then
`... |
package cond1 is
`if TOOL_NAME = "false" then
`error "Should not be here"
constant d : integer := 1;
`else
constant c : integer := 1;
`end if
`warning "this is a warning"
`if TOOL_NAME = "nvc" then
`warning "Using nvc"
`end if
`if not (TOOL_TYPE = "SIMULATION") then
`... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin end block;
BLOCK_LABEL : block (guard_condition) is begin end block;
-- Violations below
BLOCK_LABEL : block is
begin end block;
BLOCK_LABEL : block (guard_condition) is
begin end block;
end architecture RTL;
|
-- /* -------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any late... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic;
o : out std_logic
);
end;
architecture a of ent is
function inv(s : std_logic) return std_logic is
begin
return not s;
end inv;
signal test : std_logic;
begin
process(clk)
begin
if risi... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare3.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:52 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.vga_comp.all;
entity tb is
end;
architecture rtl of tb is
component vga is
port(clk : in std_logic;
reset : in std_logic;
output : out vga_out_t);
end component;
signal clk : std_logic... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VC... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "AddSubCmp"
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tbfuncs.all;
-... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use ieee.std_logic_1164.all;
entity ret02 is
port (di : std_logic_vector (7 downto 0);
res : out integer);
end ret02;
architecture behav of ret02 is
function sign (v : std_logic_vector (7 downto 0)) return integer is
begin
if v (7) = '1' then
return -1;
end if;
return 1;
... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:19 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major... |
--------------------------------------------------------------------------------
-- Copyright (c) 2016 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : RamR... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:23:44 11/20/2015
-- Design Name:
-- Module Name: random_uniform - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY instructionFetchStage IS
--MIGHT NEED TO MODIFY IF STAGE TO THE WHOLE CPU PIPELINE
port(
clk : in std_logic;
muxInput0 : in std_logic_vector(31 downto 0);
selectInputs : in std_logic;
fo... |
-- file: clk_adc.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a ... |
-- file: clk_adc.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a ... |
-- file: clk_adc.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a ... |
-- file: clk_adc.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This fi... |
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated d... |
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated d... |
--------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- d... |
--------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- d... |
--------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- d... |
--------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- d... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_1_v2
-- Module Name: Solving_Key_Equation_1_v2
-- Project ... |
-- -------------------------------------------------------------------
-- Design:
--
-- Package for VHDL text output
--
-- Note:
-- -----
-- This package uses the VHDL 95 standard.
-- If VHDL 95 is not supported by your simulator
-- you need to comment out the file access functions.
--
-- Th... |
-- -------------------------------------------------------------------
-- Design:
--
-- Package for VHDL text output
--
-- Note:
-- -----
-- This package uses the VHDL 95 standard.
-- If VHDL 95 is not supported by your simulator
-- you need to comment out the file access functions.
--
-- Th... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum_gen is
generic (
N : integer := 32);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin: In std_logic_vector(N/4 downto 0);
S: Out std_logic_vector(N-1 downto 0... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum_gen is
generic (
N : integer := 32);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin: In std_logic_vector(N/4 downto 0);
S: Out std_logic_vector(N-1 downto 0... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date... |
library verilog;
use verilog.vl_types.all;
entity counter741_vlg_check_tst is
port(
Qout : in vl_logic_vector(7 downto 0);
second : in vl_logic;
sampler_rx : in vl_logic
);
end counter741_vlg_check_tst;
|
library ieee;
use ieee.std_logic_1164.all;
entity encoder_behav is
port(
input : in std_logic_vector(5 downto 0);
output : out std_logic_vector(2 downto 0)
);
end entity encoder_behav;
architecture behav of encoder_behav is
begin
process(input)
begin
case input is
when "000001" => output <= "000";
when "0... |
entity tb_rec2 is
end tb_rec2;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_rec2 is
signal clk : std_logic;
signal sl_in : std_logic;
signal slv_in : std_logic_vector(7 downto 0);
signal int_in : integer range 0 to 15;
signal usig_in : unsigned(7... |
-------------------------------------------------------------------------------
-- Title : Useful functions for testbenches
-- Project :
-------------------------------------------------------------------------------
-- File : test_pkg.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Create... |
-------------------------------------------------------------------------------
-- Title : Useful functions for testbenches
-- Project :
-------------------------------------------------------------------------------
-- File : test_pkg.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Create... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:28:34 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBALU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool vers... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:28:34 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBALU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool vers... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:28:34 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBALU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool vers... |
package uart_chipsim_pkg is
procedure uart_chipsim_init(stop_unitl_connected : boolean);
attribute foreign of uart_chipsim_init : procedure is "VHPIDIRECT uart_chipsim_init";
-- if the function returns a positive integer, it is a valid value
-- if the function returns a negative value it is either
-- T... |
-------------------------------------------------------------------------------
--
-- File: tb_TestAD96xx_92xxSPI_Model_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright... |
-------------------------------------------------------------------------------
--
-- File: tb_TestAD96xx_92xxSPI_Model_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- Title : Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- ... |
-------------------------------------------------------------------------------
-- Title : Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- ... |
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This p... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_L... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_L... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_L... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_in is
generic (
ADDR_X : natural range 0 to 3 := 0;
ADDR_Y : natural range 0 to 3 := 0;
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_in is
generic (
ADDR_X : natural range 0 to 3 := 0;
ADDR_Y : natural range 0 to 3 := 0;
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_lo... |
architecture RTL of FIFO is
signal a, b, c, d : std_logic;
signal a,b,c,d : std_logic;
begin
process (a, b, c, d) is
begin
end process;
process (a,b,c,d) is
begin
end process;
process (a, b, c, d) is
begin
end process;
process (a, b,c
d, e, f) is
begin end process... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity SEU is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
seuout : out STD_LOGIC_VECTOR (31 downto 0));
end SEU;
architecture Behavioral of SEU is
begin
process( imm13)
begin
if(imm13(12)... |
entity test is
constant a : b :=
foo /= bar nand baz;
end;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
----------------------------------------------------------------------------------
-- Takes 12 bit input from ADC process and triggers a logic line based on the value
-- Intended to protect devices from an unsafe source (physically, protect fiber optic cable from bad alignment)
-- Runs with the clock rate of the ADC pr... |
library ieee;
use ieee.std_logic_1164.all;
package pkg is
component cmask is
generic
(mask : std_logic_vector (0 to 7));
port (d : std_logic_vector (7 downto 0);
o : out std_logic_vector (7 downto 0));
end component;
end pkg;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_... |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMon.vhd
-- /__... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Codeword Generator_n_m_v2
-- Module Name: Tb_Codeword_Generator_n_m_v2
-- Pr... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
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