content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:10:50 03/29/2014
-- Design Name:
-- Module Name: ramlut - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
-- Some comment
entity FIFO is
end entity;
library ieee;
entity FIFO is
end entity;
library ieee;
-- First Comment
-- Second Comment
-- Third Comment
entity fifo is end entity;
library ieee;
-- First Comment
-- Second Comment
-- Third Comment
entity fifo is end entity;
entity fifo is end entity;
|
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity Alarm is
port( bin_min1, bin_min10, bin_hrs1, bin_hrs10 : in std_logic_vector(3 downto 0);
time_alarm : out std_logic_vector(15 downto 0)
);
end Alarm;
-----Architecture-----
architecture Alerter... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:43:39 2017
-- Host : WK117 running 64-bit major release ... |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This progr... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PISO8bits_TB IS
END PISO8bits_TB;
ARCHITECTURE behavior OF PISO8bits_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PISO8bits
PORT(
Reset : IN std_logic;
D : IN std_logic_vector(7 downto 0);
CLK :... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;... |
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;... |
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;... |
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler... |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/27/2016
-- Design Name: i2s_tx.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-... |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_sc_fifo is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integ... |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_sc_fifo is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integ... |
-- $Header: /syn/cvs/rcs/compilers/vhdl/vhd/synattr.vhd,v 1.90.2.14.2.1 2003/07/08 18:06:01 akapoor Exp $
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997-2003 by Synplicity, Inc. All rights... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
attribute coordinate of comp_1 : component is (0.0, 17.5);
attribute coordinate of comp_1 : component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1 : component is (0.0, 17.5);
begin
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Tue Sep 20 15:46:23 2016
-- Host : chinook.andrew.cmu.edu running 64-bi... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Tue Sep 20 15:46:23 2016
-- Host : chinook.andrew.cmu.edu running 64-bi... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity datapath_tb is
end entity;
architecture TB of datapath_tb is
component datapath
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
Alu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity datapath_tb is
end entity;
architecture TB of datapath_tb is
component datapath
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
Alu... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity inc_ent is
generic (
works : integer;
vec : std_logic_vector);
end entity;
architecture default of inc_ent is
begin
assert false report integer'image(works) & " " & integer'image(vec'length);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_in is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_in is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
library ieee;
use ieee.std_logic_1164.all;
entity match01 is
port (a : in std_logic_vector (3 downto 0);
z : out std_logic);
end match01;
architecture behav of match01 is
begin
z <= a ?= "1--0";
end behav;
|
-- NEED RESULT: ARCH00281: Implicit signal GUARD used in a expression passed
-- NEED RESULT: ARCH00281: Implicit signal GUARD passed to procedure passed
-- NEED RESULT: ARCH00281: Implicit signal GUARD passed in to component passed
-- NEED RESULT: ARCH00281: Implicit signal GUARD used in a expression passed
-- NEED... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SumadorCompleto is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC);
end SumadorCompleto;
architecture Behavioral of SumadorCompleto is
signal s1 : std_logic ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 08:01:06 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity memory is
port ( Sysaddress : in std_logic_vector (15 downto 0);
Sysstrobe : in std_logic;
Sysrw : in std_logic;
Sysdata : inout std_logic_vector (7 downto 0));
end memory; |
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(16 downto 1);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60_v2;
architecture Behavior of H24_Min60_Sec60_v2 is
signal Q:unsigned(23 downto 0);
alias Second_low:u... |
--Practica5 de Diseño Automatico de Sistemas
--Piano Electronico.
--Control de Teclado PS2.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity ps2_interface is
port(
clk : in std_logic;
rst : in std_logic;
ps2_clk : in std_logic;
ps2_data... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity input_split1 is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
wa0_en : in... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity input_split1 is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
wa0_en : in... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
generic(
ADDR_WIDTH : positive := 32;
BUS_WIDTH : positive := 4;
QUEUE_LENGTH : positive := 32
);
port(
clk : in std_ulogic;
reset_n : in std_ulogic
);
end bug;
architecture behav of bug is
signal writ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:38:15 2017
-- Host : GILAMONSTER running 64-bit major rel... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY shifter_tb IS
END shifter_tb;
ARCHITECTURE behavior OF shifter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shifter
PORT(
clk : IN std_logic;
input : IN std_logic_vector(15 downto 0);
enable : I... |
architecture ARCH of ENTITY1 is
begin
INST_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
INST1 : INST1
generic map (
G_GEN_1 => 3... |
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in ... |
-- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
epcs_flash_dclk : out std_logic; ... |
package config is
constant width : integer;
end package;
-------------------------------------------------------------------------------
use work.config.all;
package types is
-- type pair is record
-- x, y : integer;
-- end record;
-- type pair_vec is array (natural range <>) of pair;
t... |
library ieee;
use ieee.std_logic_1164.all;
use work.sampling.all;
package net_config is
constant tau : positive := 20;
constant num_samplers : integer := 128;
constant num_observers : natural := 16;
constant seeds : lfsr_state_array_t(1 to num_samplers) := (others => (others => '1'));
constant biases : w... |
USE work.opc_pack.all;
ENTITY tb_opc_circuit IS END tb_opc_circuit;
ARCHITECTURE test of tb_opc_circuit is
COMPONENT opc_circuit IS
PORT(a, b: IN opc;
q, qxor, qxnor: OUT opc);
END COMPONENT;
SIGNAL a, b, q, qxor, qxnor: opc;
SIGNAL clk1, clk2: bit;
BEGIN
T1: opc_circuit PORT MAP(a, b, q, qxor, qxno... |
-- Chrono implements a simple chronometer with minutes:seconds display.
-- This is just to demonstrate VHDL code, the actual hardware is not suitable
-- for the instended purpose, at least LED drivers should be added, as it
-- stands display is too faint.
--
-- Copyright (C) 2014 Nicola Cimmino
--
-- This progra... |
--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
... |
architecture rtl of fifo is
alias designator is name;
signal sig1 : std_logic;
alias designator is name;
signal sig1 : std_logic;
alias designator is name;
begin
end architecture rtl;
|
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
entity modulo_test is
port (
a : in integer;
b : out integer;
c : out integer
);
end modulo_test;
architecture rtl of modulo_test is
begin
b <= a mod 8;
c <= a rem 8;
end rtl;
|
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) ... |
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) ... |
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) ... |
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) ... |
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity resetter is
port(
clk, rst : in std_logic;
address : out integer;
write : out std_logic
);
end resetter;
architecture Behavioral of resetter is
constant MAX_INDEX : integer := 307199;
type state is (idle, writing);
signal curr_state,... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Sun Jun 18 18:22:32 2017
-- Host : DESKTOP-GKPSR1F running 64-bit major... |
-------------------------------------------------------------------------------
-- Copyright (c) 1999-2006 Xilinx Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Title : ILA Core Xilinx XST Usage Example
-- Project : ChipScope
-----------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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