content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
use work.symmetric_pwm_deadtime_pkg.all;
entity symmetric_pwm_deadtime_tb is
end symmetric_pwm_deadtime_tb;
architecture behavior of symmetric_pwm_deadtime_tb is
constant WIDTH : positive := 8;
constant T_DEAD : natural ... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
use work.symmetric_pwm_deadtime_pkg.all;
entity symmetric_pwm_deadtime_tb is
end symmetric_pwm_deadtime_tb;
architecture behavior of symmetric_pwm_deadtime_tb is
constant WIDTH : positive := 8;
constant T_DEAD : natural ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accum... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accum... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accum... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accum... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: PS/2 Ascii Generator
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nt_ss is
port(
clk : in STD_LOGIC;
SI : in bit;
PO : out bit_VECTOR(7 downto 0)
);
end nt_ss;
--}} End of automatically maintained section
architecture nt_ss of nt_ss is
signal tmp:bit_vector(7 downto 0);
begin
process (clk)
begin
... |
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Tue May 13 22:49:19 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.math_real.all;
-- use ieee.numeric_std.all;
-- use ieee.std_logic_unsigned.all
library uart_bfm;
use uart_bfm.uart_bfm.all;
-- library uart_rx;
-- use uart_rx.uart_rx;
entity uart_tb is
end uart_tb;
architecture tb of uart_tb is
component uart is
port(
... |
-- $Id: s6_cmt_sfs_gsim.vhd 556 2014-05-29 19:01:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versi... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: rom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ======================... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity registers_tb is end;
architecture registers_tb_arc of registers_tb is
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal sel_a: std_logic_vector(... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity registers_tb is end;
architecture registers_tb_arc of registers_tb is
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal sel_a: std_logic_vector(... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xil... |
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xil... |
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xil... |
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xil... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
constant SPIFSMLength : integer := 1295;
constant SPIFSMCfg : std_logic_vector(SPIFSMLength-1 downto 0) := "0000100100000000000001010000100010100000000000000000011000100000000000100001111100000000000000000000111110000000000000000000000000000000010100000000000000100000000000000000110000110000000000100000010000000... |
-- libraries -------------------------------------------------------------------------------------------{{{
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;
use ieee.numeric_std.ALL;
use ieee.math_real.all;
use ieee.math_complex.all;
library work;
use work.all;
use work.FGPU_definitions.all;
use work.... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2_phy_wrapper is
generic(
... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
--this is the COBS encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.myDeclare.all;
entity cobs_encoder is
Port (
bus_clk : in std_logic;
reset : in std_logic;
--cobs inputs
pre_cobs_data_in : in async_stream_type;
data_in_length : in std_logic_ve... |
-- tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:46:37 02/13/2017
-- Design Name:
-- Module Name: C:/Xilinx/__testbecher/testbencher/a_tb.vhd
-- Project Name: testbencher
-- Target Device:
-- Tool versions:
-- Description:
--... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:46:37 02/13/2017
-- Design Name:
-- Module Name: C:/Xilinx/__testbecher/testbencher/a_tb.vhd
-- Project Name: testbencher
-- Target Device:
-- Tool versions:
-- Description:
--... |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/14/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX4
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file i... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Technology specific dual-port RAM.
----------------------------------------------------------... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Technology specific dual-port RAM.
----------------------------------------------------------... |
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := C... |
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := C... |
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := C... |
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := C... |
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := C... |
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := C... |
----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment th... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rec06_pkg.all;
entity rec06 is
port (inp : std_logic;
o : out myrec);
end rec06;
architecture behav of rec06 is
begin
o.b <= not inp;
o.a.c <= 2 when inp = '1' else 3;
o.a.d <= "0000" when inp = '0' else "1000";
end behav;
|
-- This file is part of the ethernet_mac_test project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clock_generator is
port(
reset_i... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY IfStatementPartiallyEnclosed IS
PORT(
a : OUT STD_LOGIC;
b : OUT STD_LOGIC;
c : IN STD_LOGIC;
clk : IN STD_LOGIC;
d : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FSqr is
port (
clk : in std_logic;
flt_in : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end FSqr;
architecture twoproc_pipeline of FSqr is
component FSqrTable is
port... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
----------------------------------------------------------------------------
--
-- Atmel AVR CPU Entity Declaration
--
-- This is the entity declaration for the complete AVR CPU. The design
-- should implement this entity to make testing possible.
--
-- Revision History:
-- 11 May 98 Glen George Initial... |
library verilog;
use verilog.vl_types.all;
entity CMMaster4Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_MASTERENABLE: in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity CMMaster4Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_MASTERENABLE: in vl_logic;
... |
library verilog;
use verilog.vl_types.all;
entity CMMaster4Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_MASTERENABLE: in vl_logic;
... |
library ieee;
use ieee.std_logic_1164.all;
entity edgedetector is
port ( rst : in std_logic;
x : in std_logic;
clk : in std_logic;
x_falling_edge : out std_logic;
x_rising_edge : out std_logic);
end edgedetector;
architecture rtl of edgedetector is
sig... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity heatersLogic is
generic(
heatNumber : natural := 20
);
port(
rsDataIn : in std_logic_vector(7 downto 0);
rsRdy : in std_logic;
rst : in std_logic;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:38:49 06/13/2011
-- Design Name:
-- Module Name: UDP_Complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
--
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versio... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:10:11 04/22/2016
-- Design Name:
-- Module Name: U:/ECE368_Project_Lab1_Team5/jump_unit_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Descripti... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- Title : or64bit
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs... |
-------------------------------------------------------------------------------
-- Module: tb_tld
-- Purpose: Testbench for Top Level Domain of ECDSA
--
-- Author: Leander Schulz
-- Date: 01.11.2017
-- Last change: 01.11.2017
-----------------------------------------------------... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA Buffer Ram
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool ver... |
-------------------------------------------------------------------------------
--! @file asyncFifo-rtl-a.vhd
--
--! @brief The asynchronous Fifo architecture.
--
--! @details This is a generic dual clocked FIFO using the dpRam component as
--! memory.
--
-------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- pragma translate_off
--library synplify;
--use synplify.attributes.all;
-- pragma translate_on
entity ADDC is
generic (
width : integer
);
port(
opa: in std_logic_vector(width-1 downto 0);
opb: in std_logic_vector... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon 64
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.s... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity PC is
port (
counter: in std_logic_vector(15 downto 0 );
new_counter: out std_logic_vector(15 downto 0 );
CLK: in std_logic;
RESET: in std_logic
);
end entity PC;
architecture PC_Arch of PC is
be... |
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
type std_logic_vector is array (integer range <>) of integer;
function to_bitvector(x : std_logic_vector) return bit_vector;
signal mode : std_logic_vector(1 downto 0);
begin
process
subtype modetype is bit_vector(mode'range);
... |
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
type std_logic_vector is array (integer range <>) of integer;
function to_bitvector(x : std_logic_vector) return bit_vector;
signal mode : std_logic_vector(1 downto 0);
begin
process
subtype modetype is bit_vector(mode'range);
... |
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