content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------
-- Increment_PC
-- This unit is a simple Adder, which increment the current value of PC,
-- coming from the PC register, by 4(since the addresses in memory must be
-- word-aligned). The output of this unit feed the MUX_branch unit.
------... |
library ieee;
use ieee.std_logic_1164.all;
entity seven_segment is
port (
clk : in std_logic;
val : in std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
mode: in std_logic
);
end seven_segment;
architecture arch of seven_segment is
component pulser is
generic(
delay:inte... |
architecture test of test2 is
constant foo : bar := baz;
begin end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity xtc_top_ppro is
port (
CLK: in std_logic;
-- Connection to the main SPI flash
--SPI_SCK: out std_logic;
--SPI_MISO: in std_logic;
--SPI_MOSI: out std_logic;
--SPI... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
entity parampow_tb is
end parampow_tb;
architecture tb ... |
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All righ... |
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All righ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std... |
use std.textio.all; -- Imports the standard textio package.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Defines a design entity, without any ports.
entity tests is
end tests;
architecture behaviour of tests is
begin
process
variable l : line;
variable a : natural := 1;
begin
rep... |
use std.textio.all; -- Imports the standard textio package.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Defines a design entity, without any ports.
entity tests is
end tests;
architecture behaviour of tests is
begin
process
variable l : line;
variable a : natural := 1;
begin
rep... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
package pkg1 is
generic (
type value_t);
end package;
package pkg2 is
generic (
type value_t);
package pkg1_inst is new work.pkg1 generic map (value_t => value_t);
use pkg1_inst.all;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit majo... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit majo... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--
-- synthesis test 2:
-- * without clock enable
-- * slow
--
--
-- Altera EP2C-8, Quartus 8.0: (same as hw1_grain)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw2_grain is
port (
CLK_I : in std_logic;
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
I... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- $Id: tb_nexys2_core.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either ve... |
architecture RTL of FIFO is
begin
process
begin
if a = '1' THEN
b <= '0';
elsif c = '1' THEN
b <= '1';
else
if x = '1' THEN
z <= '0';
elsif x = '0' THEN
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' T... |
-- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 27/06/2017 10:20:32 AM
-- Design Name: Adder for Convolutional Codes example project
-- Module Name: MyADDER - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_S... |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 15:31:55 03/22/2013
-- Design Name:
-- Module Name: smal_stack - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool ver... |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 15:31:55 03/22/2013
-- Design Name:
-- Module Name: smal_stack - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool ver... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- NEED RESULT: ARCH00659: The predefined attributes of an interface object (port) of mode 'inout' for an entity may be read passed
-- NEED RESULT: ARCH00659: The predefined attributes of an interface object (port) of mode 'inout' for a block may be read failed
-- NEED RESULT: ARCH00659: The predefined signal attribu... |
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_bram.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Block memory-based Decoder for decoding 8b/10b encoded symbols
--
-- ... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-----------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-----------------------------------------------------... |
--------------------------------------------------------------------------------------------------
-- Interpolator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
-----------------------------------------------... |
-- Copyright (c) 2015-2016 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or ... |
-- Copyright (c) 2015-2016 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- LEON3 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 05.06.2016 22:31:14
-- Module Name: tcp_tx_packet - Behavioral
--
-- Description: Construct and send out TCP packets
--
-----------------------------------------------... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
-- File: dyplo_user_logic_stub.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:19:15 11/22/2013
-- Design Name:
-- Module Name: PC_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:19:15 11/22/2013
-- Design Name:
-- Module Name: PC_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:39:23 11/19/2013
-- Design Name:
-- Module Name: My_16bitMult_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GN4GVGE46N is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GN4GVGE46N is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GN4GVGE46N is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
-- VHDL Entity R6502_TC.Reg_PC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:39:48 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Reg_PC IS
PORT(
... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00592
--
-- AUTHOR:
--
-- A. Wilm... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==========================... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==========================... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==========================... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity deblocking_filter_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer :=... |
-- $Id: xlib.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, o... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block3.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ------------------------... |
--
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : jim@synthworks.com
-- Contributor(s) :
-- Jim Lewis email : jim@synthworks.com
-- *
--
-- * In writing procedures normal, poisson, the f... |
--
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : jim@synthworks.com
-- Contributor(s) :
-- Jim Lewis email : jim@synthworks.com
-- *
--
-- * In writing procedures normal, poisson, the f... |
--
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : jim@synthworks.com
-- Contributor(s) :
-- Jim Lewis email : jim@synthworks.com
-- *
--
-- * In writing procedures normal, poisson, the f... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
package pkg is
procedure proc;
alias prog_alias is proc[];
end package;
package body pkg is
procedure proc is
begin
end;
impure function prog_alias return integer is
begin
prog_alias;
return 0;
end;
end package body;
|
package pkg is
procedure proc;
alias prog_alias is proc[];
end package;
package body pkg is
procedure proc is
begin
end;
impure function prog_alias return integer is
begin
prog_alias;
return 0;
end;
end package body;
|
package pkg is
procedure proc;
alias prog_alias is proc[];
end package;
package body pkg is
procedure proc is
begin
end;
impure function prog_alias return integer is
begin
prog_alias;
return 0;
end;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity my_ROM is
port(
addr : in vl_logic_vector(3 downto 0);
clk : in vl_logic;
\out\ : out vl_logic_vector(7 downto 0)
);
end my_ROM;
|
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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