content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
-------------------------------------------------------------------------------
--
-- File: DPHY_LaneSFEN.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2... |
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert n... |
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert n... |
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert n... |
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert n... |
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert n... |
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
... |
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
... |
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
... |
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
... |
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Activate reset asynchronously and deactivate it synchronously.
--------------------------------------------------------------------------------
libr... |
-- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is ... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
package case1 is
type t is (a, b, c);
function test1(x : t) return integer;
function test2(x : bit_vector(1 to 4)) return integer;
end package;
package body case1 is
function test1(x : t) return integer is
begin
case x is
when a => return 10;
when b => return 20;
... |
architecture a of b is
signal x : integer := 0;
begin
p: process is
begin
end process;
process
variable y : integer := 5;
begin
x <= y;
end process;
process (x) is
begin
x <= x + 1;
end process;
postponed process is
begin
end process;
... |
architecture a of b is
signal x : integer := 0;
begin
p: process is
begin
end process;
process
variable y : integer := 5;
begin
x <= y;
end process;
process (x) is
begin
x <= x + 1;
end process;
postponed process is
begin
end process;
... |
library ieee;
use ieee.std_logic_1164.all;
entity RegFile_T is
end RegFile_T;
architecture Beh of RegFile_T is
component RegFile
generic (
-- èíèöèàëèçàöèÿ ðåãèñòðà ïëþñ ðàçðÿäíîé øèíû äàííûõ
INITREG: std_logic_vector := "0000";
-- ðàçðÿäíîñòü øèíû àäðåñà
a: integer := 2);
port (
-- ñèãíàë èíèöèà... |
--
-- TEST NAME:
--
-- CT00610
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (1)
-- 9.3 (2)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00610
-- PKG00610/BODY
-- ENT00610_Test_Bench(ARCH00610_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision... |
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:52 2017
-- Host : EffulgentTome running 64-bit maj... |
-- NEED RESULT: ENT00197: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved... |
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design... |
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design... |
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design... |
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual pr... |
-- Copyright 2000. GSI Technology
-- GSI Appications
-- apps@gsitechnology.com
-- v 1.0 4/23/2002 Jeff Duagherty 1) based on G16272
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY G880E18BT IS
GENERIC (
CONSTANT A_size : integer := 19;
CONSTANT DQ_size : integer := 9;
CONSTANT b... |
-- Copyright 2000. GSI Technology
-- GSI Appications
-- apps@gsitechnology.com
-- v 1.0 4/23/2002 Jeff Duagherty 1) based on G16272
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY G880E18BT IS
GENERIC (
CONSTANT A_size : integer := 19;
CONSTANT DQ_size : integer := 9;
CONSTANT b... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:28 03/02/2015
-- Design Name:
-- Module Name: reg_128 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:28 03/02/2015
-- Design Name:
-- Module Name: reg_128 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:28 03/02/2015
-- Design Name:
-- Module Name: reg_128 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
package body main_tb_pkg is
function done (
RESULTS : T_TESTRESULTS
) return std_logic is
variable T : std_logic := '1';
begin
for I in RESULTS'range loop
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity boot_ram is
generic(memory_file : string := "boot.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 12; -- address w... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity boot_ram is
generic(memory_file : string := "boot.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 12; -- address w... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/31/2017 03:31:33 PM
-- Design Name:
-- Module Name: Debug_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencie... |
-- $Id: simbididly.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: simbididly - sim
-- Description: Bi-directional... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... |
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 19:43:36 01/31/2010
-- Design Name: SPI
-- Module Name: SPIShifter - RTL
-- Description: Shifter for SPI
--
-- Revision:
-- Revision 0.01 - File Created
--
-... |
------------------------------------------------------------------------------
---- ----
---- gmzpu zwc component testbench ----
---- ----
----... |
entity tb_uassoc03 is
end tb_uassoc03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_uassoc03 is
signal i1 : std_logic_vector(3 downto 0);
signal i2 : std_logic_vector(7 downto 0);
signal o : std_logic_vector(3 downto 0);
begin
dut: entity work.uassoc03
port map (i1, i2, o);
proc... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
termi... |
PACKAGE fifo_pkg is
end package;
PACKAGE fifo_pkg is
end package;
|
--------------------------------------------------------------------------------
-- d_reg32 test bench
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity d_reg2_TB is
end d_reg2_TB;
architecture behavior of d_reg2_TB is
-- Co... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:20:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
entity case3 is
end;
architecture behav of case3 is
subtype bv4 is bit_vector (1 to 4);
type vec2 is array (natural range <>) of bv4;
constant vects : vec2 := (x"0", x"4", x"9", x"3", x"a");
begin
process
variable i : natural := 0;
begin
for i in vects'range loop
case bv4'(vects (i)) is
... |
entity case3 is
end;
architecture behav of case3 is
subtype bv4 is bit_vector (1 to 4);
type vec2 is array (natural range <>) of bv4;
constant vects : vec2 := (x"0", x"4", x"9", x"3", x"a");
begin
process
variable i : natural := 0;
begin
for i in vects'range loop
case bv4'(vects (i)) is
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:48:33 01/13/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/alu/tb_alu.vhd
-- Project Name: alu
-- Target Device:
-- Tool versions:
-- Description:
--
-- VH... |
library ieee;
use ieee.std_logic_1164.all;
entity flopr is
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of flopr is
begin
process (clk, rst) begin
if (rst = '1') then
q <= (ot... |
library ieee;
use ieee.std_logic_1164.all;
entity flopr is
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of flopr is
begin
process (clk, rst) begin
if (rst = '1') then
q <= (ot... |
library ieee;
use ieee.std_logic_1164.all;
entity flopr is
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of flopr is
begin
process (clk, rst) begin
if (rst = '1') then
q <= (ot... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : ... |
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of In... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_ALIGN_BLOCK
--! Project Name: FELIX
--------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_ALIGN_BLOCK
--! Project Name: FELIX
--------------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the ... |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the ... |
architecture rtl of fifo is
variable sig8 : record_type_3
(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)
(elementC(4 downto 1), elementD(1 downto 0)),
element5
(
elementE
(3 downto
... |
-------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may... |
package pkg is
procedure proc;
end package;
package body pkg is
procedure proc is
type nested_prot_t is protected
procedure proc;
end protected;
type nested_prot_t is protected body
procedure proc is
begin
end procedure;
end protected body;
variable nested_prot : neste... |
package pkg is
procedure proc;
end package;
package body pkg is
procedure proc is
type nested_prot_t is protected
procedure proc;
end protected;
type nested_prot_t is protected body
procedure proc is
begin
end procedure;
end protected body;
variable nested_prot : neste... |
package pkg is
procedure proc;
end package;
package body pkg is
procedure proc is
type nested_prot_t is protected
procedure proc;
end protected;
type nested_prot_t is protected body
procedure proc is
begin
end procedure;
end protected body;
variable nested_prot : neste... |
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Devel... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Tx_queue is
generic(
HEAD_AWIDTH : natural := 5;
FIFO_AWIDTH : natural := 2;
RAM_TYPE : string := "DIS_RAM"
);
port (
clk : in std_logic;
reset : in std_logic;
... |
library verilog;
use verilog.vl_types.all;
entity SeqSideEightBitAdder is
port(
SW : in vl_logic_vector(15 downto 0);
KEY0 : in vl_logic;
SAVE : in vl_logic;
ADD : in vl_logic;
LEDR : out vl_logic_ve... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity 1bit_adder_subtractor is
Port ( mode : in STD_LOGIC;
cin : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end 1bit_adder_subtractor;
architecture Behavioral o... |
----------------------------------------------------------------------------
-- Increment_PC
-- This unit is a simple Adder, which increment the current value of PC,
-- coming from the PC register, by 4(since the addresses in memory must be
-- word-aligned). The output of this unit feed the MUX_branch unit.
------... |
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