content stringlengths 1 1.04M ⌀ |
|---|
package pkg is
type INTEGER is range -2147483648 to 2147483647;
type MY_FILE is file of INTEGER;
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
begin end;
-- @elab foo(bar)
|
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in char... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this fil... |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY d_ff IS
PORT(d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END d_ff;
ARCHITECTURE behave OF d_ff IS
BEGIN
... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX... |
--
-- USB Full-Speed/Hi-Speed Device Controller core - extra_pkg.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ad
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
use src.seven_seg_pkg.all;
library tb;
use tb.bus_tb_pkg.all;
entity seven_seg_controller_tb is
generic (
runner_cfg : ... |
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--entity MD5 is
-- Port( Clk : in std_logic;
-- Reset : in std_logic;
-- Run : in std_logic;
-- FirstRun : in std_logic;
-- w0, w1, w2, w3, w4, w5, w6, w7, w8, w... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:32 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-... |
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port (val : out std_logic_vector (63 downto 0));
end entity test2;
architecture beh of test2 is
type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
signal s_register : t_register;
begin
-- the problem is the ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:48:55 01/25/2014
-- Design Name: Nicolas Primeau
-- Module Name: booth_multiplier - Behavioral
-- Project Name: Booth Multiplier
-- Target Devices: Xilinx Spartan 6
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.defs.all;
--a one-instruction-set instruction computer
entity subleq is
port(
CLK_50: in std_logic;
LED: out std_logic_vector(7 downto 2);
SEVENSEG_SEL: out std_logic_vector(3 downto 0); --which 7seg ... |
--Practica6 de Diseño Automatico de Sistemas
--Pong El primer Videojuego.
--Sincronizador de señal de entrada con clk.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
port(
x : in std_logic;
rst : in std_logic;
clk : in... |
-- ----------------------------------------------------------------------------
-- Entity for implementation of Sourdis_Bispo NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end... |
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end... |
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end... |
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end... |
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_implication is
constant assert_name : string := "OVL_IMPLICATION";
constan... |
-- NEED RESULT: ENT00198: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved... |
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
-----------------------------------------------------------... |
entity repro2 is
end;
architecture behav of repro2 is
type bv_array is array (natural range <>) of bit_vector;
subtype byte_array is bv_array(open)(7 downto 0);
type mrec is record
b : boolean;
data : byte_array;
end record;
signal s : mrec (data... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_7_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
-----------------------------------------------------------------------
-----------------------------DESLOCADOR--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador is
port (
a: in std_logic_vector(31 dow... |
----------------------------------------------------------------------
-- brdConst_pkg (for EmCraft SoC FG896 Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Ha... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:35:50 05/31/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/arp1/arp_tb.vhd
-- Project Name: arp1
-- Target Device:
-- Tool versions:
-- D... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation;... |
--------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Alt... |
--------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Alt... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
cos : out std_logic_vector(7 downto 0);
sin : out std_logic_vector(7 downto 0));
end top;
architecture rtl of top is
--
signal reset_reg : std_logic;
signal pre_c... |
-------------------------------------------------------------------------------
-- $Id: ram_loader-c.vhd,v 1.1 2005/04/10 18:02:32 arniml Exp $
-------------------------------------------------------------------------------
configuration ram_loader_rtl_c0 of ram_loader is
for rtl
end for;
end ram_loader_rtl_c0;
|
--! @file trig_table_ea.vhd
--! @brief sin/cos lookup table generator
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-09-30
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with ... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DI... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DI... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DI... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DI... |
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
end context c1;
-- This should pass
context c1 is
end context ;
-- Split declaration across lines
context
c1
is
end
context
c1
;
|
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Stan... |
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Stan... |
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Stan... |
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Stan... |
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Stan... |
-------------------------------------------------------------------------------
-- axi_master_lite_reset.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *********************************************... |
library verilog;
use verilog.vl_types.all;
entity select2_5 is
port(
in1 : in vl_logic_vector(4 downto 0);
in2 : in vl_logic_vector(4 downto 0);
choose : in vl_logic;
\out\ : out vl_logic_vector(4 downto 0)
);
end select2_... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
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