content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual input buffer with the differential signals.
-----------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:01:45 06/05/2016
-- Design Name:
-- Module Name: SWITCHES - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ac
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
-------------------------------------------------------------------------------
--
-- The T8243 asynchronous toplevel
--
-- $Id: t8243.vhd,v 1.1 2006-07-13 22:53:56 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribu... |
-------------------------------------------------------------------------------
-- Title : Onewire Master Testbench - Read Operation
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:37:39 04/01/2014
-- Design Name:
-- Module Name: wishbone_shared_mem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:37:39 04/01/2014
-- Design Name:
-- Module Name: wishbone_shared_mem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
`protect begin_protected
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`protect ke... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Mar... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Mar... |
library verilog;
use verilog.vl_types.all;
entity finalproject_jtag_uart_sim_scfifo_r is
port(
clk : in vl_logic;
fifo_rd : in vl_logic;
rst_n : in vl_logic;
fifo_EF : out vl_logic;
fifo_rdata : out vl_logic_vector(... |
-- $Id: memlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: memlib
-- Description: Basic memory components:... |
-------------------------------------------------------------------------------
-- Filename: ac97_timing.vhd
--
-- Description: Provides the primary timing signals for the AC97 protocol.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Filename: ac97_timing.vhd
--
-- Description: Provides the primary timing signals for the AC97 protocol.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Filename: ac97_timing.vhd
--
-- Description: Provides the primary timing signals for the AC97 protocol.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Filename: ac97_timing.vhd
--
-- Description: Provides the primary timing signals for the AC97 protocol.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Filename: ac97_timing.vhd
--
-- Description: Provides the primary timing signals for the AC97 protocol.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Filename: ac97_timing.vhd
--
-- Description: Provides the primary timing signals for the AC97 protocol.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-- $Id: simlib.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2,... |
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
wait;
end process;
end architecture;
|
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
wait;
end process;
end architecture;
|
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
wait;
end process;
end architecture;
|
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
wait;
end process;
end architecture;
|
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CLK25M is
port (
CLK_IN : in std_logic;
CLK_OUT : out std_logic
);
end CLK25M;
architecture RTL of CLK25M is
signal DIVIDER : std_logic;
begin
CLK_OUT <= DIVIDER;
process (CLK_IN) begin
if(CLK_IN'event and CLK_IN = '1') th... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_5
-- Module Name: Solving_Key_Equation_5
-- Project Name: ... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrig... |
library ieee;
use ieee.std_logic_1164.all;
entity top_level_tb is
end top_level_tb;
architecture bhv of top_level_tb is
signal clk50Mhz : std_logic := '0';
signal image_select : std_logic_vector(2 downto 0) := "001";
signal VGA_R,VGA_G,VGA_B : std_logic_vector(3 downto 0);
signal VGA_VS, VGA_HS : std_logic;
signal ... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's UART Core.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_st... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
-----------------------------------------------------------... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the accumulator and the C flag.
--
-- $Id: t400_alu-c.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reser... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- Title : Testbench for integer-to-real conversion
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
---------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for integer-to-real conversion
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
---------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_210 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_210;
architecture augh of add_210 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_210 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_210;
architecture augh of add_210 is
signal carry_inA : std_l... |
-------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
--------------------------------------------------... |
--------------------------------------------------------------------------
-- This file is part of Oggonachip project
---------------------------------------------------------------------------
-- Entity: mdct
-- File: mdct.vhd
-- Author: Luis L. Azuara
-- Description: Interface of MDCT core with AMBA bus.Reads memo... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
-- +UEFSHDR----------------------------------------------------------------------
-- 2014 UEFS Universidade Estadual de Feira de Santana
-- TEC499-Sistemas Digitais
-- ------------------------------------------------------------------------------
-- TEAM: <Team identification>
-- ---------------------------------------... |
-- +UEFSHDR----------------------------------------------------------------------
-- 2014 UEFS Universidade Estadual de Feira de Santana
-- TEC499-Sistemas Digitais
-- ------------------------------------------------------------------------------
-- TEAM: <Team identification>
-- ---------------------------------------... |
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