content stringlengths 1 1.04M ⌀ |
|---|
entity repro4 is
end entity;
architecture tb of repro4 is
type channel is record
data : bit_vector;
ack : bit;
end record;
type my_bus is record
rd : channel;
wr : channel;
end record;
function init_channel (width : natural) return channel is
begin
return (data => (width - 1 downto 0... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_169 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_169;
architecture augh of add_169 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_169 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_169;
architecture augh of add_169 is
signal carry_inA : std_l... |
-------------------------------------------------------------------------------
-- leds_4bit_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_gpio_v2_00_a;
use xps_gpio_v2_00_a... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB ... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1: INST1
port map (
PORT_1 => w_port_1... |
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ /... |
-- This module is intended for power-on resetting, while accepting force reset
-- (i.e. from a button push) to reset both clock generator (DCM) and other
-- components in the design. It sets CLK_RST high for (CNT_RANGE_HIGH -
-- CLK_RESET_DELAY_CNT) cycles, Then wait for the DCM_LOCKED signal. It waits
-- for another... |
-- This module is intended for power-on resetting, while accepting force reset
-- (i.e. from a button push) to reset both clock generator (DCM) and other
-- components in the design. It sets CLK_RST high for (CNT_RANGE_HIGH -
-- CLK_RESET_DELAY_CNT) cycles, Then wait for the DCM_LOCKED signal. It waits
-- for another... |
----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation... |
----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation... |
----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation... |
-- ring_counter - ring counter logic written in vhdl
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any war... |
entity tb_iassoc03 is
end tb_iassoc03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc03 is
signal a : natural;
signal b : natural;
signal res : natural;
begin
dut: entity work.iassoc03
port map (a, b, res);
process
begin
a <= 1;
b <= 5;
wait for 1 ns;
asser... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top ... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top ... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top ... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top ... |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top ... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: standard_cc_module_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard,... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: standard_cc_module_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard,... |
Library ieee;
use ieee.std_logic_1164.all;
entity segment_decoder is
port(
hexIn: in std_logic_vector(3 downto 0);
segmentMux: out std_logic_vector(6 downto 0)
);
end segment_decoder;
architecture primary of segment_decoder is
begin
process(hexIn) begin
case hexIn is
when "0000" => segmentMux... |
--
-- Test Bench for Link interface.
--
-- Unfortunately rather incomplete.
-- The following items are verified:
-- * reset;
-- * link start, NULL exchange, FCT exchange;
-- * link autostart on first NULL;
-- * send/receive time codes, data characters, EOP/EEP;
-- * detection of timeout, disconnection, parity erro... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 19 16:38:23 2017
-- Host : vldmr-PC running 64-bit Service ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:04 10/20/2017
-- Design Name:
-- Module Name: SEU_30 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:04 10/20/2017
-- Design Name:
-- Module Name: SEU_30 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architect... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architect... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architect... |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architect... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 20:50:53
-- Design Name:
-- Module Name: bmp_wreiter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Ändert gelesene BMP datei und schreibt ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Projeto gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Descrição da Entidade: somador.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity somador is
port(a, b, cin, opSomador:in std_logic; s, cout: out std_logic);
end somador;
architecture ... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k3_k4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- comparator calculate state with minimum path metric from final path metric sum
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port(A,B : in std_logic_vector(2 downto 0);
CODE_A, CODE_B : in std_logic_vector(1 downto 0);
CMP : out std_logic_vector(... |
use work.graphics_types_pkg.all;
package npc_pkg is
constant NPC_SPEED_MAX: integer := 12;
type npc_ai_type is (AI_BOUNCER, AI_FOLLOWER, AI_PROJECTILE);
type npc_type is record
-- start position for the NPC
initial_position: point_type;
-- start velocity for the NPC
... |
--
|
----------------------------------------------------------------------------------
-- Company: University of Genova
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: VHDL package for com... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: VHDL package for com... |
-- $Id: rlink_rlbmux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: rlink_rlbmux - syn
-- Description: rlink rlb ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 05.06.2016 22:31:14
-- Module Name: udp_tx_packet - Behavioral
--
-- Description: Construct and send out UDP packets
--
-----------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:02:28 10/26/2009
-- Design Name:
-- Module Name: IpinReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:02:28 10/26/2009
-- Design Name:
-- Module Name: IpinReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:02:28 10/26/2009
-- Design Name:
-- Module Name: IpinReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.ALL;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library unisim;
use UNISIM.VComponents.all;
entity user_logic is
generic
(
C_SLV_DWIDTH ... |
-------------------------------------------------------------------------------
-- $Id: ip2bus_srmux.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux.vhd - vhdl design file for the entity and architecture
-- ... |
-------------------------------------------------------------------------------
-- $Id: ip2bus_srmux.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux.vhd - vhdl design file for the entity and architecture
-- ... |
-----------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2008 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 200... |
-------------------------------------------------------------------------------
-- ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
package myfixed is
generic ( whole : natural; frac : natural ); -- OK
constant width : natural := whole + frac; -- OK
type fixed_t is array (1 to width) of bit; -- OK
function "+"(x, y : fixed_t) return fixed_t; -- OK
end package;
package body myfixed is
function "+"(x, y : fixed_t) return... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO_CTRL is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO_CTRL is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO_CTRL is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 10:19:23 2017
-- Host : vldmr-PC running 64-bit Service ... |
entity repro is
end repro;
architecture Behavioral of repro is
constant c_CLOCK_FREQUENCY : natural := 32000000;
constant c_SWITCH_ON_TIME_ms : time := 200 ms;
constant c_switch_ms : natural := c_SWITCH_ON_TIME_ms / 1 ms;
constant c_freq1 : real := real(c_CLOCK_FREQUENCY *
(c_SWI... |
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
... |
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
... |
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
... |
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
... |
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector testbench
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
-------------------------------------------------... |
-------------------------------------------------------------------------
-- This file is part of Oggonachip project
---------------------------------------------------------------------------
-- Entities: butterfly_8
-- File: mdctcomp.vhd
-- Author: Luis L. Azuara
-- Description: Components requiered to perform the ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_baud_gen is
generic (
g_baud_acc_width : integer := 16);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baudrate_i : in std_logic_vector(g_baud_acc_width downto 0);
baud_tick_o : out std_logic;
... |
entity ent is
generic (
t1 : time := 2 sec;
t2 : time := 5 sec
);
end;
architecture a of ent is
constant t3 : time := t1 + t2;
constant diff : time := abs (t1 - t2);
constant shorter : time := minimum(t1, t2);
constant longer : time := maximum(t1, t2);
constant ratio1 : natural := t1 / t2;
constant rati... |
--Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated do... |
-------------------------------------------------------
--Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi
-------------------------------------------------------
-------------------------------------------------------
--This file is part of 64-bit Kogge-Stone adder.
--64-bit Kogge-Stone adder is free ha... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library stack;
use stack.OneHotStack.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity ctrl1_tb is
end ctrl1_tb;
architecture TB_ARCHITECTURE of ctrl1_tb is
component MROM is
port (
RE... |
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
end generate;
GEN_LABEL : case expression generate
end generate;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : DS18b20 Reader Package
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
-------------------------------------------------------------------------------... |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF ... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library verilog;
use verilog.vl_types.all;
entity Servo is
generic(
CLK_FREQUENCY : integer := 50000000;
VALUE_SCALING : integer := 256;
CTR_LEN : integer := 21;
SPEED_DATA_LEN : integer := 5;
POSITION_DATA_LEN: integer := 8;
ADDR_LEN : integer := ... |
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