content stringlengths 1 1.04M ⌀ |
|---|
------------------------------------------------------------
-- implemented the 8 Byte X 24 byte memory
--
-- Instruction memory on it is the following:
--
-- ADDI R0, 2 ; ADDI R0<-2 500002
-- ADDI R1, 1 ; ADDI R1<-1 510001
-- ADD R0, R1 ; ADD R0<-R0 + R1 001000
-- AND R0, R1 ; AND ... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is... |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is... |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is... |
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
end mwe;
architecture lulz of mwe is
constant cnt_len : integer := 2;
constant cnt_stages : integer := 2;
type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
signal ctl_cnt : ctl_sig(0 to cnt_stages-1);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
end mwe;
architecture lulz of mwe is
constant cnt_len : integer := 2;
constant cnt_stages : integer := 2;
type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
signal ctl_cnt : ctl_sig(0 to cnt_stages-1);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
end mwe;
architecture lulz of mwe is
constant cnt_len : integer := 2;
constant cnt_stages : integer := 2;
type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
signal ctl_cnt : ctl_sig(0 to cnt_stages-1);... |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
--... |
-------------------------------------------------------------------------------
--
-- The timer unit.
--
-- $Id: t400_timer.vhd,v 1.1 2006-05-20 02:47:12 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, wit... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
architecture Empty of MyReconfigLogic is
begin
CfgIntfDOut_o <= (others => '0');
AdcDoConvert_o <= '0';
I2C_DataIn_o <= "00000000";
I2C_ErrAckParam_o <= '0';
I2C_F100_400_n_o <= '0';
I2C_FIFOReadNext_o <= '0';
I2C_FIFOWrite_o <= '0';
I2C_ReceiveSend_n_o <= '0';
I2C_StartProcess_o <= '0';
I2C_ReadCou... |
component pr_region_default_sysid_qsys_0 is
port (
clock : in std_logic := 'X'; -- clk
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X'; -- address
reset_n : in std_logic := 'X' -- reset_n
... |
-- $Id: gray2bin_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
-- $Id: gray2bin_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version ... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon Jan 26 10:14:21 2015
-- Host : xilinxvivadotools running 64-bit unkn... |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publicat... |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' t... |
----------------------------------------------------------------------------------
-- Company: XILINX
-- Engineer: Stephan Koster
--
-- Create Date: 07.03.2014 15:16:37
-- Design Name: stats module
-- Module Name: stats_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Sniffs... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_signed.all;
use IEEE.STD_logic_arith.all;
entity operational_unit is
generic(
N: integer := 4
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(12 downto 1);
d1 : in STD_LOGIC_VECTOR(N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- S... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity AveragingFilter_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
... |
library ieee;
use ieee.std_logic_1164.all;
entity test_tb is
end entity;
architecture beh of test_tb is
signal rx_data : std_logic_vector(159 downto 0);
procedure to_t( signal sa : out std_logic_vector(31 downto 0)) is
begin
sa <= (others => '1');
assert false report "lol";
end procedure... |
library ieee;
use ieee.std_logic_1164.all;
entity test_tb is
end entity;
architecture beh of test_tb is
signal rx_data : std_logic_vector(159 downto 0);
procedure to_t( signal sa : out std_logic_vector(31 downto 0)) is
begin
sa <= (others => '1');
assert false report "lol";
end procedure... |
---------------------------------------------------------------
-- Title : Dual Ported IRAM with Wishbone Interface
-- Project : -
---------------------------------------------------------------
-- File : iram_dp_wb.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Org... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 05:33:33 2019
-- Host : varun-laptop running 64-bit Serv... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:18:10 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------... |
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------... |
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------... |
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------... |
library IEEE;
use IEEE.std_logic_1164.all;
entity spi is
generic
(
SPI_SIZE: integer := 8;
CPOL : std_logic := '0';
CPHA : std_logic := '0'
);
port
(
--AXI BUS
Clk: in std_logic;
Rst: in std_logic;
--CPU baud rate select
ps_val: in std_logic_vecto... |
entity static is
generic ( G : integer := 1 );
end entity;
architecture test of static is
begin
process is
subtype byte is bit_vector(7 downto 0);
variable bv : byte;
variable i : integer;
attribute hello : integer;
attribute hello of bv : variable is 6;
begin
... |
entity vunit5 is
generic ( vunit5 : integer ); -- OK (hides entity)
end entity;
architecture test of vunit5 is
signal x : integer := vunit5; -- OK
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company: ITESM - CQ
-- Engineer: Me
--
-- Create Date: 09:01:11 10/06/2015
-- Design Name:
-- Module Name: Counter0to19 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Si... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segment is
Port
... |
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redist... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- Copyright (c) 2016 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and-or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2016 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and-or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
entity tb_match01 is
end tb_match01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_match01 is
signal a : std_logic_vector(3 downto 0);
signal z : std_logic;
begin
dut: entity work.match01
port map (a, z);
process
begin
a <= "1000";
wait for 1 ns;
assert z = '1' severit... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
-------------------------------------------------------------------------------
--! @file fetch_page_sram_dim.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare SRAM page with DIM data for NanoFIP communication.
-------------... |
entity bounds2 is
end entity;
architecture test of bounds2 is
begin
asssignment_delays: block
signal b1,b2,b3,b4,b5,b6,b7 : boolean;
begin
b1 <= true; -- OK
b2 <= true after 10 ns; -- OK
b3 <= true after 0 ns; -- OK
b4 <= true after ... |
library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0: in std_logic; -- $SOL:0:0$
ip1: in std_logic; -- $SOL:1:0$
ip2: in std_logic;
ip3: in std_logic;
op0: out std_logic;
op1: out std_logic;
op2: out std_logic;
op3: out std_logic
);
end;
archi... |
library ieee;
use ieee.std_logic_1164.all;
entity FourBitAdder is
generic(WIDTH : integer := 4);
port(
A, B: IN std_logic_vector(WIDTH - 1 downto 0);
S: OUT std_logic_vector(WIDTH - 1 downto 0);
COUT: out std_logic
);
end FourBitAdder;
architecture impl of FourBitAdder is
component OneBitAdder is
port(
... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:19:47 2015
-- Host : Vangelis-PC running 64-bit major rel... |
--
-- This file is part of top_optim_sharp_driver
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eith... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Extender is
generic (N : integer := 8);
port (A : in std_logic_vector(N-1 downto 0);
Y : out std_logic_vector((2*N)-1 downto 0)
);
end Extender;
architecture Behavioral of Extender is
begin
process(A)
begin
if (A(N-1) = '0') then
Y(... |
-- $Id: tbd_serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, ei... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:10:20 05/21/2017
-- Design Name:
-- Module Name: mux_result - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report... |
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report... |
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report... |
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report... |
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
/*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
-- $Id: $
-- File name: tb_tristate.vhd
-- Created: 4/19/2012
-- Author: John Wyant
-- Lab Section: 337-02
-- Version: 1.0 Initial Test Bench
library ieee;
--library gold_lib; --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use gold_lib.all; --UNCOM... |
-- Twofish_ecb_tbl_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any lat... |
library ieee;
use ieee.std_logic_1164.all;
entity IDEX_register is
port(Clk, reset : in std_logic;
sign_extended_i, pc_i, data1_i, data2_i: in std_logic_vector(31 downto 0);
sign_extended_o, pc_o, data1_o, data2_o: out std_logic_vector(31 downto 0);
register_address_0_i, register_address_1_... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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