content stringlengths 1 1.04M ⌀ |
|---|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- VHDL de um contador de modulo 16
-- OBS: Para esse experimento so eh utilizada a contagem ate 11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador is
port(clock : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem ... |
-- Pushbutton Debounce Module
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY Debo IS
PORT (
clk: IN STD_LOGIC; ---make it a low frequency Clock input
key: IN STD_LOGIC; -- active low input
pulse: OUT STD_LOGIC);
END Debo;
ARCHITECTURE onepulse OF Debo IS
SIGNAL cnt: STD_LO... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00604
--
-- AUTHOR:
--
-- G. Tomi... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO is
generic(
WIDTH : integer := 16;
DEPTH : integer := 4
);
port(
RB : in vl_logic;
CLR : in vl_logic;
CLK : in vl_logic;
W... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO is
generic(
WIDTH : integer := 16;
DEPTH : integer := 4
);
port(
RB : in vl_logic;
CLR : in vl_logic;
CLK : in vl_logic;
W... |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO is
generic(
WIDTH : integer := 16;
DEPTH : integer := 4
);
port(
RB : in vl_logic;
CLR : in vl_logic;
CLK : in vl_logic;
W... |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_2i_core_ip is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 ... |
architecture RTL of FIFO is
begin
process
begin
if a then
if b then
if c then
c <= d;
end if;
a <= b;
end if;
b <= c;
end if;
z <= a;
-- Violations below
if a then
if b then
if c then
c <= d;
end if;
... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Generate analog 640x480 VGA, double-doublescanned from 19200 bytes of RAM
--
----------------------------------------------------------------------------------
libra... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_uns... |
---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_uns... |
---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_uns... |
--
-- This file is part of top_chenillard
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versi... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_516 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_516;
architecture augh of add_516 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_516 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_516;
architecture augh of add_516 is
signal carry_inA : std_l... |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_capture_4x.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_mem_if_i
-- architecture - arch_sip_mem_if_i
--
-- LANGUAGE : VHDL
--... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
... |
architecture RTL of FIFO is
begin
-- These are passing
a <=
b or
d;
a <=
'0' when c = '0' else
'1' when d = '1' else
'Z';
-- Failing variations
a <=
b or
d;
a <=
'0' when c = '0' else
'1' when d = '1' else
'Z';
-- Arrays should be ignored
a <= (
... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze System on FPGA... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) u... |
package ppkg1 is
type line is access string;
procedure rep1 (variable msg : line := new string (1 to 7));
procedure rep2;
procedure rep3;
end ppkg1;
package body ppkg is
procedure rep1 (msg : line := new string (1 to 7)) is
begin
msg.all := (others => ' ');
end rep1;
procedure rep2 is
begin
... |
package ppkg1 is
type line is access string;
procedure rep1 (variable msg : line := new string (1 to 7));
procedure rep2;
procedure rep3;
end ppkg1;
package body ppkg is
procedure rep1 (msg : line := new string (1 to 7)) is
begin
msg.all := (others => ' ');
end rep1;
procedure rep2 is
begin
... |
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HeRhTr is
Port ( clk : in STD_LOGIC;
reset:in STD_LOGIC;
sd_in: in STD_LOGIC;
sd_out:out STD_LOGIC;
TbmHeader:out STD_LOGIC;
RocHeader:out STD_LOGIC;
TbmTrailer:out STD_LOGIC;
TP:out STD_LOGI... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HeRhTr is
Port ( clk : in STD_LOGIC;
reset:in STD_LOGIC;
sd_in: in STD_LOGIC;
sd_out:out STD_LOGIC;
TbmHeader:out STD_LOGIC;
RocHeader:out STD_LOGIC;
TbmTrailer:out STD_LOGIC;
TP:out STD_LOGI... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity verzoegerung is
port(
CLK, START : in std_logic;
STOP : in std_logic; -- Aufgabe 2
ALARM : out std_logic
);
end entity;
architecture behaviour of verzoegerung is
signal z : unsigned(2 downto 0) := "000";
... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:28:51 05/22/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_trace_memory.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Desc... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity ADT7310P32S16_tb is
end ADT7310P32S16_tb;
architecture behavior of ADT7310P32S16_tb is
component ADT7310P32S16
port (
Reset_n_i : in std_logic;
Clk_i : in std_l... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
entity test is
package a is new b generic map(c => foo(bar));
end;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.harris_package_components.all;
--use work.harris_package_variables.all;
entity pipliner_7x7 is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH... |
library IEEE;
use IEEE.std_logic_1164.ALL;
package mips_instruction_set is
-- --------------------------------------------------------------------------------------------------------
-- _____ _ _ _____ _______ _____ _ _ _____ _______ _____ ____ _ _ _____ ______ _______
-- |_ _| \ | |/ ____|... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:50:59 03/16/2014
-- Design Name:
-- Module Name: TB_DUAL_RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--u... |
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Pu... |
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Pu... |
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Pu... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Pixel_On_Text determines if the current pixel is on text
-- param:
-- textlength, use to init the string
-- input:
-- VGA clock(the clk you used to update VGA)
-- display text
-- top left corner of the text box
-- current X and Y position
-- output:
-- a bit that represent whether is the pixel in text
... |
-- NEED RESULT: ARCH00145.P1: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P2: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P3: Multi inertial transactions occurred on signal asg with slice name... |
library ieee;
use ieee.std_logic_1164.all;
entity d_testbench is end d_testbench;
architecture behavioral of d_testbench is
component d_Latch
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component d_... |
constant TRFSM0Length : integer := 820;
constant TRFSM0Cfg : std_logic_vector(TRFSM0Length-1 downto 0) := "00001001000000001010000100010100000000000001100010000001000011111000000000000000111110000000000000001111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000000000... |
elsif std_match(mem_dout, "00000000") then -- NOP
elsif std_match(mem_dout, "00000010") then -- LD (BC) A
elsif std_match(mem_dout, "00000111") then -- RLCA
elsif std_match(mem_dout, "00001000") then -- LD (d16) SP
elsif std_match(mem_dout, "00001010") then -- LD A (BC)
elsif std_match(mem_dout, "000011... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:34 05/19/2016
-- Design Name:
-- Module Name: RAM_single_port - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:48:18 11/17/2016
-- Design Name:
-- Module Name: USB_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
---------------------------------------------------------------
-- Title : Altera remote update controller model
-- Project : -
---------------------------------------------------------------
-- Author : Andreas Geissler
-- Email : Andreas.Geissler@men.de
-- Organization : MEN Mikro Elektr... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
-------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity StackPointer is
port (
D_IN_BUS : in STD_LOGIC_VECTOR (7 downto 0);
SEL : in STD_LOGIC_VECTOR (1 downto 0);
LD : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY kernel_tb IS
END kernel_tb;
ARCHITECTURE behavior OF kernel_tb IS
-- Component Declaration for the Unit Under Test (UUT)... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 09:42:15 09/11/2015
-- Design Name:
-- Module Name: Ripple_Counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Descrip... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:10 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
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