content stringlengths 1 1.04M ⌀ |
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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** *... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Convert the push button to a 1PPS that can be used to restart
-- camera initialisation
-----------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split6 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split6 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in ... |
------------------------------------------------------------------------------
-- simple_timebase.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE... |
library IEEE;
use IEEE.std_logic_1164.all;
entity issue2 is
port(
a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(2 downto 0)
);
end issue2;
architecture behavior of issue2 is
begin
b <= a;
end behavior;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex1_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(18 downto 0)
);
end ex1_rnd;
architecture behaviour of ex1_rnd is
constant s1: std_logic_vector(4 downto 0) := "111... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
component ghrd_10as066n2_ocm_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X'; -- reset_req
address : in std_logic_vector(... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- $Id: tbcore_rlink_dcm.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either ... |
entity repro is
end entity;
architecture A of repro is
signal S1 : bit := '0';
signal S2_transport : bit;
signal S2_delayed : bit;
begin
S1 <= '1' after 10 ns, '0' after 20 ns;
S2_transport <= transport S1 after 100 ns;
S2_delayed <= S1'delayed(100 ns);
process (S1) is
begin
... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: fifo_tx_udp.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- =========================================... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_one_hot is
constant assert_name : string := "OVL_O... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add32 is
port(
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
sum : out std_logic_vector(31 downto 0)
);
end add32;
architecture arch of add32 is
signal temp_c : std_logic_vector(32... |
-- author: Madhav P. Desai
library ieee;
use ieee.std_logic_1164.all;
package Utility_Package is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant c_word_length : integer := 32;
co... |
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. Al... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
--Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner log... |
-------------------------------------------------------------------
-- FPGA Audio Project SoC IP
-- V0.1
-- Ultra-Embedded.com
-- Copyright 2011 - 2012
--
-- Email: admin@ultra-embedded.com
--
-- Licen... |
library verilog;
use verilog.vl_types.all;
entity View_output is
port(
clk : in vl_logic;
reset : in vl_logic;
hex0_out : out vl_logic_vector(7 downto 0);
hex1_out : out vl_logic_vector(7 downto 0);
hex2_out : out vl... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev28 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity FSM is
PORT(
clock,reset,nivel, abierto, cerrado: IN std_logic;
piso,boton: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
boton_memoria: out STD_LOGIC_VECTOR (1 DOWNTO 0);
accionador_puerta: out STD_LOGIC;
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity putchar_testbench is
generic (
output_file : string := "putchar.out");
port (
-- inputs:
signal address : in std_logic_vector (1 downto 0);
signal chipselect : in std_logic;
signal ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
port (clk : in std_logic;
reset : in std_logic;
addrA : in std_logic_vector(2 downto 0);
addrB : in std_logic_vector(2 downto 0);
showAB: in std_logi... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
siw : in std_logic_vector (7 downto 0) := "00000000";
led : out std_logic_vector (7 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
led(0) <= (not siw(0));
led(1) <= siw(1) and (not siw(2));
led(2) <= siw(1) or siw(3... |
-- ###################################################################################
--
-- #### #### #####
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ... |
-- NEED RESULT: ARCH00090.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090.P2: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00090.P3: Multi transport transactions occurred on signal asg with s... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_wrapper_zpu is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"20";
g_internal_prg : bo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_wrapper_zpu is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"20";
g_internal_prg : bo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_wrapper_zpu is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"20";
g_internal_prg : bo... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "S... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "S... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "S... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "S... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "S... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "S... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "S... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic ( delay : positive := 1;
signal_type : string := "S... |
-- SIMON 64/128
-- Encryption & decryption test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_simon IS
END tb_simon;
ARCHITECTURE behavior OF tb_simon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT simon
po... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity counter is
port(Clock: in... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- $Id: gcpad_ctrl-c.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $
--
-------------------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iir is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
-- ready : in std_logic;
done : out std_logic;
-- coefficient
i_b_0 : in std_logic_vector(14 downto 0);
i_b_1 : in s... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter4 is
port( clk : in std_logic;
reset : in std_logic;
enable: in std_logic;
count : out std_logic_vector(1 downto 0));
end Counter4;
-- Contador de 0 ... |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the followin... |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the followin... |
------------------------------------------------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the followin... |
architecture test of test2 is
constant foo : bar := "hel"lo";
begin end;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_804 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_804;
architecture augh of cmp_804 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_804 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_804;
architecture augh of cmp_804 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
... |
-- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/opb_v20/opb_v20_v1_10_d/hdl/src/vhdl/Attic/family.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
--------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- END_CHANGELOG
----------... |
-- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/opb_v20/opb_v20_v1_10_d/hdl/src/vhdl/Attic/family.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
--------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- END_CHANGELOG
----------... |
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, ... |
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, ... |
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, ... |
entity textio1 is
end entity;
use std.textio.all;
architecture test of textio1 is
begin
process is
variable l : line;
begin
write(l, string'("hello, world"));
writeline(output, l);
assert l'length = 0;
write(l, string'("one"));
write(l, ' ');
write(l, ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00616: Con... |
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