content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0 Nano Linux project --
-- http... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:57:10)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! ... |
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity tute3 is port(
clk_clk, clk_reset_n: i... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
--
-- All rights reserved.
--
-- Redistribution and use... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_splice_e_s
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:03:31 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_SPLICE -sheet CONN=CONN_SPLICE ../../macro.xls
--
-- !!! Do ... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_16.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : P R E D I C T I O N
--
--
-- The particles are loaded into the local RAM by the Framework... |
package p is
type r1 is record -- OK
x : integer;
y : integer;
end record;
type r2 is record -- Error
x, x : integer;
end record;
type r3;
type r3 is record -- Error
x : r3;
end record;
type r4 is ... |
-- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or info... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : bin2bcd.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rstkey is
port
(
rstkey_port_rst: in std_logic;
rstkey_rst: out std_logic
);
end rstkey;
architecture Behavioral of rstkey is
begin
rstkey_rst <= rstkey_port_rst;
end Behavioral;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural... |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
-- FILE NAME : GPR.vhd
-- MODULE NAME : GPR
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : bogdan.ardelean@yahoo.com
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VER... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myr... |
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myr... |
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myr... |
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myr... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
----------------------------------------------------------------------------------------------------
-- Linear Feedback Shift Register
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
-----------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clkgen is
port(
res: in std_logic;
clk_ext: in std_logic;
res_out: out std_logic;
clk_sdram: out std_logic;
clk_sdram_shift: out std_logic
);
end entity clkgen;
architecture clkgen_arch of clkge... |
--======================================================================
-- reset.vhd :: Debounce and Synchonize Reset
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity XRESET is
p... |
--======================================================================
-- reset.vhd :: Debounce and Synchonize Reset
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity XRESET is
p... |
LIBRARY ieee;
USE ieee.numeric_std.ALL;
PACKAGE range_util IS
FUNCTION range_start(base, size : POSITIVE) return POSITIVE;
END PACKAGE;
PACKAGE BODY range_util IS
FUNCTION range_start(base, size : POSITIVE) return POSITIVE IS
BEGIN
RETURN base + size - 1;
END FUNCTION;
END PACKAGE BOD... |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_clkrst_vp780.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_clkrst_vp780
-- architecture - arch_sip_clkrst_vp780
--
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Vtminus is
port
( clock : in std_logic;
Vtminusone : in std_logic_vector (31 downto 0);
Vref : in std_logic_vector (31 downto 0);
koft : in std_logic_vector (31 downto 0);
Vtminus : out std_logic_vect... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_8_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Auth... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_tb is
end entity;
architecture behavv of counter_tb is
component counter is
port(
clk, res_as, up : in std_logic;
count : out std_logic_vector (3 downto 0)
);
end component;
for counter_0 : counter use entity work.count... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_184 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_184;
architecture augh of add_184 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_184 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_184;
architecture augh of add_184 is
signal carry_inA : std_l... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY VGA IS
-----SYNC PARAMETERS FOR 640x480 VGA DISPLAY (25MHz clock)-----
GENERIC(
Ha: INTEGER:=96; -- Hpulse
Hb: INTEGER:=143; -- Hpulse+Hbp
Hc: INTEGER:=783; -- Hpulse+Hbp+Hactive
Hd: INTEGER:=800; -- Hpulse+Hbp+Hactive+Hfp
Va: ... |
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 06
-- Project :
-------------------------------------------------------------------------------
-- File : wave_gen.vhd
-- Author : Tuomas Huuki
-- Company : TUT
-- Created : 23.11.2015... |
library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHB2APB is
generic(
TPD : real := 0.100000;
T0 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
T2 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1);
T345 : vl_logic_vector(2... |
library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHB2APB is
generic(
TPD : real := 0.100000;
T0 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
T2 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1);
T345 : vl_logic_vector(2... |
library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHB2APB is
generic(
TPD : real := 0.100000;
T0 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
T2 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1);
T345 : vl_logic_vector(2... |
-- NEED RESULT: ARCH00268: 'All' in an attribute spec applies to all entities of the specified class declared in the same declarative region as the attribute spec passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:56:26 05/26/2014
-- Design Name:
-- Module Name: wishbone_ping - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:56:26 05/26/2014
-- Design Name:
-- Module Name: wishbone_ping - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "spi_slave"
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
---------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Testbench for design "spi_slave"
-------------------------------------------------------------------------------
-- Author : cjt@users.sourceforge.net
---------------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.rv_components.all;
use work.utils.all;
--Sets waitrequest on the slave if too many outstanding requests are in flight.
--This is needed for certain interconnect tools that want a bounded number of
--requests in progress.
entit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port (val : out std_logic_vector (63 downto 0));
end entity test2;
architecture beh of test2 is
type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
signal s_register : t_register;
begin
-- the problem is the ... |
library ieee;
use ieee.std_logic_1164.all;
entity reg_5bits is
port (EN, CLK, RST: in std_logic;
D: in std_logic_vector(4 downto 0);
Q: out std_logic_vector(4 downto 0)
);
end reg_5bits;
architecture bhv of reg_5bits is
begin
process(CLK, D)
begin
if RST = '0' then--reset assíncrono do registrador.
Q <... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--! @file dpRamSplxNbe-e.vhd
--
--! @brief Simplex Dual Port Ram without byteenables entity
--
--! @details This is the Simplex DPRAM without byteenables entity.
--! The DPRAM has one write and one read port only.
--
--------------... |
-------------------------------------------------------------------------------------
-- Company: NTUA - BNL
-- Engineer: Paris Moschovakos, Panagiotis Gkountoumis & Christos Bakalis
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos, Panagiotis Gkountoumis & Christos Bakalis
--
-- Thi... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Fifo Using SRL16
---------------------------------------------... |
--
-- This is the top level VHDL file.
--
-- It iobufs for bidirational signals (towards an optional
-- external fast SRAM.
--
-- Pins fit the AVNET Virtex-E Evaluation board
--
-- For other boards, change pin assignments in this file.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:06:28 11/19/2013
-- Design Name:
-- Module Name: My_32bit4x1Mux_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: ... |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_mst_arbiter
-- Architectures: lipif_mst_arbiter_rtl
-- Description:
--
-- Dependencies:
--
-- Revisi... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
entity names2 is
end entity;
architecture test of names2 is
type array1 is array (natural range <>) of integer;
type array2 is array (natural range <>) of array1(1 to 10);
type array3 is array (natural range <>) of array2(1 to 10);
type rec is record
x : array1(1 to 3);
y : integer;
... |
entity tb_test3 is
end tb_test3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test3 is
signal clk : std_logic;
signal wr : std_logic;
signal arst : std_logic;
begin
dut: entity work.test3
port map (clk, wr, arst);
process
procedure pulse is
begin
clk <= '0';
w... |
-- fifo_vw testbench
-- Greg Stitt
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.tb_pkg.all;
entity fifo_vw_tb is
generic(
parallel_io : positive := 4;
data_width : positive := 8;
... |
--RAM for the result vector R
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
use IEEE.Std_logic_unsigned.all;
-----------------------------------------
entity ramR is
port(
clock : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
address : in std_logic_vector ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version :... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:32:20 09/25/2015
-- Design Name:
-- Module Name: /home/kurtisn/mtc/Scrod_mTC_Firmware/src/firmware-general/General/sim/RstSim.vhd
-- Project Name: scrodMtc
-- Target Device:
-- Tool... |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3 Based Computer System designed for the
--Digilent Nexys 2 FPGA Development Board
--
--Module Title: Output_Port_MUX
--Module Description:
-- This module holds four ... |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3 Based Computer System designed for the
--Digilent Nexys 2 FPGA Development Board
--
--Module Title: Output_Port_MUX
--Module Description:
-- This module holds four ... |
entity module is end entity;
architecture arch of module is
function func(a:natural) return natural is
begin
if a=32 then return 2;
elsif a=16 then return 1;
else return 0;
end if;
end function;
constant DATAPATH :natural := 32;
constant LSLICES :natural :=... |
entity module is end entity;
architecture arch of module is
function func(a:natural) return natural is
begin
if a=32 then return 2;
elsif a=16 then return 1;
else return 0;
end if;
end function;
constant DATAPATH :natural := 32;
constant LSLICES :natural :=... |
entity module is end entity;
architecture arch of module is
function func(a:natural) return natural is
begin
if a=32 then return 2;
elsif a=16 then return 1;
else return 0;
end if;
end function;
constant DATAPATH :natural := 32;
constant LSLICES :natural :=... |
entity test is
type t is (foo, bar, 'b', 'q');
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FMul is
port (
clk : in std_logic;
flt_in1 : in std_logic_vector(31 downto 0);
flt_in2 : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end FMul;
architecture dataflow_pip... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:03:50)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's Timer Core. Please refer to the documentation
--! in plasoc_timer.vhd for more information.
--------------------------------------... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
---------------------------------------------------------------------------
-- Copyright 2015 - 2017 Systems Group, ETH Zurich
--
-- This hardware module is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity AddBB is
port (
CLK : in std_logic;
RST : in std_logic;
VALID_IN : in std_logic;
READY_IN : in std... |
ENTITY fullAdder IS
PORT(a : in bit;
b : in bit;
cin : in bit;
s : out bit;
cout : out bit);
BEGIN
END ENTITY fullAdder;
ARCHITECTURE ARCH OF fullAdder IS
SIGNAL axorb : bit;
BEGIN
axorb <= (a xor b);
s <= (axorb xor cin);
cout <= ((axorb and cin) or (a and b));
END ARCHITECTURE ful... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 09:22:45 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-... |
library verilog;
use verilog.vl_types.all;
entity EX_MEM is
port(
clock : in vl_logic;
reset : in vl_logic;
ex_alu_result : in vl_logic_vector(15 downto 0);
mem_write_en : in vl_logic;
mem_write_data : in vl_logic_vector(15 downto... |
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package version is
constant grlib_version : integer := 1401;
-- pragma translate_off
constant grlib_date : string := "20150506";
-- pragma translate_on
constant grlib_build : integer := 4156;
end;
|
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