content stringlengths 1 1.04M ⌀ |
|---|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: DEBUG UNIT
-- Project Name: DEBUG UNIT
-- Target Devices: Spartan-3... |
architecture RTL of ENTITY1 is
function FUNC1 (A : in natural) return natural is
variable temp : natural;
begin
temp := A;
while (temp /= 10) loop
temp := temp + 1;
end loop;
while (temp /= 20) loop
temp := temp + 1;
end loop;
while (temp /= 30) loop
temp := temp +... |
package vunit2 is
type int_ptr is access integer;
type array_of_access is array (natural range <>) of int_ptr;
impure function get_one (idx : natural) return int_ptr;
end package;
package body vunit2 is
shared variable a : array_of_access(1 to 5);
impure function get_one (idx : natural) return i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/16/2016 04:17:04 AM
-- Design Name:
-- Module Name: spi_slave - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY noise_tb IS
END noise_tb;
ARCHITECTURE beha... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll50.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- =============================================... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity compar_fsm_tb is
end entity;
architecture behav of compar_fsm_tb is
component compar_fsm is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector(1 downto 0);
--this is pair of bits of two numbers, a0b0, a1... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Mult_GF_2_M
-- Module Name: Tb_Mult_GF_2_M
-- Project Name: GF_2_M Arithm... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity iqit_node is
generic(
sample_width : integer := 8;
qp_width : integer := 8;
wo_dc_width : integer := 8;
data_width : integer := 64;
addr_width : i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.CONSCTANS.ALL;
entity KITT is
port (
CLK : in std_logic;
RESET : in std_logic;
LEDS : out std_logic_vector (7 downto 0)
);
end KITT;
architecture KITT_BODY of KITT is
signal CNT_OUT : std_logic_vector (OUTPUT_WIDTH - 1 downto 0);
signal UP, TOP, BOTTOM ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Nov 10 10:29:04 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../genwidth.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_k3_k4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'high = 3 report "TEST FAILED T high" severity FAILURE;
report "TEST PASSED T high" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'high = 3 report "TEST FAILED T high" severity FAILURE;
report "TEST PASSED T high" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'high = 3 report "TEST FAILED T high" severity FAILURE;
report "TEST PASSED T high" severity NOTE;
wait;
end process p;
end only;
|
-- $Id: tb_nexys3_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: T... |
-- Alias of enum in another package
--
package pack1 is
type t is (foo, bar, baz);
end package;
use work.pack1.all;
package pack2 is
alias t is work.pack1.t; -- OK
end package;
use work.pack2.all;
package pack3 is
constant c1 : t := foo; -- OK
end package;
use work.pack1.all;
use... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
-- #################################################################################################
-- # << NEO430 - 32-bit Wishbone Bus Interface Adapter >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity hello_world is
end ;
architecture hello_world of hello_world is
begin
stimulus : PROCESS
begin
assert false report "Hello, world!"
severity note ;
wait ;
end PROCESS stimulus ;
end hello_world ;
|
entity hello_world is
end ;
architecture hello_world of hello_world is
begin
stimulus : PROCESS
begin
assert false report "Hello, world!"
severity note ;
wait ;
end PROCESS stimulus ;
end hello_world ;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
nCWP: in STD_LOGIC;
CLK: in STD_LOGIC;
rst: in STD_LOGIC;
icc: out STD_LOGIC_VECTOR(3 downto 0);
CWP: out STD_LOGIC;
C : out STD_LOGIC);
end PSR;
architecture... |
architecture RTL of FIFO is
begin
process
begin
SIMPLE_LABEL : x := z;
a := b;
CONDITIONAL_LABEL : x := z when b = 0 else y;
x := z when b = 0 else y;
SELECTED_LABEL : with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end arc... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_sound2 is
generic(
ADDR_WIDTH: integer := 4
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(5 downto 0)
);
end test_sound2;
architecture content of te... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity GPIO is
generic (BitWidth: integer);
port ( IO_sel: in std_logic;
IO: inout std_logic_vector (BitWidth-1 downto 0);
WrtData: in std_logic_vector (BitWidth-1 downto 0);
RdData: out ... |
--------------------------------------------------------------------------------------------------
-- Multi-channel FIR Filter Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
-----------------------------------... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:42:42 03/05/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet/rx_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Descripti... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:09:11 09/11/2011
-- Design Name:
-- Module Name: deconcat3b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (... |
library ieee;
--library vunit_lib;
--context vunit_lib.vunit_context;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_counter is
generic (runner_cfg : string);
end tb_counter;
architecture arch_tb_counter of tb_counter is
component counter is
port (
key0: in std_logic;
key3: in ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hex2seg is
Port ( clk : in STD_LOGIC; -- Clock of the display (30-100Hz?)
en : in STD_LOGIC;
hex : in STD_LOGIC_VECTOR (3 downto 0); -- HEX number you want to display 0-F
seg : out STD_LOGIC_VECTOR (6 downto 0)); -- 7-Segment o... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patri... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
sgn : signed(7 downto 0) := x"f8";
uns : unsigned(7 downto 0) := x"07";
nat : natural := 15;
int : integer := -3;
mul_int_int : out integer;
mul_uns_uns : out unsigned(15 downto 0);
mul_uns_nat : out unsigned(15 d... |
------------------------------------------------------------------------------
-- ZIPPY global architecture declarations
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Insti... |
entity test is
package a is new b generic map(c => foo'subtype range 0 to 2);
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:58:34 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bi... |
entity tb_fsm_6s is
end tb_fsm_6s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_6s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_6s
port map (
done => done,
d => din,
clk => clk,... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_acf... |
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_acf... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ... |
---------------------------------------------------------------------------------
--RAM------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--4--Afte... |
---------------------------------------------------------------------------------
--RAM------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--4--Afte... |
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert ... |
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert ... |
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert ... |
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert ... |
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert ... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | _... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:51 01/08/2014
-- Design Name:
-- Module Name: contador10bits - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
component ghrd_10as066n2_avlmm_pr_freeze_bridge_1 is
port (
clock : in std_logic := 'X'; -- clk
freeze_conduit_freeze : in std_logic := 'X'; -- freeze
freeze_conduit_illegal_request : out std_l... |
architecture behav of tb is
begin
assert work.pkg2.get2 = 5;
end behav;
|
architecture behav of tb is
begin
assert work.pkg2.get2 = 5;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multi_oc_tb is
end entity;
architecture behav of multi_oc_tb is
component multi_oc
port(
si : in std_logic_vector (3 downto 0);
se : in std_logic_vector (1 downto 0);
so : out std_logic
);
end component;
for multi_oc_0 : multi_oc ... |
library IEEE;
use IEEE.std_logic_1164.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity NOC is
port(
clock : in regNrot;
reset : in std_logic;
clock_rxLocal : in regNrot;
rxLocal : in regNrot;
data_inLocal : in arrayNrot_regflit;
credit_oLocal : out reg... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
-- Entity Declaration
ENTITY pid_controller IS
PORT
(
CLK : IN STD_LOGIC;
en : IN STD_LOGIC;
init : IN STD_LOGIC;
error : IN STD_LOGIC_VECTOR(15 downto 0);
in... |
library verilog;
use verilog.vl_types.all;
entity test is
port(
clk : in vl_logic;
sda : in vl_logic;
\out\ : out vl_logic
);
end test;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
KEYB_ADDR : in std_logic_vector(7 downto 0);
KEYB_DATA : ou... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity state_machine is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
state_input : in STD_LOGIC;
tc : out STD_LOGIC);
end state_machine;
architecture architecture_state_machine of... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementPartialOverrideNopVal IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
clk : IN STD_LOGIC;
e : OUT STD_LOGIC
);
END ENTITY;
ARCHITE... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
generic (
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
generic (
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains con... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- author: Antonio Gutierrez
-- date: 03/10/13
-- description: shift register
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity shift_register is
generic (N: integer := 4;); ---- number of stages
port (
din, clk, rst: in std_logic... |
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