content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
entity MULT is
port (a,b: in std_logic_vector(3 downto 0);
s: out std_logic_vector(3 downto 0));
end MULT;
architecture arch_MULT of MULT is
function deslocar(x: std_logic_vector(3 downto 0))
return std_logic_vector is
variable y: std_logic_vector(3 downto 0);
... |
entity attr9 is
end entity;
architecture test of attr9 is
begin
process is
type my_small_int is range 1 to 10;
begin
assert integer'value("1") = 1;
assert natural'value(" 12_3") = 123;
assert my_small_int'value("5 ") = 5;
assert boolean'value("true") = true;
a... |
entity attr9 is
end entity;
architecture test of attr9 is
begin
process is
type my_small_int is range 1 to 10;
begin
assert integer'value("1") = 1;
assert natural'value(" 12_3") = 123;
assert my_small_int'value("5 ") = 5;
assert boolean'value("true") = true;
a... |
entity attr9 is
end entity;
architecture test of attr9 is
begin
process is
type my_small_int is range 1 to 10;
begin
assert integer'value("1") = 1;
assert natural'value(" 12_3") = 123;
assert my_small_int'value("5 ") = 5;
assert boolean'value("true") = true;
a... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
entity carry_sel_gen is
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end carry_sel_gen;
architecture STRUCTURAL... |
library ieee;
use ieee.std_logic_1164.all;
entity carry_sel_gen is
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end carry_sel_gen;
architecture STRUCTURAL... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: clockbuzzer.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ==============================... |
------------------------------------------------------------------------------------------------------------------------
-- n sychronizer of the async fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the foll... |
------------------------------------------------------------------------------------------------------------------------
-- n sychronizer of the async fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the foll... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all; -- to read files
use work.lz4_pkg.all;
-- Test bench has no ports
entity lz4_tb is
end lz4_tb;
architecture behavior of lz4_tb is
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signa... |
------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rat... |
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
ATTRIBUTE COORDINATE OF comp_1:component is (0.0, 17.5);
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_174 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_174;
architecture augh of cmp_174 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_174 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_174;
architecture augh of cmp_174 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
constant C_WIDTH : integer := 16;
constant C_DEPTH : integer := 512;
constant C_WORD : integer := 1024;
begin
end architecture RTL;
|
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity e000 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DAT... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ece324_latency_tracker is
port( response : in std_logic;
pulse : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
missed : out std_logic_vector(15 downto 0);
latency : out std_logic_vecto... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ece324_latency_tracker is
port( response : in std_logic;
pulse : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
missed : out std_logic_vector(15 downto 0);
latency : out std_logic_vecto... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4_block.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle sim... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic := '1';
r... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Devices
Library IEEE; use IEEE.std_logic_1164.ALL;
Library manoBasic; use manoBasic.defines.all;
package devices is
component Decoder is
generic(N: integer:=4);
port(
... |
configuration conf of repro is
for behav
for c : comp
use entity work.comp;
for behav
for c2 : comp2
use entity work.comp2 (behav);
end for;
end for;
end for;
end for;
end conf;
architecture behav of comp2 is
begin
assert s = '1';
end behav;
|
configuration conf of repro is
for behav
for c : comp
use entity work.comp;
for behav
for c2 : comp2
use entity work.comp2 (behav);
end for;
end for;
end for;
end for;
end conf;
architecture behav of comp2 is
begin
assert s = '1';
end behav;
|
configuration conf of repro is
for behav
for c : comp
use entity work.comp;
for behav
for c2 : comp2
use entity work.comp2 (behav);
end for;
end for;
end for;
end for;
end conf;
architecture behav of comp2 is
begin
assert s = '1';
end behav;
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo VGA_Adapter.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- ************************************... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- $Id: mult_gen_pkg_v11_2.vhd,v 1.5 2011/03/17 13:01:31 gordono Exp $
--------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected und... |
--!
--! @file: my_package.vhd
--! @brief: example9_2
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package my_package is
function order_and_fill(input : uns... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity LIFO_T is
end LIFO_T;
architecture Beh of LIFO_T is
component LIFO is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in s... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segm... |
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eit... |
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eit... |
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eit... |
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; eit... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Codeword_Generator_n_m_v2
-- Module Name: Codeword_Generator_n_m_v2
-- Project... |
library verilog;
use verilog.vl_types.all;
entity DiceGame_controller_vlg_check_tst is
port(
Lose : in vl_logic;
Roll : in vl_logic;
Win : in vl_logic;
sampler_rx : in vl_logic
);
end DiceGame_controller_vlg_check_tst;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maxPool_process is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
... |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- ... |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- ... |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- ... |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- ... |
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for ... |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_mm_clock_crossing_bridge is
generic(
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH: integer := 1;
COMMAND_FIFO_DEPTH: integer := 4;
RES... |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_mm_clock_crossing_bridge is
generic(
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH: integer := 1;
COMMAND_FIFO_DEPTH: integer := 4;
RES... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is... |
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
-- Copyright (c) 1990 UCI CADLAB, Dept. of ICS
-- Author : Sanjiv Naraya... |
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
-- Copyright (c) 1990 UCI CADLAB, Dept. of ICS
-- Author : Sanjiv Naraya... |
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
-- Copyright (c) 1990 UCI CADLAB, Dept. of ICS
-- Author : Sanjiv Naraya... |
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
-- Copyright (c) 1990 UCI CADLAB, Dept. of ICS
-- Author : Sanjiv Naraya... |
-- register file circuit
-- contains 31 32-bit general-purpose registers, plus 1 register that is always hardcoded to 0
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity register_file is
port (
-- read addresses
a_addr : in std_logic_... |
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in in... |
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in in... |
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in in... |
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in in... |
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in in... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pl_console is
port(
RESET : In std_logic;
user_clk : In std_logic;
user_wren : In std_logic;
user_rden : In std_logic;
UART_CTL : Out std_logic;
UART_BUSY : I... |
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- ... |
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- ... |
-- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: A.vhd
-- Megafunction Name(s):
-- altaccumulate
--
-- Simulation Library Files(s):
-- altera_mf
-- ================... |
---------------------------------------------------------------------------------------------------
-- PICO 1802 Tiny BASIC - 4K x 8 RAM module
---------------------------------------------------------------------------------------------------
-- Generic synchronous RAM entity
-- When not selected, the outputs are dr... |
library foo;
entity test is end;
|
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