content stringlengths 1 1.04M ⌀ |
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: Computes XOR masks fo... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: Computes XOR masks fo... |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
USE IEEE.std_logic_signed.all; --math operations for signed std_logic
ENTITY counter_up_down_4bit IS
PORT(up, c... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:39:36 11/01/2015
-- Design Name:
-- Module Name: clock_divider_V2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
-- *******************************************************************
-- Copyright 2008 Ray Salemi
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dual_port_ram is
generic (
DATA_WIDTH : natural := 1;
ADDRESS_WIDTH : natural := 18
);
port (
clock: in std_logic;
write_enable : in std_logic;
address_A : in std_logic_vector(ADDRESS_WIDTH-1... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolAdder is
Port ( a : ... |
architecture RTL of FIFO is
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: dsDMA_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.30 - DMA engine divided into 2 modules:... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/16 00:32:43 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: global_logic_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Guls... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/16 00:32:43 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: global_logic_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Guls... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory_matrix is
generic(ROWS: integer := 350; COLUMNS: integer := 350; CLK_DELAY_COUNT: integer := 9);
port(
x_write: in std_logic_vector(9 downto 0) := (others => '0');
y_write: in std_logic_vector(9 downto 0) := (others ... |
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
use work.amba.all;
package ddmlib is
component ddm
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
--This should pass
context c1 is
end context c1;
--These should fail
context c1 is
end context c1;
context
c1
is
end
context -- Some comment
c1;
-- Comment
context c1 is
end -- Some comment
context c1; -- Some other comment
-- other comments
context c1 -- Yet another commet
-- Some comment
is
end
-- Co... |
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(... |
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(... |
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library verilog;
use verilog.vl_types.all;
entity Multiple_Cycles_CPU is
port(
Clk : in vl_logic;
PC_in : out vl_logic_vector(31 downto 0);
PC_out : out vl_logic_vector(31 downto 0);
Mem_addr_in : out vl_logic_vector(31 downto 0);
... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
-- Date : Sun Mar 26 22:18:09 2017
-- Host : andrewandrepowell2-desktop running 6... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(7 downto 0);
stdin_data : in std_logic_vector(7 do... |
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(7 downto 0);
stdin_data : in std_logic_vector(7 do... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- this unit introduces 1 cycle delay between d and q
entity scrambler is
generic (
width : positive := 8
);
port (
clk : in std_logic;
clk_en : in std_logic;
rst : in std_logic;
sync : in std_logic;
d : in std_logic_vector(width-1... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.counter_div_trig;
use work.dbgram;
entity dbgsnap is
port
( clk : in std_logic
; tr : in std_logic
;dbg_in : in std_logic_vector(15 downto 0)
);
end entity dbgsnap;
archi... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.counter_div_trig;
use work.dbgram;
entity dbgsnap is
port
( clk : in std_logic
; tr : in std_logic
;dbg_in : in std_logic_vector(15 downto 0)
);
end entity dbgsnap;
archi... |
package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
|
package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
|
package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
|
package issue247 is
subtype natural_down is natural range 10 downto 0;
type array_t is array (natural_down range <>) of boolean;
constant c : array_t(9 downto 5); -- ok
end package issue247;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
--!
--! \file mem_plb46.vhd
--!
--! Memory bus interface for the 64-bit PLB v34.
--!
--! \author Enno Luebbers <enno.luebbers@upb.de>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (ht... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00125
--
-- AUTHOR:
--
-- G. Tomi... |
-- test2 - clock divider controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <xdsopl@googlemail.com>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without an... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:29 11/26/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Subsystems/FlashProgrammer/FlashProgrammer_TB.vhd
-- Project Name: FlashProgrammer
-- Target... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific co... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific co... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific co... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Project specific co... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
-- Twofish_testbenches_secondary_circuits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) an... |
entity FIFO is
generic (
G_GEN1 : INTEGER;
G_GEN2 : STD_LOGIC;
G_GENA : t_user2;
G_GEN3 : STD_LOGIC_VECTOR(3 downto 0);
G_GEN4 : SIGNED(15 downto 0);
G_GEN5 : UNSIGNED(7 downto 0);
G_GEN6 : STD_ULOGIC;
G_GEN7 : t_user1
);
end entity FIFO;
-- Violation below
entity FIFO is
ge... |
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal clock_en : std_logic := '0'; -- for counters and stuff
signal reset ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 10:54:36 2017
-- Host : PC4719 running 64-bit Service Pa... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg.all;
entity foo is
port (
bus_in : in bus_t(data(7 downto 0));
bus_out : out bus_t(data(7 downto 0))
);
end foo;
architecture foo of foo is
begin
bus_out <= bus_in;
end foo;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.40... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Fredrik Ringhage, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 200... |
entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
p1: process is
variable x : integer := 0;
variable y : my_int;
variable z : integer := 1;
begin
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
assert ... |
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.synt... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
---------------------------------------------------------------... |
-- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, t... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 8;
type lut_type is arra... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 8;
type lut_type is arra... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisl... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
use work.rgbctrl_wb8_init.all;
entity rgbctrl_wb8 is
generic(
CLOCKFREQ: integer := (50 * 1000 * 1000) -- frequency (MHz)
);
-- signal naming according to Wishbone B4 spec
port(
CLK_I: in std_logic;
ST... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
term... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the L... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the L... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the L... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity imem is
port (a: in std_logic_vector(5 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture imem_arq of imem is
type mem is array (0 to 63) of std_logic_vector(31 downto 0);
begin
process(a)
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity imem is
port (a: in std_logic_vector(5 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture imem_arq of imem is
type mem is array (0 to 63) of std_logic_vector(31 downto 0);
begin
process(a)
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm4 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm4;
architecture BEHAVIORAL of dcm... |
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