content stringlengths 1 1.04M ⌀ |
|---|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library verilog;
use verilog.vl_types.all;
entity reservation_alu0_entry is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE_VALID : in vl_logic;
iREGIST_VALID : in vl_logic;
iREGIST_CMD : in vl_logic_vector(4 downto 0);
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
use work.sprites_pkg.all;
use work.graphics_types_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.npc_pkg.all;
package resource_data_pkg is
-- Here we define all the sprites used in the game
constant GAME_SPRITES: sprite_init_array_type := (
(SP... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ac_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:39:03 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig... |
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad.vhd,v 1.2 2004-10-05 18:22:40 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised form... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY TOP IS
GENERIC (
RESULT_WIDTH : integer := 9;
NODES : integer := 15;
ADDR_SHIFT : integer := 4);
PORT (
--//////////// CLOCK //////////
GCLKIN : IN std_logic;
GCLKOUT_FPGA : OUT std_logic;
OSC_50_BANK2 : IN std_logic;
OSC_50_BANK3 : IN ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:33 07/06/2016
-- Design Name:
-- Module Name: kb_rf_fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:33 07/06/2016
-- Design Name:
-- Module Name: kb_rf_fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity GAME is
port (
CLK : in std_logic;
RST : in std_logic;
BLANKING : in std_logic;
KEYCODE : in std_logic_vector(7 downto 0);
CODE_ENABLE : in std_logic;
MAP_X, MAP_Y : in std_logic... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ddrv4
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: dd... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------------
-- FILE NAME : fmc150_spi_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc150_spi_ctrl
-- architecture - fmc150_spi_ctrl_syn
--
-- LANGU... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Thu Jun 01 02:21:04 2017
--Host : GILAMONSTER running 64-bit major release ... |
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : UART
-- Date : 07/25/2016
--
-- Description :
--
-- -----------------------------------------------------------... |
architecture rtl of fifo is
variable sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
0)... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NEED RESULT: ARCH00404.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00404: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00404: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00404: One i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
architecture a of one is
signal x : integer;
signal y, z : integer := 7;
begin
end architecture;
architecture b of one is
begin
end b;
architecture c of one is
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_out is
generic (
width : positive
);
port (
par_in : in std_logic_vector(width - 1 downto 0);
-- when load is high, par_in is loaded into the shift register
-- if ce is also high, ser_out will immediately output the MSB
load : in std_lo... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_out is
generic (
width : positive
);
port (
par_in : in std_logic_vector(width - 1 downto 0);
-- when load is high, par_in is loaded into the shift register
-- if ce is also high, ser_out will immediately output the MSB
load : in std_lo... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library IEEE;
use IEEE.std_logic_1164.all;
entity pfb_core_snbxfft32 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
en_in: in std_logic;
pol0_in: in std_logic_vector(35 downto 0);
pol1_in: in std_logic_vector(35 downto 0);
sync_in: in std_logic;
en_out: out std_logic;
pol0_... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick ... |
entity tb_dpram2r is
end tb_dpram2r;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dpram2r is
signal raddr : natural range 0 to 3;
signal rnib : natural range 0 to 1;
signal rdat : std_logic_vector (3 downto 0);
signal waddr : natural range 0 to 3;
signal wdat : std_logic_vector(7 down... |
-- $Id: tb_tst_rlink_cuff_ic_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_cuff_ic_n2
-- Descriptio... |
-------------------------------------------------------------------------------
--
-- The Program Memory control unit.
-- All operations related to the Program Memory are managed here.
--
-- $Id: pmem_ctrl.vhd,v 1.5 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- Al... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:45:03 07/06/2016
-- Design Name:
-- Module Name: segment_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Rev... |
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.math_pkg.all;
p... |
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.math_pkg.all;
p... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait f... |
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait f... |
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait f... |
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait f... |
entity proc7 is
end entity;
architecture test of proc7 is
procedure foo(signal b : in bit_vector; i : in integer) is
variable c : bit_vector(b'range);
begin
assert c(c'left) = '0';
--wait for 1 ns;
for i in b'range loop
c(i) := b(i);
end loop;
wait f... |
------------------------------------------------------------------------------
-- Schedule controller; implemented as a Mealy FSM
--
-- Project :
-- File : $URL: svn+ssh://plessl@yosemite.ethz.ch/home/plessl/SVN/simzippy/trunk/vhdl/schedulectrl.vhd $
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- ... |
use std.textio.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
type binary_file is file of character;
file fptr_text : text;
file fptr_binary : binary_file;
begin
file_open(fptr_text, "file.txt", write_mode);
write(fptr_text, string'("a"));
write(fptr_text, str... |
use std.textio.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
type binary_file is file of character;
file fptr_text : text;
file fptr_binary : binary_file;
begin
file_open(fptr_text, "file.txt", write_mode);
write(fptr_text, string'("a"));
write(fptr_text, str... |
use std.textio.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
type binary_file is file of character;
file fptr_text : text;
file fptr_binary : binary_file;
begin
file_open(fptr_text, "file.txt", write_mode);
write(fptr_text, string'("a"));
write(fptr_text, str... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue3 is
port (foo : in integer;
foobar : out signed (3 downto 0));
end issue3;
architecture beh of issue3 is
subtype n_int is integer range -1 to 1;
begin
with n_int'(foo) select
foobar <= signed'("0001") whe... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
... |
-------------------------------------------------------------------------------
--
-- Title : ID_EXE_Register
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block3.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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