content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
package FIFO_PKG is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic);
-- Violations below this line
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity tb_test2 is
end tb_test2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test2 is
signal clk : std_logic;
signal wr : std_logic;
signal rst : std_logic;
begin
dut: entity work.test2
port map (clk, wr, rst);
process
procedure pulse is
begin
clk <= '0';
wai... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/11/2014
--! Module Name: CRresetManager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/11/2014
--! Module Name: CRresetManager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/11/2014
--! Module Name: CRresetManager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- ... |
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permissio... |
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permissio... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity eth is
generic(
MII_WIDTH : natural := 8;
RAM_RD_CYCLE : natural := 2;
RAM_WR_CYCLE : natural := 2;
RAM_RD_DELAY : natural := 1 ; --1... |
---------------------------------------------------------------------------------------------
-- VIDEO DELAY - Hex to 7 Segment
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
---------------------------------------------------------------------------------------... |
architecture rtl of fifo is
begin
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(
port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow);
connect_ports(port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow);
... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 17:41:30
-- Nombre del módulo: clk_rom - Behavioral
-- Comentarios adicionales:
-- Este divisor de frecuencia toma su... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 17:41:30
-- Nombre del módulo: clk_rom - Behavioral
-- Comentarios adicionales:
-- Este divisor de frecuencia toma su... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
library verilog;
use verilog.vl_types.all;
entity LOG_Table is
port(
address : in vl_logic_vector(12 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(7 downto 0)
);
end LOG_Table;
|
library verilog;
use verilog.vl_types.all;
entity LOG_Table is
port(
address : in vl_logic_vector(12 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(7 downto 0)
);
end LOG_Table;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
--
-- PhaseGenerator.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseGenerator is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
... |
--
-- PhaseGenerator.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseGenerator is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
... |
entity t87 is
end;
architecture behav of t87 is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end beha... |
entity t87 is
end;
architecture behav of t87 is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end beha... |
library IEEE;
use IEEE.std_logic_1164.all;
entity SEMI_MIPS is
port (
clk : in std_logic;
external_reset : in std_logic;
we : out std_logic;
re : out std_logic;
address : out std_logic_vector(7 downto 0);
memory_in : in std_logic_vector(15 downto 0);
memory_out : o... |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.03.2016 12:10:07
-- Design Name:
-- Module Name: VRAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Rev... |
-- NEED RESULT: ARCH00181.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS failed
-- NEED RESULT: ARCH00181.P3: Multi iner... |
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 06
-- Project :
-------------------------------------------------------------------------------
-- File : wave_gen_bonus.vhd
-- Author : Tuomas Huuki
-- Company : TUT
-- Created : 23.1... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BlockRamScore is
Port (
Clock : in STD_LOGIC;
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (4 downto 0);
Column : in STD_LOGIC_VECTOR (4 downto 0);
DataOutPixel : out ... |
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY boothmul_pipelined IS
generic (N : integer := 8);
PORT(
Clock : in std_logic;
Reset : in std_logic;
sign : in std_logic;
A : IN std_logic_vector (N-1 downto 0);
B : IN std_logic_vector (N-1 downto 0);
P : OUT st... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.iface.all;
use work.amba.all;
-- Version with stereo and 16 bits on each channel
-- Record function disabled
-- 20.02.02 LA
entity ddm is
port (
rst : in std_logic;
clk : in clk_type;... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 26-04-2016
-- Module Name: p12.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity blockPHfinding is
port (clk_i : in std_logic;
reset_i : in std_logic;
framing_i : in std_logic;
block_o : out std_logic);
end blockPHfinding;
archit... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity blockPHfinding is
port (clk_i : in std_logic;
reset_i : in std_logic;
framing_i : in std_logic;
block_o : out std_logic);
end blockPHfinding;
archit... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Core_tb is
end Core_tb;
architecture behavior of Core_tb is
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
LFXT_Clk_i : in std_logic;
Cpu_En_i : in ... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use ... |
entity e is end entity;
architecture a of e is
signal x : bit_vector(1 to 3);
signal y : bit;
begin
-- Test corner case in lexer
-- http://www.eda-stds.org/isac/IRs-VHDL-93/IR1045.txt
x <= bit_vector'('1','0','1');
y <= bit'('1');
end architecture;
|
-- VHDL Entity my_project1_lib.fifo_test.symbol
--
-- Created:
-- by - mg147.bin (srge00.ecn.purdue.edu)
-- at - 18:18:44 04/10/12
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY fifo_test IS
g... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end pll_125;
architecture syn of pll_125 is
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cyc... |
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end pll_125;
architecture syn of pll_125 is
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cyc... |
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end pll_125;
architecture syn of pll_125 is
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cyc... |
--! @file reset_sequencer_tb.vhd
--! @brief Test Bench for Reset Sequencer
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-09-30
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance ... |
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity testbench is
--generic declarations
end entity testbench;
--------------------------------------
architecture circuit of testbench is
signal clk: std_logic := '0';
signal rst: std_logic := '0';
begin
-- generation ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity vga_node is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth ... |
entity bounds24 is
end entity;
architecture test of bounds24 is
function func (n : natural) return bit is
variable r : bit_vector(1 to 3) := (1 to n => '1');
begin
return r(1) xor r(2) xor r(3);
end function;
signal n : integer := 3;
begin
main: process is
begin
asser... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- The processor --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.processor_functions.all;
ENTITY processor IS
PORT (clk, nrst, WAKE_signal: IN std_logic;
-- Switches
switches: IN std_logic_vector(17 downto 0);
-- Leds vermelhos
red_leds: OUT std_logic_vector(17 downto 0);
-- Leds ve... |
-- file: Interface_Master_BD_clk_wiz_0_0_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAI... |
-- EULER module for Betty SDR
-- implements a rectangle to polar conversion
-- file: euler.vhd
-- author: Sebastian Weiss DL3YC <dl3yc@darc.de>
-- version: 1.0
-- depends on: vcordic.vhd
--
-- change log:
-- - release implementation 1.0
-- - buggy phase in vcordic
--
library IEEE;
use IEEE.std_logic_1164.al... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
package tdc_sample_prep_pkg is
constant TDC_EVENT_POS_BITS: natural := 2;
type tdc_event_t is
record
valid: std_logic;
pos: unsigned(1 downto 0);
end record;
function to_std_logic... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Single Port Block RAM needed to load either the boot
--! loader, jumper loader, or the main application.
------------------------------------------------... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Single Port Block RAM needed to load either the boot
--! loader, jumper loader, or the main application.
------------------------------------------------... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Single Port Block RAM needed to load either the boot
--! loader, jumper loader, or the main application.
------------------------------------------------... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 14:51:03 2017
-- Host : Juice-Laptop running 64-bit majo... |
-- ----------------------------------------------------------------------------
-- Entity for implementation of SINDHU PRASANA NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
--... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- file: my_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a l... |
-- NEED RESULT: ARCH00147.P1: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P2: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00147.P3: Multi inertial transactions occurred on signal asg with slice name... |
--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your... |
--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your... |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 26-May-11
-- Project : RT Video Lab 1: Exercise 3
-- Description: Components for 2D 5x5-FIR filter
-----------------------------------------------------------... |
--!
--! @file: exercise5_13.vhd
--! @brief: barrel shifter with std_logic_vector
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity barrel_shifter is
generic (... |
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_router_003 is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpa... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--8线-3线优先编码器。A的编码等级最低
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ENCODER IS
PORT(A,B,C,D,E,F,G,H:IN STD_LOGIC;
Y0,Y1,Y2:OUT STD_LOGIC);
END ENTITY ENCODER;
--使用条件赋值语句
ARCHITECTURE ART1 OF ENCODER IS
SIGNAL SY:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--优先级在此处体现，哈哈
SY(2 DOWNTO 0)<="... |
-- Transmitter, part of UART.
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
en: in... |
library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity rslatch_tb is
end rslatch_tb;
architecture TB_ARCHITECTURE of rslatch_tb is
-- Component declaration of the tested unit
component rs_latch_param
port(
S : in STD_LOGIC;
R : in STD_LOGIC;
Q : out STD_L... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:40:27 04/09/2017
-- Design Name:
-- Module Name: anode_fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: ... |
-- Module Name: InputGate - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity test is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic );
end test;
architecture Behavioral of test is
begin
c <= a and b;
end Behavioral;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:51:15 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
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