content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_ALIGN_BLOCK
--! Project Name: FELIX
--------------------------------------------------------------------------------... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_ALIGN_BLOCK
--! Project Name: FELIX
--------------------------------------------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
a <= b;
end block;
BLOCK_LABEL : block is
begin
a <= b;
end block;
end architecture RTL;
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is d... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Title : top level module for 16z091-01 design
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : ip_16z091_01_top
-- Author : Susanne Reinfelder
-- Ema... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block9.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdderSub is
Port ( C_in : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
Add_Sub: in STD_LOGIC;
C_out : out STD_LOGIC;
Sum : out STD_LOGIC);
end FullAdderSub;
architecture Behavioral of FullAdderSub is
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdderSub is
Port ( C_in : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
Add_Sub: in STD_LOGIC;
C_out : out STD_LOGIC;
Sum : out STD_LOGIC);
end FullAdderSub;
architecture Behavioral of FullAdderSub is
... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2014, Ajit Mathew <ajitmathew04@gmail.com>
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following co... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2014, Ajit Mathew <ajitmathew04@gmail.com>
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following co... |
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2014, Ajit Mathew <ajitmathew04@gmail.com>
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following co... |
library verilog;
use verilog.vl_types.all;
entity stx_n_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
modulus : in vl_logic_vector(31 downto 0);
time_delay : in vl_logic_vector(31 do... |
-------------------------------------------------------------------------------------
-- FILE NAME : lfsr_external.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
---------------------------------------------... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 24-04-2016
-- Module Name: main_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.a... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 24-04-2016
-- Module Name: main_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.a... |
--------------------------------------------
-- 通用偶数分频器
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity gen_div is
-- 分频因子, 分频为2*div_param, 默认2分频
generic(div_param : integer := 1);
port(
clk_in : in... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tb is
end uart_tb;
architecture behav of uart_tb is
component uart
port
(
clk : in std_logic;
rst : in std_logic;
d : in std_logic_vector(7 downto 0);
we : in std_logic;
full : out std_logic;
tx : out std_logic
... |
--------------------------------------------------------------------------------
--
-- Title : rtl_game_int.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : M... |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==================================... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture RTL of ENT is
begin
end rtl;
architecture RTL of ENT is
begin
end rtl;
architecture RTL of ENT is
begin
end rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--RegisterBasic
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity registerBa... |
---------------------------------------------------------------------------------------------------
--
-- Title : Two End Point Example for Ring Control Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
--------------------------------------------------------------------... |
---------------------------------------------------------------------------------------------------
--
-- Title : Two End Point Example for Ring Control Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
--------------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_6502_decode.all;
entity implied is
port (
inst : in std_logic_vector(7 downto 0);
c_in : in std_logic;
i_in : in std_logic;
n_in : in std_logic;
z_in ... |
entity repro is
end repro;
architecture behav of repro is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (0 ns);
end process;
process
begin
s <= 3;
wait for 1 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wa... |
entity repro is
end repro;
architecture behav of repro is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (0 ns);
end process;
process
begin
s <= 3;
wait for 1 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wa... |
entity repro is
end repro;
architecture behav of repro is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (0 ns);
end process;
process
begin
s <= 3;
wait for 1 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wa... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eAnd is
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end;
-- Arquitectura
architecture aAnd of eAnd is
beg... |
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eAnd is
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end;
-- Arquitectura
architecture aAnd of eAnd is
beg... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
-- Copyright (c) 2016 David Banks
-- Copyright (c) 2019 Google LLC
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numer... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:53:13 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package array32 is
subtype reg is std_logic_vector(31 downto 0); -- a byte
type reg_array is array (31 downto 0) of reg; -- array of bytes
end array32;
package body array32 is
end array32; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture rtl of fifo is
begin
a <= (others => (others => '0'));
process begin
a <= (others => (others => '0'));
end process;
end architecture;
architecture rtl of fifo is
begin
a <= (others=> (others => '0'));
process begin
a <= (others => (others=> '0'));
end proce... |
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_propos... |
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated docume... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/14/2017 03:53:11 PM
-- Design Name:
-- Module Name: filter_kernel - Combinational
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- R... |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX1
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This fil... |
-- -------------------------------------------------------------
--
-- Entity Declaration for INST_AB_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MI... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-----------------------------------------------------------------------------
-- Testbench for rxsync
--
-- Authors:
-- -- Kristoffer E. Koch
-----------------------------------------------------------------------------
-- Copyright 2008 Authors
--
-- This file is part of hwpulse.
--
-- hwpulse is... |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! Wrapper Plasma-SoC Top Module.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.a... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick ... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
entity proc3 is
end entity;
architecture test of proc3 is
procedure p1(x : out integer) is
begin
wait for 10 ns;
x := 1;
wait for 5 ns;
end procedure;
begin
p2: process is
variable x : integer;
begin
p1(x);
wait;
end process;
end architecture;... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter_Down4 is
port( clk : in std_logic;
count : out std_logic_vector(3 downto 0));
end counter_Down4;
architecture Behavioral of Counter_Down4 is
signal s_count : unsigned (3 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)... |
component soc_design is
port (
dram_addr : out std_logic_vector(12 downto 0); -- addr
dram_ba : out std_logic_vector(1 downto 0); -- ba
dram_cas_n : out std_logic; -- cas_n
dram_cke : out std_logic; ... |
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