content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' generate
end generate;
-- Violations below
IF_LABEL : if a = '1' generate
end generate;
end;
|
-- $Id: serport_uart_rx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- The uart expects CLKDIV+1 wide input bit symbols.
-- This implementation counts the number of 1's in the first CLKDIV clock
-- cycles, a... |
library ieee;
use ieee.std_logic_1164.all;
entity map1 is
port
(
F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15: out std_logic_vector(31 downto 0)
);
end map1;
architecture map1_struct of map1 is
begin
F0 <= "00000000001000000000110000000000";
F1 <= "00000000000000011000110000011000";
... |
----------------------------------------------------------------------------------
-- Engineer: Noxet && Niklas
--
-- Create Date: 14:56:58 09/22/2014
-- Module Name: controller - Behavioral
-- Description:
-- The Brutus system controller
----------------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Engineer: Noxet && Niklas
--
-- Create Date: 14:56:58 09/22/2014
-- Module Name: controller - Behavioral
-- Description:
-- The Brutus system controller
----------------------------------------------------------------------... |
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Generate reset according to Microsemi application note AC380.
-- The reset is activated asynchronously and deactivated synchronously.
-- The asynchro... |
-- NEED RESULT: ARCH00429: Character literals passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- niosii_rst_controller_002.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : ... |
-- niosii_rst_controller_002.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : ... |
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY PROGRAM_COUNTER IS
PORT (
EnablePC : IN std_logic;
input: IN std_logic_vector (7 DOWNTO 0);
clk : IN std_logic;
output: OUT std_logic_vector (7 DOWNTO 0) := "00000000"
);
END PROGRAM_COUNTER;
ARCHITECTURE PROGRAM_COUNTER_ARCH... |
-- Z:\USERS\YOU\STATECADFSM\CELLRAM.vhd
-- VHDL code created by Xilinx's StateCAD 10.1
-- Fri Jun 06 15:22:06 2014
-- This VHDL code (for use with Xilinx XST) was generated using:
-- one-hot state assignment with boolean code format.
-- Minimization is enabled, implied else is disabled,
-- and outputs... |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
--Date : Tue Nov 17 20:19:34 2015
--Host : ALI-WORKSTATION running 64-bit major rele... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------
-- Program-Memory
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use std.textio.all;
-- Important NOTE:
-- ---------------
--
-- The ROM_BITS generic controls the size of the internal
-... |
------------------------------------------------------
-- Program-Memory
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use std.textio.all;
-- Important NOTE:
-- ---------------
--
-- The ROM_BITS generic controls the size of the internal
-... |
------------------------------------------------------
-- Program-Memory
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use std.textio.all;
-- Important NOTE:
-- ---------------
--
-- The ROM_BITS generic controls the size of the internal
-... |
-------------------------------------------------------------------------------
-- Copyright (C) 2021 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity implied is
port (
inst : in std_logic_vector(7 downto 0);
enable : in std_logic;
c_in : in std_logic;
i_in : in std_logic;
n_in : in std_logic... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity implied is
port (
inst : in std_logic_vector(7 downto 0);
enable : in std_logic;
c_in : in std_logic;
i_in : in std_logic;
n_in : in std_logic... |
-- ======================================================================
-- DES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute... |
use std.textio.all;
package issue284_pkg is
procedure check_it;
end package issue284_pkg;
package body issue284_pkg is
file my_file : text;
procedure check_it is
variable contents : line;
begin
file_open(my_file, "test.txt", WRITE_MODE);
write(contents, string'("hello"));
writeline(my_file, ... |
use std.textio.all;
package issue284_pkg is
procedure check_it;
end package issue284_pkg;
package body issue284_pkg is
file my_file : text;
procedure check_it is
variable contents : line;
begin
file_open(my_file, "test.txt", WRITE_MODE);
write(contents, string'("hello"));
writeline(my_file, ... |
use std.textio.all;
package issue284_pkg is
procedure check_it;
end package issue284_pkg;
package body issue284_pkg is
file my_file : text;
procedure check_it is
variable contents : line;
begin
file_open(my_file, "test.txt", WRITE_MODE);
write(contents, string'("hello"));
writeline(my_file, ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
... |
-- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
... |
-- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
... |
-- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
... |
-- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
... |
-- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
... |
-- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
... |
entity record2 is
end entity;
architecture test of record2 is
type r1 is record
x, y : integer;
end record;
type r1_ptr is access r1;
begin
p1: process is
variable r : r1;
variable x : integer;
begin
r := (x, x);
wait;
end process;
p2: process is... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_202 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end cmp_202;
architecture augh of cmp_202 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_202 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end cmp_202;
architecture augh of cmp_202 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- lcd_tb.vhd
--
-- Created on: 21 May 2017
-- Author: Fabian Meyer
--
-- Testbench for LCD component.
library ieee;
use ieee.std_logic_1164.all;
entity lcd_tb is
end lcd_tb;
architecture behavior of lcd_tb is
-- Component Declaration for the Unit Under Test (UUT)
component lcd
generic(RSTDEF: std_lo... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.arith.all;
library ims;
use ims.coprocessor.all;
entity RESOURCE_CUSTOM_7 is
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end;
architecture... |
library verilog;
use verilog.vl_types.all;
entity MSS_APB is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSPADDR ... |
library verilog;
use verilog.vl_types.all;
entity MSS_APB is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSPADDR ... |
library verilog;
use verilog.vl_types.all;
entity MSS_APB is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSPADDR ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 14:49:08 2016
--Host : DESKTOP-I329812 running 64-bit major re... |
entity tb_test is
generic(
ROW_BITS : integer := 4;
WIDTH : integer := 64
);
end tb_test;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test is
signal clk : std_logic;
signal rd_addr : std_logic_vector(ROW_BITS - 1 downto 0);
signal rd_data : std_logic_vector(WIDTH - 1... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
package cnn_types is
constant PIXEL_CONST : integer := 8;
type pixel_array is array ( integer range <> ) of std_logic_vector (PIXEL_CONST-1 downto 0);
end cnn_types;
|
--! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Xilinx
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity p4mem1k8 is
port(
clk : in std_logic;
clk2x : in std_logic;
dia : in t_data;
addra : in st... |
-- This is one neuron
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity neuron is
generic (
-- Parameters for the neurons
WDATA : natural := 32;
WWEIGHT : natural := 16;
WACCU : natural := 32;
-- Parameters for the frame size
FSIZE : natural := 784;
WADDR : natural :=... |
architecture rtl of fifo is
alias DESIGNATOR is name;
alias DESIGNATOR is name;
begin
end architecture rtl;
|
entity sub is
port ( x : buffer natural );
end entity;
architecture test of sub is
begin
test: process is
begin
x <= 1;
wait for 1 ns;
x <= 2;
wait for 1 ns;
assert x = 2;
wait;
end process;
end architecture;
entity buffer1 is
end entity;
architecture... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_in_8b_sync is
generic (
FIFO_DEPTH : natural range 8 to 64 := 16;
BUS_WIDTH : natural range 16 to... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pipeline_Polynomial_Calc_v2
-- Module Name: Pipeline_Polynomial_Calc_v2
-- Proj... |
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
----... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY timer_tb IS
END timer_tb;
ARCHITECTURE behavior OF timer_tb IS
-- Component Declaration for the Unit Under... |
--------------------------------------------------------------------------------
-- Mycron® DDR SDRAM - MT46V32M16 - 8 Meg x 16 x 4 banks --
--------------------------------------------------------------------------------
-- Copyright (C)2012 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> ... |
-------------------------------------------------------------------------------
-- sync_cntl.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
--
-- Copyright (c) 2008-2015 Sytse van Slooten
--
-- Permission is hereby granted to any person obtaining a copy of these VHDL source files and
-- other language source files and associated documentation files ("the materials") to use
-- these materials solely for personal, non-commercial purposes.
-- You are also gr... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.