content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:48:29 11/18/2013
-- Design Name:
-- Module Name: My_16bitOr_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY tb_FramerTop IS
--port (
--);
END;
ARCHITECTURE structure of tb_FramerTop IS
Signal bits: integer:= 32;
Signal clk : STD_LOGIC;
Signal resetb : STD_LOGIC;
Signal sin : STD_LOGIC;
Signal sout : STD_ULOGIC;
Signal clk_div_8 : ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY rs IS
PORT
(
r : IN std_logic;
s : IN std_logic;
q : OUT std_logic;
qi : OUT std_logic
);
END rs;
ARCHITECTURE behavior OF rs IS
SIGNAL a, b : std_logic;
BEGIN
q <= a;
qi <= b;
a <= s nand b;
b <= r nand a;
END behavior;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- ... |
entity impure_ex2 is
port (
clk : in bit;
arg : in bit;
res : out bit
);
end impure_ex2;
architecture rtl of impure_ex2 is
-- An impure function called from a combinatorial process with "all"
-- sensitivity triggers an exception.
impure function foo return bit is
begin
return arg;
end... |
--===========================================================================--
-- --
-- Synthesizable 8 bit Timer --
-- --
... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in s... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in s... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in s... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in s... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in s... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
-- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity clock_gen is
generic (period : time := 10 ns);
port (clk, reset : out std_logic);
en... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
entity logic_analyzer_32 is
generic (
g_timer_div : positive := 50 );
port (
clock : in std_logic;
reset : in st... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
-- Concept:
-- The actual commands are implemented by the application software.
-- This allows direct coupling between a file and the read/write commands that
-- the drive p... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:02:32 10/20/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_SynthBench_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 19:57:07 12/03/2013
-- Design Name:
-- Module Name: VGA_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
-- $Id: pdp11_ledmux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ledmux - syn
-- Description: pdp11:... |
-- NEED RESULT: ARCH00691: Allocators with generic composite qualified expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------... |
package p is
procedure foo(x : in integer; y : out integer);
procedure yah is -- Error
begin
null;
end procedure;
end package;
package body p is
procedure foo(x : in integer; y : out integer) is
variable i : integer;
begin
y := x + 1;
end proce... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any X... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
LIBRARY work;
entity ffd_en is
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
D : in std_logic;
Q : out std_logic
);
end entity ffd_en;
architecture Behavioral of ffd_en is
signal q_tmp : std_logic;
begin
proce... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity detectroi_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------... |
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out i... |
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out i... |
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out i... |
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out i... |
entity sub is
port ( x : out integer );
end entity;
architecture test of sub is
begin
x <= 4;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
library other;
architecture test of top is
component sub is
port ( x : out i... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : Syst... |
------------------------------------------------------------------------------
---- ----
---- ZPU Trace Module ----
---- ----
----... |
library verilog;
use verilog.vl_types.all;
entity pll_testbench is
end pll_testbench;
|
library verilog;
use verilog.vl_types.all;
entity pll_testbench is
end pll_testbench;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
-------------------------------------------------------------------------------
-- SPI Status Register Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] ... |
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo AudioVideo_Init.vhd
-- Versione 1.02 - 18.03.2013
-- **********************************************************
-- ********************************... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:04:53 01/02/2016
-- Design Name:
-- Module Name: C:/Users/Kurtis/Desktop/mtcSvn/temp/LucaIRS3D_Ethernet_firmware/src/firmware-general/General/sim/ByteLinkTest.vhd
-- Project Nam... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: tst_serlooplib.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_502 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_502;
architecture augh of mul_502 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_502 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_502;
architecture augh of mul_502 is
signal tmp_res : signed(... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:28 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... |
--------------------------------------------------------------------------------
-- Entity: mul_add
-- Date:2018-08-02
-- Author: gideon
--
-- Description: VHDL only version of multiply accumulate with double accu
--------------------------------------------------------------------------------
library ieee;
use ... |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity TBCommon is
port (
clk : buffer std_logic;
a : out std_logic_vector(31 downto 0) := (others => '0');
b : out std_logic_vector(31 downto 0) := (others => '0');
d : in st... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:45:59 2017
-- Host : GILAMONSTER running 64-bit major rel... |
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
-----------------------... |
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
-----------------------... |
------------------------------------------------------------------------------
-- "standard_additions" package contains the additions to the built in
-- "standard.std" package. In the final version this package will be implicit.
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
-----------------------... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.i2s_controller;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_streaming_dma_rx_fifo;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl33... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.i2s_controller;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_streaming_dma_rx_fifo;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl33... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity uart_tx is
port(
clk : in vl_logic;
reset : in vl_logic;
tx_start : in vl_logic;
tx_data : in vl_logic_vector(7 downto 0);
tx_busy : out vl_logic;
tx_end ... |
-- $Id: tb_nexys3_core.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivat... |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivat... |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivat... |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivat... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library verilog;
use verilog.vl_types.all;
entity select4_8 is
port(
in1 : in vl_logic_vector(7 downto 0);
in2 : in vl_logic_vector(7 downto 0);
in3 : in vl_logic_vector(7 downto 0);
in4 : in vl_logic_vector(7 downto 0);... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity FIFO_T is
end FIFO_T;
architecture Beh of FIFO_T is
component FIFO is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in s... |
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------... |
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
---------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memInst2 is
generic (
wlength: integer := 32;
words : integer := 10
);
Port(
data: IN std_logic_vector(wlength-1 downto 0);
address: IN std_logic_vector(words-1 downto 0);
clock, wren: IN std_logic;
q: OUT std_logic_vector(w... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FiRoCtrlE is
generic (
EXTRACT : boolean := true
);
port (
--+ system if
Clk_i : in std_logic;
Reset_i : in std_logic;
--+ ctrl/status
Start_i : in std_logic;
Wait_i : in std_logic... |
entity tb_asgn07 is
end tb_asgn07;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn07 is
signal s0 : std_logic;
signal clk : std_logic;
signal r : std_logic_vector (65 downto 0);
begin
dut: entity work.asgn07
port map (clk => clk, s0 => s0, r => r);
process
procedure pulse ... |
----------------------------------------------------------------------------------
--Top module for Headstage SerDes FPGA
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponen... |
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std... |
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std... |
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std... |
-- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master ... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Di... |
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