plateform stringclasses 1
value | repo_name stringclasses 2
values | name stringlengths 1 78 | ext stringclasses 2
values | path stringlengths 15 1.11k | size int64 1 8.55M | source_encoding stringclasses 11
values | md5 stringlengths 32 32 | text stringlengths 0 8.49M |
|---|---|---|---|---|---|---|---|---|
google | android | nv84_fence | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nv84_fence.c | 7,649 | utf_8 | 685fb6b47f0ae3d40672c58fa33af198 | /*
*
* Authors: Ben Skeggs
*/
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_fence.h"
#include "nv50_display.h"
u64
nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
{
struct nv84_fence_chan *fctx = chan->fence;
return fctx->dispc_vma[crtc].offset;
}
static int
nv84_fence_emit32(struct n... |
google | android | nouveau_prime | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nouveau_prime.c | 3,291 | utf_8 | e13cd61568f444439c9b3acd62e8ed5e | /*
*
* Authors: Dave Airlie
*/
#include <drm/drmP.h>
#include <linux/dma-buf.h>
#include "nouveau_drm.h"
#include "nouveau_gem.h"
struct sg_table *nouveau_gem_prime_get_sg_table(struct drm_gem_object *obj)
{
struct nouveau_bo *nvbo = nouveau_gem_object(obj);
int npages = nvbo->bo.num_pages;
return drm_prime_pages... |
google | android | nouveau_abi16 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nouveau_abi16.c | 15,688 | utf_8 | d4d3bd2adff2776d5ca26f4687b57e0a | /*
*
*/
#include <nvif/client.h>
#include <nvif/driver.h>
#include <nvif/ioctl.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_gem.h"
#include "nouveau_chan.h"
#include "nouveau_abi16.h"
static struct nouveau_abi16 *
nouveau_abi16(struct drm_file... |
google | android | nouveau_chan | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nouveau_chan.c | 11,786 | utf_8 | 3fb824c2a7eb5a01eecc5cf7af21ce3e | /*
*
* Authors: Ben Skeggs
*/
#include <nvif/os.h>
#include <nvif/class.h>
#include <nvif/ioctl.h>
/*XXX*/
#include <core/client.h>
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_bo.h"
#include "nouveau_chan.h"
#include "nouveau_fence.h"
#include "nouveau_abi16.h"
MODULE_PARM_DESC(vram_pushbuf, ... |
google | android | nouveau_ttm | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nouveau_ttm.c | 11,184 | utf_8 | faba550beb8a318de96871348ae52da4 | /*
*/
#include "nouveau_drm.h"
#include "nouveau_ttm.h"
#include "nouveau_gem.h"
#include "drm_legacy.h"
#include <core/tegra.h>
static int
nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
struct nouveau_drm *drm = nouveau_bdev(man->bdev);
struct nvkm_fb *fb = nvxx_fb(&drm->device);... |
google | android | nouveau_nvif | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nouveau_nvif.c | 3,395 | utf_8 | f98cc288f9d6a95f410c281f7861fe51 | /*
*/
/*******************************************************************************
* NVIF client driver - NVKM directly linked
******************************************************************************/
#include <core/client.h>
#include <core/notify.h>
#include <core/ioctl.h>
#include <nvif/client.h>
#includ... |
google | android | nv04_fbcon | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nv04_fbcon.c | 7,883 | utf_8 | a7f084d4d2374b5b287f67948f137acb | /*
*/
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_fbcon.h"
int
nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct nouveau_fbdev *nfbdev = info->par;
struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
struct nouveau_channel *chan = drm->channel;
int ret;
r... |
google | android | nouveau_sgdma | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nouveau_sgdma.c | 2,659 | utf_8 | 6f9270aaed2a468c02b6e1b871060772 | #include <linux/pagemap.h>
#include <linux/slab.h>
#include "nouveau_drm.h"
#include "nouveau_ttm.h"
struct nouveau_sgdma_be {
/* this has to be the first field so populate/unpopulated in
* nouve_bo.c works properly, otherwise have to move them here
*/
struct ttm_dma_tt ttm;
struct nvkm_mem *node;
};
static v... |
google | android | nv10_fence | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nv10_fence.c | 3,121 | utf_8 | 0dc99a6aeb4bfdd3b33951b0a94175d7 | /*
*/
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nv10_fence.h"
int
nv10_fence_emit(struct nouveau_fence *fence)
{
struct nouveau_channel *chan = fence->channel;
int ret = RING_SPACE(chan, 2);
if (ret == 0) {
BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
OUT_RING (chan, fence->base.seqno);
FI... |
google | android | nouveau_dma | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nouveau_dma.c | 7,100 | utf_8 | bc1439e10c931b1461943e8e045638b5 | /*
*
*/
#include "nouveau_drm.h"
#include "nouveau_dma.h"
void
OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
{
bool is_iomem;
u32 *mem = ttm_kmap_obj_virtual(&chan->push.buffer->kmap, &is_iomem);
mem = &mem[chan->dma.cur];
if (is_iomem)
memcpy_toio((void __force __iomem *)mem, da... |
google | android | xtensa | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c | 5,657 | utf_8 | 5e159a29e1e8a42008b6c1904354ca2d | /*
*/
#include <engine/xtensa.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
static int
nvkm_xtensa_oclass_get(struct nvkm_oclass *oclass, int index)
{
struct nvkm_xtensa *xtensa = nvkm_xtensa(oclass->engine);
int c = 0;
while (xtensa->func->sclass[c].oclass) {
if (c++ == index) {
oclass->base = xtensa->... |
google | android | falcon | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 10,323 | utf_8 | aabf0c91405f31875c269b5f618cce3d | /*
*/
#include <engine/falcon.h>
#include <core/gpuobj.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
static int
nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index)
{
struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine);
int c = 0;
while (falcon->func->sclass[c].oclass) {
if (c++ == index) {
... |
google | android | nv10 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c | 2,300 | utf_8 | 4082453ad196ebc81eb660352274e0fe | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "chan.h"
#include "nvsw.h"
#include <nvif/ioctl.h>
/*******************************************************************************
******************************************************************************/
static const struct nvkm_sw_chan_func
nv10_sw_c... |
google | android | nvsw | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c | 2,515 | utf_8 | 46e20e082aaa5f21c0ce98d969fe168b | /*
*/
#include "nvsw.h"
#include "chan.h"
#include <nvif/class.h>
static int
nvkm_nvsw_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
struct nvkm_nvsw *nvsw = nvkm_nvsw(object);
if (nvsw->func->mthd)
return nvsw->func->mthd(nvsw, mthd, data, size);
return -ENODEV;
}
static int
nvkm_nvsw_ntfy_... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 4,501 | utf_8 | 462b264e0945e483013d559607be7293 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/gpuobj.h>
#include <engine/disp.h>
#include <engine/fifo/chan.h>
#include <subdev/bar.h>
#include <nvif/event.h>
#include <nvif/ioctl.h>
/*******************************************************************************
***********************************... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c | 3,833 | utf_8 | 146cc225ce6a948ea004037dcf7dfafc | /*
*
* Authors: Ben Skeggs
*/
#define nv04_sw_chan(p) container_of((p), struct nv04_sw_chan, base)
#include "priv.h"
#include "chan.h"
#include "nvsw.h"
#include <nvif/class.h>
#include <nvif/ioctl.h>
#include <nvif/unpack.h>
struct nv04_sw_chan {
struct nvkm_sw_chan base;
atomic_t ref;
};
/***********************... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c | 3,189 | utf_8 | 05a47f5d05a474fc68dd476417cede59 | /*
*/
#include "priv.h"
#include "chan.h"
#include <engine/fifo.h>
bool
nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data)
{
struct nvkm_sw_chan *chan;
bool handled = false;
unsigned long flags;
spin_lock_irqsave(&sw->engine.lock, flags);
list_for_each_entry(chan, &sw->chan, head) {
if (ch... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c | 4,601 | utf_8 | 2c3927f2eb4fb4566aafece014fe90ee | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/gpuobj.h>
#include <subdev/bar.h>
#include <engine/disp.h>
#include <engine/fifo.h>
#include <nvif/event.h>
#include <nvif/ioctl.h>
/*******************************************************************************
****************************************... |
google | android | chan | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c | 3,059 | utf_8 | c3f8c61db5648634913d8ff18337ea08 | /*
*/
#include "chan.h"
#include <core/notify.h>
#include <engine/fifo.h>
#include <nvif/event.h>
#include <nvif/unpack.h>
bool
nvkm_sw_chan_mthd(struct nvkm_sw_chan *chan, int subc, u32 mthd, u32 data)
{
switch (mthd) {
case 0x0000:
return true;
case 0x0500:
nvkm_event_send(&chan->event, 1, 0, NULL, 0);
retu... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c | 2,428 | utf_8 | 03e7e54fd3e50a02d6a6141a5217e796 | /*
*
* Authors: Ben Skeggs
*/
#include "nv31.h"
#include <subdev/instmem.h>
#include <nvif/class.h>
bool
nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
{
struct nvkm_instmem *imem = device->imem;
u32 inst = data << 4;
u32 dma0 = nvkm_instmem_rd32(imem, inst + 0);
u32 dma1 = nvkm_instmem_rd32(... |
google | android | nv31 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 8,025 | utf_8 | 3a8394786cbc220f7ad93b7c3a8ae08b | /*
*
* Authors: Ben Skeggs
*/
#include "nv31.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
#include <nvif/class.h>
/*******************************************************************************
* MPEG object classes
****************... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c | 1,555 | utf_8 | f48842275e848e4bcc54f0b0713f396a | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_engine_func
g84_mpeg = {
.init = nv50_mpeg_init,
.intr = nv50_mpeg_intr,
.cclass = &nv50_mpeg_cclass,
.sclass = {
{ -1, -1, G82_MPEG, &nv31_mpeg_object },
{}
}
};
int
g84_mpeg_new(struct nvkm_device *device, int... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c | 4,000 | utf_8 | 85f271e0307d1f5b755a524ce67ce9e8 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/gpuobj.h>
#include <subdev/timer.h>
#include <nvif/class.h>
/*******************************************************************************
* PMPEG context
******************************************************************************/
static int
nv50... |
google | android | nv44 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c | 6,183 | utf_8 | cd9e4b92ed65308fc28980dc47902aa2 | /*
*
* Authors: Ben Skeggs
*/
#define nv44_mpeg(p) container_of((p), struct nv44_mpeg, engine)
#include "priv.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <nvif/class.h>
struct nv44_mpeg {
struct nvkm_engine engine;
struct list_head chan;
};
/******************************... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c | 5,306 | utf_8 | dd05e918993650d064a070b08c4188bd | /*
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
static const struct nvkm_specsrc
gt215_zcull_sources[] = {
{ 0x402ca4, (const struct nvkm_specmux[]) {
{ 0x7fff, 0, "unk0" },
{ 0xff, 24, "unk24" },
{}
}, "pgraph_zcull_pm_unka4" },
{}
};
static const struct nvkm_specdom
gt215_pm[] = {
{ 0x20, (const stru... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c | 3,554 | utf_8 | 80e966c25c9c19bdad5414c68bf7eca9 | /*
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
static void
nv40_perfctr_init(struct nvkm_pm *pm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
struct nvkm_device *device = pm->engine.subdev.device;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
for (i = 0; i < 4; i++)
src |= ctr->signal[i]... |
google | android | gf117 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c | 2,704 | utf_8 | 284c6cd083a76ae08ded7be21a7be0b8 | /*
*
* Authors: Samuel Pitoiset
*/
#include "gf100.h"
static const struct nvkm_specsrc
gf117_pmfb_sources[] = {
{ 0x140028, (const struct nvkm_specmux[]) {
{ 0x3fff, 0, "unk0" },
{ 0x7, 16, "unk16" },
{ 0x3, 24, "unk24" },
{ 0x2, 28, "unk28" },
{}
}, "pmfb0_pm_unk28" },
{ 0x14125c, (const struct n... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c | 5,764 | utf_8 | 5f9cb2eea6e429db5490663db0cfc131 | /*
*
* Authors: Ben Skeggs
*/
#include "gf100.h"
static const struct nvkm_specsrc
gk104_pmfb_sources[] = {
{ 0x140028, (const struct nvkm_specmux[]) {
{ 0x3fff, 0, "unk0" },
{ 0x7, 16, "unk16" },
{ 0x3, 24, "unk24" },
{ 0x2, 28, "unk28" },
{}
}, "pmfb0_pm_unk28" },
{ 0x14125c, (const struct nvkm_s... |
google | android | gt200 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c | 5,652 | utf_8 | 0b30b779a6c6f1a47aa2edb1f5100bc6 | /*
*
* Authors: Samuel Pitoiset
*/
#include "nv40.h"
const struct nvkm_specsrc
gt200_crop_sources[] = {
{ 0x407008, (const struct nvkm_specmux[]) {
{ 0xf, 0, "sel0", true },
{ 0x1f, 16, "sel1", true },
{}
}, "pgraph_rop0_crop_pm_mux" },
{}
};
const struct nvkm_specsrc
gt200_prop_sources[] = {
{ 0x40875... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c | 5,776 | utf_8 | c483650c2a0d2eeed13a622dcbf49f0d | /*
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
const struct nvkm_specsrc
g84_vfetch_sources[] = {
{ 0x400c0c, (const struct nvkm_specmux[]) {
{ 0x3, 0, "unk0" },
{}
}, "pgraph_vfetch_unk0c" },
{}
};
static const struct nvkm_specsrc
g84_prop_sources[] = {
{ 0x408e50, (const struct nvkm_specmux[]) {
{ 0... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c | 6,073 | utf_8 | 38858580d145e3c9bf3c585acaeeeee6 | /*
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
const struct nvkm_specsrc
nv50_zcull_sources[] = {
{ 0x402ca4, (const struct nvkm_specmux[]) {
{ 0x7fff, 0, "unk0" },
{}
}, "pgraph_zcull_pm_unka4" },
{}
};
const struct nvkm_specsrc
nv50_zrop_sources[] = {
{ 0x40708c, (const struct nvkm_specmux[]) {
{ 0x... |
google | android | gf108 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c | 2,453 | utf_8 | bab68a4da41d46d4a0a4ba931b598fb0 | /*
*
* Authors: Samuel Pitoiset
*/
#include "gf100.h"
static const struct nvkm_specdom
gf108_pm_hub[] = {
{}
};
static const struct nvkm_specdom
gf108_pm_part[] = {
{ 0xe0, (const struct nvkm_specsig[]) {
{ 0x14, "part00_pbfb_00", gf100_pbfb_sources },
{ 0x15, "part00_pbfb_01", gf100_pbfb_sources },
{ 0x2... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c | 20,384 | utf_8 | e9b01b4570def8b334e821b99259f0a6 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/client.h>
#include <core/option.h>
#include <nvif/class.h>
#include <nvif/ioctl.h>
#include <nvif/unpack.h>
static u8
nvkm_pm_count_perfdom(struct nvkm_pm *pm)
{
struct nvkm_perfdom *dom;
u8 domain_nr = 0;
list_for_each_entry(dom, &pm->domains, head)
... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c | 6,941 | utf_8 | f57753a84b81634bfe963af1bfc5a844 | /*
*
* Authors: Ben Skeggs
*/
#include "gf100.h"
const struct nvkm_specsrc
gf100_pbfb_sources[] = {
{ 0x10f100, (const struct nvkm_specmux[]) {
{ 0x1, 0, "unk0" },
{ 0x3f, 4, "unk4" },
{}
}, "pbfb_broadcast_pm_unk100" },
{}
};
const struct nvkm_specsrc
gf100_pmfb_sources[] = {
{ 0x140028, (const struct... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c | 1,540 | utf_8 | 2a5eafa76ab5c1811c2c4c31dfb03d79 | /*
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gt215_msppp = {
.pmc_enable = 0x00400002,
.init = g98_msppp_init,
.sclass = {
{ -1, -1, GT212_MSPPP },
{}
}
};
int
gt215_msppp_new(struct nvkm_device *device, int index... |
google | android | g98 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c | 1,727 | utf_8 | 6b4a99b3515132b23cc0533676e9aafb | /*
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
void
g98_msppp_init(struct nvkm_falcon *msppp)
{
struct nvkm_device *device = msppp->engine.subdev.device;
nvkm_wr32(device, 0x086010, 0x0000ffd2);
nvkm_wr32(device, 0x08601c, 0x0000fff2);
}
static const struct... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c | 1,388 | utf_8 | 060e5baeaa607e0ace2ea7a9d2141817 | /*
*/
#include "priv.h"
int
nvkm_msppp_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
int index, struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, index, true, 0x086000, pengine);
} |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c | 1,721 | utf_8 | 3b75cc03513e26c4e1930ba20aac00b2 | /*
*
* Authors: Maarten Lankhorst
*/
#include "priv.h"
#include <nvif/class.h>
static void
gf100_msppp_init(struct nvkm_falcon *msppp)
{
struct nvkm_device *device = msppp->engine.subdev.device;
nvkm_wr32(device, 0x086010, 0x0000fff2);
nvkm_wr32(device, 0x08601c, 0x0000fff2);
}
static const struct nvkm_falcon_fun... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c | 1,542 | utf_8 | 62be1b1d26c076caceff1853163245cc | /*
*
* Authors: Ben Skeggs, Ilia Mirkin
*/
#include <engine/bsp.h>
#include <nvif/class.h>
static const struct nvkm_xtensa_func
g84_bsp = {
.pmc_enable = 0x04008000,
.fifo_val = 0x1111,
.unkd28 = 0x90044,
.sclass = {
{ -1, -1, NV74_BSP },
{}
}
};
int
g84_bsp_new(struct nvkm_device *device, int index, struct... |
google | android | rootgm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm204.c | 1,904 | utf_8 | 12cf56264ad8522345822720a629b045 | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gm204_disp_root = {
.init = gf119_disp_root_init,
.fini = gf119_disp_root_fini,
.dmac = {
&gm204_disp_core_oclass,
&gk110_disp_base_oclass,
&gk104_disp_ovly_oclass,
},
... |
google | android | oimmnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c | 2,291 | utf_8 | 08055c99586c100978e779c5d7ecb401 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_disp_oimm_new(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp_root *root, int chid,
const struct... |
google | android | ovlyg84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c | 2,238 | utf_8 | e0e6128f37166c2434e9d46c57687557 | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
g84_disp_ovly_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
{ 0x0080, 0x000000 },
{ 0x0084, 0x6109a0 },
{ 0x0088, 0x6109c0 },
{ 0x008c, 0x6109c8 },
{ 0x00... |
google | android | g94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c | 2,092 | utf_8 | cf50078ace5d2bcd05e71d128e608e3b | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
static const struct nv50_disp_func
g94_disp = {
.intr = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.super = nv50_disp_intr_supervisor,
.root = &g94_disp_root_oclass,
.head.vblank_init = nv50_disp_vblank_init,
.head.vblank_fini = nv50_... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c | 2,133 | utf_8 | 89334f06e1f1d0ad0b58c9e4168dac70 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
static const struct nv50_disp_func
gt215_disp = {
.intr = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.super = nv50_disp_intr_supervisor,
.root = >215_disp_root_oclass,
.head.vblank_init = nv50_disp_vblank_init,
.head.vblank_fini = n... |
google | android | piornv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c | 3,860 | utf_8 | dbc0a39b84d4e803f6b639b7fd851fb9 | /*
*
* Authors: Ben Skeggs
*/
#include "outpdp.h"
#include "nv50.h"
#include <core/client.h>
#include <subdev/i2c.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_pior_power(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
const u32 soff = out... |
google | android | piocnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c | 2,745 | utf_8 | 6baeca21f0675886e208b8544636b7fb | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <subdev/timer.h>
static void
nv50_disp_pioc_fini(struct nv50_disp_chan *chan)
{
struct nv50_disp *disp = chan->root->disp;
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_device *device = subdev->device;
int ch... |
google | android | gm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c | 2,008 | utf_8 | 35791d8012fd709ff44888973caade6b | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
static const struct nv50_disp_func
gm107_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gm107_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini... |
google | android | rootnv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c | 4,068 | utf_8 | 0f42fd572fc61a6428951fbe5eb73c9e | /*
*
* Authors: Ben Skeggs
*/
#define nv04_disp_root(p) container_of((p), struct nv04_disp_root, object)
#include "priv.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
struct nv04_disp_root {
struct nvkm_object object;
struct nvkm_disp *disp;
};
static int
nv04_disp_scanoutpos(struct n... |
google | android | coregm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregm107.c | 1,493 | utf_8 | 33181d0e126c25c3fff0e59a770cde8b | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gm107_disp_core_oclass = {
.base.oclass = GM107_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.... |
google | android | rootnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c | 11,674 | utf_8 | 826937ef2ab8ee74ea8a5066243fec51 | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_disp_root_scanoutpos(NV50_DISP_MTHD_V0)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
cons... |
google | android | rootgk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c | 1,904 | utf_8 | 926ca352e635b3d1e4ce240c6b383c18 | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gk104_disp_root = {
.init = gf119_disp_root_init,
.fini = gf119_disp_root_fini,
.dmac = {
&gk104_disp_core_oclass,
&gk104_disp_base_oclass,
&gk104_disp_ovly_oclass,
},
... |
google | android | oimmg84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmg84.c | 1,421 | utf_8 | e38517b5fef036a131204d53e0de355a | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
g84_disp_oimm_oclass = {
.base.oclass = G82_DISP_OVERLAY,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_oimm_new,
.func = &nv50_disp_pioc_func,
.chid = 5,
}; |
google | android | channv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c | 8,470 | utf_8 | 3aa98960cb9da6328ae7a09dcc08e3a2 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <engine/dma.h>
#include <nvif/class.h>
#include <nvif/event.h>
#include <nvif/unpack.h>
static void
nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c,
const s... |
google | android | ovlygt200 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c | 2,329 | utf_8 | 311769dc709d4fe955121027c229a4f6 | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
gt200_disp_ovly_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
{ 0x0080, 0x000000 },
{ 0x0084, 0x6109a0 },
{ 0x0088, 0x6109c0 },
{ 0x008c, 0x6109c8 },
{ 0x... |
google | android | dmacgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c | 3,515 | utf_8 | e5ef1bea37f68be58c8dff9ba2cc3e82 | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <core/ramht.h>
#include <subdev/timer.h>
int
gf119_disp_dmac_bind(struct nv50_disp_dmac *chan,
struct nvkm_object *object, u32 handle)
{
return nvkm_ramht_insert(chan->base.root->ramht, object,
chan->base.chid, -9, handle... |
google | android | rootg84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c | 1,878 | utf_8 | 61920a1a7d048cbbca5f37657dcf190e | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
g84_disp_root = {
.init = nv50_disp_root_init,
.fini = nv50_disp_root_fini,
.dmac = {
&g84_disp_core_oclass,
&g84_disp_base_oclass,
&g84_disp_ovly_oclass,
},
.pioc = {
... |
google | android | cursgk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgk104.c | 1,426 | utf_8 | 130aa9e6a230b4ceef0e3bec923737d2 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gk104_disp_curs_oclass = {
.base.oclass = GK104_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &gf119_disp_pioc_func,
.chid = 13,
}; |
google | android | rootgk110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c | 1,904 | utf_8 | 4770ace6fabe2d22e47798cdf7206d5a | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gk110_disp_root = {
.init = gf119_disp_root_init,
.fini = gf119_disp_root_fini,
.dmac = {
&gk110_disp_core_oclass,
&gk110_disp_base_oclass,
&gk104_disp_ovly_oclass,
},
... |
google | android | cursnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c | 2,287 | utf_8 | 18fd863ec6310107aecf77f74f7794f3 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_disp_curs_new(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp_root *root, int chid,
const struct... |
google | android | piocgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c | 2,752 | utf_8 | a98733ac928757b957ff7db4a819014e | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <subdev/timer.h>
static void
gf119_disp_pioc_fini(struct nv50_disp_chan *chan)
{
struct nv50_disp *disp = chan->root->disp;
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_device *device = subdev->device;
int c... |
google | android | hdagf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c | 2,711 | utf_8 | faeca3c0c6e00b6f2d1ab847ca5696b6 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "outp.h"
#include <core/client.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
gf119_hda_eld(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.dev... |
google | android | gk110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c | 2,008 | utf_8 | 135bb3d932ff814afd4d92a176ccbbb8 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
static const struct nv50_disp_func
gk110_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gk110_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini... |
google | android | rootg94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c | 1,884 | utf_8 | 14fabe773730291b52ef307d984f0bf4 | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
g94_disp_root = {
.init = nv50_disp_root_init,
.fini = nv50_disp_root_fini,
.dmac = {
&g94_disp_core_oclass,
>200_disp_base_oclass,
>200_disp_ovly_oclass,
},
.pioc ... |
google | android | sorgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c | 3,917 | utf_8 | 1d7992acb80073be8b4610f057c5ee0f | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "outpdp.h"
static inline u32
gf119_sor_soff(struct nvkm_output_dp *outp)
{
return (ffs(outp->base.info.or) - 1) * 0x800;
}
static inline u32
gf119_sor_loff(struct nvkm_output_dp *outp)
{
return gf119_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x8... |
google | android | basegt200 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/basegt200.c | 1,490 | utf_8 | 380f52635a621a295a61713551160f47 | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gt200_disp_base_oclass = {
.base.oclass = GT200_DISP_BASE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_base_new,
.func = &nv50_disp_dmac_func,
.mthd = &g84_disp_base_chan_mthd,
.chi... |
google | android | oimmgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c | 1,426 | utf_8 | 62f570aa1b43f59fb77b92c17c2648eb | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gf119_disp_oimm_oclass = {
.base.oclass = GF110_DISP_OVERLAY,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_oimm_new,
.func = &gf119_disp_pioc_func,
.chid = 9,
}; |
google | android | coreg84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c | 3,175 | utf_8 | 9c33676c629952ec596da412a3c9d7cd | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_mthd_list
g84_disp_core_mthd_dac = {
.mthd = 0x0080,
.addr = 0x000008,
.data = {
{ 0x0400, 0x610b58 },
{ 0x0404, 0x610bdc },
{ 0x0420, 0x610bc4 },
{}
}
};
const struct nv50_disp_mthd_l... |
google | android | gf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c | 14,936 | utf_8 | 72ad74ce1eb4560b04c2317cc3e0f01b | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
#include <subdev/bios.h>
#include <subdev/bios/disp.h>
#include <subdev/bios/init.h>
#include <subdev/bios/pll.h>
#include <subdev/devinit.h>
void
gf119_disp_vblank_init(struct nv50_disp *disp, int head)
{
struct nvkm_device *device = disp->base.... |
google | android | ovlynv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c | 3,243 | utf_8 | 78b359c47caa274a8ebbb9d4c13d0822 | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_disp_ovly_new(const struct nv50_disp_dmac_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp_root *root, int chid,
const struct... |
google | android | coreg94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c | 1,976 | utf_8 | 8c3d28da9bf7e1809289fbeaa948ed7c | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_mthd_list
g94_disp_core_mthd_sor = {
.mthd = 0x0040,
.addr = 0x000008,
.data = {
{ 0x0600, 0x610794 },
{}
}
};
const struct nv50_disp_chan_mthd
g94_disp_core_chan_mthd = {
.name = "Core",... |
google | android | hdmig84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c | 3,452 | utf_8 | c2b2284c21f4dab2b30705e22b8403cf | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
const u32 hoff = (head * 0x800);
union {
struct nv50_disp_sor_hdmi_pwr_v0 v0;
} *args = ... |
google | android | vga | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c | 6,449 | utf_8 | eb7b91da8e1bdd2ed23a46293e9ad5e9 | /*
*
* Authors: Ben Skeggs
*/
#include <subdev/vga.h>
u8
nvkm_rdport(struct nvkm_device *device, int head, u16 port)
{
if (device->card_type >= NV_50)
return nvkm_rd08(device, 0x601000 + port);
if (port == 0x03c0 || port == 0x03c1 || /* AR */
port == 0x03c2 || port == 0x03da || /* INP0 */
port == 0x03d... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c | 2,008 | utf_8 | 22a4a1efcd393749f3aa68e0c3d4f0bd | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
static const struct nv50_disp_func
gk104_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gk104_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini... |
google | android | dport | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c | 10,714 | utf_8 | f394da6dc5dcb6dd8e11dd1a0bbe5885 | /*
*
* Authors: Ben Skeggs
*/
#include "dport.h"
#include "outpdp.h"
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
#include <subdev/i2c.h>
#include <nvif/class.h>
/******************************************************************************
* link training
*****************************... |
google | android | gt200 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c | 2,063 | utf_8 | bc77e73dd2286ef169518a5e569da914 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
static const struct nv50_disp_func
gt200_disp = {
.intr = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.super = nv50_disp_intr_supervisor,
.root = >200_disp_root_oclass,
.head.vblank_init = nv50_disp_vblank_init,
.head.vblank_fini = n... |
google | android | cursgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c | 1,426 | utf_8 | 5a898c730a47f7f34d52554994cf9499 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gf119_disp_curs_oclass = {
.base.oclass = GF110_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &gf119_disp_pioc_func,
.chid = 13,
}; |
google | android | coregf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c | 6,216 | utf_8 | 82ff76d2f2929f3b6f967acb65a72956 | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
const struct nv50_disp_mthd_list
gf119_disp_core_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
{ 0x0080, 0x660080 },
{ 0x008... |
google | android | hdagt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c | 2,563 | utf_8 | 97428335408f323d1ac43ba760a60439 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "outp.h"
#include <core/client.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
gt215_hda_eld(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
union {
struct nv50_disp_sor_hda_eld_v0 v0;
}... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c | 2,055 | utf_8 | 16f9d6e4a67c6e2ff4c86be122df5325 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
static const struct nv50_disp_func
g84_disp = {
.intr = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.super = nv50_disp_intr_supervisor,
.root = &g84_disp_root_oclass,
.head.vblank_init = nv50_disp_vblank_init,
.head.vblank_fini = nv50_... |
google | android | sorgm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c | 4,637 | utf_8 | eb752fab02e9c3b56da718f728bb9a3d | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "outpdp.h"
#include <subdev/timer.h>
static inline u32
gm204_sor_soff(struct nvkm_output_dp *outp)
{
return (ffs(outp->base.info.or) - 1) * 0x800;
}
static inline u32
gm204_sor_loff(struct nvkm_output_dp *outp)
{
return gm204_sor_soff(outp) + !(outp->base.in... |
google | android | basegk110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/basegk110.c | 1,493 | utf_8 | 2c46ce181719e19d102aca27e351e45b | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gk110_disp_base_oclass = {
.base.oclass = GK110_DISP_BASE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_base_new,
.func = &gf119_disp_dmac_func,
.mthd = &gf119_disp_base_chan_mthd,
.... |
google | android | basenv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c | 3,445 | utf_8 | fac81b4a1c1faa56b2f2e0347721891f | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_disp_base_new(const struct nv50_disp_dmac_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp_root *root, int chid,
const struct... |
google | android | basegk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/basegk104.c | 1,493 | utf_8 | b0a64601ec43e1297e922077f6f692d5 | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gk104_disp_base_oclass = {
.base.oclass = GK104_DISP_BASE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_base_new,
.func = &gf119_disp_dmac_func,
.mthd = &gf119_disp_base_chan_mthd,
.... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c | 23,395 | utf_8 | 73bceb61cfeda6253d42492af9729ddc | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <subdev/bios.h>
#include <subdev/bios/disp.h>
#include <subdev/bios/init.h>
#include <subdev/bios/pll.h>
#include <subdev/devinit.h>
static const struct nvkm_disp_oc... |
google | android | coregt200 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregt200.c | 1,490 | utf_8 | d839c970abe2ba9d28ce3de942765b3f | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gt200_disp_core_oclass = {
.base.oclass = GT200_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &nv50_disp_core_func,
.mthd = &g84_disp_core_chan_mthd,
.chi... |
google | android | sorg94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c | 5,286 | utf_8 | 3dd0a08660ac4030f874dfc1fef4d57c | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "outpdp.h"
#include <subdev/timer.h>
static inline u32
g94_sor_soff(struct nvkm_output_dp *outp)
{
return (ffs(outp->base.info.or) - 1) * 0x800;
}
static inline u32
g94_sor_loff(struct nvkm_output_dp *outp)
{
return g94_sor_soff(outp) + !(outp->base.info.sor... |
google | android | coregt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregt215.c | 1,490 | utf_8 | ca848aa46c177569e18088238c240d83 | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gt215_disp_core_oclass = {
.base.oclass = GT214_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &nv50_disp_core_func,
.mthd = &g94_disp_core_chan_mthd,
.chi... |
google | android | dmacnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c | 7,211 | utf_8 | 612b588ab316bdc49467171c1a1b10ca | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <core/oproxy.h>
#include <core/ramht.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <engine/dma.h>
struct nv50_disp_dmac_object {
struct nvkm_oproxy oproxy;
struct nv50_disp_root *root;
int ha... |
google | android | hdmigk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c | 2,956 | utf_8 | 8b486c3dc9157dc8ef743b3154a382d3 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
const u32 hoff = (head * 0x800);
const u32 hdmi = (head * 0x400);
union {
struct nv50_... |
google | android | gm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c | 2,039 | utf_8 | 9339c7eb3ebfb051e603c95cb1ffdd9c | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "rootnv50.h"
static const struct nv50_disp_func
gm204_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gm204_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini... |
google | android | rootgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c | 5,469 | utf_8 | c870e7d90b72c62cfa085011f6425c1f | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
con... |
google | android | rootgm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c | 1,904 | utf_8 | 74dccce15ae6e1c036b2a1f4f55f8ed3 | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gm107_disp_root = {
.init = gf119_disp_root_init,
.fini = gf119_disp_root_fini,
.dmac = {
&gm107_disp_core_oclass,
&gk110_disp_base_oclass,
&gk104_disp_ovly_oclass,
},
... |
google | android | changf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c | 2,036 | utf_8 | d42fcb1f7547d28ccda8e5bfd80e91b7 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
static void
gf119_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
{
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
struct nvkm_device *device = disp->base.engine.subdev.device;
nvkm_mask(device, 0x610090, 0x00000001 << ... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c | 2,671 | utf_8 | df12bc3dbd20333b7a04643e2b0abec9 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static const struct nvkm_disp_oclass *
nv04_disp_root(struct nvkm_disp *disp)
{
return &nv04_disp_root_oclass;
}
static void
nv04_disp_vblank_init(struct nvkm_disp *disp, int head)
{
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_wr32(device, 0x600140... |
google | android | ovlygk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c | 2,888 | utf_8 | 027d40f451da7efa08bbac581899a7ea | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
gk104_disp_ovly_mthd_base = {
.mthd = 0x0000,
.data = {
{ 0x0080, 0x665080 },
{ 0x0084, 0x665084 },
{ 0x0088, 0x665088 },
{ 0x008c, 0x66508c },
{ 0x0090, 0x665090 },
... |
google | android | conn | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c | 3,831 | utf_8 | 991b82bf206f157809d5a836c08f9060 | /*
*
* Authors: Ben Skeggs
*/
#include "conn.h"
#include "outp.h"
#include "priv.h"
#include <subdev/gpio.h>
#include <nvif/event.h>
static int
nvkm_connector_hpd(struct nvkm_notify *notify)
{
struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd);
struct nvkm_disp *disp = conn->disp;
struct nvkm_... |
google | android | sornv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c | 2,388 | utf_8 | f40fd08d97d4cf62d3fb2c2272f39816 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "outp.h"
#include <core/client.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_sor_power(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
union {
struct nv50_disp_sor_pwr_v0 v0;
} *a... |
google | android | hdmigt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c | 3,474 | utf_8 | 34f28d7faeddbd9ded98a68e0d1d7e58 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "outp.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
const u32 soff = outp->or * 0x800;
union {
struct nv50_disp_sor_hdmi_... |
google | android | hdmigf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c | 2,861 | utf_8 | ca7d3404987e07f94b67dc715b2199a0 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
gf119_hdmi_ctrl(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
const u32 hoff = (head * 0x800);
union {
struct nv50_disp_sor_hdmi_pwr_v0 v0;
} *args ... |
google | android | outpdp | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c | 8,255 | utf_8 | 3642884391e0328352603885181904e9 | /*
*
* Authors: Ben Skeggs
*/
#include "outpdp.h"
#include "conn.h"
#include "dport.h"
#include "priv.h"
#include <subdev/i2c.h>
#include <nvif/event.h>
int
nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait)
{
struct nvkm_output_dp *outp = nvkm_output_dp(base);
bool retrain = true;
u8 link[2]... |
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