plateform stringclasses 1
value | repo_name stringclasses 2
values | name stringlengths 1 78 | ext stringclasses 2
values | path stringlengths 15 1.11k | size int64 1 8.55M | source_encoding stringclasses 11
values | md5 stringlengths 32 32 | text stringlengths 0 8.49M |
|---|---|---|---|---|---|---|---|---|
google | android | rootgt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c | 1,902 | utf_8 | bf77f0a20947d1abc4b4fb5c4a1e6520 | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gt215_disp_root = {
.init = nv50_disp_root_init,
.fini = nv50_disp_root_fini,
.dmac = {
>215_disp_core_oclass,
>215_disp_base_oclass,
>215_disp_ovly_oclass,
},
.p... |
google | android | oimmgk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgk104.c | 1,426 | utf_8 | 8f5452f3bc6ac22fcd84b2d9d8f28f69 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gk104_disp_oimm_oclass = {
.base.oclass = GK104_DISP_OVERLAY,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_oimm_new,
.func = &gf119_disp_pioc_func,
.chid = 9,
}; |
google | android | dacnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c | 3,725 | utf_8 | d4662f7882c8f08318b5f03fbd5ab654 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "outp.h"
#include <core/client.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_dac_power(NV50_DISP_MTHD_V1)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
const u32 doff = outp->or * 0x800;
union {
s... |
google | android | basegf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c | 3,072 | utf_8 | 456c33062ff4398b7c5d116cec71223f | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
gf119_disp_base_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
{ 0x0080, 0x661080 },
{ 0x0084, 0x661084 },
{ 0x0088, 0x661088 },
{ 0x008c, 0x66108c },
{ 0x... |
google | android | cursgt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgt215.c | 1,445 | utf_8 | cced8ee767b6473fb7964dae8c1f3e2d | /*
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gt215_disp_curs_oclass = {
.base.oclass = GT214_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &nv50_disp_pioc_func,
.chid = 7,
}; |
google | android | ovlygf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c | 2,840 | utf_8 | 49c937a70de393dcc303b88bcf98613e | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
gf119_disp_ovly_mthd_base = {
.mthd = 0x0000,
.data = {
{ 0x0080, 0x665080 },
{ 0x0084, 0x665084 },
{ 0x0088, 0x665088 },
{ 0x008c, 0x66508c },
{ 0x0090, 0x665090 },
... |
google | android | coregk110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk110.c | 1,493 | utf_8 | 595064fd4a6405eaaacba993891bc4f8 | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gk110_disp_core_oclass = {
.base.oclass = GK110_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.... |
google | android | corenv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c | 6,397 | utf_8 | 28b415daba534a3a2e67df2e4ca58f40 | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <core/client.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
int
nv50_disp_core_new(const struct nv50_disp_dmac_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp_root *root, i... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c | 10,991 | utf_8 | ff9e15665641e9c29414472df7d7601b | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "conn.h"
#include "outp.h"
#include <core/client.h>
#include <core/notify.h>
#include <core/oproxy.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <nvif/class.h>
#include <nvif/event.h>
#include <nvif/unpack.h>
static void
nvkm_disp_vblank_fi... |
google | android | outp | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c | 2,637 | utf_8 | 4c2bfc38ad989f43a04507ee83d42b66 | /*
*
* Authors: Ben Skeggs
*/
#include "outp.h"
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/i2c.h>
void
nvkm_output_fini(struct nvkm_output *outp)
{
if (outp->func->fini)
outp->func->fini(outp);
}
void
nvkm_output_init(struct nvkm_output *outp)
{
if (outp->func->init)
outp->func->ini... |
google | android | rootgt200 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c | 1,898 | utf_8 | 7e6ac4b79427fad6686ea5a36d270e81 | /*
*
* Authors: Ben Skeggs
*/
#include "rootnv50.h"
#include "dmacnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_root_func
gt200_disp_root = {
.init = nv50_disp_root_init,
.fini = nv50_disp_root_fini,
.dmac = {
>200_disp_core_oclass,
>200_disp_base_oclass,
>200_disp_ovly_oclass,
},
.p... |
google | android | baseg84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c | 2,327 | utf_8 | a8688f1fc76ea412215a34bb18af9b54 | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
g84_disp_base_mthd_base = {
.mthd = 0x0000,
.addr = 0x000000,
.data = {
{ 0x0080, 0x000000 },
{ 0x0084, 0x0008c4 },
{ 0x0088, 0x0008d0 },
{ 0x008c, 0x0008dc },
{ 0x00... |
google | android | coregm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregm204.c | 1,493 | utf_8 | 951f6bf012742d83e4766d722d719fe7 | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gm204_disp_core_oclass = {
.base.oclass = GM204_DISP_CORE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_core_new,
.func = &gf119_disp_core_func,
.mthd = &gk104_disp_core_chan_mthd,
.... |
google | android | cursg84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursg84.c | 1,441 | utf_8 | d17ed15e3296f2705d02ace1c6a4aad4 | /*
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
g84_disp_curs_oclass = {
.base.oclass = G82_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &nv50_disp_pioc_func,
.chid = 7,
}; |
google | android | ovlygt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt215.c | 1,493 | utf_8 | 3950397f4316f3efa15262bddd77abf7 | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gt215_disp_ovly_oclass = {
.base.oclass = GT214_DISP_OVERLAY_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_ovly_new,
.func = &nv50_disp_dmac_func,
.mthd = &g84_disp_ovly_chan_mthd,
.... |
google | android | oimmgt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgt215.c | 1,425 | utf_8 | 215a5dd8288e735886cabe28127fe413 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gt215_disp_oimm_oclass = {
.base.oclass = GT214_DISP_OVERLAY,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_oimm_new,
.func = &nv50_disp_pioc_func,
.chid = 5,
}; |
google | android | coregk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c | 3,658 | utf_8 | 1dbad0617d008cd05b063c6838ea7327 | /*
*
* Authors: Ben Skeggs
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
static const struct nv50_disp_mthd_list
gk104_disp_core_mthd_head = {
.mthd = 0x0300,
.addr = 0x000300,
.data = {
{ 0x0400, 0x660400 },
{ 0x0404, 0x660404 },
{ 0x0408, 0x660408 },
{ 0x040c, 0x66040c },
{ 0x... |
google | android | basegt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/basegt215.c | 1,490 | utf_8 | db5c72917a303361d46e517dc50f0e11 | /*
*/
#include "dmacnv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_dmac_oclass
gt215_disp_base_oclass = {
.base.oclass = GT214_DISP_BASE_CHANNEL_DMA,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_base_new,
.func = &nv50_disp_dmac_func,
.mthd = &g84_disp_base_chan_mthd,
.chi... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c | 1,545 | utf_8 | a64ceaf655b3047f9b295107d8d3b448 | /*
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gt215_mspdec = {
.pmc_enable = 0x01020000,
.init = g98_mspdec_init,
.sclass = {
{ -1, -1, GT212_MSPDEC },
{}
}
};
int
gt215_mspdec_new(struct nvkm_device *device, int i... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c | 1,512 | utf_8 | 986210995c761032909dae82303602e5 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gk104_mspdec = {
.pmc_enable = 0x00020000,
.init = gf100_mspdec_init,
.sclass = {
{ -1, -1, GK104_MSPDEC },
{}
}
};
int
gk104_mspdec_new(struct nvkm_device *device, int index,
struct nvkm_engine **... |
google | android | g98 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c | 1,735 | utf_8 | f45e2ef9e9d4be5099bfd3f5d80b32a3 | /*
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
void
g98_mspdec_init(struct nvkm_falcon *mspdec)
{
struct nvkm_device *device = mspdec->engine.subdev.device;
nvkm_wr32(device, 0x085010, 0x0000ffd2);
nvkm_wr32(device, 0x08501c, 0x0000fff2);
}
static const str... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c | 1,393 | utf_8 | 9407b54fd26ff585db54fe50c8cea2ca | /*
*/
#include "priv.h"
int
nvkm_mspdec_new_(const struct nvkm_falcon_func *func,
struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, index, true, 0x085000, pengine);
} |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c | 1,724 | utf_8 | a5c7f46f8f058d7715218814a2f81ecf | /*
*
* Authors: Maarten Lankhorst
*/
#include "priv.h"
#include <nvif/class.h>
void
gf100_mspdec_init(struct nvkm_falcon *mspdec)
{
struct nvkm_device *device = mspdec->engine.subdev.device;
nvkm_wr32(device, 0x085010, 0x0000fff2);
nvkm_wr32(device, 0x08501c, 0x0000fff2);
}
static const struct nvkm_falcon_func
gf... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c | 4,011 | utf_8 | 3ce917f1a0daf4c47fb56d371741995e | /*
*
* Authors: Ben Skeggs
*/
#include <engine/cipher.h>
#include <engine/fifo.h>
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <nvif/class.h>
static int
g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj... |
google | android | gf110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c | 3,574 | utf_8 | 3bbdbf83ab72b092d12505bc24ef6357 | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gf110_gr_init_sm_0[] = {
{... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c | 1,737 | utf_8 | e1cc3fedaec2be5db90352b76fd1e75e | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
static const struct nvkm_gr_func
gt215_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.tlb_flush = g84_gr_tlb_flush,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, 0x0030, &nv50_gr_object },
{ -1, -1, 0x502d, &nv50_gr_object }... |
google | android | gm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 13,475 | utf_8 | 649b29b6597b7c94ee29cf60f3627e0d | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/bios.h>
#include <subdev/bios/P0260.h>
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
stati... |
google | android | ctxgk110b | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c | 3,423 | utf_8 | 230e6244a3ea4df09719195234222a34 | /*
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gk110b_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x0000000... |
google | android | ctxgm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c | 35,623 | utf_8 | e248cca93c461bd93e14df63c3eb94eb | /*
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gm204_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x000000... |
google | android | nv2a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 4,272 | utf_8 | b5ecbd237bf7135ff0aa7714975ea58b | #include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct n... |
google | android | ctxgf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 44,143 | utf_8 | ae74cf11c30750872da4cfee0264a889 | /*
*
* Authors: Ben Skeggs
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************... |
google | android | nv10 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 33,554 | utf_8 | 0cc10680a5030af7eaee4a2598668917 | /*
*/
#include "nv10.h"
#include "regs.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
struct pipe_state {
u32 pipe_0x0000[0x040/4];
u32 pipe_0x0040[0x010/4];
u32 pipe_0x0200[0x0c0/4];
u32 pipe_0x4400[0x080/4];
u32 pipe_0x6400[0x3b... |
google | android | ctxgk110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c | 29,095 | utf_8 | ec59cc9a812262f24b9395ff4221cc44 | /*
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gk110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x000000... |
google | android | ctxgf110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c | 12,570 | utf_8 | cb8b8e08d5aaf60a7396e9b77c89f2f6 | /*
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x000000... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 14,080 | utf_8 | 885d4896e3ce5ff8721df236a9d6553a | /*
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
#include "regs.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
u64
nv40_gr_units(struct nvkm_gr *gr)
{
return nvkm_rd32(gr->engine.subdev.device, 0x1540);
}
/*******************************... |
google | android | nv30 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 7,085 | utf_8 | 66c8b8251b372c6417db929fbf6473e2 | #include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
s... |
google | android | gf104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c | 4,157 | utf_8 | 2b460e16b08910d7c40130cfe50279bb | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gf104_gr_init_ds_0[] = {
{ 0x4058... |
google | android | gf117 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c | 4,262 | utf_8 | 82736928cc040d60393391869c2f353b | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gf117_gr_init_pe_0[] = {
{... |
google | android | nv20 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 12,226 | utf_8 | f5bcaab57ff028279efb570f72bd1edc | #include "nv20.h"
#include "regs.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
/*******************************************************************************
* PGRAPH context
******************************... |
google | android | gk110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c | 5,847 | utf_8 | 69f0cd8720d9d682ac14d9fa14237664 | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/timer.h>
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gk110_gr... |
google | android | nv34 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 4,701 | utf_8 | 995893497d9b972467600b7b3c715dfd | #include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct n... |
google | android | ctxgk208 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c | 18,710 | utf_8 | e1e5f7dcd85672914e9f72bfbb192329 | /*
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gk208_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x000000... |
google | android | gf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c | 5,773 | utf_8 | 552c13b1a5b6655fe58ac7ba19da90f2 | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gf119_gr_init_pd_0[] = {
{ 0x4060... |
google | android | gm206 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c | 1,672 | utf_8 | db6fedbd032aa5e3107ada61b7dcc8a1 | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
static const struct gf100_gr_func
gm206_gr = {
.init = gm204_gr_init,
.mmio = gm204_gr_pack_mmio,
.ppc_nr = 2,
.grctx = &gm206_grctx,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, MAXWELL_B, &gf10... |
google | android | ctxgm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 35,335 | utf_8 | 2ab9107dcf7b59dd8d9b91614baba3fb | /*
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gm107_grctx_init... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 10,232 | utf_8 | 298828f4231220ae7fda07c3ea38788f | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gk104_gr_init_main_0[] = {
{ 0x40... |
google | android | gt200 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c | 1,698 | utf_8 | 778cd7d3dc8b4a0161932cec40d6745a | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
static const struct nvkm_gr_func
gt200_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.tlb_flush = g84_gr_tlb_flush,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, 0x0030, &nv50_gr_object },
{ -1, -1, 0x502d, &nv50_gr_object }... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c | 5,257 | utf_8 | 125d89e4f90f169d636da003baadab80 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/timer.h>
static const struct nvkm_bitfield nv50_gr_status[] = {
{ 0x00000001, "BUSY" }, /* set when any bit is set */
{ 0x00000002, "DISPATCH" },
{ 0x00000004, "UNK2" },
{ 0x00000008, "UNK3" },
{ 0x00000010, "UNK4" },
{ 0x00000020, "UNK5" },
{ 0... |
google | android | nv35 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 4,701 | utf_8 | 3a5a13696e77ddf5797eef502601ed50 | #include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct n... |
google | android | ctxgf117 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c | 8,299 | utf_8 | 62feb94102d305ab6d5692f54265d481 | /*
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf117_grctx_init... |
google | android | ctxnv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c | 20,120 | utf_8 | edf4d48c49d33bf3ebfcdf11ded9b785 | /*
*
* Authors: Ben Skeggs
*/
/* NVIDIA context programs handle a number of other conditions which are
* not implemented in our versions. It's not clear why NVIDIA context
* programs have this code, nor whether it's strictly necessary for
* correct operation. We'll implement additional handling if/when we
* di... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 23,957 | utf_8 | a1ddf58f72f2ad8d78e0542e839500ec | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
u64
nv50_gr_units(struct nvkm_gr *gr)
{
return nvkm_rd32(gr->engine.subdev.device, 0x1540);
}
/*******************************************************************************
* Graphics object... |
google | android | gk208 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c | 5,353 | utf_8 | 1d51f3ef8e616ca53094b42ac3051007 | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/timer.h>
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
g... |
google | android | mcp89 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c | 1,737 | utf_8 | 6b6491b79378e5e3e0192d752aaab2db | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
static const struct nvkm_gr_func
mcp89_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.tlb_flush = g84_gr_tlb_flush,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, 0x0030, &nv50_gr_object },
{ -1, -1, 0x502d, &nv50_gr_object }... |
google | android | gf108 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c | 3,871 | utf_8 | d7bfef435f6157d02f1bac96657def28 | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gf108_gr_init_gpc_unk_0[] = {
{ 0... |
google | android | ctxgk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | 34,336 | utf_8 | b23f21e565e9cf72bb20e565b884ff3b | /*
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gk104_grctx_init... |
google | android | gm20b | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 2,671 | utf_8 | 17a1db9365966cc8e5582c7e76a04795 | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/timer.h>
#include <nvif/class.h>
static void
gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 val;
/* TODO this needs to be removed once secure boot works */
if (1) {
nvkm_wr32(device, 0x10... |
google | android | gm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c | 11,689 | utf_8 | 8920b53e8234314dcbab56fc312e19fb | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gm204_gr_init_main_0[] = {
... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 39,993 | utf_8 | 26cd8cee97d41a36d56d70c62e9c18d3 | /*
*/
#include "priv.h"
#include "regs.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/instmem.h>
#include <subdev/timer.h>
static u32
nv04_gr_ctx_regs[] = {
0x0040053c,
0x00400544,
0x00400540,
0x00400548,
NV04_PGRAPH_CTX_SWITCH1,
NV04_... |
google | android | ctxgm20b | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c | 3,166 | utf_8 | 76c33b350a04ece9f4f775148a546db8 | /*
*/
#include "ctxgf100.h"
static void
gm20b_grctx_generate_r406028(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 tpc_per_gpc = 0;
int i;
for (i = 0; i < gr->gpc_nr; i++)
tpc_per_gpc |= gr->tpc_nr[i] << (4 * i);
nvkm_wr32(device, 0x406028, tpc_per_gpc);
nvkm_wr32(devic... |
google | android | ctxgf104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c | 3,381 | utf_8 | 26ddfa675ee41b916d7f6ca62b0714ef | /*
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
const struct gf100_gr_init
gf104_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{... |
google | android | nv44 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c | 3,758 | utf_8 | 6889e251e4966cd020e465f185cad361 | /*
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
#include "regs.h"
#include <subdev/fb.h>
#include <engine/fifo.h>
static void
nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
{
struct nv40_gr *gr = nv40_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fifo *fif... |
google | android | mcp79 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c | 1,666 | utf_8 | aa777ced294fda7a6ad256a98ebe2aa6 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
static const struct nvkm_gr_func
mcp79_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, 0x0030, &nv50_gr_object },
{ -1, -1, 0x502d, &nv50_gr_object },
{ -1, -1, 0x5039, &nv50_gr_o... |
google | android | ctxnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 126,376 | iso_8859_16 | c825d73d54fd66f7dd25057d09ff80cd | /*
*/
#define CP_FLAG_CLEAR 0
#define CP_FLAG_SET 1
#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
#define CP_FLAG_SWAP_DIRECTION_LOAD 0
#define CP_FLAG_SWAP_DIRECTION_SAVE 1
#define CP_FLAG_UNK01 ((0 * 32) + 1)
#define CP_FLAG_UNK01_CLEAR 0
#define... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c | 3,403 | utf_8 | d85ac6a075bb30809b0041acf135a60b | /*
*/
#include "priv.h"
#include <engine/fifo.h>
static void
nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->tile)
gr->func->tile(gr, region, tile);
}
u64
nvkm_gr_units(struct nvkm_gr *gr)
{
if (gr->func->units)
return gr->fun... |
google | android | nv17 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c | 2,424 | utf_8 | 4cca56bdf17fceb5576e37a4830e03cf | /*
*/
#include "nv10.h"
static const struct nvkm_gr_func
nv17_gr = {
.init = nv10_gr_init,
.intr = nv10_gr_intr,
.tile = nv10_gr_tile,
.chan_new = nv10_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object ... |
google | android | gk110b | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c | 3,951 | utf_8 | 5904da0dacd651fec1b734726762694f | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gk110b_gr_init_l1c_0[] = {
... |
google | android | ctxgm206 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm206.c | 2,563 | utf_8 | f556cb3253dbfe41c37b31d62bc4dfe6 | /*
*/
#include "ctxgf100.h"
static const struct gf100_gr_init
gm206_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
{ 0x418700, 1, 0x04, 0x00000002 },
{ 0x418704, 1, 0x04, 0x00000080 },
{ 0x418708, 1, 0x04, 0x40000000 },
{ 0x41870c, 2, 0x04, 0x00000000... |
google | android | ctxgf108 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c | 28,085 | utf_8 | 4393f9b34912ec492fcd5e22e126807c | /*
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf108_grctx_init_icmd_0[] = {
{ 0x0010... |
google | android | ctxgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c | 17,504 | utf_8 | 100ff1e36cf5a17f2d84ce326a54beea | /*
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf119_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x000000... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 50,335 | utf_8 | 2ca4c4ab0e4a14834e3e59fe2ca1a196 | /*
*
* Authors: Ben Skeggs
*/
#include "gf100.h"
#include "ctxgf100.h"
#include "fuc/os.h"
#include <core/client.h>
#include <core/option.h>
#include <subdev/fb.h>
#include <subdev/mc.h>
#include <subdev/pmu.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
/*****... |
google | android | nv25 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 4,650 | utf_8 | 8f055f67cc0696df466e6a226388c201 | #include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct n... |
google | android | ctxgk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 2,753 | utf_8 | ae7145fb0cc260a9426851c1abc0b614 | /*
*/
#include "ctxgf100.h"
#include "gf100.h"
#include <subdev/mc.h>
static void
gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
int idle_timeout_save;
int i;
gf100_gr_mm... |
google | android | nv15 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c | 2,438 | utf_8 | 5bd9940e6539edf0fdf7165d7837ba1b | /*
*/
#include "nv10.h"
static const struct nvkm_gr_func
nv15_gr = {
.init = nv10_gr_init,
.intr = nv10_gr_intr,
.tile = nv10_gr_tile,
.chan_new = nv10_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object ... |
google | android | gk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 8,874 | utf_8 | 9cfd3683084af2367d0dbecf5d228a50 | /*
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/timer.h>
#include <nvif/class.h>
static void
gk20a_gr_init_dtor(struct gf100_gr_pack *pack)
{
vfree(pack);
}
struct gk20a_fw_av
{
u32 addr;
u32 data;
};
static struct gf100_gr_pack *
gk20a_gr_av_to_init(struct gf100_gr_fuc *fuc)
{
struct gf100_gr_init... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c | 1,540 | utf_8 | a85aadeaf818c34a9156407dac804442 | /*
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gt215_msvld = {
.pmc_enable = 0x04008000,
.init = g98_msvld_init,
.sclass = {
{ -1, -1, GT212_MSVLD },
{}
}
};
int
gt215_msvld_new(struct nvkm_device *device, int index... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c | 1,505 | utf_8 | d4cc95f106a0af2a2263a7552b8f4433 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gk104_msvld = {
.pmc_enable = 0x00008000,
.init = gf100_msvld_init,
.sclass = {
{ -1, -1, GK104_MSVLD },
{}
}
};
int
gk104_msvld_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengi... |
google | android | mcp89 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c | 1,541 | utf_8 | 4b25899d3bd477f5bc35c5d19b63a411 | /*
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
mcp89_msvld = {
.pmc_enable = 0x04008000,
.init = g98_msvld_init,
.sclass = {
{ -1, -1, IGT21A_MSVLD },
{}
}
};
int
mcp89_msvld_new(struct nvkm_device *device, int inde... |
google | android | g98 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c | 1,727 | utf_8 | d9f6dd333eea7af49730741ae3e06ee4 | /*
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
void
g98_msvld_init(struct nvkm_falcon *msvld)
{
struct nvkm_device *device = msvld->engine.subdev.device;
nvkm_wr32(device, 0x084010, 0x0000ffd2);
nvkm_wr32(device, 0x08401c, 0x0000fff2);
}
static const struct... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c | 1,388 | utf_8 | 6faae3a7f506e30792c33a4f0b28ac15 | /*
*/
#include "priv.h"
int
nvkm_msvld_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
int index, struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, index, true, 0x084000, pengine);
} |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c | 1,714 | utf_8 | e90af916ddca82705f40222bf8a3bb6b | /*
*
* Authors: Maarten Lankhorst
*/
#include "priv.h"
#include <nvif/class.h>
void
gf100_msvld_init(struct nvkm_falcon *msvld)
{
struct nvkm_device *device = msvld->engine.subdev.device;
nvkm_wr32(device, 0x084010, 0x0000fff2);
nvkm_wr32(device, 0x08401c, 0x0000fff2);
}
static const struct nvkm_falcon_func
gf100... |
google | android | acpi | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c | 1,832 | utf_8 | 773f2476aa4f679aee3855409e57cd12 | /*
*
* Authors: Ben Skeggs
*/
#include "acpi.h"
#include <core/device.h>
#ifdef CONFIG_ACPI
static int
nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data)
{
struct nvkm_device *device =
container_of(nb, typeof(*device), acpi.nb);
struct acpi_bus_event *info = data;
if (!strcmp(info->device_... |
google | android | tegra | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 7,810 | utf_8 | 279d399739fe9bc2c68ca285d5c2d836 | /*
*/
#include <core/tegra.h>
#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
#include "priv.h"
static int
nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
{
int ret;
ret = regulator_enable(tdev->vdd);
if (ret)
goto err_power;
ret = clk_prepare_enable(tdev->clk);
if (ret)
goto err_clk;
ret = clk_prepare_enab... |
google | android | user | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 9,532 | utf_8 | 23359942ce3554651ed5f23dd7ebb47d | /*
*
* Authors: Ben Skeggs
*/
#define nvkm_udevice(p) container_of((p), struct nvkm_udevice, object)
#include "priv.h"
#include "ctrl.h"
#include <core/client.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
struct nvkm_udevice {
struct... |
google | android | pci | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c | 52,929 | utf_8 | ba758c70166897fbf4fcf48fdd614e45 | /*
*/
#include <core/pci.h>
#include "priv.h"
struct nvkm_device_pci_device {
u16 device;
const char *name;
const struct nvkm_device_pci_vendor *vendor;
};
struct nvkm_device_pci_vendor {
u16 vendor;
u16 device;
const char *name;
const struct nvkm_device_quirk quirk;
};
static const struct nvkm_device_pci_vendo... |
google | android | ctrl | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c | 5,856 | utf_8 | 1039101f5b7a3142af2c57f5d1883213 | /*
*/
#include "ctrl.h"
#include <core/client.h>
#include <subdev/clk.h>
#include <nvif/class.h>
#include <nvif/ioctl.h>
#include <nvif/unpack.h>
static int
nvkm_control_mthd_pstate_info(struct nvkm_control *ctrl, void *data, u32 size)
{
union {
struct nvif_control_pstate_info_v0 v0;
} *args = data;
struct nvkm_c... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 61,148 | utf_8 | 4784b4d179a9285fd6b57bed7247ab00 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "acpi.h"
#include <core/notify.h>
#include <core/option.h>
#include <subdev/bios.h>
static DEFINE_MUTEX(nv_devices_mutex);
static LIST_HEAD(nv_devices);
static struct nvkm_device *
nvkm_device_find_locked(u64 handle)
{
struct nvkm_device *device;
list_for_ea... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c | 2,772 | utf_8 | 4d663e749c418ab415dea6ffa372ab91 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "fuc/gt215.fuc3.h"
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <nvif/class.h>
static const struct nvkm_enum
gt215_ce_isr_error_name[] = {
{ 0x0001, "ILLEGAL_MTHD" },
{ 0x0002, "INVALID_ENUM" },
... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c | 2,158 | utf_8 | f98fa682cef7d5c7ceca5ec8891460b0 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <nvif/class.h>
void
gk104_ce_intr(struct nvkm_engine *ce)
{
const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x1000;
struct nvkm_subdev *subdev = &ce->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x104908 + base)... |
google | android | gm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c | 1,807 | utf_8 | f4fcf5e5ec0fc590ef2e8ab579eff5ad | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_engine_func
gm204_ce = {
.intr = gk104_ce_intr,
.sclass = {
{ -1, -1, MAXWELL_DMA_COPY_A },
{}
}
};
int
gm204_ce_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
{
if (index == NVKM_... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c | 2,415 | utf_8 | ae67a00dd06653f8cd67cd03819f3215 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "fuc/gf100.fuc3.h"
#include <nvif/class.h>
static void
gf100_ce_init(struct nvkm_falcon *ce)
{
struct nvkm_device *device = ce->engine.subdev.device;
const int index = ce->engine.subdev.index - NVKM_ENGINE_CE0;
nvkm_wr32(device, ce->addr + 0x084, index);
}
... |
google | android | g98 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c | 2,697 | utf_8 | 5cc2eb8f5cc31327a182b5a28157ac7b | /*
*
* Authors: Ben Skeggs
*/
#include <engine/sec.h>
#include <engine/fifo.h>
#include "fuc/g98.fuc0s.h"
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <nvif/class.h>
static const struct nvkm_enum g98_sec_isr_error_name[] = {
{ 0x0000, "ILLEGAL_MTHD" },
{ 0x0001, "INVALID_BITFIE... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c | 1,537 | utf_8 | f0ccedd56b39c4110205416611012c01 | /*
*
* Authors: Ben Skeggs, Ilia Mirkin
*/
#include <engine/vp.h>
#include <nvif/class.h>
static const struct nvkm_xtensa_func
g84_vp = {
.pmc_enable = 0x01020000,
.fifo_val = 0x111,
.unkd28 = 0x9c544,
.sclass = {
{ -1, -1, NV74_VP2 },
{}
}
};
int
g84_vp_new(struct nvkm_device *device, int index, struct nvk... |
google | android | usernv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c | 4,368 | utf_8 | 78d944b4e4d899e74f155e11557163dd | /*
*
* Authors: Ben Skeggs
*/
#define nv50_dmaobj(p) container_of((p), struct nv50_dmaobj, base)
#include "user.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
struct nv50_dmaobj {
struct nvkm_dmaobj base;
u32 flags0;
u32 flags5;
};
stat... |
google | android | user | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c | 4,092 | utf_8 | 2d62d420c7c9a2014daccbef501dcfb6 | /*
*
* Authors: Ben Skeggs
*/
#include "user.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static int
nvkm_dmaobj_bind(struct nvkm_object *base, struct nvkm_gpuobj *gpuobj,
int align, struct nvkm_gpuobj **pg... |
google | android | gf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c | 1,406 | utf_8 | 3fb3a24419688385c8db71bb2489e819 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "user.h"
static const struct nvkm_dma_func
gf119_dma = {
.class_new = gf119_dmaobj_new,
};
int
gf119_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&gf119_dma, device, index, pdma);
} |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c | 1,402 | utf_8 | 57d56f382951406765109460708b9636 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "user.h"
static const struct nvkm_dma_func
nv50_dma = {
.class_new = nv50_dmaobj_new,
};
int
nv50_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&nv50_dma, device, index, pdma);
} |
google | android | usergf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c | 3,785 | utf_8 | 40724d51e64e0888d07d611c165be926 | /*
*
* Authors: Ben Skeggs
*/
#define gf119_dmaobj(p) container_of((p), struct gf119_dmaobj, base)
#include "user.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
struct gf119_dmaobj {
struct nvkm_dmaobj base;
u32 flags0;
};
static int
gf1... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c | 1,402 | utf_8 | b8132b9433477ce08af0b5b5a28b2973 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "user.h"
static const struct nvkm_dma_func
nv04_dma = {
.class_new = nv04_dmaobj_new,
};
int
nv04_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&nv04_dma, device, index, pdma);
} |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c | 4,306 | utf_8 | 92c2cac8a3133fba341e75bb2391c1cd | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/client.h>
#include <engine/fifo.h>
#include <nvif/class.h>
struct nvkm_dmaobj *
nvkm_dma_search(struct nvkm_dma *dma, struct nvkm_client *client, u64 object)
{
struct rb_node *node = client->dmaroot.rb_node;
while (node) {
struct nvkm_dmaobj *dmaobj ... |
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