plateform stringclasses 1
value | repo_name stringclasses 2
values | name stringlengths 1 78 | ext stringclasses 2
values | path stringlengths 15 1.11k | size int64 1 8.55M | source_encoding stringclasses 11
values | md5 stringlengths 32 32 | text stringlengths 0 8.49M |
|---|---|---|---|---|---|---|---|---|
google | android | usernv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c | 3,803 | utf_8 | 35b5a66c80b13de546e6f5b84af03466 | /*
*
* Authors: Ben Skeggs
*/
#define nv04_dmaobj(p) container_of((p), struct nv04_dmaobj, base)
#include "user.h"
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu/nv04.h>
#include <nvif/class.h>
struct nv04_dmaobj {
struct nvkm_dmaobj base;
bool clone;
u32 flags0;
u32 flags2;
};
static int
n... |
google | android | usergf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c | 4,105 | utf_8 | 35a509ff50a25a8a7a6a48b602b8b34d | /*
*
* Authors: Ben Skeggs
*/
#define gf100_dmaobj(p) container_of((p), struct gf100_dmaobj, base)
#include "user.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
struct gf100_dmaobj {
struct nvkm_dmaobj base;
u32 flags0;
u32 flags5;
};
s... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c | 1,406 | utf_8 | 7df9f707bba54440e03fe30b954b4c19 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "user.h"
static const struct nvkm_dma_func
gf100_dma = {
.class_new = gf100_dmaobj_new,
};
int
gf100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&gf100_dma, device, index, pdma);
} |
google | android | dmanv17 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c | 3,300 | utf_8 | 260e1c549740e6d49089e979873421c6 | /*
*
* Authors: Ben Skeggs
*/
#include "channv04.h"
#include "regsnv04.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/instmem.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static int
nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
void *data, u32 size, str... |
google | android | channv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c | 7,974 | utf_8 | 474856f13afd58e0632a609f2e6fdc65 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <subdev/mmu.h>
#include <subdev/timer.h>
static int
nv50_fifo_chan_engine_addr(struct nvkm_engine *engine)
{
switch (engine->subdev.index) {
case NVKM_ENGINE_DMAOBJ:
case NVKM_ENGINE_SW : return -1;
c... |
google | android | dmanv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c | 7,303 | utf_8 | 9a6863654e307bfe0af7a2eadbf41dc4 | /*
*
* Authors: Ben Skeggs
*/
#include "channv04.h"
#include "regsnv04.h"
#include <core/client.h>
#include <core/ramht.h>
#include <subdev/instmem.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static bool
nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx)
{
switch (engine->subdev.index) {
... |
google | android | nv10 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c | 2,111 | utf_8 | 94d2857727206db433aff6f2b12d436a | /*
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "channv04.h"
#include "regsnv04.h"
static const struct nv04_fifo_ramfc
nv10_fifo_ramfc[] = {
{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
{ 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
{ 16, 0, 0x0c, ... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 4,206 | utf_8 | cded40352a5e575f9c1e896e2e01f29b | /*
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "channv04.h"
#include "regsnv04.h"
#include <core/ramht.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
static const struct nv04_fifo_ramfc
nv40_fifo_ramfc[] = {
{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA... |
google | android | gpfifogm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c | 1,372 | utf_8 | 3f0d3de2457901ee5a31a5ae84748739 | /*
*
* Authors: Ben Skeggs
*/
#include "changk104.h"
#include <nvif/class.h>
const struct nvkm_fifo_chan_oclass
gm204_fifo_gpfifo_oclass = {
.base.oclass = MAXWELL_CHANNEL_GPFIFO_A,
.base.minver = 0,
.base.maxver = 0,
.ctor = gk104_fifo_gpfifo_new,
}; |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 21,238 | utf_8 | e063ed88a040a4d52bfe20c5e29bb506 | /*
*
* Authors: Ben Skeggs
*/
#include "gk104.h"
#include "changk104.h"
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <subdev/bar.h>
#include <engine/sw.h>
#include <nvif/class.h>
void
gk104_fifo_uevent_fini(struct nvkm_fifo *fifo)
{
struct nvkm_device *device = fifo->engine.subd... |
google | android | chang84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c | 8,195 | utf_8 | 9d95489bee0f4e92ff20338da3543a0f | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <subdev/mmu.h>
#include <subdev/timer.h>
#include <nvif/class.h>
int
g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
struct nvkm_event **pevent)
{
switch (type) {
case G82_CHANNEL_DMA_V0_NTF... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c | 2,037 | utf_8 | ed9dcdde912eb74b58326cf43ae02116 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "channv50.h"
static void
g84_fifo_uevent_fini(struct nvkm_fifo *fifo)
{
struct nvkm_device *device = fifo->engine.subdev.device;
nvkm_mask(device, 0x002140, 0x40000000, 0x00000000);
}
static void
g84_fifo_uevent_init(struct nvkm_fifo *fifo)
{
struct nvkm_de... |
google | android | gpfifogk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 9,857 | utf_8 | d3e0e18a3dbf729cad97a9c3253a6cb0 | /*
*
* Authors: Ben Skeggs
*/
#include "changk104.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static int
gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan)
{
struct gk104_fifo *fifo =... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c | 4,141 | utf_8 | 48c7845d6d1835ace48c8014b281b3ee | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "channv50.h"
#include <core/gpuobj.h>
static void
nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo)
{
struct nvkm_device *device = fifo->base.engine.subdev.device;
struct nvkm_memory *cur;
int i, p;
cur = fifo->runlist[fifo->cur_runlist];
fifo->cur_... |
google | android | gk208 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c | 1,662 | utf_8 | 62b61a144306fc1cf95c9bd0ee335950 | /*
*
* Authors: Ben Skeggs
*/
#include "gk104.h"
#include "changk104.h"
static const struct nvkm_fifo_func
gk208_fifo = {
.dtor = gk104_fifo_dtor,
.oneinit = gk104_fifo_oneinit,
.init = gk104_fifo_init,
.fini = gk104_fifo_fini,
.intr = gk104_fifo_intr,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk1... |
google | android | gm20b | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c | 1,664 | utf_8 | c903431d05ececf8cda93e2cc908ad54 | /*
*/
#include "gk104.h"
#include "changk104.h"
static const struct nvkm_fifo_func
gm20b_fifo = {
.dtor = gk104_fifo_dtor,
.oneinit = gk104_fifo_oneinit,
.init = gk104_fifo_init,
.fini = gk104_fifo_fini,
.intr = gk104_fifo_intr,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.cha... |
google | android | gm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c | 1,662 | utf_8 | fab9acd1f3f071a4f254fcfbd80dbe5b | /*
*
* Authors: Ben Skeggs
*/
#include "gk104.h"
#include "changk104.h"
static const struct nvkm_fifo_func
gm204_fifo = {
.dtor = gk104_fifo_dtor,
.oneinit = gk104_fifo_oneinit,
.init = gk104_fifo_init,
.fini = gk104_fifo_fini,
.intr = gk104_fifo_intr,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk1... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 11,485 | utf_8 | c28e026fd3ee9bb9ce64ffe1f54365ee | /*
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "channv04.h"
#include "regsnv04.h"
#include <core/client.h>
#include <core/ramht.h>
#include <subdev/instmem.h>
#include <subdev/timer.h>
#include <engine/sw.h>
static const struct nv04_fifo_ramfc
nv04_fifo_ramfc[] = {
{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DM... |
google | android | gpfifogf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c | 8,969 | utf_8 | 4473feba6b307a69266d558c79d66e0d | /*
*
* Authors: Ben Skeggs
*/
#include "changf100.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static u32
gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
{
switch (engine->subdev.index) {
case NVKM_E... |
google | android | dmanv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c | 3,154 | utf_8 | e9afcccbaa5a2694b672ecf1c879a756 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static int
nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
struct nvkm_object *p... |
google | android | gpfifonv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c | 3,153 | utf_8 | b5f5e2faf5c8393e8555252ac684c208 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static int
nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
struct nvkm_obj... |
google | android | dmag84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c | 3,263 | utf_8 | 6992c3dde3ce814b0d2895d3a89515b6 | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static int
g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
struct nvkm_object *par... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 6,671 | utf_8 | 6d65a74d17173a8c75138498e156607e | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "chan.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <core/notify.h>
#include <nvif/event.h>
#include <nvif/unpack.h>
void
nvkm_fifo_pause(struct nvkm_fifo *fifo, unsigned long *flags)
{
return fifo->func->pause(fifo, flags);
}
void
nvkm_fifo_s... |
google | android | nv17 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c | 3,501 | utf_8 | cfb377bb2568f71dbd23fbf33b2c89d1 | /*
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "channv04.h"
#include "regsnv04.h"
#include <core/ramht.h>
#include <subdev/instmem.h>
static const struct nv04_fifo_ramfc
nv17_fifo_ramfc[] = {
{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
{ 32, 0, 0x08... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 17,678 | utf_8 | aad544e11a88d51817c419365f0e8079 | /*
*
* Authors: Ben Skeggs
*/
#include "gf100.h"
#include "changf100.h"
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <subdev/bar.h>
#include <engine/sw.h>
#include <nvif/class.h>
static void
gf100_fifo_uevent_init(struct nvkm_fifo *fifo)
{
struct nvkm_device *device = fifo->engi... |
google | android | dmanv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c | 7,095 | utf_8 | b948f0f0303c5f5c36eb4f1e0bfdfb4c | /*
*
* Authors: Ben Skeggs
*/
#include "channv04.h"
#include "regsnv04.h"
#include <core/client.h>
#include <core/ramht.h>
#include <subdev/instmem.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
void
nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie)
{
struct nv04_fifo_chan *chan = nv04_fifo_ch... |
google | android | chan | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c | 10,831 | utf_8 | 2f0ca2f31eab5bed09aebc265af67f6f | /*
*
* Authors: Ben Skeggs
*/
#include "chan.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <core/oproxy.h>
#include <subdev/mmu.h>
#include <engine/dma.h>
struct nvkm_fifo_chan_object {
struct nvkm_oproxy oproxy;
struct nvkm_fifo_chan *chan;
int hash;
};
static int
nvkm_fifo_chan_child_fini(struct... |
google | android | gpfifog84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c | 3,262 | utf_8 | 2eb63d888674affb3f7d93aa12cad8eb | /*
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include <core/client.h>
#include <core/ramht.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static int
g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
struct nvkm_objec... |
google | android | gk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c | 1,664 | utf_8 | 5d39fd20b25d3846b4f7c9faefb9bd09 | /*
*/
#include "gk104.h"
#include "changk104.h"
static const struct nvkm_fifo_func
gk20a_fifo = {
.dtor = gk104_fifo_dtor,
.oneinit = gk104_fifo_oneinit,
.init = gk104_fifo_init,
.fini = gk104_fifo_fini,
.intr = gk104_fifo_intr,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.cha... |
google | android | dmanv10 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c | 3,253 | utf_8 | f57fe80216c96b49060a21cdbbe523cc | /*
*
* Authors: Ben Skeggs
*/
#include "channv04.h"
#include "regsnv04.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/instmem.h>
#include <nvif/class.h>
#include <nvif/unpack.h>
static int
nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
void *data, u32 size, str... |
google | android | option | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/option.c | 3,590 | utf_8 | caaf08a53ccab59d8cdcb542f97a1e39 | /*
*
* Authors: Ben Skeggs
*/
#include <core/option.h>
#include <core/debug.h>
const char *
nvkm_stropt(const char *optstr, const char *opt, int *arglen)
{
while (optstr && *optstr != '\0') {
int len = strcspn(optstr, ",=");
switch (optstr[len]) {
case '=':
if (!strncasecmpz(optstr, opt, len)) {
optstr... |
google | android | object | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/object.c | 6,808 | utf_8 | 8a7de8c06789b11508a0f77bb19c4158 | /*
*
* Authors: Ben Skeggs
*/
#include <core/object.h>
#include <core/client.h>
#include <core/engine.h>
int
nvkm_object_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
if (likely(object->func->mthd))
return object->func->mthd(object, mthd, data, size);
return -ENODEV;
}
int
nvkm_object_ntfy(s... |
google | android | enum | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/enum.c | 1,725 | utf_8 | 3090bfd9c90cd1e428b93ab980494b80 | /*
*
*/
#include <core/enum.h>
const struct nvkm_enum *
nvkm_enum_find(const struct nvkm_enum *en, u32 value)
{
while (en->name) {
if (en->value == value)
return en;
en++;
}
return NULL;
}
void
nvkm_snprintbf(char *data, int size, const struct nvkm_bitfield *bf, u32 value)
{
bool space = false;
while (siz... |
google | android | notify | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/notify.c | 4,759 | utf_8 | ab3a1226b270a4cf7a6173c5a4b43547 | /*
*/
#include <core/notify.h>
#include <core/event.h>
static inline void
nvkm_notify_put_locked(struct nvkm_notify *notify)
{
if (notify->block++ == 0)
nvkm_event_put(notify->event, notify->types, notify->index);
}
void
nvkm_notify_put(struct nvkm_notify *notify)
{
struct nvkm_event *event = notify->event;
unsig... |
google | android | mm | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/mm.c | 7,390 | utf_8 | a5443236efff7aa996b50568bfb4ed16 | /*
*
* Authors: Ben Skeggs
*/
#include <core/mm.h>
#define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \
list_entry((root)->nl_entry.dir, struct nvkm_mm_node, nl_entry)
void
nvkm_mm_dump(struct nvkm_mm *mm, const char *header)
{
struct nvkm_mm_node *node;
printk(KERN_ERR "nvkm: %s\n", h... |
google | android | gpuobj | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 6,659 | utf_8 | 8caa75225f582c6d37f619173a581adc | /*
*
* Authors: Ben Skeggs
*/
#include <core/gpuobj.h>
#include <core/engine.h>
#include <subdev/instmem.h>
#include <subdev/bar.h>
#include <subdev/mmu.h>
/* fast-path, where backend is able to provide direct pointer to memory */
static u32
nvkm_gpuobj_rd32_fast(struct nvkm_gpuobj *gpuobj, u32 offset)
{
return ior... |
google | android | client | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/client.c | 7,650 | utf_8 | 2f6f94c8dc65c2745df82b689ebddcb0 | /*
*
* Authors: Ben Skeggs
*/
#include <core/client.h>
#include <core/device.h>
#include <core/notify.h>
#include <core/option.h>
#include <nvif/class.h>
#include <nvif/event.h>
#include <nvif/unpack.h>
struct nvkm_client_notify {
struct nvkm_client *client;
struct nvkm_notify n;
u8 version;
u8 size;
union {
... |
google | android | memory | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/memory.c | 2,016 | utf_8 | 4d9cb50f297cf3a998a4c124e77b58e0 | /*
*/
#include <core/memory.h>
#include <subdev/instmem.h>
void
nvkm_memory_ctor(const struct nvkm_memory_func *func,
struct nvkm_memory *memory)
{
memory->func = func;
}
void
nvkm_memory_del(struct nvkm_memory **pmemory)
{
struct nvkm_memory *memory = *pmemory;
if (memory && !WARN_ON(!memory->func)) {
if (mem... |
google | android | engine | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/engine.c | 4,488 | utf_8 | b2edfad3b5cd7863963f37a49658fa0f | /*
*
* Authors: Ben Skeggs
*/
#include <core/engine.h>
#include <core/device.h>
#include <core/option.h>
#include <subdev/fb.h>
void
nvkm_engine_unref(struct nvkm_engine **pengine)
{
struct nvkm_engine *engine = *pengine;
if (engine) {
mutex_lock(&engine->subdev.mutex);
if (--engine->usecount == 0)
nvkm_sub... |
google | android | oproxy | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/oproxy.c | 5,270 | utf_8 | 54c256b0876e13132eca6295bc633ddf | /*
*/
#include <core/oproxy.h>
static int
nvkm_oproxy_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
return nvkm_object_mthd(nvkm_oproxy(object)->object, mthd, data, size);
}
static int
nvkm_oproxy_ntfy(struct nvkm_object *object, u32 mthd,
struct nvkm_event **pevent)
{
return nvkm_object_ntfy... |
google | android | ioctl | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 10,926 | utf_8 | d8a3296c2b9fbc9dc7833c8209332c07 | /*
*/
#include <core/ioctl.h>
#include <core/client.h>
#include <core/engine.h>
#include <nvif/unpack.h>
#include <nvif/ioctl.h>
static int
nvkm_ioctl_nop(struct nvkm_object *object, void *data, u32 size)
{
union {
struct nvif_ioctl_nop_v0 v0;
} *args = data;
int ret;
nvif_ioctl(object, "nop size %d\n", size);
... |
google | android | subdev | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/subdev.c | 5,666 | utf_8 | ee7c3da67a54f7da676ccac78bd590ed | /*
*
* Authors: Ben Skeggs
*/
#include <core/subdev.h>
#include <core/device.h>
#include <core/option.h>
static struct lock_class_key nvkm_subdev_lock_class[NVKM_SUBDEV_NR];
const char *
nvkm_subdev_name[NVKM_SUBDEV_NR] = {
[NVKM_SUBDEV_BAR ] = "bar",
[NVKM_SUBDEV_VBIOS ] = "bios",
[NVKM_SUBDEV_BUS ] = "bu... |
google | android | ramht | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/ramht.c | 4,096 | utf_8 | 22fc68e559dc0f52374f84b7db41a56b | /*
*/
#include <core/ramht.h>
#include <core/engine.h>
static u32
nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle)
{
u32 hash = 0;
while (handle) {
hash ^= (handle & ((1 << ramht->bits) - 1));
handle >>= ramht->bits;
}
hash ^= chid << (ramht->bits - 4);
return hash;
}
struct nvkm_gpuobj *
nvkm_... |
google | android | event | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/core/event.c | 2,932 | utf_8 | 9c8956b66f7c5c52c5434fe4e6f52758 | /*
*/
#include <core/event.h>
#include <core/notify.h>
void
nvkm_event_put(struct nvkm_event *event, u32 types, int index)
{
assert_spin_locked(&event->refs_lock);
while (types) {
int type = __ffs(types); types &= ~(1 << type);
if (--event->refs[index * event->types_nr + type] == 0) {
if (event->func->fini)
... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c | 1,760 | utf_8 | a4496e6dda4d951fe3d898541f8df9db | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "fuc/gt215.fuc3.h"
static void
gt215_pmu_reset(struct nvkm_pmu *pmu)
{
struct nvkm_device *device = pmu->subdev.device;
nvkm_mask(device, 0x022210, 0x00000001, 0x00000000);
nvkm_mask(device, 0x022210, 0x00000001, 0x00000001);
}
static const struct nvkm_pmu_... |
google | android | gm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c | 1,596 | utf_8 | 76f77fce46ba9e4576f5c7c8398bdec3 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#define gk208_pmu_code gm107_pmu_code
#define gk208_pmu_data gm107_pmu_data
#include "fuc/gk208.fuc5.h"
static const struct nvkm_pmu_func
gm107_pmu = {
.code.data = gm107_pmu_code,
.code.size = sizeof(gm107_pmu_code),
.data.data = gm107_pmu_data,
.data.size = sizeo... |
google | android | gk110 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c | 3,148 | utf_8 | b6ac5d9287e850eedcd4f30be077dd60 | /*
*
* Authors: Ben Skeggs
*/
#define gf119_pmu_code gk110_pmu_code
#define gf119_pmu_data gk110_pmu_data
#include "priv.h"
#include "fuc/gf119.fuc4.h"
#include <subdev/timer.h>
void
gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
{
struct nvkm_device *device = pmu->subdev.device;
static const struct {
u32 add... |
google | android | gf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c | 1,520 | utf_8 | e052d984eca7dddf47567915e7e8210c | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "fuc/gf119.fuc4.h"
static const struct nvkm_pmu_func
gf119_pmu = {
.code.data = gf119_pmu_code,
.code.size = sizeof(gf119_pmu_code),
.data.data = gf119_pmu_data,
.data.size = sizeof(gf119_pmu_data),
};
int
gf119_pmu_new(struct nvkm_device *device, int inde... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c | 3,545 | utf_8 | fd5f22fa57b397e8baab134f8d8306b9 | /*
*
* Authors: Ben Skeggs
*/
#define gf119_pmu_code gk104_pmu_code
#define gf119_pmu_data gk104_pmu_data
#include "priv.h"
#include "fuc/gf119.fuc4.h"
#include <core/option.h>
#include <subdev/fuse.h>
#include <subdev/timer.h>
static void
magic_(struct nvkm_device *device, u32 ctrl, int size)
{
nvkm_wr32(device, 0... |
google | android | gk208 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c | 1,545 | utf_8 | f5688706954097f3774f6d691d5c8249 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "fuc/gk208.fuc5.h"
static const struct nvkm_pmu_func
gk208_pmu = {
.code.data = gk208_pmu_code,
.code.size = sizeof(gk208_pmu_code),
.data.data = gk208_pmu_data,
.data.size = sizeof(gk208_pmu_data),
.pgob = gk110_pmu_pgob,
};
int
gk208_pmu_new(struct nvkm... |
google | android | memx | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c | 4,650 | utf_8 | 532036b7d84f4be13a506e252161d1d8 | #ifndef __NVKM_PMU_MEMX_H__
#define __NVKM_PMU_MEMX_H__
#include "priv.h"
struct nvkm_memx {
struct nvkm_pmu *pmu;
u32 base;
u32 size;
struct {
u32 mthd;
u32 size;
u32 data[64];
} c;
};
static void
memx_out(struct nvkm_memx *memx)
{
struct nvkm_device *device = memx->pmu->subdev.device;
int i;
if (memx... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c | 7,974 | utf_8 | c5595cf68e7cd263804695257afdd896 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <subdev/timer.h>
void
nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
{
if (pmu && pmu->func->pgob)
pmu->func->pgob(pmu, enable);
}
int
nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
u32 process, u32 message, u32 data0, u32 data1)
{
struct nvkm_... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c | 1,520 | utf_8 | aeca1135e1dec8a5b64e277f1dbd42e3 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "fuc/gf100.fuc3.h"
static const struct nvkm_pmu_func
gf100_pmu = {
.code.data = gf100_pmu_code,
.code.size = sizeof(gf100_pmu_code),
.data.data = gf100_pmu_data,
.data.size = sizeof(gf100_pmu_data),
};
int
gf100_pmu_new(struct nvkm_device *device, int inde... |
google | android | gk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c | 6,176 | utf_8 | cba0a4e0bbae754c9de3b6def10d6979 | /*
*/
#define gk20a_pmu(p) container_of((p), struct gk20a_pmu, base.subdev)
#include "priv.h"
#include <subdev/clk.h>
#include <subdev/timer.h>
#include <subdev/volt.h>
#define BUSY_SLOT 0
#define CLK_SLOT 7
struct gk20a_pmu_dvfs_data {
int p_load_target;
int p_load_max;
int p_smooth;
unsigned int avg_load;
};
str... |
google | android | gm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c | 1,553 | utf_8 | 08351389e1c8769db51f2b4b3be8a2ba | /*
*
* Authors: Martin Peres
*/
#include "priv.h"
static u32
gm107_fuse_read(struct nvkm_fuse *fuse, u32 addr)
{
struct nvkm_device *device = fuse->subdev.device;
return nvkm_rd32(device, 0x021100 + addr);
}
static const struct nvkm_fuse_func
gm107_fuse = {
.read = gm107_fuse_read,
};
int
gm107_fuse_new(struct nv... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c | 1,855 | utf_8 | ee677c5deba83dd3dceb730d3285c7b1 | /*
*
* Authors: Martin Peres
*/
#include "priv.h"
static u32
nv50_fuse_read(struct nvkm_fuse *fuse, u32 addr)
{
struct nvkm_device *device = fuse->subdev.device;
unsigned long flags;
u32 fuse_enable, val;
/* racy if another part of nvkm start writing to this reg */
spin_lock_irqsave(&fuse->lock, flags);
fuse_e... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c | 1,789 | utf_8 | f8b8c86a7607b636b0ec960fa9a32515 | /*
*
* Authors: Martin Peres
*/
#include "priv.h"
u32
nvkm_fuse_read(struct nvkm_fuse *fuse, u32 addr)
{
return fuse->func->read(fuse, addr);
}
static void *
nvkm_fuse_dtor(struct nvkm_subdev *subdev)
{
return nvkm_fuse(subdev);
}
static const struct nvkm_subdev_func
nvkm_fuse = {
.dtor = nvkm_fuse_dtor,
};
int
n... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c | 1,947 | utf_8 | f971eb0f596c6ac1ce5806993347a500 | /*
*
* Authors: Martin Peres
*/
#include "priv.h"
static u32
gf100_fuse_read(struct nvkm_fuse *fuse, u32 addr)
{
struct nvkm_device *device = fuse->subdev.device;
unsigned long flags;
u32 fuse_enable, unk, val;
/* racy if another part of nvkm start writing to these regs */
spin_lock_irqsave(&fuse->lock, flags);... |
google | android | gpio | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c | 2,826 | utf_8 | ca27705bf1d7c95bf30002b6308703ca | /*
*
* Authors: Ben Skeggs
*/
#include <subdev/volt.h>
#include <subdev/bios.h>
#include <subdev/bios/gpio.h>
#include <subdev/gpio.h>
static const u8 tags[] = {
DCB_GPIO_VID0, DCB_GPIO_VID1, DCB_GPIO_VID2, DCB_GPIO_VID3,
DCB_GPIO_VID4, DCB_GPIO_VID5, DCB_GPIO_VID6, DCB_GPIO_VID7,
};
int
nvkm_voltgpio_get(struct n... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.c | 1,533 | utf_8 | 161878c39c383411cebc089df83ec1b7 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static const struct nvkm_volt_func
nv40_volt = {
.vid_get = nvkm_voltgpio_get,
.vid_set = nvkm_voltgpio_set,
};
int
nv40_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
{
struct nvkm_volt *volt;
int ret;
ret = nvkm_volt_new_(&nv40_volt, d... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c | 3,580 | utf_8 | efcbd624130ee218b2730f6c203daf20 | /*
*
* Authors: Martin Peres
*/
#include "priv.h"
#include <subdev/volt.h>
#include <subdev/gpio.h>
#include <subdev/bios.h>
#include <subdev/bios/volt.h>
#define gk104_volt(p) container_of((p), struct gk104_volt, base)
struct gk104_volt {
struct nvkm_volt base;
struct nvbios_volt bios;
};
int
gk104_volt_get(struc... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c | 5,029 | utf_8 | 959406f7a29ba16d10e78c57237df1f8 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bios/vmap.h>
#include <subdev/bios/volt.h>
int
nvkm_volt_get(struct nvkm_volt *volt)
{
int ret, i;
if (volt->func->volt_get)
return volt->func->volt_get(volt);
ret = volt->func->vid_get(volt);
if (ret >= 0) {
for (i = 0... |
google | android | gk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c | 5,663 | utf_8 | 2821ae38906b0e9003b9501ae7cfedc4 | /*
*/
#define gk20a_volt(p) container_of((p), struct gk20a_volt, base)
#include "priv.h"
#include <core/tegra.h>
struct cvb_coef {
int c0;
int c1;
int c2;
int c3;
int c4;
int c5;
};
struct gk20a_volt {
struct nvkm_volt base;
struct regulator *vdd;
};
const struct cvb_coef gk20a_cvb_coef[] = {
/* MHz, c... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c | 13,599 | utf_8 | 234e0c810813a862a3ba56707aa2dffe | /*
*
* Authors: Ben Skeggs
* Roy Spliet
*/
#define gt215_clk(p) container_of((p), struct gt215_clk, base)
#include "gt215.h"
#include "pll.h"
#include <engine/fifo.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
struct gt215_clk {
struct nvkm_clk base;
struct gt215_clk_... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c | 5,911 | utf_8 | 6c57d55a9d1098177df4c8f4eb11cf45 | /*
*
* Authors: Ben Skeggs
*/
#define nv40_clk(p) container_of((p), struct nv40_clk, base)
#include "priv.h"
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
struct nv40_clk {
struct nvkm_clk base;
u32 ctrl;
u32 npll_ctrl;
u32 npll_coef;
u32 spll;
};
static u32
read_pll_1(struct nv40_clk *... |
google | android | pllnv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c | 6,666 | utf_8 | dbb22fbbce3ec8b76134e982590c45cd | /*
*/
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
static int
getMNP_single(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
int *pN, int *pM, int *pP)
{
/* Find M, N and P for a single stage PLL
*
* Note that some bioses (NV3x) have lookup tables of precomputed MNP
... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 12,775 | utf_8 | 5505b91ba713d80263b285b15583c9de | /*
*
* Authors: Ben Skeggs
*/
#define gk104_clk(p) container_of((p), struct gk104_clk, base)
#include "priv.h"
#include "pll.h"
#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
struct gk104_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
u32 dsrc;
u32 ddiv;
u32 coef;
};
struct gk104_clk... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c | 1,787 | utf_8 | 0b9da318c486fc8f180e7b47bcadfecb | /*
*/
#include "nv50.h"
static const struct nvkm_clk_func
g84_clk = {
.read = nv50_clk_read,
.calc = nv50_clk_calc,
.prog = nv50_clk_prog,
.tidy = nv50_clk_tidy,
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
{ nv_clk_src_shader , 0x... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c | 15,044 | utf_8 | df1b207aac9fc5576ba664722c8372db | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include "pll.h"
#include "seq.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
static u32
read_div(struct nv50_clk *clk)
{
struct nvkm_device *device = clk->base.subdev.device;
switch (device->chipset) {
case 0x50: /* it exists, but only has bit 31, not the... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c | 2,449 | utf_8 | b190243c6d61ff88c714e5abe95a75ab | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/devinit/nv04.h>
int
nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info,
int clk, struct nvkm_pll_vals *pv)
{
int N1, M1, N2, M2, P;
int ret = nv04_pll_calc(&clo... |
google | android | pllgt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c | 2,507 | utf_8 | b325a1231b271ace66a28eaf84271b9f | /*
*
* Authors: Ben Skeggs
*/
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
int
gt215_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info,
u32 freq, int *pN, int *pfN, int *pM, int *P)
{
u32 best_err = ~0, err;
int M, lM, hM, N, fN;
*P = info->vco1.max_freq / freq;
if (*... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c | 15,538 | utf_8 | d54f2ad44e4cae4bff2f0ea75041df1e | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bios/boost.h>
#include <subdev/bios/cstep.h>
#include <subdev/bios/perf.h>
#include <subdev/fb.h>
#include <subdev/therm.h>
#include <subdev/volt.h>
#include <core/option.h>
/****************************************************... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 11,793 | utf_8 | 10f8d7f47b03ff52c44ee7563d6b68fa | /*
*
* Authors: Ben Skeggs
*/
#define gf100_clk(p) container_of((p), struct gf100_clk, base)
#include "priv.h"
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
struct gf100_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
u32 dsrc;
u32 ddiv;
u32 coef;
};
struct gf100_clk... |
google | android | mcp77 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c | 11,162 | utf_8 | b7b46891204b4b8fb2cf83906d58c64c | /*
*
* Authors: Ben Skeggs
*/
#define mcp77_clk(p) container_of((p), struct mcp77_clk, base)
#include "gt215.h"
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
struct mcp77_clk {
struct nvkm_clk base;
enum nv_clk_src csrc, ssrc, vsrc;
u32 cctrl, sctrl;
u32 ccoef, ... |
google | android | gk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | 17,016 | utf_8 | bc4951968fdab0d95120862f9e5d2e6d | /*
*
* Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
*
*/
#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
#include "priv.h"
#include <core/tegra.h>
#include <subdev/timer.h>
#define MHZ (1000 * 1000)
#define MASK(w) ((1 << w) - 1)
#define SYS_GPCPLL_CFG_BASE 0x00137000
#define GPC_BCASE_G... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c | 1,899 | utf_8 | d0e6f84a869156a1382ca1566fa2db2f | /*
*/
#include "nv50.h"
#include <subdev/timer.h>
void
g84_bar_flush(struct nvkm_bar *bar)
{
struct nvkm_device *device = bar->subdev.device;
unsigned long flags;
spin_lock_irqsave(&bar->lock, flags);
nvkm_wr32(device, 0x070000, 0x00000001);
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x070000) & 0x00000002... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 6,077 | utf_8 | 5a31f308e5363a6b36741f60d0c3c36d | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
#include <subdev/timer.h>
struct nvkm_vm *
nv50_bar_kmap(struct nvkm_bar *base)
{
return nv50_bar(base)->bar3_vm;
}
int
nv50_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vm... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c | 2,380 | utf_8 | fe308f6753b378a16d1e86f65b453678 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
void
nvkm_bar_flush(struct nvkm_bar *bar)
{
if (bar && bar->func->flush)
bar->func->flush(bar);
}
struct nvkm_vm *
nvkm_bar_kmap(struct nvkm_bar *bar)
{
/* disallow kmap() until after vm has been bootstrapped */
if (bar && bar->func->kmap && bar->subdev.oneinit)
... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 4,795 | utf_8 | fa81e4356a79942f9b83ee25a0f9dbf8 | /*
*
* Authors: Ben Skeggs
*/
#include "gf100.h"
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
static struct nvkm_vm *
gf100_bar_kmap(struct nvkm_bar *base)
{
return gf100_bar(base)->bar[0].vm;
}
int
gf100_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma)
{
struct ... |
google | android | gk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c | 1,567 | utf_8 | e1ffc4251b6b1240dc53f86ef60e5ce0 | /*
*/
#include "gf100.h"
static const struct nvkm_bar_func
gk20a_bar_func = {
.dtor = gf100_bar_dtor,
.oneinit = gf100_bar_oneinit,
.init = gf100_bar_init,
.umap = gf100_bar_umap,
.flush = g84_bar_flush,
};
int
gk20a_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
{
int ret = gf100_bar_new... |
google | android | gm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c | 4,273 | utf_8 | 9b88e7677ba2cb5ebd4c6e266d85b244 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <subdev/fb.h>
#include <subdev/timer.h>
static void
gm107_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit)
{
struct nvkm_device *device = ltc->subdev.device;
nvkm_wr32(device, 0x17e270, start);
nvkm_wr32(device, 0x17e274, limit);
nvkm_wr32(device,... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c | 2,046 | utf_8 | 858ce3a23bc880861a13320445445956 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static void
gk104_ltc_init(struct nvkm_ltc *ltc)
{
struct nvkm_device *device = ltc->subdev.device;
u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);
nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
nvkm_wr32(device, 0x17... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c | 3,745 | utf_8 | 2b85a20a5061f9c6da1c948911726893 | /*
*/
#include "priv.h"
#include <subdev/fb.h>
int
nvkm_ltc_tags_alloc(struct nvkm_ltc *ltc, u32 n, struct nvkm_mm_node **pnode)
{
int ret = nvkm_mm_head(<c->tags, 0, 1, n, n, 1, pnode);
if (ret)
*pnode = NULL;
return ret;
}
void
nvkm_ltc_tags_free(struct nvkm_ltc *ltc, struct nvkm_mm_node **pnode)
{
nvkm_mm_f... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c | 7,212 | utf_8 | ff4560542274ec9ff3c5c4702560a744 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/enum.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
void
gf100_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit)
{
struct nvkm_device *device = ltc->subdev.device;
nvkm_wr32(device, 0x17e8cc, start);
nvkm_wr32(device, 0x17e8d0, limit);
n... |
google | android | g94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c | 2,605 | utf_8 | df790c2a82b1529af84643142e47cd87 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
void
g94_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{
struct nvkm_device *device = gpio->subdev.device;
u32 intr0 = nvkm_rd32(device, 0x00e054);
u32 intr1 = nvkm_rd32(device, 0x00e074);
u32 stat0 = nvkm_rd32(device, 0x00e050) & intr0;
u32 stat1 = nvk... |
google | android | nv10 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c | 3,310 | utf_8 | 71c9549e2724d9578d8dcc5b84ba807e | /*
*
*/
#include "priv.h"
static int
nv10_gpio_sense(struct nvkm_gpio *gpio, int line)
{
struct nvkm_device *device = gpio->subdev.device;
if (line < 2) {
line = line * 16;
line = nvkm_rd32(device, 0x600818) >> line;
return !!(line & 0x0100);
} else
if (line < 10) {
line = (line - 2) * 4;
line = nvkm_rd... |
google | android | gf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.c | 2,792 | utf_8 | 3008a8841f55b52c75d4adbcc8f19107 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
void
gf119_gpio_reset(struct nvkm_gpio *gpio, u8 match)
{
struct nvkm_device *device = gpio->subdev.device;
struct nvkm_bios *bios = device->bios;
u8 ver, len;
u16 entry;
int ent = -1;
while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
u32 data = nv... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c | 2,629 | utf_8 | 1d5444a9a6486aa93c8dd181cf372b49 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static void
gk104_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)
{
struct nvkm_device *device = gpio->subdev.device;
u32 intr0 = nvkm_rd32(device, 0x00dc00);
u32 intr1 = nvkm_rd32(device, 0x00dc80);
u32 stat0 = nvkm_rd32(device, 0x00dc08) & intr0;
u32 st... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c | 3,794 | utf_8 | d90404bb4cda1957a0f59794ea2b6cfc | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
void
nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match)
{
struct nvkm_device *device = gpio->subdev.device;
struct nvkm_bios *bios = device->bios;
u8 ver, len;
u16 entry;
int ent = -1;
while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
static const u... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 5,585 | utf_8 | 1014b03628e796eeed24f934aaf0c345 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/notify.h>
static int
nvkm_gpio_drive(struct nvkm_gpio *gpio, int idx, int line, int dir, int out)
{
return gpio->func->drive(gpio, line, dir, out);
}
static int
nvkm_gpio_sense(struct nvkm_gpio *gpio, int idx, int line)
{
return gpio->func->sense(gpio,... |
google | android | nv41 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c | 2,542 | utf_8 | 249b1ea07c113f1b4339a35725a50b20 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "regsnv04.h"
static void
nv41_timer_init(struct nvkm_timer *tmr)
{
struct nvkm_subdev *subdev = &tmr->subdev;
struct nvkm_device *device = subdev->device;
u32 f = device->crystal;
u32 m = 1, n, d;
/* aim for 31.25MHz, which gives us nanosecond timestamps ... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c | 2,610 | utf_8 | 8ea81270830e2a768a7e5aa5384cf8fc | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "regsnv04.h"
static void
nv40_timer_init(struct nvkm_timer *tmr)
{
struct nvkm_subdev *subdev = &tmr->subdev;
struct nvkm_device *device = subdev->device;
u32 f = 0; /*XXX: figure this out */
u32 n, d;
/* aim for 31.25MHz, which gives us nanosecond timest... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c | 4,122 | utf_8 | 9a43dee8e93e52a0c42f85efcada7b82 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "regsnv04.h"
void
nv04_timer_time(struct nvkm_timer *tmr, u64 time)
{
struct nvkm_subdev *subdev = &tmr->subdev;
struct nvkm_device *device = subdev->device;
u32 hi = upper_32_bits(time);
u32 lo = lower_32_bits(time);
nvkm_debug(subdev, "time low :... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c | 4,073 | utf_8 | fde659607d08178ea92a673c5dcd3e85 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
u64
nvkm_timer_read(struct nvkm_timer *tmr)
{
return tmr->func->read(tmr);
}
void
nvkm_timer_alarm_trigger(struct nvkm_timer *tmr)
{
struct nvkm_alarm *alarm, *atemp;
unsigned long flags;
LIST_HEAD(exec);
/* move any due alarms off the pending list */
spin_lock_i... |
google | android | gk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c | 1,522 | utf_8 | f7581d581c029fb7f86c313814efa163 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static const struct nvkm_timer_func
gk20a_timer = {
.intr = nv04_timer_intr,
.read = nv04_timer_read,
.time = nv04_timer_time,
.alarm_init = nv04_timer_alarm_init,
.alarm_fini = nv04_timer_alarm_fini,
};
int
gk20a_timer_new(struct nvkm_device *device, int index, s... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c | 2,280 | utf_8 | 86dd7d0860ead5fac61d697a57f8107c | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
const struct nvkm_mc_intr
nv50_mc_intr[] = {
{ 0x04000000, NVKM_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */
{ 0x00000001, NVKM_ENGINE_MPEG },
{ 0x00000100, NVKM_ENGINE_FIFO },
{ 0x00001000, NVKM_ENGINE_GR },
{ 0x00004000, NVKM_ENGINE_CI... |
google | android | g98 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c | 2,254 | utf_8 | c5e2e61ed606dd1d8ac28b36441e812b | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static const struct nvkm_mc_intr
g98_mc_intr[] = {
{ 0x04000000, NVKM_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */
{ 0x00000001, NVKM_ENGINE_MSPPP },
{ 0x00000100, NVKM_ENGINE_FIFO },
{ 0x00001000, NVKM_ENGINE_GR },
{ 0x00004000, NVKM_ENGINE_SEC }... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c | 2,592 | utf_8 | bf7dba7cd9eec4c581f9199afeb549a5 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
const struct nvkm_mc_intr
nv04_mc_intr[] = {
{ 0x00000001, NVKM_ENGINE_MPEG }, /* NV17- MPEG/ME */
{ 0x00000100, NVKM_ENGINE_FIFO },
{ 0x00001000, NVKM_ENGINE_GR },
{ 0x00010000, NVKM_ENGINE_DISP },
{ 0x00020000, NVKM_ENGINE_VP }, /* NV40- */
{ 0x00100000, NVKM_S... |
google | android | nv44 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c | 1,831 | utf_8 | fe04ede0214e2d986ccd7ebac043c620 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
void
nv44_mc_init(struct nvkm_mc *mc)
{
struct nvkm_device *device = mc->subdev.device;
u32 tmp = nvkm_rd32(device, 0x10020c);
nvkm_wr32(device, 0x000200, 0xffffffff); /* everything enabled */
nvkm_wr32(device, 0x001700, tmp);
nvkm_wr32(device, 0x001704, 0);
nvkm... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c | 2,991 | utf_8 | 26fa4af507e29fc6754a1f1c365fb125 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/option.h>
void
nvkm_mc_unk260(struct nvkm_mc *mc, u32 data)
{
if (mc->func->unk260)
mc->func->unk260(mc, data);
}
void
nvkm_mc_intr_unarm(struct nvkm_mc *mc)
{
return mc->func->intr_unarm(mc);
}
void
nvkm_mc_intr_rearm(struct nvkm_mc *mc)
{
return m... |
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