plateform stringclasses 1
value | repo_name stringclasses 2
values | name stringlengths 1 78 | ext stringclasses 2
values | path stringlengths 15 1.11k | size int64 1 8.55M | source_encoding stringclasses 11
values | md5 stringlengths 32 32 | text stringlengths 0 8.49M |
|---|---|---|---|---|---|---|---|---|
google | android | pcir | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c | 2,490 | utf_8 | e1aa9910ad59beab29af900c677d722d | /*
*/
#include <subdev/bios.h>
#include <subdev/bios/pcir.h>
u32
nvbios_pcirTe(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr)
{
u32 data = nvbios_rd16(bios, base + 0x18);
if (data) {
data += base;
switch (nvbios_rd32(bios, data + 0x00)) {
case 0x52494350: /* PCIR */
case 0x53494752: /* RGIS */
case 0... |
google | android | M0209 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c | 3,926 | utf_8 | 51ffaa8be3c4e7a155880b91a025bd36 | /*
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/M0209.h>
u32
nvbios_M0209Te(struct nvkm_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_M;
u32 data = 0x00000000;
if (!bit_entry(bios, 'M', &bit_M)) {
if (bi... |
google | android | i2c | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c | 4,773 | utf_8 | 8a526f7897d26f7edbc6c5ac2ae578df | /*
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/i2c.h>
u16
dcb_i2c_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u16 i2c = 0x0000;
u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
if (dcb) {
if (*ver >= 0x15)
i2c = nvbios_rd16(bios... |
google | android | dcb | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c | 6,106 | utf_8 | 48396035f305ee1a850dc0d81637bc57 | /*
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
u16
dcb_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct nvkm_subdev *subdev = &bios->subdev;
struct nvkm_device *device = subdev->device;
u16 dcb = 0x0000;
if (device->card_type > NV_04)
dcb = nvbios_... |
google | android | gt215 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c | 4,497 | utf_8 | a5f2e81f709ec55c0e559755076ce832 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
#include <subdev/bios/pll.h>
#include <subdev/clk/pll.h>
int
gt215_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
{
struct nvkm_subdev *subdev = &init->subdev;
struct nvkm_device *device = subdev-... |
google | android | gm107 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c | 2,039 | utf_8 | e7a573b2c93aaca5f4bca545749d35f5 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
u64
gm107_devinit_disable(struct nvkm_devinit *init)
{
struct nvkm_device *device = init->subdev.device;
u32 r021c00 = nvkm_rd32(device, 0x021c00);
u32 r021c04 = nvkm_rd32(device, 0x021c04);
u64 disable = 0ULL;... |
google | android | nv10 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c | 3,107 | utf_8 | cae3e829076cffe784fe5142d2afb7c9 | /*
*
*/
#include "nv04.h"
#include "fbmem.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
static void
nv10_devinit_meminit(struct nvkm_devinit *init)
{
struct nvkm_subdev *subdev = &init->subdev;
struct nvkm_device *device = subdev->device;
static const int mem_width[] = { 0x10, 0x00, 0x20 };
int mem_wi... |
google | android | nv20 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c | 2,532 | utf_8 | 60c94830764cfaf60c164f140db97082 | /*
*
*/
#include "nv04.h"
#include "fbmem.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
static void
nv20_devinit_meminit(struct nvkm_devinit *init)
{
struct nvkm_subdev *subdev = &init->subdev;
struct nvkm_device *device = subdev->device;
uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900);
uint... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c | 2,246 | utf_8 | 90083e6452398147c50a0de4cbc53f9c | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
static u64
g84_devinit_disable(struct nvkm_devinit *init)
{
struct nvkm_device *device = init->subdev.device;
u32 r001540 = nvkm_rd32(device, 0x001540);
u32 r00154c = nvkm_rd32(device, 0x00154c);
u64 disable = ... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c | 5,220 | utf_8 | c13197041fbc0ee8456d5427aa277578 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/disp.h>
#include <subdev/bios/init.h>
#include <subdev/bios/pll.h>
#include <subdev/clk/pll.h>
#include <subdev/vga.h>
int
nv50_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
{
... |
google | android | mcp89 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c | 2,245 | utf_8 | f340a187289b5d785f52524a3c9cc453 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
static u64
mcp89_devinit_disable(struct nvkm_devinit *init)
{
struct nvkm_device *device = init->subdev.device;
u32 r001540 = nvkm_rd32(device, 0x001540);
u32 r00154c = nvkm_rd32(device, 0x00154c);
u64 disable ... |
google | android | g98 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c | 2,209 | utf_8 | 4d7db2facecadf46b5fc51f1f9f78d44 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
static u64
g98_devinit_disable(struct nvkm_devinit *init)
{
struct nvkm_device *device = init->subdev.device;
u32 r001540 = nvkm_rd32(device, 0x001540);
u32 r00154c = nvkm_rd32(device, 0x00154c);
u64 disable = ... |
google | android | gm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c | 5,317 | utf_8 | af7a159352a352569ee84be020cb75c8 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/pmu.h>
static void
pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
{
struct nvkm_device *device = init->base.subdev.device;
struct nvkm_bios *bios = device->bios;
in... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c | 13,175 | utf_8 | 4911a521db781ee566e6f017f6bf34e7 | /*
*
*/
#include "nv04.h"
#include "fbmem.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
#include <subdev/bios/pll.h>
#include <subdev/clk/pll.h>
#include <subdev/vga.h>
static void
nv04_devinit_meminit(struct nvkm_devinit *init)
{
struct nvkm_subdev *subdev = &init->subdev;
struct nvkm_device *device = ... |
google | android | nv1a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.c | 1,562 | utf_8 | 25049ba699f5d19d4e7b183ed3b727b9 | /*
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
static const struct nvkm_devinit_func
nv1a_devinit = {
.dtor = nv04_devinit_dtor,
.preinit = nv04_devinit_preinit,
.post = nv04_devinit_post,
.pll_set = nv04_devinit_pll_set,
};
int
nv1a_devinit_new(struct nvkm... |
google | android | nv05 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c | 4,410 | utf_8 | fbbe0c84ad3e40624916770dea74eba7 | /*
*
*/
#include "nv04.h"
#include "fbmem.h"
#include <subdev/bios.h>
#include <subdev/bios/bmp.h>
#include <subdev/bios/init.h>
#include <subdev/vga.h>
static void
nv05_devinit_meminit(struct nvkm_devinit *init)
{
static const u8 default_config_tab[][2] = {
{ 0x24, 0x00 },
{ 0x28, 0x00 },
{ 0x24, 0x01 },
{ ... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c | 3,317 | utf_8 | a227d69663932f73add7d8bb45f35a73 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/option.h>
#include <subdev/vga.h>
u32
nvkm_devinit_mmio(struct nvkm_devinit *init, u32 addr)
{
if (init->func->mmio)
addr = init->func->mmio(init, addr);
return addr;
}
int
nvkm_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 khz)
{
return ... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c | 3,095 | utf_8 | 3ea466cf37a135440465856b1611ace3 | /*
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/bios.h>
#include <subdev/bios/init.h>
#include <subdev/bios/pll.h>
#include <subdev/clk/pll.h>
int
gf100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
{
struct nvkm_subdev *subdev = &init->subdev;
struct nvkm_device *device = subdev-... |
google | android | g94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c | 2,111 | utf_8 | fd88b99311ffe8d1024c2ce59a032056 | /*
* Ben Skeggs
*/
#include "priv.h"
#include <subdev/timer.h>
static int
g94_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
{
struct nvkm_device *device = bus->subdev.device;
int i;
nvkm_mask(device, 0x001098, 0x00000008, 0x00000000);
nvkm_wr32(device, 0x001304, 0x00000000);
nvkm_wr32(device,... |
google | android | hwsq | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c | 4,578 | utf_8 | a55c2adfa6cf93203d5d6a14cf4cc179 | /*
*/
#include "priv.h"
struct nvkm_hwsq {
struct nvkm_subdev *subdev;
u32 addr;
u32 data;
struct {
u8 data[512];
u16 size;
} c;
};
static void
hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[])
{
memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));
hwsq->c.size += size;
}
int
nvkm_hwsq_ini... |
google | android | nv31 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c | 2,715 | utf_8 | 59574daa93e9b9b70f145924652037f5 | /*
* Ben Skeggs
*/
#include "priv.h"
#include <subdev/gpio.h>
#include <subdev/therm.h>
static void
nv31_bus_intr(struct nvkm_bus *bus)
{
struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
u32 gpio ... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c | 3,094 | utf_8 | 38a4172e6e298e016c01f4924a9e4827 | /*
* Ben Skeggs
*/
#include "priv.h"
#include <subdev/therm.h>
#include <subdev/timer.h>
static int
nv50_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
{
struct nvkm_device *device = bus->subdev.device;
int i;
nvkm_mask(device, 0x001098, 0x00000008, 0x00000000);
nvkm_wr32(device, 0x001304, 0x00... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c | 2,335 | utf_8 | 549be659d6b480b37e3eec118eab1c31 | /*
* Ben Skeggs
*/
#include "priv.h"
#include <subdev/gpio.h>
#include <subdev/gpio.h>
static void
nv04_bus_intr(struct nvkm_bus *bus)
{
struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
if (stat &... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c | 1,971 | utf_8 | 02a4ff62dc217e4e2925146790ae0520 | /*
*/
#include "priv.h"
static void
nvkm_bus_intr(struct nvkm_subdev *subdev)
{
struct nvkm_bus *bus = nvkm_bus(subdev);
bus->func->intr(bus);
}
static int
nvkm_bus_init(struct nvkm_subdev *subdev)
{
struct nvkm_bus *bus = nvkm_bus(subdev);
bus->func->init(bus);
return 0;
}
static void *
nvkm_bus_dtor(struct nvkm... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c | 2,490 | utf_8 | c352e4076b8c255a1a3880eb583e8c40 | /*
* Ben Skeggs
*/
#include "priv.h"
static void
gf100_bus_intr(struct nvkm_bus *bus)
{
struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
if (stat & 0x0000000e) {
u32 addr = nvkm_rd32(device, 0x0... |
google | android | g94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c | 2,370 | utf_8 | 5674083d3cbc2d7dec487fb702d3c839 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pad.h"
void
g94_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
{
struct nvkm_device *device = i2c->subdev.device;
u32 intr = nvkm_rd32(device, 0x00e06c);
u32 stat = nvkm_rd32(device, 0x00e068) & intr, i;
for (i = 0, *hi = *lo = *rq = *... |
google | android | padnv4e | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv4e.c | 1,420 | utf_8 | e58477cf66ab0289dc78c633587b9805 | /*
*
* Authors: Ben Skeggs
*/
#include "pad.h"
#include "bus.h"
static const struct nvkm_i2c_pad_func
nv4e_i2c_pad_func = {
.bus_new_4 = nv4e_i2c_bus_new,
};
int
nv4e_i2c_pad_new(struct nvkm_i2c *i2c, int id, struct nvkm_i2c_pad **ppad)
{
return nvkm_i2c_pad_new_(&nv4e_i2c_pad_func, i2c, id, ppad);
} |
google | android | padnv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.c | 1,420 | utf_8 | f410b810ed9cbef5371ff5eb04465517 | /*
*
* Authors: Ben Skeggs
*/
#include "pad.h"
#include "bus.h"
static const struct nvkm_i2c_pad_func
nv04_i2c_pad_func = {
.bus_new_0 = nv04_i2c_bus_new,
};
int
nv04_i2c_pad_new(struct nvkm_i2c *i2c, int id, struct nvkm_i2c_pad **ppad)
{
return nvkm_i2c_pad_new_(&nv04_i2c_pad_func, i2c, id, ppad);
} |
google | android | padnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv50.c | 1,420 | utf_8 | 9137ca002008ae37895caaa0d71966d5 | /*
*
* Authors: Ben Skeggs
*/
#include "pad.h"
#include "bus.h"
static const struct nvkm_i2c_pad_func
nv50_i2c_pad_func = {
.bus_new_4 = nv50_i2c_bus_new,
};
int
nv50_i2c_pad_new(struct nvkm_i2c *i2c, int id, struct nvkm_i2c_pad **ppad)
{
return nvkm_i2c_pad_new_(&nv50_i2c_pad_func, i2c, id, ppad);
} |
google | android | aux | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c | 4,320 | utf_8 | 008546e3bfc3d6c190436c2da2cc4fa5 | /*
*
* Authors: Ben Skeggs
*/
#include "aux.h"
#include "pad.h"
static int
nvkm_i2c_aux_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
struct nvkm_i2c_aux *aux = container_of(adap, typeof(*aux), i2c);
struct i2c_msg *msg = msgs;
int ret, mcnt = num;
ret = nvkm_i2c_aux_acquire(aux);
if (ret)... |
google | android | busnv4e | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c | 2,845 | utf_8 | e9795d262915f1ee965dd7804bec91f1 | /*
*/
#define nv4e_i2c_bus(p) container_of((p), struct nv4e_i2c_bus, base)
#include "bus.h"
struct nv4e_i2c_bus {
struct nvkm_i2c_bus base;
u32 addr;
};
static void
nv4e_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state)
{
struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base);
struct nvkm_device *device = bus->base.p... |
google | android | busnv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c | 3,070 | utf_8 | 799a5d7791e13e9e76784ccfd6e44439 | /*
*/
#define nv04_i2c_bus(p) container_of((p), struct nv04_i2c_bus, base)
#include "bus.h"
#include <subdev/vga.h>
struct nv04_i2c_bus {
struct nvkm_i2c_bus base;
u8 drive;
u8 sense;
};
static void
nv04_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state)
{
struct nv04_i2c_bus *bus = nv04_i2c_bus(base);
struc... |
google | android | gf117 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.c | 1,408 | utf_8 | b5aecd5a482b851d63b85c09d095fec3 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pad.h"
static const struct nvkm_i2c_func
gf117_i2c = {
.pad_x_new = gf119_i2c_pad_x_new,
};
int
gf117_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&gf117_i2c, device, index, pi2c);
} |
google | android | padgm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm204.c | 2,504 | utf_8 | 2a4b3a28f54b108b6a49cd9907cc2895 | /*
*
* Authors: Ben Skeggs
*/
#include "pad.h"
#include "aux.h"
#include "bus.h"
static void
gm204_i2c_pad_mode(struct nvkm_i2c_pad *pad, enum nvkm_i2c_pad_mode mode)
{
struct nvkm_subdev *subdev = &pad->i2c->subdev;
struct nvkm_device *device = subdev->device;
const u32 base = (pad->id - NVKM_I2C_PAD_HYBRID(0)) ... |
google | android | gf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.c | 1,508 | utf_8 | e18abf9f4cf2c94566b3d9ec3961a93b | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pad.h"
static const struct nvkm_i2c_func
gf119_i2c = {
.pad_x_new = gf119_i2c_pad_x_new,
.pad_s_new = gf119_i2c_pad_s_new,
.aux = 4,
.aux_stat = g94_aux_stat,
.aux_mask = g94_aux_mask,
};
int
gf119_i2c_new(struct nvkm_device *device, int index, struct nv... |
google | android | gk104 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c | 2,388 | utf_8 | c47c53c61cae1529782c5cd4f61caef9 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pad.h"
void
gk104_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
{
struct nvkm_device *device = i2c->subdev.device;
u32 intr = nvkm_rd32(device, 0x00dc60);
u32 stat = nvkm_rd32(device, 0x00dc68) & intr, i;
for (i = 0, *hi = *lo = *rq =... |
google | android | busgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c | 3,145 | utf_8 | 060533b7579b864bb031c4956fe0ee77 | /*
*/
#define gf119_i2c_bus(p) container_of((p), struct gf119_i2c_bus, base)
#include "bus.h"
struct gf119_i2c_bus {
struct nvkm_i2c_bus base;
u32 addr;
};
static void
gf119_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state)
{
struct gf119_i2c_bus *bus = gf119_i2c_bus(base);
struct nvkm_device *device = bus->... |
google | android | anx9805 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c | 7,115 | utf_8 | bacaf83b85581b8aba0c87e5057de4cf | /*
*/
#define anx9805_pad(p) container_of((p), struct anx9805_pad, base)
#define anx9805_bus(p) container_of((p), struct anx9805_bus, base)
#define anx9805_aux(p) container_of((p), struct anx9805_aux, base)
#include "aux.h"
#include "bus.h"
struct anx9805_pad {
struct nvkm_i2c_pad base;
struct nvkm_i2c_bus *bus;
u8... |
google | android | bit | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.c | 4,638 | utf_8 | af7c3fe77c33245b761c9cc5656721bf | /*
*
* Authors: Ben Skeggs
*/
#include "bus.h"
#ifdef CONFIG_NOUVEAU_I2C_INTERNAL
#define T_TIMEOUT 2200000
#define T_RISEFALL 1000
#define T_HOLD 5000
static inline void
nvkm_i2c_drive_scl(struct nvkm_i2c_bus *bus, int state)
{
bus->func->drive_scl(bus, state);
}
static inline void
nvkm_i2c_drive_sda(struct n... |
google | android | busnv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c | 3,500 | utf_8 | 4e2e287236f7c9996a6b52eec1a87754 | /*
*/
#define nv50_i2c_bus(p) container_of((p), struct nv50_i2c_bus, base)
#include "bus.h"
#include <subdev/vga.h>
struct nv50_i2c_bus {
struct nvkm_i2c_bus base;
u32 addr;
u32 data;
};
static void
nv50_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state)
{
struct nv50_i2c_bus *bus = nv50_i2c_bus(base);
struc... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c | 1,402 | utf_8 | 58a030b3d0cdbe665e1fb7214da19a58 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pad.h"
static const struct nvkm_i2c_func
nv50_i2c = {
.pad_x_new = nv50_i2c_pad_new,
};
int
nv50_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&nv50_i2c, device, index, pi2c);
} |
google | android | auxgm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm204.c | 5,219 | utf_8 | 8aba0fa8adf654b5c6f70bd14b576057 | /*
*/
#define gm204_i2c_aux(p) container_of((p), struct gm204_i2c_aux, base)
#include "aux.h"
struct gm204_i2c_aux {
struct nvkm_i2c_aux base;
int ch;
};
static void
gm204_i2c_aux_fini(struct gm204_i2c_aux *aux)
{
struct nvkm_device *device = aux->base.pad->i2c->subdev.device;
nvkm_mask(device, 0x00d954 + (aux->ch... |
google | android | gm204 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c | 1,512 | utf_8 | e8fd3e25c755291243b5e0f5ff2f21a2 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pad.h"
static const struct nvkm_i2c_func
gm204_i2c = {
.pad_x_new = gf119_i2c_pad_x_new,
.pad_s_new = gm204_i2c_pad_s_new,
.aux = 8,
.aux_stat = gk104_aux_stat,
.aux_mask = gk104_aux_mask,
};
int
gm204_i2c_new(struct nvkm_device *device, int index, struc... |
google | android | padgf119 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgf119.c | 1,788 | utf_8 | 6cf5f7f571264da704a903a9a644bce1 | /*
*
* Authors: Ben Skeggs
*/
#include "pad.h"
#include "aux.h"
#include "bus.h"
static const struct nvkm_i2c_pad_func
gf119_i2c_pad_s_func = {
.bus_new_4 = gf119_i2c_bus_new,
.aux_new_6 = g94_i2c_aux_new,
.mode = g94_i2c_pad_mode,
};
int
gf119_i2c_pad_s_new(struct nvkm_i2c *i2c, int id, struct nvkm_i2c_pad **ppa... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.c | 1,402 | utf_8 | 48139fb49e0464cfb2554eb18dd3f4f0 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pad.h"
static const struct nvkm_i2c_func
nv04_i2c = {
.pad_x_new = nv04_i2c_pad_new,
};
int
nv04_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&nv04_i2c, device, index, pi2c);
} |
google | android | nv4e | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.c | 1,402 | utf_8 | a3af3ebacbca87ffd0b25b6955ecd77f | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "pad.h"
static const struct nvkm_i2c_func
nv4e_i2c = {
.pad_x_new = nv4e_i2c_pad_new,
};
int
nv4e_i2c_new(struct nvkm_device *device, int index, struct nvkm_i2c **pi2c)
{
return nvkm_i2c_new_(&nv4e_i2c, device, index, pi2c);
} |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c | 9,888 | utf_8 | 6bbf35a18e34a7e9096215b4b429bc97 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "aux.h"
#include "bus.h"
#include "pad.h"
#include <core/notify.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/i2c.h>
static struct nvkm_i2c_pad *
nvkm_i2c_pad_find(struct nvkm_i2c *i2c, int id)
{
struc... |
google | android | bus | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.c | 6,521 | utf_8 | 081cac14ed48932ad5441fb4e24ff0dc | /*
*/
#include "bus.h"
#include "pad.h"
#include <core/option.h>
/*******************************************************************************
* i2c-algo-bit
******************************************************************************/
static int
nvkm_i2c_bus_pre_xfer(struct i2c_adapter *adap)
{
struct nvkm_i2... |
google | android | pad | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.c | 3,160 | utf_8 | e1757e5ddd1410acce92556a00936147 | /*
*/
#include "pad.h"
static void
nvkm_i2c_pad_mode_locked(struct nvkm_i2c_pad *pad, enum nvkm_i2c_pad_mode mode)
{
PAD_TRACE(pad, "-> %s", (mode == NVKM_I2C_PAD_AUX) ? "aux" :
(mode == NVKM_I2C_PAD_I2C) ? "i2c" : "off");
if (pad->func->mode)
pad->func->mode(pad, mode);
}
void
nvkm_i2c_pad_mode(struct nv... |
google | android | padg94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c | 2,475 | utf_8 | 5b716fd05c419417fe3e8a9394db5c8e | /*
*
* Authors: Ben Skeggs
*/
#include "pad.h"
#include "aux.h"
#include "bus.h"
void
g94_i2c_pad_mode(struct nvkm_i2c_pad *pad, enum nvkm_i2c_pad_mode mode)
{
struct nvkm_subdev *subdev = &pad->i2c->subdev;
struct nvkm_device *device = subdev->device;
const u32 base = (pad->id - NVKM_I2C_PAD_HYBRID(0)) * 0x50;
... |
google | android | auxg94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c | 5,181 | utf_8 | 3281c3ca76f24727845be3b197caff86 | /*
*/
#define g94_i2c_aux(p) container_of((p), struct g94_i2c_aux, base)
#include "aux.h"
struct g94_i2c_aux {
struct nvkm_i2c_aux base;
int ch;
};
static void
g94_i2c_aux_fini(struct g94_i2c_aux *aux)
{
struct nvkm_device *device = aux->base.pad->i2c->subdev.device;
nvkm_mask(device, 0x00e4e4 + (aux->ch * 0x50), ... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c | 7,331 | utf_8 | ddae0626cdf88af939f0fdf7ee8321aa | /*
*
* Authors: Ben Skeggs
*/
#define nv40_instmem(p) container_of((p), struct nv40_instmem, base)
#include "priv.h"
#include <core/memory.h>
#include <core/ramht.h>
#include <engine/gr/nv40.h>
struct nv40_instmem {
struct nvkm_instmem base;
struct nvkm_mm heap;
void __iomem *iomem;
};
/**************************... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c | 6,910 | utf_8 | 8ac5a2ee25d37eed35ad00c3ed70949d | /*
*
* Authors: Ben Skeggs
*/
#define nv50_instmem(p) container_of((p), struct nv50_instmem, base)
#include "priv.h"
#include <core/memory.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
struct nv50_instmem {
struct nvkm_instmem base;
unsigned long lock_flags;
spinlock_t lock;
u64 addr;... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c | 6,382 | utf_8 | 6e62ac0a30d112e1ccc1e5b66db7f567 | /*
*
* Authors: Ben Skeggs
*/
#define nv04_instmem(p) container_of((p), struct nv04_instmem, base)
#include "priv.h"
#include <core/memory.h>
#include <core/ramht.h>
struct nv04_instmem {
struct nvkm_instmem base;
struct nvkm_mm heap;
};
/****************************************************************************... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c | 7,960 | utf_8 | 0341bc8aabfc93412b11ccc7c0eed461 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/memory.h>
#include <subdev/bar.h>
/******************************************************************************
* instmem object base implementation
*****************************************************************************/
#define nvkm_instobj(p... |
google | android | gk20a | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 17,122 | utf_8 | 96dbec88c5d7d3874afb4d997b286443 | /*
*/
/*
* GK20A does not have dedicated video memory, and to accurately represent this
* fact Nouveau will not create a RAM device for it. Therefore its instmem
* implementation must be done directly on top of system memory, while
* preserving coherency for read and write operations.
*
* Instmem can be allocate... |
google | android | g94 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c | 1,510 | utf_8 | d6ee85ebef573b306b373f45ed1fdba0 | /*
*/
#include "priv.h"
static const struct nvkm_pci_func
g94_pci_func = {
.init = g84_pci_init,
.rd32 = nv40_pci_rd32,
.wr08 = nv40_pci_wr08,
.wr32 = nv40_pci_wr32,
.msi_rearm = nv40_pci_msi_rearm,
};
int
g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
{
return nvkm_pci_new_(&g94_pci_... |
google | android | nv46 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c | 1,856 | utf_8 | 5b358e45687e79130449cab2f326be8f | /*
*/
#include "priv.h"
#include <core/pci.h>
/* MSI re-arm through the PRI appears to be broken on NV46/NV50/G84/G86/G92,
* so we access it via alternate PCI config space mechanisms.
*/
void
nv46_pci_msi_rearm(struct nvkm_pci *pci)
{
struct nvkm_device *device = pci->subdev.device;
struct pci_dev *pdev = device->... |
google | android | nv40 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c | 2,042 | utf_8 | 14f6ac6afdf852c8220068252733e554 | /*
*/
#include "priv.h"
u32
nv40_pci_rd32(struct nvkm_pci *pci, u16 addr)
{
struct nvkm_device *device = pci->subdev.device;
return nvkm_rd32(device, 0x088000 + addr);
}
void
nv40_pci_wr08(struct nvkm_pci *pci, u16 addr, u8 data)
{
struct nvkm_device *device = pci->subdev.device;
nvkm_wr08(device, 0x088000 + addr,... |
google | android | g84 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c | 2,190 | utf_8 | 706fbd72d2e01f67d1c44925c7e7f24b | /*
*/
#include "priv.h"
#include <core/pci.h>
void
g84_pci_init(struct nvkm_pci *pci)
{
/* The following only concerns PCIe cards. */
if (!pci_is_pcie(pci->pdev))
return;
/* Tag field is 8-bit long, regardless of EXT_TAG.
* However, if EXT_TAG is disabled, only the lower 5 bits of the tag
* field should be us... |
google | android | agp | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c | 5,321 | utf_8 | 60f0e9fecd690943caecaf5baff79551 | /*
*/
#include "agp.h"
#ifdef __NVKM_PCI_AGP_H__
#include <core/option.h>
struct nvkm_device_agp_quirk {
u16 hostbridge_vendor;
u16 hostbridge_device;
u16 chip_vendor;
u16 chip_device;
int mode;
};
static const struct nvkm_device_agp_quirk
nvkm_device_agp_quirks[] = {
/* VIA Apollo PRO133x / GeForce FX 5600 Ultr... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.c | 1,943 | utf_8 | 0eb0c378f28ab25e45b84ee7d2739e36 | /*
*/
#include "priv.h"
static u32
nv04_pci_rd32(struct nvkm_pci *pci, u16 addr)
{
struct nvkm_device *device = pci->subdev.device;
return nvkm_rd32(device, 0x001800 + addr);
}
static void
nv04_pci_wr08(struct nvkm_pci *pci, u16 addr, u8 data)
{
struct nvkm_device *device = pci->subdev.device;
nvkm_wr08(device, 0x... |
google | android | nv4c | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.c | 1,456 | utf_8 | c26d1225e3b6309066d9a262f8960d1d | /*
*/
#include "priv.h"
static const struct nvkm_pci_func
nv4c_pci_func = {
.rd32 = nv40_pci_rd32,
.wr08 = nv40_pci_wr08,
.wr32 = nv40_pci_wr32,
};
int
nv4c_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
{
return nvkm_pci_new_(&nv4c_pci_func, device, index, ppci);
} |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c | 4,442 | utf_8 | 34e891dc8982a2e17dbdb3c70b02974d | /*
*/
#include "priv.h"
#include "agp.h"
#include <core/option.h>
#include <core/pci.h>
#include <subdev/mc.h>
u32
nvkm_pci_rd32(struct nvkm_pci *pci, u16 addr)
{
return pci->func->rd32(pci, addr);
}
void
nvkm_pci_wr08(struct nvkm_pci *pci, u16 addr, u8 data)
{
pci->func->wr08(pci, addr, data);
}
void
nvkm_pci_wr32(... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c | 1,611 | utf_8 | a34e966d9df3a99ead74d11271687116 | /*
*/
#include "priv.h"
static void
gf100_pci_msi_rearm(struct nvkm_pci *pci)
{
nvkm_pci_wr08(pci, 0x0704, 0xff);
}
static const struct nvkm_pci_func
gf100_pci_func = {
.init = g84_pci_init,
.rd32 = nv40_pci_rd32,
.wr08 = nv40_pci_wr08,
.wr32 = nv40_pci_wr32,
.msi_rearm = gf100_pci_msi_rearm,
};
int
gf100_pci_ne... |
google | android | nv41 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c | 4,115 | utf_8 | 430a9b7b4c5baaf9ff6de022a2389b9b | /*
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include <core/gpuobj.h>
#include <core/option.h>
#include <subdev/timer.h>
#define NV41_GART_SIZE (512 * 1024 * 1024)
#define NV41_GART_PAGE ( 4 * 1024)
/*******************************************************************************
* VM map/unmap callbacks
******... |
google | android | nv50 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 6,080 | utf_8 | 44993b735961fc0c4a674520bf43376c | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <engine/gr.h>
static void
nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_memory *pgt[2])
{
u64 phys = 0xdeadcafe00000000ULL;
u32 coverage = 0;
if (pgt[0]) {
/* presen... |
google | android | nv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c | 4,060 | utf_8 | 882bbd3953891e7a7059482351fbea52 | /*
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include <core/gpuobj.h>
#define NV04_PDMA_SIZE (128 * 1024 * 1024)
#define NV04_PDMA_PAGE ( 4 * 1024)
/*******************************************************************************
* VM map/unmap callbacks
*********************************************************... |
google | android | nv44 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c | 6,594 | utf_8 | 8f59730d34f76898935f172448f07ed4 | /*
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include <core/gpuobj.h>
#include <core/option.h>
#include <subdev/timer.h>
#define NV44_GART_SIZE (512 * 1024 * 1024)
#define NV44_GART_PAGE ( 4 * 1024)
/*******************************************************************************
* VM map/unmap callbacks
******... |
google | android | base | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c | 12,544 | utf_8 | 5fb603d1086d31ca1e700a4214b4934e | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/gpuobj.h>
#include <subdev/fb.h>
void
nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node)
{
struct nvkm_vm *vm = vma->vm;
struct nvkm_mmu *mmu = vm->mmu;
struct nvkm_mm_node *r;
int big = vma->node->type != mmu->func->spg_shift;
u... |
google | android | gf100 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c | 6,843 | utf_8 | efbbf5f33901a42208afcb1ad4694374 | /*
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <subdev/fb.h>
#include <subdev/ltc.h>
#include <subdev/timer.h>
#include <core/gpuobj.h>
/* Map from compressed to corresponding uncompressed storage type.
* The value 0xff represents an invalid storage type.
*/
const u8 gf100_pte_storage_type_map[256] =
{
... |
google | android | dac | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/dac.c | 17,948 | utf_8 | 76a27ab7662a7543d8514d49f789d864 | /*
*/
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include "nouveau_drm.h"
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
#include "nouveau_crtc.h"
#include "hw.h"
#include "nvreg.h"
#include <subdev/bios/gpio.h>
#include <subdev/gpio.h>
#include <subdev/timer.h>
int nv04_dac_output_offset(stru... |
google | android | dfp | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/dfp.c | 24,607 | utf_8 | 226ea765d0d67773fd45189a7d40a99a | /*
*/
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
#include "nouveau_crtc.h"
#include "hw.h"
#include "nvreg.h"
#include <drm/i2c/sil164.h>
#include <subdev/i2c.h>
#define FP_TG_CONTROL_ON (NV_PRAMD... |
google | android | arb | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/arb.c | 7,968 | utf_8 | 4b2fd2795a84be8bd07cffd2fccdb038 | /*
*/
#include <drm/drmP.h>
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "hw.h"
/****************************************************************************\
* *
* The video arbitration routines calculate some "magic" numbers. F... |
google | android | cursor | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/cursor.c | 2,159 | utf_8 | add7fad687d9274e5ee1b920d5e139ee | #include <drm/drmP.h>
#include <drm/drm_mode.h>
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "nouveau_crtc.h"
#include "hw.h"
static void
nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
{
nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
}
static void
nv04_cursor_hide(struct nouveau_... |
google | android | tvnv17 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 24,663 | utf_8 | 49875edf992bc45a83742e05c36e4da2 | /*
*
*/
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
#include "nouveau_crtc.h"
#include "hw.h"
#include "tvnv17.h"
MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
"\t\tSupported: PAL, PAL-M, PAL-N... |
google | android | tvmodesnv17 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c | 21,872 | utf_8 | e6e4c060ec662660342ce425f9f384ae | /*
*
*/
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include "nouveau_drm.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"
#include "hw.h"
#include "tvnv17.h"
const char * const nv17_tv_norm_names[NUM_TV_NORMS] = {
[TV_NORM_PAL] = "PAL",
[TV_NORM_PAL_M] = "PAL-M",
[TV_NORM_PAL_N] = "PAL-N",
[T... |
google | android | disp | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/disp.c | 5,343 | utf_8 | ac2f85966235a4d7fff3226d15d4f836 | /*
*
* Author: Ben Skeggs
*/
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "hw.h"
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
int
nv04_display_create(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm... |
google | android | crtc | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/crtc.c | 37,677 | utf_8 | 3c37d5a0c9b90b05466e03f71fcac6a3 | /*
*/
#include <linux/pm_runtime.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "nouveau_bo.h"
#include "nouveau_gem.h"
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
#include "nouveau_crtc.h"
#include ... |
google | android | hw | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/hw.c | 27,567 | utf_8 | c73b3d357993a492fd2ca5dd7624b5ca | /*
*/
#include <drm/drmP.h>
#include "nouveau_drm.h"
#include "hw.h"
#include <subdev/bios/pll.h>
#define CHIPSET_NFORCE 0x01a0
#define CHIPSET_NFORCE2 0x01f0
/*
* misc hw access wrappers/control functions
*/
void
NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
{
NVWritePRMVIO(dev, hea... |
google | android | tvnv04 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c | 7,563 | utf_8 | afe6399c955394c0d701019a99c54dd2 | /*
*
*/
#include <drm/drmP.h>
#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
#include "nouveau_crtc.h"
#include "hw.h"
#include <drm/drm_crtc_helper.h>
#include <drm/i2c/ch7006.h>
static struct nvkm_i2c_bus_probe nv04_tv_encoder_info[] = {
{
{
I2C_B... |
google | android | overlay | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/dispnv04/overlay.c | 14,503 | utf_8 | 61c1bc5e2d8f47e14debea90c8247225 | /*
*
* Implementation based on the pre-KMS implementation in xf86-video-nouveau,
* written by Arthur Huillet.
*/
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_fourcc.h>
#include "nouveau_drm.h"
#include "nouveau_bo.h"
#include "nouveau_connector.h"
#include "nouveau_display.h"
#include "nvreg.h"... |
google | android | device | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvif/device.c | 1,901 | utf_8 | b4af733bc8cf53a94942f26d54e8974a | /*
*/
#include <nvif/device.h>
u64
nvif_device_time(struct nvif_device *device)
{
struct nv_device_time_v0 args = {};
int ret = nvif_object_mthd(&device->object, NV_DEVICE_V0_TIME,
&args, sizeof(args));
WARN_ON_ONCE(ret != 0);
return args.time;
}
void
nvif_device_fini(struct nvif_device *device)
{
nvif_obj... |
google | android | object | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvif/object.c | 6,714 | utf_8 | ec73a46b831a1b328f22ba5ef94829ea | /*
*/
#include <nvif/object.h>
#include <nvif/client.h>
#include <nvif/driver.h>
#include <nvif/ioctl.h>
int
nvif_object_ioctl(struct nvif_object *object, void *data, u32 size, void **hack)
{
struct nvif_client *client = object->client;
union {
struct nvif_ioctl_v0 v0;
} *args = data;
if (size >= sizeof(*args) &... |
google | android | notify | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvif/notify.c | 5,583 | utf_8 | 4ec7b937b6d8ac96d8eae04a80a3318f | /*
*/
#include <nvif/client.h>
#include <nvif/driver.h>
#include <nvif/notify.h>
#include <nvif/object.h>
#include <nvif/ioctl.h>
#include <nvif/event.h>
static inline int
nvif_notify_put_(struct nvif_notify *notify)
{
struct nvif_object *object = notify->object;
struct {
struct nvif_ioctl_v0 ioctl;
struct nvif_... |
google | android | client | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/nouveau/nvif/client.c | 2,887 | utf_8 | 313445d1ac7a964357ed198fa88a34e5 | /*
*/
#include <nvif/client.h>
#include <nvif/driver.h>
#include <nvif/ioctl.h>
int
nvif_client_ioctl(struct nvif_client *client, void *data, u32 size)
{
return client->driver->ioctl(client->object.priv, client->super, data, size, NULL);
}
int
nvif_client_suspend(struct nvif_client *client)
{
return client->driver->... |
google | android | r128_cce | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/r128/r128_cce.c | 24,319 | utf_8 | f4f6515805ba841294314a78b07e2db7 | /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
*/
#include <linux/firmware.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <drm/drmP.h>
#include <drm/r128_drm.h>
#include "r128_drv.h"
#define R128_FIFO_DEBUG 0
#define FIRMWARE_NAME "r128/r128_cce.bin"
MODULE_FIR... |
google | android | r128_state | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/r128/r128_state.c | 40,790 | utf_8 | 0c9476ab707b6446543f164c88e4da0a | /* r128_state.c -- State support for r128 -*- linux-c -*-
*/
#include <drm/drmP.h>
#include <drm/r128_drm.h>
#include "r128_drv.h"
/* ================================================================
* CCE hardware state programming functions
*/
static void r128_emit_clip_rects(drm_r128_private_t *dev_priv,
stru... |
google | android | r128_drv | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/r128/r128_drv.c | 3,461 | utf_8 | a463887eb6462b6f50ebb9856d0188b8 | /* r128_drv.c -- ATI Rage 128 driver -*- linux-c -*-
*/
#include <linux/module.h>
#include <drm/drmP.h>
#include <drm/r128_drm.h>
#include "r128_drv.h"
#include <drm/drm_pciids.h>
static struct pci_device_id pciidlist[] = {
r128_PCI_IDS
};
static const struct file_operations r128_driver_fops = {
.owner = THIS_MODULE... |
google | android | r128_ioc32 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/r128/r128_ioc32.c | 7,005 | utf_8 | 8e2a96644ef70c93bafd662e16f1422b | /**
* \file r128_ioc32.c
*
* 32-bit ioctl compatibility routines for the R128 DRM.
*
*/
#include <linux/compat.h>
#include <drm/drmP.h>
#include <drm/r128_drm.h>
#include "r128_drv.h"
typedef struct drm_r128_init32 {
int func;
unsigned int sarea_priv_offset;
int is_pci;
int cce_mode;
int cce_secure;
int ring... |
google | android | r128_irq | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/r128/r128_irq.c | 3,541 | utf_8 | d824163e5bff84dd1217e38d0ee5e4ac | /* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- */
/*
*/
#include <drm/drmP.h>
#include <drm/r128_drm.h>
#include "r128_drv.h"
u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
{
const drm_r128_private_t *dev_priv = dev->dev_private;
if (pipe != 0)
return 0;
return atomic_read(&dev_p... |
google | android | i810_drv | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i810/i810_drv.c | 3,148 | utf_8 | d0646ad78e6951768cc0b42768ebf915 | /* i810_drv.c -- I810 driver -*- linux-c -*-
*/
#include <linux/module.h>
#include <drm/drmP.h>
#include <drm/i810_drm.h>
#include "i810_drv.h"
#include <drm/drm_pciids.h>
static struct pci_device_id pciidlist[] = {
i810_PCI_IDS
};
static const struct file_operations i810_driver_fops = {
.owner = THIS_MODULE,
.open... |
google | android | i810_dma | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/i810/i810_dma.c | 33,266 | utf_8 | 6cb0d8a2e81e10050690e8870ed852ad | /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
*
*/
#include <drm/drmP.h>
#include <drm/i810_drm.h>
#include "i810_drv.h"
#include <linux/interrupt.h> /* For task queue support */
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pagemap.h>
#define I810_BUF_FREE 2
#define I810_BUF_CLIENT 1... |
google | android | panel-sharp-lq101r1sx01 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c | 10,668 | utf_8 | 8708cdbb6f6200894131ee963fd60013 | /*
*/
#include <linux/backlight.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_panel.h>
#include <video/mipi_display.h>
struct sharp_panel {
struct... |
google | android | panel-lg-lg4573 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/panel/panel-lg-lg4573.c | 6,672 | utf_8 | 3af6f702e51962c2218f80665d84ebda | /*
*/
#include <drm/drmP.h>
#include <drm/drm_panel.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <video/mipi_display.h>
#include <video/of_videomode.h>
#include <video/videomode.h>
struct lg4573 {
struct drm_panel panel;
struct spi_device *spi;
struct ... |
google | android | panel-simple | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/panel/panel-simple.c | 32,670 | utf_8 | bdafa62c30192ebfd78c4f988e1429d5 | /*
*/
#include <linux/backlight.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_panel.h>
#include <video/... |
google | android | panel-samsung-s6e8aa0 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/panel/panel-samsung-s6e8aa0.c | 29,670 | utf_8 | 7ff20973c1c18a88bbb9502b793f34b7 | /*
* MIPI-DSI based s6e8aa0 AMOLED LCD 5.3 inch panel driver.
*
*/
#include <drm/drmP.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_panel.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
#include <video/of_videomode.h>
#include <video/videomode.h>
#define ... |
google | android | panel-samsung-ld9040 | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/panel/panel-samsung-ld9040.c | 11,440 | utf_8 | c088c5af7281eff3f605c70ddd56288a | /*
* ld9040 AMOLED LCD drm_panel driver.
*
*/
#include <drm/drmP.h>
#include <drm/drm_panel.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <video/mipi_display.h>
#include <video/of_videomode.h>
#include <video/videomode.h>
/* Manufacturer Command Set */
#... |
google | android | ast_drv | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/ast/ast_drv.c | 5,636 | utf_8 | 1d79a1f78123a02e0fc3739649ca82dc | /*
*/
#include <linux/module.h>
#include <linux/console.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include "ast_drv.h"
int ast_modeset = -1;
MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
module_param_named(modeset, ast_modeset, int, 0400);
#define PCI_VENDOR_ASPEED 0x1a03
static struct drm_d... |
google | android | ast_mode | .c | platform/hardware/bsp/kernel/intel/edison-v4.4/drivers/gpu/drm/ast/ast_mode.c | 34,743 | utf_8 | 775a16dd5f09311e58200af20ff8f757 | /*
*/
#include <linux/export.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>
#include "ast_drv.h"
#include "ast_tables.h"
static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
stat... |
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