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To: Joseph Losby <joseph.losby at ucalgary.ca<mailto:joseph.losby at ucalgary.ca>>; labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: Re: [labnetwork] Is your facility ISO certified?
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Joseph,
ISO certification is primarily for a manufacturing facility. I don't know of any benefit a shared use facility (I'm assuming that's what you have) would gain.
Becoming ISO certified is extremely expensive and disruptive, you must also allow annual "audits" to your facility which again are very expensive and disruptive.
Iso Certification, in simple terms is just an accreditation that you do what you document and document what you do.
I remember confronting the CEO of a company that I used to work for and asking him if it made the facility any better, his answer was a firm "NO". I then inquired as to why we do it and the answer was "Because our competition has it".
Best of luck,
Steve Paolini Equipment Dood
Harvard University
________________________________
From: labnetwork <labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu>> on behalf of Joseph Losby <joseph.losby at ucalgary.ca<mailto:joseph.losby at ucalgary.ca>>
Sent: Wednesday, March 22, 2023 12:47 PM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu> <labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>>
Subject: [labnetwork] Is your facility ISO certified?
Hello.
Is your cleanroom facility ISO certified? What are your reasons for having or not having ISO certification? Are there any particular changes you have had to make to your facility to adhere to standards?
The costs appear to be substantial, and we are still deciding whether or not we should go this route.
Cheers and thanks for your replies,
Joe
Joseph Losby, PhD.
Operations Manager, qLab
Quantum City, University of Calgary
The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. Is e buidheann carthannais a th' ann an Oilthigh Dh?n ?ideann, cl?raichte an Alba, ?ireamh cl?raidh SC005336.
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From sturm at princeton.edu Fri Mar 24 10:48:49 2023
From: sturm at princeton.edu (James C. Sturm)
Date: Fri, 24 Mar 2023 14:48:49 +0000
Subject: [labnetwork] Dry Bed Scrubber for silane, etc
Message-ID: <DM6PR04MB439672E86ED63FDBEB6FFD82BB849@DM6PR04MB4396.namprd04.prod.outlook.com>
We have a Si/Ge UHV CVD system for which we want to purchase a dedicated dry bed scrubber.
Total N2 purges ~38 lpm (from several dry pumps, etc)
Total H2 100 sccm when purging, but normally < 20 sccm
Silane ~2 sccm, Germane < 0.05 sccm, Diborane and phosphine < 0.01 sccm.
Running < 10 hours a week on average.
We are looking into a Callisto dry bed scrubber (by Jupiter). We have no experience with such systems, having used a hot "combustion chamber" with air pumped in for 20+ years.
Comments/suggestions/other manufacturers/"been there done that" are welcome.
Thanks,
Jim Sturm and Zoe Cyue, Princeton University
********************************************
Prof. James C. Sturm
Chair, Department of Electrical and Computer Engineering
Stephen R. Forrest Professor in Electrical Engineering
Princeton University
B210 E-Quad, Olden St.
Princeton, NJ 08540
609-258-5610, fax: 609-258-1177
sturm at princeton.edu<mailto:sturm at princeton.edu>
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From deolivei at ualberta.ca Fri Mar 24 13:37:04 2023
From: deolivei at ualberta.ca (Gustavo de Oliveira Luiz)
Date: Fri, 24 Mar 2023 11:37:04 -0600
Subject: [labnetwork] Strange "sample memory" with LOR 5B
Message-ID: <CALPuYFzLg-QX5tPGX7qShke=8o75W=xVb_NB0tUYquFskr4FRg@mail.gmail.com>
Hello everyone,
While working on a recipe for LOR 5B/AZ 1512 in our automatic development
system, I encountered some intriguing effects when reusing wafers for my
tests. This could be a problem for our users when developing their own
process, so we'd appreciate it if anyone could help us to understand what
is going on.
Below is a picture of a sample right before exposure, taken using our
MLA150. The dark/bright features you see are NOT etched on the wafer (these
wafers were never etched). The marks are from a previous lithography test.
They become apparent after coating the sample with LOR 5B and even more
after adding AZ 1512. And I don't see them when coating only with AZ 1512
(I reused wafers for that process development without any issues).
[image: Si_w_Oxide_LOR5b-AZ1512_AsCoated.png]
And what is more intriguing is that these features affect
exposure/development of my test mask. For instance, on a virgin sample I
can expose and auto-develop with the same recipe (dose and development
time) I use for the manual process. On a reused sample, the reisst stack
behaves as if it were underexposed (a dose test made this very obvious).
Here are the steps during my tests:
1. Piranha clean
2. HMDS prime on a YES oven
3. Spin-coat with LOR 5B/AZ 1512 (marks show up on a reused sample)
4. Expose using either a mask aligner or DWL
5. Auto-develop in our Laurell EDC-650 (resist seems underexposed over
the marks)
1. AZ Developer 1:1 ? 90 s
2. Rinse (DI water) and dry (N2+spin) ? 60-120 s
3. MF-319 ? 5 s
4. Rinse (DI water) and dry (N2+spin) ? 60-120 s
6. Strip resist with Remover PG
7. Repeat all steps for every iteration
At first I thought that this could actually be some etching of my Si wafers
by MF-319, even though unlikely given the low TMAH concentration (and I'm