module_content stringlengths 18 1.05M |
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module sky130_fd_sc_lp__buflp_m (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A)
);
endmodule |
module at89s5xdip40(data, ale, write, read, osc_in, zif);
inout [7:0] data;
input ale;
input write;
input read;
input osc_in; /* 24MHz oscillator */
inout [48:1] zif;
/* Interface to the microcontroller */
wire read_oe; /* Read output-enable */
reg [7:0] address; /* Cached address value */
reg [7:0] read_da... |
module Write_Back(
clk_i,
rst_i,
gbl_stl_i,
wait_to_fill_pipe_i,
control_signal_i,
p_i,
dat_i,
eff_adr_i,
mem_stl_i,
a_o,
x_o,
y_o,
mem_w_enb_o,
mem_w_cnt_o,
mem_w_adr_o,
mem_w_dat_o
`ifdef DEBUG
,debug_o
`endif
);
//Input signals ... |
module sky130_fd_sc_ls__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
... |
module sky130_fd_sc_hdll__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module FLOW_CONTROLLER(
clk,
rst_n,
init_rst_i,
mrd_start_i,
mrd_len_i,
//mrd_cur_rd_count_i,
mrd_tlp_sent_i,
cpld_data_size_i,
cfg_rd_comp_bound_i,
rd_metering_i,
mwr_start_i,
trn_tbuf_av_i,
mrd_start_fc_o,
... |
module sky130_fd_sc_lp__srsdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPB ,
inp... |
module altera_mem_if_ddr3_phy_0001_new_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_mem_address,
... |
module vga_controller_640_60 (rst,pixel_clk,HS,VS,hcounter,vcounter,blank);
input rst, pixel_clk; // global reset, pixel clock
output reg HS, VS, blank; // sync controls, blank indicator
output reg [10:0] hcounter, vcounter; // pixel coordinates
/*
parameter HMAX = 800; // maxium value for the horizontal pixel ... |
module mfp_ahb_lite_eic
(
//ABB-Lite side
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0 ] ... |
module
//GT Parameters
parameter REF_CLK_FREQ = 0, // Reference Clock Frequency
parameter PCIE_EXT_CLK = "TRUE",
parameter PCIE_EXT_GT_COMMON = "FALSE",
parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP
parameter PCIE_DRP ... |
module MemoryManagerUnit(
input clk, //very slow clock
input clk_50M,
input[14:0] MemAddr,
input MemWrite,
input MemRead,
input SaveHalf,
input LoadHalf,
input[31:0] MemWriteData,
input ChipSelect,
output[31:0] MemReadData,
output reg MemOK,
output hsync, //ÐÐͬ²½ÐźÅ
output vsync, //³¡Í¬²½ÐźÅ
output vga_r,
output v... |
module sky130_fd_sc_ms__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module regfile_16x32b_4rd_2wr_tb;
// Inputs
reg clk;
reg rst;
reg [3:0] rdport1_ctrl_add;
reg [3:0] rdport2_ctrl_add;
reg [3:0] rdport3_ctrl_add;
reg [3:0] rdport4_ctrl_add;
reg [3:0] wrport1_ctrl_add;
reg [31:0] wrport1_data_in;
reg wrport1_wren;
reg [3:0] wrport2_ctrl_add;
reg [3... |
module sky130_fd_sc_ls__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_... |
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5... |
module userio_osd
(
input clk, // 28MHz clock
input clk7_en,
input clk7n_en,
input reset, //reset
input c1, //clk28m domain clock enable
input c3,
input sol, //start of video line
input sof, //start of video frame
input varbeamen,
input [7:0] osd_ctrl, //keycode for OSD control (Amiga ... |
module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI... |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
genvar g;
integer i;
reg [31:0] v;
reg [31:0] gen_pre_PLUSPLUS = 32'h0;
reg [31:0] gen_pre_MINUSMINUS = 32'h0;
reg [31:0] gen_post_PLUSPLUS = 32'h0;
reg [31:0] gen_post_MINUSMINUS = 32'h0;
reg [31:0] gen_PLUSEQ... |
module design_1_auto_us_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_... |
module bus_master_mux (
/********** ÊäÈëÊä³öÐźŠ**********/
// 0ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m0_addr, // µØÖ·
input wire m0_as_, // µØַѡͨ
input wire m0_rw, // ¶Á/д
input wire [`WordDataBus] m0_wr_data, // дÈëµÄÊý¾Ý
input wire m0_grnt_, // ¸³Óè×ÜÏß
// 1ºÅ×ÜÏßÖ÷¿Ø
... |
module CPU(input clk,rst);
wire[1:0] stackContrl,pcContrl;
wire[5:0] cntrlInstruc;
DataPath dp(clk,rst,RdOrR2,AluOrMem,RFWE,MWE,stackContrl,pcContrl,Zero,Cout,cntrlInstruc);
Controller cntrl(clk,rst,RdOrR2,AluOrMem,RFWE,MWE,stackContrl,pcContrl,Zero,Cout,cntrlInstruc);
endmodule |
module CPUTB();
initial begin
$dumpfile("CPUTB.vcd");
$dumpvars;
end
//integer outfile,regFile;
integer i,ramOut;
reg clk,rst;
parameter delta = 10;
initial begin clk = 0; forever #delta clk = ~clk; end
CPU UUT(clk,rst);
initial begin
ramOut = $fopen("ramModified.bin") | 1;
//regFile = $fopen("regsOut.... |
module pcie_7x_v1_11_0_pipe_eq #
(
parameter PCIE_SIM_MODE = "FALSE",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_RXEQ_MODE_GEN3 = 1
)
(
//---------- Input -------------------------------------
input EQ_CLK,
input EQ_RST_N... |
module sky130_fd_sc_hd__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
... |
module DatapathTestFinal;
// Inputs
reg clock;
reg resetGral;
// Outputs
wire ALUzero;
wire ALUOverflow;
// Instantiate the Unit Under Test (UUT)
Datapath1 uut (
.clock(clock),
.resetGral(resetGral),
.ALUzero(ALUzero),
.ALUOverflow(ALUOverflow)
);
initial begin
// Initialize Inputs
clock = ... |
module exunit_mul
(
input wire clk,
input wire reset,
input wire [`DATA_LEN-1:0] ex_src1,
input wire [`DATA_LEN-1:0] ex_src2,
input wire dstval,
input wire [`SPECTAG_LEN-1:0] spectag,
input wire specbit,
input wire src1_signed,
input wire src2_signed,
input wi... |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule |
module sky130_fd_sc_hdll__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module TopLevel(clk,
key_in,
switch_in,
switch_second,
type_in,
s_out,
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RW,
LCD_RS,
LCD_DATA
);
input [3:0] key_in;
input clk;// 50Mhz clock signal
input switch_in; // switch of settime of countdowner
input [15:0] switch_second;... |
module simpleio (
input wire clk,
input wire rst,
input wire [3:0] AD,
input wire [7:0] DI,
output reg [7:0] DO,
input wire rw,
input wire cs,
output wire irq,
input wire clk_in,
// physical connections
output reg [7:0] leds,
output reg [7:0] led7hi,
output reg [7:0] led7lo,
output reg ... |
module fir_bp_lr(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]" */;
input aclk;
input s_axis_data_tval... |
module sky130_fd_sc_hs__udp_dff$NSR_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
input SET ,
//# {{clocks|Clocking}}
input CLK_N,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule |
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output ... |
module sky130_fd_sc_hd__ha_2 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
... |
module sky130_fd_sc_hd__ha_2 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
... |
module cmd_proc
(
output reg reply_data,
output reg reply_complete,
output reg dr,
output reg [1:0]m,
output reg trext,
output reg en_2nd_clk_cp,
output reg en_tx,
output reg en_prng_idol,
output reg en_prng_act,
output reg en_crc16_for_rpy,
output reg en_if,
output reg [18:0]addr,
input clk_cp,
input cl... |
module sky130_fd_sc_hd__tapvgnd2 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule |
module scratch_pad_tb;
//TODO: clean up code, fewer display statements
`include "log2.vh"
`include "abs.vh"
`include "constants.vh"
parameter PORTS = 4;
parameter REORDER_DEPTH=64;
parameter OUT_FILE="simulation.csv";
//TODO: track down why WIDTH=8 does not work
`define WIDTH 64
... |
module NormaliseProd(
input [35:0] cout_Multiply,
input [35:0] zout_Multiply,
input [31:0] sout_Multiply,
input [49:0] productout_Multiply,
input [1:0] modeout_Multiply,
input operationout_Multiply,
input NatLogFlagout_Multiply,
input [7:0] InsTag_Multiply,
input clock,
input [1:0] idle_Multiply,
... |
module design_1_xlslice_6_3 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(30),
.DIN_TO(7)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule |
module mig_7series_v1_9_memc_ui_top_std #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
param... |
module NW_vc_switch_allocator (req,
req_priority, // for flit prioritisation support
output_port,
grant,
vc_mux_sel, // not used by Lochside
xbar_select, // not used by Lochside
any_request_for_output, // not used by Lochs... |
module state_control(
input CLK, START, RESET, BTN_PLAYER1, BTN_PLAYER2,
input [3:0] iSW,
output [7:0] OLED,
output reg [8:0] occupied,
output reg [8:0] symbol
);
// state parameter
localparam IDLE = 2'd0;
localparam PLAYER1 = 2'd1;
localparam PLAYER2 = 2'd2;
localparam FINISH = 2'd3;
// win parameter
localparam ... |
module ssdCtrl(
CLK,
RST,
DIN,
AN,
SEG,
DOT,
bcdData
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input CLK;
input ... |
module sky130_fd_sc_ms__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module mult #(parameter WIREWIDTH = 1) (input wire clk,
input wire [WIREWIDTH:0] x,y,
output reg [WIREWIDTH:0] res); /* FIXME: reswidth! */
initial begin
$schematic_boundingbox(100,120);
$schematic_arc(50,60,40);
$schematic_linestart;
$schematic_coord(20,110);
$schematic_coo... |
module mpram_lvt
#( parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter nRPF = 2 , // number of fixed read ports
parameter nWPF = 2 , // number of fixed write ports
parameter nRPS = 2 , // number of switched read ports
parameter nWPS = 2 , // number of sw... |
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'b... |
module db_pipeline(
//input
clk ,
rst_n ,
tu_edge_i ,
pu_edge_i ,
qp_p_i ,
qp_q_i ,
cbf_p_i ,
cbf_q_i ,
mv_p_i ,
mv_q_i ,
mb_type_i ,
is_ver_i ,
is_luma_i ,
is_tran_i ,
p_i ,
q_i ,
//out... |
module tb_sys_top();
localparam HCLK = 5;
localparam PCLK = 2*HCLK; /* Clock period */
reg clk;
reg nrst;
always
#HCLK clk = !clk;
initial
begin
/* Set tracing */
if(!$test$plusargs("NOTRACE"))
begin
$dumpfile(`TRACE_FILE);
$dumpvars(0, tb_sys_top);
end
clk = 1;
nrst = 0;
#(10*PCLK) nr... |
module zc702_auto_us_df_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_... |
module sky130_fd_sc_ls__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input V... |
module sky130_fd_sc_hs__dlymetal6s6s (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output O... |
module system_vga_hessian_1_0(clk_x16, active, rst, x_addr, y_addr, g_in,
hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]" */;
input clk_x16;
input active;
input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
... |
module sky130_fd_sc_hs__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule |
module lab3_master_0_timing_adt (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input [ 7: 0] in_data,
// Interface: out
output reg out_valid,
output re... |
module add_sub_carry_out_W8_DW01_add_0 ( A, B, CI, SUM, CO );
input [8:0] A;
input [8:0] B;
output [8:0] SUM;
input CI;
output CO;
wire n3, n4;
wire [8:1] carry;
CMPR32X2TS U1_6 ( .A(A[6]), .B(B[6]), .C(carry[6]), .CO(carry[7]), .S(SUM[6]) );
CMPR32X2TS U1_5 ( .A(A[5]), .B(B[5]), .C(carry[5]), .C... |
module add_sub_carry_out_W8_DW01_sub_0 ( A, B, CI, DIFF, CO );
input [8:0] A;
input [8:0] B;
output [8:0] DIFF;
input CI;
output CO;
wire n12, n13, n14, n15, n16, n17, n18, n19, n20;
wire [9:0] carry;
CMPR32X2TS U2_7 ( .A(A[7]), .B(n13), .C(carry[7]), .CO(carry[8]), .S(DIFF[7]) );
CMPR32X2TS U2_6... |
module add_sub_carry_out_W8 ( op_mode, Data_A, Data_B, Data_S );
input [7:0] Data_A;
input [7:0] Data_B;
output [8:0] Data_S;
input op_mode;
wire N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17,
N18, N19, N20, n3;
add_sub_carry_out_W8_DW01_add_0 add_36 ( .A({1'b0, Data_A}), .B... |
module Greater_Comparator_W9 ( Data_A, Data_B, gthan );
input [8:0] Data_A;
input [8:0] Data_B;
output gthan;
wire N0, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35;
assign gthan = N0;
INVX2TS U1 ( .A(n19), .Y(n29) );
... |
module Comparator_Less_W9 ( Data_A, Data_B, less );
input [8:0] Data_A;
input [8:0] Data_B;
output less;
wire N0, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35;
assign less = N0;
AOI22X1TS U1 ( .A0(n24), .A1(n30), .B0(... |
module Comparators_W_Exp9 ( exp, overflow, underflow );
input [8:0] exp;
output overflow, underflow;
Greater_Comparator_W9 GTComparator ( .Data_A(exp), .Data_B({1'b0, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0}), .gthan(overflow) );
Comparator_Less_W9 LTComparator ( .Data_A(exp), .Data_B({1'b0, 1... |
module RegisterAdd_W8 ( clk, rst, load, D, Q );
input [7:0] D;
output [7:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n17,
n19, n20;
DFFRX2TS \Q_reg[7] ( .D(n17), .CK(clk), .RN(n20), .Q(Q[7]), .QN(n8) );
DFFRX2TS \Q_reg[6] ( .D(n15), .CK(cl... |
module RegisterAdd_W1_3 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4, n6;
DFFRX2TS \Q_reg[0] ( .D(n3), .CK(clk), .RN(n6), .Q(Q[0]), .QN(n4) );
OAI2BB2XLTS U2 ( .B0(n4), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n6) );
endmodule |
module RegisterAdd_W1_2 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4, n6;
DFFRX2TS \Q_reg[0] ( .D(n3), .CK(clk), .RN(n6), .Q(Q[0]), .QN(n4) );
OAI2BB2XLTS U2 ( .B0(n4), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n6) );
endmodule |
module Exp_Operation ( clk, rst, load_a_i, load_b_i, Data_A_i, Data_B_i,
Add_Subt_i, Data_Result_o, Overflow_flag_o, Underflow_flag_o );
input [7:0] Data_A_i;
input [7:0] Data_B_i;
output [7:0] Data_Result_o;
input clk, rst, load_a_i, load_b_i, Add_Subt_i;
output Overflow_flag_o, Underflow_flag_o;
... |
module fifo_65_256 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [64:0] data;
input rdreq;
input wrreq;
output empty;
output [64:0] q;
wire sub_wire0;
wire [64:0] sub_wire1;
wire empty = sub_wire0;
wire [64:0] q = sub_wire1[64:0];
scfifo scfifo_componen... |
module byte_lane #(
// these are used to scale the index into phaser,calib,scan,mc vectors
// to access fields used in this instance
parameter ABCD = "A", // A,B,C, or D
parameter PO_DATA_CTL = "FALSE",
parameter BITLANES = 12'b1111... |
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
... |
module dmem(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
input [7:0] WD;
output [7:0] RD;
input WEN, REN;
input [9:0] WADDR, RADDR;
input RWCLK, RESET;
wire VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
RAM4K9 dmem_R0C1(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
WADDR[9]), .ADDRA8(WADD... |
module TEST_MAIN;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg C0;
// Outputs
wire [3:0] F;
wire C4;
// Instantiate the Unit Under Test (UUT)
MAIN uut (
.A(A),
.B(B),
.C0(C0),
.F(F),
.C4(C4)
);
initial begin
// Initialize Inputs
A = 4'b0000;
B = 4'b0000;
C0 = 0;
... |
module sky130_fd_sc_lp__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module
//-------------------------------------------------------------------
address_swap_module_8 client_side_asm (
.rx_ll_clock (ll_clk_i),
.rx_ll_reset (ll_reset_i),
.rx_ll_data_in (rx_ll_data_i),
.rx_ll_sof_in_n (rx_ll_sof_n_i),
.rx_ll_eof... |
module sky130_fd_sc_hd__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule |
module sky130_fd_sc_ms__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
... |
module usb_system_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
... |
module usb_system_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
... |
module usb_system_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
... |
module usb_system_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
... |
module usb_system_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
... |
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = ... |
module sky130_fd_sc_ls__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn;
// ... |
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input ... |
module sky130_fd_sc_lp__sdfstp_lp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input ... |
module sky130_fd_sc_lp__sdfstp_lp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
... |
module sky130_fd_sc_hs__a21oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
... |
module sky130_fd_sc_hs__a21oi_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule |
module pulse_synchronizer
( input pulse_in_clkA,
input clkA,
output pulse_out_clkB,
input clkB,
input reset_clkA,
input reset_clkB
);
reg ackA;
reg ackB;
reg ackA_synch;
reg ackA_clkB;
reg ackB_synch;
reg ackB_clkA;
reg p... |
module picorv32 #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] LATCHED_MEM_RDATA = 0,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] ... |
module doubleMulWrapper (
clock,
dataa,
datab,
result,
dummy_enable);
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
input dummy_enable;
doubleMul doubleMul (
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule |
module tb_rxadc_2;
// SPI slave port
reg SPI_CSL;
reg SPI_MOSI;
wire SPI_MISO;
reg SPI_SCLK;
// rxadc board interface
reg rxadc_clk;
wire rxadc_dfs;
reg rxadc_otr;
reg [9:0] rxadc_dat;
// DAC I2S output
wire dac_mclk;
wire dac_sdout;
wire dac_sclk;
wire dac_lrck;
// MCU I2S output... |
module sky130_fd_sc_hs__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sky130_fd_sc_ls__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB... |
module jbi_l2_buf2(/*AUTOARG*/
// Outputs
jbi_sctag_req_buf, scbuf_jbi_data_buf, jbi_scbuf_ecc_buf,
jbi_sctag_req_vld_buf, scbuf_jbi_ctag_vld_buf,
scbuf_jbi_ue_err_buf, sctag_jbi_iq_dequeue_buf,
sctag_jbi_wib_dequeue_buf, sctag_jbi_por_req_buf,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf... |
module sky130_fd_sc_ms__bufbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module system_buffer_register_1_0(clk, val_in, val_out)
/* synthesis syn_black_box black_box_pad_pin="clk,val_in[31:0],val_out[31:0]" */;
input clk;
input [31:0]val_in;
output [31:0]val_out;
endmodule |
module sky130_fd_sc_hd__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
... |
module sky130_fd_sc_hd__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
... |
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20,
n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
n35, n36, n37, n38, n3... |
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