module_content stringlengths 18 1.05M |
|---|
module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule |
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45... |
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule |
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule |
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),... |
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule |
module v145d1e (
input [31:0] vb79ed5,
input [7:0] vc74a9c,
input v6287a6,
input v19f646,
output [31:0] vb76294
);
wire [0:31] w0;
wire [0:31] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:31] w5;
wire [0:31] w6;
wire [0:31] w7;
wire [0:7] w8;
wire w9;
wire w10;
assign w6 = vb79ed5;
assign ... |
module v15006c (
input [31:0] v53354a,
input [31:0] v3d79e8,
input v2d3366,
output [31:0] vd99bd0
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:31] w3;
wire [0:31] w4;
wire [0:31] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire [0:7] w13;
wire [0... |
module v1bbb5b (
input [7:0] v2a1cbe,
input [7:0] v9d7ae8,
input v2d3366,
output [7:0] v9d2a6a
);
wire [0:3] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire [0:3] w10;
assign v9d2a6a = w1;
assign w2 = v2a1cbe;
assign w... |
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
... |
module v78e0a3 (
input [7:0] v12d067,
input [7:0] v6127ee,
input [7:0] vea9d11,
input [7:0] v29bdec,
output [31:0] v7d0a31
);
wire [0:31] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
assign v7d0a31 = w0;
assign w1 = v29bdec;
assign w2 = vea9d11;
assign w3 = v6127ee;
assign w4 = v12d067... |
module v78e0a3_v9a2a06 (
input [7:0] i3,
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [31:0] o
);
assign o = {i3, i2, i1, i0};
endmodule |
module vda0861 #(
parameter vfffc23 = 0
) (
output [7:0] vffb58f
);
localparam p0 = vfffc23;
wire [0:7] w1;
assign vffb58f = w1;
vffc517 #(
.vc5c8ea(p0)
) v778577 (
.va0aeac(w1)
);
endmodule |
module vffc517 #(
parameter vc5c8ea = 0
) (
output [7:0] va0aeac
);
localparam p0 = vc5c8ea;
wire [0:7] w1;
assign va0aeac = w1;
vffc517_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule |
module vffc517_v465065 #(
parameter VALUE = 0
) (
output [7:0] k
);
assign k = VALUE;
endmodule |
module v04e061 #(
parameter v001ed5 = 1
) (
input vd6bebe,
output v4642b6,
output [4:0] vb385cd,
output vd9f5b6
);
localparam p1 = v001ed5;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:4] w8;
wire w9;
wire w10;
wire w11;
wire [0:4] w12;
assign v4642b6 = w2;
assign vd9f5b6 =... |
module v144728 #(
parameter v573b2a = 0
) (
input v6dda25,
input v27dec4,
input v92a149,
output v4642b6
);
localparam p0 = v573b2a;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w5 = v6dda25;
assign v4642b6 = w6;
assign w8 = v27dec4;
assign w9 = v92a149;
ass... |
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule |
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule |
module vaf1249 (
input v6dda25,
input ve556f1,
output [4:0] va1c800,
output ve37344
);
wire w0;
wire [0:4] w1;
wire [0:4] w2;
wire w3;
wire [0:4] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign va1c800 = w4;
assign ve37344 = w5;
assign w4 = w1;
v6ed669 vad9b51 (
.v782748(w0),
.vcc30ea(... |
module v6ed669 (
input v6dda25,
input v782748,
input [4:0] v35dd11,
output [4:0] vcc30ea
);
wire [0:4] w0;
wire [0:3] w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:4] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = v35dd11;
assign vcc30ea = w5;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 =... |
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),... |
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
a... |
module vcdce79 (
input vee8a83,
input [3:0] v167ed7,
output [4:0] v6a2e9e
);
wire [0:4] w0;
wire w1;
wire [0:3] w2;
assign v6a2e9e = w0;
assign w1 = vee8a83;
assign w2 = v167ed7;
vcdce79_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule |
module vcdce79_v9a2a06 (
input i1,
input [3:0] i0,
output [4:0] o
);
assign o = {i1, i0};
endmodule |
module vd0bb30 #(
parameter v6c5139 = 1
) (
input [4:0] vd03823,
output v4642b6,
output [4:0] vb4c454
);
localparam p1 = v6c5139;
wire w0;
wire [0:4] w2;
wire [0:4] w3;
assign v4642b6 = w0;
assign w2 = vd03823;
assign vb4c454 = w3;
va17f79 #(
.vd73390(p1)
) vc288d0 (
.v4642b6(w0),
.va6f14e(w2),
.v9... |
module va17f79 #(
parameter vd73390 = 0
) (
input [4:0] va6f14e,
output v4642b6,
output [4:0] v919f01
);
localparam p1 = vd73390;
wire w0;
wire [0:4] w2;
wire [0:4] w3;
wire [0:4] w4;
assign v4642b6 = w0;
assign w3 = va6f14e;
assign v919f01 = w4;
v0cfc7a v530cb5 (
.v4642b6(w0),
.v225d34(w2),
.vbb6b94... |
module v0cfc7a (
input [4:0] v225d34,
input [4:0] vbb6b94,
output v4642b6,
output [4:0] vae8b91
);
wire w0;
wire w1;
wire [0:4] w2;
wire [0:4] w3;
wire [0:4] w4;
wire w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire w9;
wire [0:3] w10;
assign w2 = vbb6b94;
assign w3 = v225d34;
assign vae8b91 = w4;
ass... |
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w... |
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
... |
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)... |
module v51353d (
input [4:0] v083523,
input v427380,
output [4:0] v81cd93
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:4] w8;
wire w9;
wire [0:4] w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
assign w1 = v427380;
assign w2 = v427380;
assign... |
module v60f5a9 (
input [4:0] v427dd1,
output v53baa6,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:4] w5;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign v53baa6 = w4;
assign w5 = v427d... |
module v60f5a9_v9a2a06 (
input [4:0] i,
output o4,
output o3,
output o2,
output o1,
output o0
);
assign o4 = i[4];
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule |
module v36cddd (
input v684b0d,
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [4:0] v6a2e9e
);
wire w0;
wire w1;
wire [0:4] w2;
wire w3;
wire w4;
wire w5;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign v6a2e9e = w2;
assign w3 = vf8041d;
assign w4 = vd84a57;
assign w5 = v684b0d;
... |
module v36cddd_v9a2a06 (
input i4,
input i3,
input i2,
input i1,
input i0,
output [4:0] o
);
assign o = {i4, i3, i2, i1, i0};
endmodule |
module altera_up_character_lcd_communication (
// Inputs
clk,
reset,
data_in,
enable,
rs,
rw,
display_on,
back_light_on,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
data_out,
transfer_complete
);
/************************************************************... |
module small_async_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 3,
parameter ALMOST_FULL_SIZE = 5,
parameter ALMOST_EMPTY_SIZE = 3
)
(
//wr interface
output wfull,
output w_almost_full,
input [DSIZE-1:0] wdata,
input winc, wclk, wrst_n,
//rd interfa... |
module sync_r2w #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk, wrst_n);
reg [ADDRSIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rp... |
module sync_w2r #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] rq2_wptr,
input [ADDRSIZE:0] wptr,
input rclk, rrst_n);
reg [ADDRSIZE:0] rq1_wptr;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;
else {rq2_wptr,rq1_wptr} <= {rq1_wptr... |
module rptr_empty
#(parameter ADDRSIZE = 3,
parameter ALMOST_EMPTY_SIZE=3)
(output reg rempty,
output reg r_almost_empty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input [ADDRSIZE :0] rq2_wptr,
input rinc, rclk, rrst_n);
reg [ADDRSIZE:0] rbin;
wire [ADDRS... |
module wptr_full
#(parameter ADDRSIZE = 3,
parameter ALMOST_FULL_SIZE=5
)
(output reg wfull,
output reg w_almost_full,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input [ADDRSIZE :0] wq2_rptr,
input winc, wclk, wrst_n);
reg [ADDRSIZE:0] wbin;
wire [AD... |
module fifo_mem #(parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 3) // Number of mem address bits
(output [DATASIZE-1:0] rdata,
input [DATASIZE-1:0] wdata,
input [ADDRSIZE-1:0] waddr, raddr,
input wclken, wfull, wclk);
// RTL Verilog memory model
localparam DE... |
module block_design_m01_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_... |
module ded_top
#(parameter BYTES = 16)
(
// Global Signals
input de_clk, // Drawing Engine Clock
de_rstn, // Drawing Engine Reset
// Host/ XY Windows
input hb_clk, // host bus clock
hb_rstn, // host bus reset
... |
module mt48lc4m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter addr_bits = 12;
parameter data_bits = 16;
parameter col_bits = 8;
parameter mem_sizes = 1048575;
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input ... |
module pcie3_7x_0_pipe_sync #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
... |
module pcie (
input wire sys_clk_250, // 250 Mhz Clock
input wire sys_clk_125, // 125 Mhz Clock
input wire rst_n, // asynchronous system reset.
input wire inta_n,
i... |
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module pipeline_CPU (
input clk,
input rst,
input[`RegDataWidth-1:0] data_from_mem,
output[`MemAddrWidth-1:0] mem_addr,
output[3:0] mem_byte_slct,
output[`RegDataWidth-1:0] data_to_write_mem,
output mem_we,
output mem_re,
input[`InstDataWidth-1:0] inst_from_rom,
output[`InstAddrWi... |
module
mulAddRecF16_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output [15:0] out_imul
);
wire [16:0] re... |
module
mulAddRecF32_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output [31:0] out_imul
);
wire [32:0] re... |
module
mulAddRecF64_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output [63:0] out_imul
);
wire [64:0] re... |
module
mulAddRecF128_add (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [127:0] out_imul;
wire [128:0] recF128_1 = 129'h08000000000... |
module
mulAddRecF16_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output [15:0] out_imul
);
wire [16:0] ze... |
module
mulAddRecF32_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output [31:0] out_imul
);
wire [32:0] ze... |
module
mulAddRecF64_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output [63:0] out_imul
);
wire [64:0] ze... |
module
mulAddRecF128_mul (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [128:0] zeroAddend = {a[128] ^ b[128], 128'b0};
wire [127... |
module
mulAddRecF16 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [16:0] a,
input [16:0] b,
input [16:0] c,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output... |
module
mulAddRecF32 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [32:0] a,
input [32:0] b,
input [32:0] c,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output... |
module
mulAddRecF64 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [64:0] a,
input [64:0] b,
input [64:0] c,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output... |
module
mulAddRecF128 (
input [(`floatControlWidth - 1):0] control,
input [2:0] op,
input [128:0] a,
input [128:0] b,
input [128:0] c,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [127:0] out_imu... |
module sky130_fd_sc_lp__dlygate4s50 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module wb_mux (sys_clk,
resetcpu,
// High priority bus
h_cyc,
h_stb,
h_we,
h_sel,
h_ack,
h_adr,
h_dat_o,
h_dat_i,
// Low prio... |
module okWireIn_sync (
input wire clk,
input wire okClk,
input wire [112:0] okHE,
input wire [7:0] ep_addr,
output reg [31:0] ep_dataout
);
wire [31:0] control_bus;
wire [31:0] q_buff;
wire rdempty;
reg rdreq;... |
module pipeline(
input Clk,
output [31:0] PC_in,PC_out,
output [2:0]PCSrc,
//1
/*output[5:0] Op_IF,
output[4:0] Rs_IF,Rt_IF,Rd_IF,Shamt_IF,
output[5:0] Func_IF,
*/
//3
/*output[31:0] Branch_addr_EX,PC_Add_EX,
output[2:0] Condition_EX,
output Branch_EX,
output[2:0]PC_write_EX,
output[3:0]Mem_Write_Byte_en_EX,Rd_Write_By... |
module sky130_fd_sc_hdll__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module cls_spi_tb;
// Inputs
reg clock;
reg reset;
reg [31:0] data;
reg miso;
// Outputs
wire ss;
wire mosi;
wire sclk;
// Instantiate the Unit Under Test (UUT)
cls_spi uut (
.clock(clock),
.reset(reset),
.data(data),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sclk(sclk)
);
initial begin
... |
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
... |
module sky130_fd_sc_ms__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and... |
module single_bit_cdc_synchronizer #(
parameter NUM_STAGES = 3 // minimum 2 stages, recommended 3 stages
// probability of metastability decreases
// exponentially with #stages
) (
input clk, //latch clock
input d_in,
output q_out;
);
reg[NUM_STAGES-1... |
module SPIMemoryTest;
// SPI interface.
reg _select, sck, mosi;
wire miso;
// Memory interface.
wire [`SPI_MEM_ADDR_WIDTH-1:0] addr;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_in;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_out;
wire rd, wr;
// Instantiate the Unit Under Test (UUT).
SPIMemory spi_memory(
.... |
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
reg SLEEP;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
SLEEP = 1'bX;
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20... |
module counter_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del contador
wire [26:0] data;
//-- Registro para comprobar si el contador cuenta correctamente
reg [26:0] counter_check = 1;
//-- Instanciar el contador
counter C1(
.clk(clk),
.data(data)
);
//-- Generador de r... |
module sky130_fd_sc_hs__o41ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ... |
module sky130_fd_sc_lp__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire ... |
module sky130_fd_sc_ms__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
... |
module bsg_channel_tunnel #(parameter width_p = 1
, parameter `BSG_INV_PARAM(num_in_p)
, parameter `BSG_INV_PARAM(remote_credits_p)
, use_pseudo_large_fifo_p = 0
, harden_small_fifo_p = 0
... |
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41,... |
module gayle
(
input clk,
input clk7_en,
input reset,
input [23:1] address_in,
input [15:0] data_in,
output [15:0] data_out,
input rd,
input hwr,
input lwr,
input sel_ide, // $DAxxxx
input sel_gayle, // $DExxxx
output irq,
output nrdy, // fifo is not ready for reading
input [1:0] hdd_ena, // ena... |
module qsys_serial_device#(
parameter address_size=8)(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output reg[31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [7:0] avs_ctrl_address,
input avs_ctrl_write,
input... |
module t (
input wire CLK
);
foo #(.WIDTH (1)) foo1 (.*);
foo #(.WIDTH (7)) foo7 (.*);
foo #(.WIDTH (8)) foo8 (.*);
foo #(.WIDTH (32)) foo32 (.*);
foo #(.WIDTH (33)) foo33 (.*);
foo #(.WIDTH (40)) foo40 (.*);
foo #(.WIDTH (41)) foo41 (.*);
foo #(.WIDTH (64)) foo64 (.*);
foo ... |
module foo
#(
parameter WIDTH = 32
)
(
input CLK
);
logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value;
logic [ WIDTH - 1 : 0 ] value_q /* verilator public */;
integer i;
initial begin
initial_value = '1;
for (i = 0; i < WIDTH / 8; i++)
initial_value[ i * 8 ... |
module bar
#(
parameter WIDTH = 32
)
(
input CLK
);
foo #(.WIDTH (WIDTH)) foo (.*);
endmodule |
module spi_slave_0_base(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [... |
module redFour__NMOSwk_X_1_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
rtranif1 #(100) NMOSfwk_0 (d, s, g);
endmodule |
module redFour__PMOSwk_X_0_833_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
rtranif0 #(100) PMOSfwk_0 (d, s, g);
endmodule |
module scanChainFive__scanL(in, out);
input in;
output out;
supply1 vdd;
supply0 gnd;
wire net_4, net_7;
redFour__NMOSwk_X_1_Delay_100 NMOSwk_0(.g(out), .d(in), .s(net_7));
redFour__NMOSwk_X_1_Delay_100 NMOSwk_1(.g(out), .d(net_7), .s(gnd));
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_0(.g(out), .d(net_4... |
module redFour__NMOS_X_6_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule |
module redFour__PMOS_X_3_333_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule |
module scanChainFive__scanP(in, src, drn);
input in;
input src;
output drn;
supply1 vdd;
supply0 gnd;
wire net_1;
redFour__NMOS_X_6_667_Delay_100 NMOS_0(.g(in), .d(drn), .s(src));
redFour__PMOS_X_3_333_Delay_100 PMOS_0(.g(net_1), .d(drn), .s(src));
not (strong0, strong1) #(0) inv_0 (net_1, in);
endm... |
module scanChainFive__scanRL(phi1, phi2, rd, sin, sout);
input phi1;
input phi2;
input rd;
input sin;
output sout;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_3;
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
scanChainFive__scanL foo2(.in(net_0), .out(sout));
scanChainFive__scanP scanP... |
module jtag__BR(SDI, phi1, phi2, read, SDO);
input SDI;
input phi1;
input phi2;
input read;
output SDO;
supply1 vdd;
supply0 gnd;
scanChainFive__scanRL scanRL_0(.phi1(phi1), .phi2(phi2), .rd(read),
.sin(SDI), .sout(SDO));
endmodule |
module scanChainFive__scanIRH(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
sout);
input mclr;
input phi1;
input phi2;
input rd;
input sin;
input wr;
output dout;
output doutb;
output sout;
supply1 vdd;
supply0 gnd;
wire net_2, net_4, net_6, net_7;
scanChainFive__scanL foo1(.in(net_6), ... |
module scanChainFive__scanIRL(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
sout);
input mclr;
input phi1;
input phi2;
input rd;
input sin;
input wr;
output dout;
output doutb;
output sout;
supply1 vdd;
supply0 gnd;
wire net_2, net_3, net_4, net_6;
scanChainFive__scanL foo1(.in(net_2), ... |
module jtag__IR(SDI, phi1, phi2, read, reset, write, IR, IRb, SDO);
input SDI;
input phi1;
input phi2;
input read;
input reset;
input write;
output [8:1] IR;
output [8:1] IRb;
output SDO;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4, net_5, net_6, net_7;
scanChainFive__scanIRH s... |
module redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
endmodule |
module jtag__IRdecode(IR, IRb, Bypass, ExTest, SamplePreload, ScanPath);
input [4:1] IR;
input [4:1] IRb;
output Bypass;
output ExTest;
output SamplePreload;
output [12:0] ScanPath;
supply1 vdd;
supply0 gnd;
wire H00, H01, H10, H11, L00, L01, L10, L11, net_19, net_21, net_23, net_25;
wire net_26, n... |
module redFour__PMOSwk_X_0_222_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
rtranif0 #(100) PMOSfwk_0 (d, s, g);
endmodule |
module jtag__clockGen(clk, phi1_fb, phi2_fb, phi1_out, phi2_out);
input clk;
input phi1_fb;
input phi2_fb;
output phi1_out;
output phi2_out;
supply1 vdd;
supply0 gnd;
wire net_0, net_1, net_3, net_4, net_6;
not (strong0, strong1) #(100) inv_0 (phi2_out, net_3);
not (strong0, strong1) #(100) inv_1 ... |
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