module_content stringlengths 18 1.05M |
|---|
module jtag__capture_ctl(capture, phi2, sel, out, phi1);
input capture;
input phi2;
input sel;
output out;
input phi1;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4;
scanChainFive__scanL foo(.in(net_2), .out(net_3));
not (strong0, strong1) #(100) inv_0 (net_1, capture);
not (strong0,... |
module jtag__shift_ctl(phi1_fb, phi2_fb, sel, shift, phi1_out, phi2_out,
phi1_in, phi2_in);
input phi1_fb;
input phi2_fb;
input sel;
input shift;
output phi1_out;
output phi2_out;
input phi1_in;
input phi2_in;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4, net_7;
jtag__clock... |
module jtag__update_ctl(sel, update, out, phi2);
input sel;
input update;
output out;
input phi2;
supply1 vdd;
supply0 gnd;
wire net_1;
not (strong0, strong1) #(100) inv_0 (out, net_1);
nand (strong0, strong1) #(100) nand3_0 (net_1, sel, update, phi2);
endmodule |
module jtag__jtagIRControl(capture, phi1_fb, phi1_in, phi2_fb, phi2_in, shift,
update, phi1_out, phi2_out, read, write);
input capture;
input phi1_fb;
input phi1_in;
input phi2_fb;
input phi2_in;
input shift;
input update;
output phi1_out;
output phi2_out;
output read;
output write;
supp... |
module redFour__NMOS_X_8_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule |
module redFour__PMOS_X_4_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule |
module jtag__tsinvBig(Din, en, enb, Dout);
input Din;
input en;
input enb;
output Dout;
supply1 vdd;
supply0 gnd;
wire net_13, net_14, net_22, net_23;
redFour__NMOS_X_8_Delay_100 NMOS_0(.g(Din), .d(net_13), .s(gnd));
redFour__NMOS_X_8_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_13));
redFour__NMOS_X... |
module jtag__jtagScanControl(TDI, capture, phi1_fb, phi1_in, phi2_fb, phi2_in,
sel, shift, update, TDO, phi1_out, phi2_out, read, write);
input TDI;
input capture;
input phi1_fb;
input phi1_in;
input phi2_fb;
input phi2_in;
input sel;
input shift;
input update;
output TDO;
output phi1_out;
... |
module redFour__NMOS_X_5_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule |
module redFour__PMOS_X_2_833_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule |
module jtag__tsinv(Din, Dout, en, enb);
input Din;
input Dout;
input en;
input enb;
supply1 vdd;
supply0 gnd;
wire net_1, net_2;
redFour__NMOS_X_5_667_Delay_100 NMOS_0(.g(Din), .d(net_1), .s(gnd));
redFour__NMOS_X_5_667_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_1));
redFour__PMOS_X_2_833_Delay_100... |
module jtag__mux2_phi2(Din0, Din1, phi2, sel, Dout);
input Din0;
input Din1;
input phi2;
input sel;
output Dout;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_5, net_6;
not (strong0, strong1) #(100) inv_0 (net_5, sel);
not (strong0, strong1) #(100) inv_1 (net_1, net_6);
not (strong0, s... |
module jtag__scanAmp1w1648(in, out);
input in;
output out;
supply1 vdd;
supply0 gnd;
wire net_0;
tranif1 nmos_0(gnd, net_0, in);
tranif1 nmos_1(gnd, out, net_0);
tranif0 pmos_0(net_0, vdd, in);
tranif0 pmos_1(out, vdd, net_0);
endmodule |
module redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
endmodule |
module redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
endmodule |
module redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
endmodule |
module orangeTSMC180nm__wire_R_26m_100_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_100_C_0_025f wire_0(.a(a));
endmodule |
module jtag__o2a(inAa, inAb, inOb, out);
input inAa;
input inAb;
input inOb;
output out;
supply1 vdd;
supply0 gnd;
wire net_0;
nor (strong0, strong1) #(100) nor2_0 (net_0, inAa, inAb);
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(inOb), .inb(net_0), .out(out));
... |
module orangeTSMC180nm__wire_R_26m_500_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_500_C_0_025f wire_0(.a(a));
endmodule |
module jtag__slaveBit(din, phi2, slave);
input din;
input phi2;
output slave;
supply1 vdd;
supply0 gnd;
wire net_6, net_7;
not (strong0, strong1) #(100) inv_0 (slave, net_7);
scanChainFive__scanL scanL_0(.in(net_6), .out(net_7));
scanChainFive__scanP scanP_0(.in(phi2), .src(din), .drn(net_6));
ora... |
module redFour__NMOS_X_1_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule |
module orangeTSMC180nm__wire_R_26m_750_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_750_C_0_025f wire_0(.a(a));
endmodule |
module orangeTSMC180nm__wire_R_26m_1000_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_1000_C_0_025f wire_0(.a(a));
endmodule |
module jtag__stateBit(next, phi1, phi2, rst, master, slave, slaveBar);
input next;
input phi1;
input phi2;
input rst;
output master;
output slave;
output slaveBar;
supply1 vdd;
supply0 gnd;
wire net_12, net_13, net_14, net_17;
redFour__NMOS_X_1_667_Delay_100 NMOS_0(.g(rst), .d(net_12), .s(gnd));... |
module redFour__PMOS_X_1_5_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule |
module jtag__stateBitHI(next, phi1, phi2, rstb, master, slave, slaveBar);
input next;
input phi1;
input phi2;
input rstb;
output master;
output slave;
output slaveBar;
supply1 vdd;
supply0 gnd;
wire net_10, net_11, net_12, net_15;
redFour__PMOS_X_1_5_Delay_100 PMOS_0(.g(rstb), .d(net_12), .s(vdd... |
module orangeTSMC180nm__wire_R_26m_675_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_675_C_0_025f wire_0(.a(a));
endmodule |
module orangeTSMC180nm__wire_R_26m_1500_C_0_025f(a);
input a;
supply0 gnd;
endmodule |
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_1500_C_0_025f wire_0(.a(a));
endmodule |
module jtag__tapCtlJKL(TMS, TRSTb, phi1, phi2, CapDR, CapIR, Idle, PauseDR,
PauseIR, Reset, Reset_s, SelDR, SelIR, ShftDR, ShftIR, UpdDR, UpdIR,
X1DR, X1IR, X2DR, X2IR);
input TMS;
input TRSTb;
input phi1;
input phi2;
output CapDR;
output CapIR;
output Idle;
output PauseDR;
output PauseI... |
module jtag__jtagControl(TCK, TDI, TDIx, TMS, TRSTb, phi1_fb, phi2_fb, Cap,
ExTest, SelBS, SelDR, Shft, TDOb, Upd, phi1, phi2);
input TCK;
input TDI;
input TDIx;
input TMS;
input TRSTb;
input phi1_fb;
input phi2_fb;
output Cap;
output ExTest;
output SelBS;
output [12:0] SelDR;
output Shft... |
module jtag__JTAGamp(leaf, root);
input [8:1] leaf;
input [5:1] root;
supply1 vdd;
supply0 gnd;
jtag__scanAmp1w1648 toLeaf_5_(.in(root[5]), .out(leaf[5]));
jtag__scanAmp1w1648 toLeaf_4_(.in(root[4]), .out(leaf[4]));
jtag__scanAmp1w1648 toLeaf_3_(.in(root[3]), .out(leaf[3]));
jtag__scanAmp1w1648 toLeaf_... |
module jtag__jtagScanCtlWBuf(TDI, cap, phi1, phi2, sel, shift, upd, TDO,
leaf);
input TDI;
input cap;
input phi1;
input phi2;
input sel;
input shift;
input upd;
output TDO;
input [8:1] leaf;
supply1 vdd;
supply0 gnd;
wire [5:2] a;
jtag__JTAGamp JTAGamp_0(.leaf(leaf[8:1]), .root({a[5],... |
module jtag__jtagScanCtlGroup(TDI, capture, phi1_in, phi2_in, selBS, sel,
shift, update, TDO, BS, leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6,
leaf7, leaf8, leaf9, leaf10, leaf11, leaf12);
input TDI;
input capture;
input phi1_in;
input phi2_in;
input selBS;
input [12:0] sel;
input shift;... |
module jtag__jtagCentral_LEIGNORE_1(TCK, TDI, TMS, TRSTb, ExTest, TDOb, BS,
leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6, leaf7, leaf8, leaf9,
leaf10, leaf11, leaf12);
input TCK;
input TDI;
input TMS;
input TRSTb;
output ExTest;
output TDOb;
input [8:1] BS;
input [8:1] leaf0;
input [8... |
module scanFansFour__jtag_endcap(jtag);
input [8:4] jtag;
endmodule |
module testCell(TCK, TDI, TMS, TRSTb, TDOb);
input TCK;
input TDI;
input TMS;
input TRSTb;
output TDOb;
supply1 vdd;
supply0 gnd;
wire jtagCent_0_ExTest;
wire [4:0] net_5;
wire [4:0] net_6;
wire [4:0] net_7;
wire [4:0] net_8;
wire [4:0] net_9;
wire [4:0] net_10;
wire [4:0] net_11;
wire ... |
module tb_cocotb (
//Parameters
//Registers/Wires
input rst, //reset
input clk,
output linkup, //link is finished
output sata_ready,
output sata_busy,
//input write_data_stb,
//input read_data_stb,
i... |
module receives an Ethernet frame on an AXI stream interface, decodes
and strips the headers, then produces the header fields in parallel along
with the payload in a separate AXI stream.
*/
reg read_eth_header_reg = 1'b1, read_eth_header_next;
reg read_eth_payload_reg = 1'b0, read_eth_payload_next;
reg [PTR_WIDTH-1:0... |
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
reg notifier ;
wire ... |
module tb_top();
reg clk;
reg lfextclk;
reg rst_n;
wire hfclkrst;
wire hfclk = clk & (~hfclkrst);
`define CPU_TOP u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top
`define EXU `CPU_TOP.u_e200_cpu.u_e200_core.u_e200_exu
`define ITCM `CPU_TOP.u_e200_srams.u_e200_itcm_ram.u_e200... |
module sparc_exu_byp
( /*AUTOARG*/
// Outputs
so, byp_alu_rs1_data_e, byp_alu_rs2_data_e_l, byp_alu_rs2_data_e,
exu_lsu_rs3_data_e, exu_spu_rs3_data_e, exu_lsu_rs2_data_e,
byp_alu_rcc_data_e, byp_irf_rd_data_w, exu_tlu_wsr_data_m,
byp_irf_rd_data_w2, byp_ecc_rs3_data_e, byp_ecc_rcc_data_e,
byp_ecl... |
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [17:0] sw,
output wire [8:0] ledg,
ou... |
module axi_ad9144_if (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
dac_data_2_0,
dac_data_2_1,
dac_data_2_2,
dac... |
module sky130_fd_sc_lp__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
... |
module Lab2Part1Fall2015AJM(Rows, ClockIn, Load, Reset, RotateOnce, Columns, KeyNumberLEDs, ClockLocked);
parameter LENGTH = 4;
input [LENGTH-1:0] Rows;
input ClockIn, Load, Reset, RotateOnce;
output [LENGTH-1:0] Columns;
output [LENGTH:0] KeyNumberLEDs;
output ClockLocked;
wire DebouncedShift, Rotate;
Cloc... |
module outputs
wire [63 : 0] cpu_dmem_master_araddr,
cpu_dmem_master_awaddr,
cpu_dmem_master_wdata,
cpu_imem_master_araddr,
cpu_imem_master_awaddr,
cpu_imem_master_wdata;
wire [7 : 0] cpu_dmem_master_arlen,
cpu_dmem_master_awlen,
cpu_dmem_master_wstrb,
cpu_imem_master_arlen,
... |
module antiDroopIIR_16 (
input clk,
input trig,
input signed [15:0] din,
input signed [6:0] tapWeight,
input accClr_en,
//input oflowClr,
(* shreg_extract = "no" *) output reg oflowDetect = 1'd0,
output reg signed [15:0] dout = 16'sd0);
parameter IIR_scale = 15; // define the scaling factor for the IIR multipl... |
module dsu_uartlite(
clk, rst,
txd, rxd,
spr_dat_i,
reg_txdata, reg_txdata_we,
reg_ctrl, reg_ctrl_we,
reg_sta, reg_sta_we,
reg_rxdata, reg_rxdata_we,
sram_ce,
sram_we,
sram_addr,
sram_wdata,
download_enable
);
//
input clk;
input rs... |
module execute_mul_booth32(
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
output wire [63:0] oDATA,
output wire oHSF,
output wire oHOF,
output wire oHCF,
output wire oHPF,
output wire oHZF,
output wire oLSF,
output wire oLOF,
output wire oLCF,
output wire oLPF... |
module daala_zynq_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AX... |
module bsg_cache_non_blocking_dma
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter lg_set... |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam [ 0:0] one1_lp = 1;
localparam [ 1:0] one2_lp = 1;
localparam [ 2:0] one3_lp = 1;
localparam [ 3:0] one4_lp = 1;
localparam [ 4:0] one5_lp = 1;
localparam [ 5:0] one6_lp = 1;
localparam [ 6:0] one7_lp = 1;
localparam [ 7:... |
module th44w3 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th44w3";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N6 ( .d(net042), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(a),... |
module dex_smblt
(
input de_clk,
input de_rstn,
input [1:0] dir,
input goblt,
input stpl_pk_1,
input mcrdy,
input cache_rdy,
input signx,
input signy,
input yeqz,
input xeqz,
input read_2,
input ps16_1,
input ps32_1,
... |
module cpx_buf_p3(/*AUTOARG*/
// Outputs
scache3_cpx_req_bufp3_cq, scache3_cpx_atom_bufp3_cq,
io_cpx_req_bufp3_cq, cpx_scache3_grant_bufp3_ca_l,
cpx_spc5_data_rdy_bufp3_cx, cpx_spc6_data_rdy_bufp3_cx,
cpx_spc7_data_rdy_bufp3_cx, arbcp0_cpxdp_grant_bufp3_ca_l_5,
arbcp0_cpxdp_q0_hold_bufp3_ca_5, arb... |
module bcam_tb;
// simulation parameter
localparam CAMD = `CAMD ; // memory depth
localparam CAMW = `CAMW ; // data width
localparam SEGW = `SEGW ; // segment width for Segmented Transposed-RAM implementation
localparam CYCC = `CYCC ; // simulation cycles count
localparam CY... |
module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] core_mem_master_araddr,
core_mem_master_awaddr,
core_mem_master_wdata,
cpu_imem_master_araddr,
cpu_imem_master_awaddr,
cpu_imem_master_wdata,
mv_tohost_value;
wire [15 : 0] dma_server_bid, dma_server_rid;
wire [7 : 0] core_mem_master_arle... |
module \$__inpad (input I, output O);
PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
endmodule |
module \$__outpad (input I, output O);
PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
endmodule |
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
// VT: This is not consistent and ACE will complain: assign Y = ~A[0];
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
... |
module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_
(.q(Q), .d(D), .ck(C));
endmodule |
module sky130_fd_sc_hs__sdfstp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire b... |
module outputs
wire [69 : 0] deq;
wire [1 : 0] notEmpty, notFull;
// inlined wires
wire [2 : 0] inputVCQueues_ifc_mf_ifc_new_head$wget,
inputVCQueues_ifc_mf_ifc_new_tail$wget;
wire [1 : 0] inputVCQueues_ifc_mf_ifc_rdFIFO$wget,
inputVCQueues_ifc_mf_ifc_wrFIFO$wget;
// register inputVCQueues... |
module system_ov7670_controller_1_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
inp... |
module system_ov7670_controller_1_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_... |
module system_ov7670_controller_1_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
... |
module system_ov7670_controller_1_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:... |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire... |
module tmu2_geninterp18(
input sys_clk,
input load,
input next_point,
input signed [17:0] init,
input positive,
input [16:0] q,
input [16:0] r,
input [16:0] divisor,
output signed [17:0] o
);
reg positive_r;
reg [16:0] q_r;
reg [16:0] r_r;
reg [16:0] divisor_r;
always @(posedge sys_clk) begin
if(load) beg... |
module proj1_testbench;
//Inputs: Regs
//Out: Wires
reg A;
reg B;
wire out;
reg select;
reg clk;
toplevel DUT(A, B, select, out, clk);
always
#5 clk=~clk;
initial begin
select = 1'b0;
clk = 1'b0;
A = 1'b0;
B = 1'b0;
end
always @(posedge clk)
begin
... |
module sky130_fd_sc_ls__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule |
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
... |
module RIOT(A, // Address bus input
Din, // Data bus input
Dout, // Data bus output
CS, // Chip select input
CS_n, // Active low chip select input
R_W_n, // Active low read/write input
RS_n, // Active low rom select input
RES_n, // Active low reset input
IRQ_n, // Active low inte... |
module sineTable #(
parameter ANGLE_WIDTH = 12,
parameter OUT_WIDTH = 18
) (
input wire clk, ///< System Clock
input wire [ANGLE_WIDTH-1:0] angle, ///< Angle to take sine of
output reg signed [OUT_WIDTH-1:0] sine ///< Sine of angle
);
//////////////////////////////////... |
module Image_viewer_top(ClkPort,
Hsync, Vsync, vgaRed, vgaGreen, vgaBlue,
MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE,
MemAdr, data,
An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp, Led,
btnC, btnR, btnL, btnU, btnD
);
// =====================================================================... |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(In0, In1, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],dout[1:0]" */;
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [1:0] [3:0] [3:0] array_simp; // big endian array
logic [3:0] array_oned;
initial begin
array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
if (array_oned != 4'b0101) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'... |
module top_tb;
// Inputs
reg ClkPort;
reg btnC;
reg btnR;
reg btnL;
// Outputs
wire Hsync;
wire Vsync;
wire [2:0] vgaRed;
wire [2:0] vgaGreen;
wire [2:1] vgaBlue;
wire MemOE;
wire MemWR;
wire MemClk;
wire RamCS;
wire RamUB;
wire RamLB;
wire RamAdv;
wire RamCRE;
wire [26:1] MemAdr;
wire An0;
wire... |
module sky130_fd_sc_lp__and4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hd__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
//... |
module ymplayer(
input clk50,
input rst,
// sound
output reg speaker_left,
output reg speaker_right,
// switches
input [3:0] sw_sel, //
input send_data, // 1=Send music over UART, 0=stop
// UART wires
input uart_rx,
output uart_tx,
output [7:0] led
);
wire locked, rst_clk, rst_clk50;
// Send data
reg ... |
module mac_scale
(input wire signed [39:0] to_scaling,
input wire [2:0] c_scalefactor,
output wire scale_overflow,
output reg [39:0] from_scaling);
reg scale_pos_overflow;
reg scale_neg_overflow;
assign scale_overflow = scale_neg_overflow | scale_pos_o... |
module FifoCore32w8r(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full,
prog_empty
);
input rst;
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
output prog_full;
output prog_empt... |
module axi_ad9234_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rd... |
module wb_intercon
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_iwmb_adr_i,
input [31:0] wb_iwmb_dat_i,
input [3:0] wb_iwmb_sel_i,
input wb_iwmb_we_i,
input wb_iwmb_cyc_i,
input wb_iwmb_stb_i,
input [2:0] wb_iwmb_cti_i,
input [1:... |
module dmix_t;
// ins
reg rst;
reg clk;
parameter TCLK = 40;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg signal;
reg sck;
parameter TCLK_SCK = 80;
reg mosi;
reg ss;
parameter TclkSPDIF = 40; // 24.576MHz == 192Khz * 32 bit * 2 (biphase)
nkmdhpa uut(
.rst(rst),
.clk245760_pad(clk),
.spdif_i(signa... |
module sky130_fd_sc_ms__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_... |
module sky130_fd_sc_ms__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221o base (
... |
module watchdog(
input nLDS, RW,
input A23I, A22I,
input [21:17] M68K_ADDR_U,
//input [12:1] M68K_ADDR_L,
input WDCLK,
output nHALT,
output nRESET,
input nRST
);
reg [3:0] WDCNT;
initial
WDCNT <= 4'b0000;
// IMPORTANT:
// nRESET is an open-collector output on B1, so that the 68k can ... |
module fifo_over_ufc_tb
#(
parameter FIFO_DATA_WIDTH = 32,
parameter AURORA_DATA_WIDTH = 64
)
();
reg clk;
reg reset;
wire a_tx_req;
wire [7:0] a_tx_ms;
reg a_tx_tready... |
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;... |
module sky130_fd_sc_hs__bufbuf_16 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule |
module sky130_fd_sc_lp__buflp_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.