author int64 658 755k | date stringlengths 19 19 | timezone int64 -46,800 43.2k | hash stringlengths 40 40 | message stringlengths 5 490 | mods list | language stringclasses 20 values | license stringclasses 3 values | repo stringlengths 5 68 | original_message stringlengths 12 491 |
|---|---|---|---|---|---|---|---|---|---|
136,197 | 08.05.2017 14:24:22 | -28,800 | 80d50a59199eece9ca979e9266805772274e843e | soraka: Add battery information
BRANCH=none
TEST=soraka EC boots and charges battery
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "board/poppy/battery.c",
"new_path": "board/poppy/battery.c",
"diff": "#define SB_SHIP_MODE_REG 0x3a\n#define SB_SHUTDOWN_DATA 0xC574\n+#ifdef BOARD_SORAKA\n+static const struct battery_info info = {\n+ .voltage_max = 8800,\n+ .voltage_normal = 7700,\n+ .voltag... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | soraka: Add battery information
BRANCH=none
BUG=b:35585396
TEST=soraka EC boots and charges battery
Change-Id: I06e0ce7cb143ee039fecada0b4e15a64bcf5968b
Reviewed-on: https://chromium-review.googlesource.com/497530
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,405 | 17.04.2017 11:37:18 | 25,200 | 44b9f9df83b3c54b46eb09f593cce32fe822f30a | Fizz: Enable/disable USB Type-A ports
This change makes Fizz enable USB type-A ports on resume and disable
them on shutdown.
BRANCH=none
TEST=Boot Fizz off of USB flash drive on a USB-A port. | [
{
"change_type": "MODIFY",
"old_path": "board/fizz/board.c",
"new_path": "board/fizz/board.c",
"diff": "@@ -128,6 +128,14 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = {\n}\n};\n+const int usb_port_enable[USB_PORT_COUNT] = {\n+ GPIO_USB1_ENABLE,\n+ GPIO_USB2_ENABLE,\n+ GPIO_USB3_ENABLE,\n+... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Fizz: Enable/disable USB Type-A ports
This change makes Fizz enable USB type-A ports on resume and disable
them on shutdown.
BUG=b:38226666
BRANCH=none
TEST=Boot Fizz off of USB flash drive on a USB-A port.
Change-Id: I7f22438271ffc080e950f5f300937d89706e08a4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/481078 |
136,392 | 07.05.2017 14:42:46 | -28,800 | 00da0f8c87e04ef5aaacebfc882e9055056bb30f | stm32: add clock configuration for stm32f412 to run at 96 MHz
Add clock definition for stmf412. New stm32f4 chip variant will have to
define their own clock definitions.
TEST=`make BOARD=rose- j`
Commit-Ready: Wei-Ning Huang
Tested-by: Wei-Ning Huang | [
{
"change_type": "MODIFY",
"old_path": "chip/stm32/clock-stm32f4.c",
"new_path": "chip/stm32/clock-stm32f4.c",
"diff": "@@ -91,20 +91,23 @@ void config_hispeed_clock(void)\npllinputclock = srcclock / plldiv;\n/* PLL output clock: Must be 100-432MHz */\n- /* Valid values 50-432, we'll get 336MHz */\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | stm32: add clock configuration for stm32f412 to run at 96 MHz
Add clock definition for stmf412. New stm32f4 chip variant will have to
define their own clock definitions.
BUG=b:37187312
TEST=`make BOARD=rose- j`
Change-Id: Ie053298d2f1255d7bc152f6018a674281bda7004
Reviewed-on: https://chromium-review.googlesource.com/487848
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org> |
136,405 | 20.04.2017 17:44:38 | 25,200 | 05a8637ca0f5118da1af8d14d460d210cc2665b3 | Fizz: Add recovery button
Cr50 masks the recovery button signal on a proto board when the
power button is being pressed (b:37682117). This bug has to be
fixed for the recovery button to work.
BRANCH=none
TEST=make buildall | [
{
"change_type": "MODIFY",
"old_path": "board/fizz/board.c",
"new_path": "board/fizz/board.c",
"diff": "@@ -464,3 +464,18 @@ int board_is_consuming_full_charge(void)\nreturn chg_perc > 2 && chg_perc < 95;\n}\n+\n+const struct button_config buttons[CONFIG_BUTTON_COUNT] = {\n+ [BUTTON_RECOVERY] = {\n+... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Fizz: Add recovery button
Cr50 masks the recovery button signal on a proto board when the
power button is being pressed (b:37682117). This bug has to be
fixed for the recovery button to work.
BUG=b:37274183
BRANCH=none
TEST=make buildall
Change-Id: Ia413ffce84d67b6f24f983ccce8ae8277452ac2c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494069
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,405 | 24.04.2017 17:04:36 | 25,200 | c2f640c159b65bf6595714f24c316f2553c986e4 | Fizz: Add LED control
This patch adds code to control the power LED.
BRANCH=none
TEST=Verify LED turns green, red, amber, off. Verify LED turns green
or off when chipset is on or off, respectively. | [
{
"change_type": "MODIFY",
"old_path": "board/fizz/build.mk",
"new_path": "board/fizz/build.mk",
"diff": "@@ -12,3 +12,4 @@ CHIP_VARIANT:=npcx5m6g\nboard-y=board.o\nboard-$(CONFIG_BATTERY_SMART)+=battery.o\nboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o\n+board-y+=led.o\n"
},
{
"change_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Fizz: Add LED control
This patch adds code to control the power LED.
BUG=b:37646390
BRANCH=none
TEST=Verify LED turns green, red, amber, off. Verify LED turns green
or off when chipset is on or off, respectively.
Change-Id: I1d7940d9bb4414d97c541ead802efeb8f279533e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486947 |
136,422 | 13.03.2017 16:28:48 | 25,200 | a30bb73e783cac43d9d7583a38bfe72bb2d41478 | cr50: add LONG_LIFE bit to suppress RO uart.
BRANCH=None
Commit-Ready: Marius Schilder
Tested-by: Marius Schilder | [
{
"change_type": "MODIFY",
"old_path": "board/cr50/scratch_reg1.h",
"new_path": "board/cr50/scratch_reg1.h",
"diff": "#define BOARD_WP_ASSERTED (1 << 8)\n#define BOARD_FORCING_WP (1 << 9)\n+/*\n+ * Bit to signal to compatible RO to suppress its uart output.\n+ * Helps to reduce time to resume from d... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: add LONG_LIFE bit to suppress RO uart.
BRANCH=None
BUG=None
Change-Id: Icfb20bff28a593c9058d67ad09f188c567b7401c
Reviewed-on: https://chromium-review.googlesource.com/454240
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> |
136,393 | 12.05.2017 15:01:54 | 25,200 | dee69a236f67b99e87746fee5894c915682623ee | CR50: remove duplicate SHA #defines
Include the appropriate SHA header files
and remove duplicate #defines.
BRANCH=none
TEST=compilation succeeds
Commit-Ready: Nagendra Modadugu
Tested-by: Nagendra Modadugu | [
{
"change_type": "MODIFY",
"old_path": "chip/g/dcrypto/rsa.c",
"new_path": "chip/g/dcrypto/rsa.c",
"diff": "#include \"cryptoc/sha.h\"\n#include \"cryptoc/sha256.h\"\n+#include \"cryptoc/sha384.h\"\n+#include \"cryptoc/sha512.h\"\n#include \"cryptoc/util.h\"\n/* Extend the MSB throughout the word. *... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | CR50: remove duplicate SHA #defines
Include the appropriate SHA header files
and remove duplicate #defines.
BRANCH=none
BUG=none
TEST=compilation succeeds
Change-Id: I15b77c3f40a07af8ea397f41d671386f303287eb
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/505200
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Andrey Pronin <apronin@chromium.org> |
136,396 | 15.05.2017 17:46:50 | 25,200 | 7456475f99831bbeeca72c9c153e05b4558f832b | cr50: drop obsolete/addressed TODOs
There many TODOs sprinkled in the code, some of them have been
addressed or do not apply any mode. This patch removes them.
BRANCH=cr50
TEST=built and ran cr50 on reef | [
{
"change_type": "MODIFY",
"old_path": "board/cr50/board.h",
"new_path": "board/cr50/board.h",
"diff": "/* Flash configuration */\n#undef CONFIG_FLASH_PSTATE\n-/* TODO(crosbug.com/p/44745): Bringup only! Do the right thing for real! */\n#define CONFIG_WP_ALWAYS\n-/* TODO(crosbug.com/p/44745): For de... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: drop obsolete/addressed TODOs
There many TODOs sprinkled in the code, some of them have been
addressed or do not apply any mode. This patch removes them.
BRANCH=cr50
BUG=none
TEST=built and ran cr50 on reef
Change-Id: Ica6edb204e5cc0cc9dc7f0d43fd39e7ddaf56809
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/506496
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,260 | 18.05.2017 09:45:13 | -19,080 | 335bbbf2204a0814f2a1fc09054ed579a0b2cca9 | stoney: Remove throttle cpu from S3S0 power state
This was causing cpu to give lower performance.
Hard throttling is being handled in chipset_throttle_cpu.
TEST=Improved CPU benchmark | [
{
"change_type": "MODIFY",
"old_path": "power/stoney.c",
"new_path": "power/stoney.c",
"diff": "#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)\n#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)\n-static int throttle_cpu; /* Throttle CPU? */\nstatic int forcing_coldreset; /* Forc... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | stoney: Remove throttle cpu from S3S0 power state
This was causing cpu to give lower performance.
Hard throttling is being handled in chipset_throttle_cpu.
BUG=None
TEST=Improved CPU benchmark
Change-Id: I0bff47ec0ce60f31fa1f30fdea94d45dfe05aa38
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://chromium-review.googlesource.com/508569
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: YH Lin <yueherngl@chromium.org> |
136,396 | 22.05.2017 15:43:41 | 25,200 | c6cfdbf669e932d60b9e743bcbbf1723352dd1c1 | cr50: prepare to release version 0.0.20
BRANCH=cr50
TEST=built an image, observed version number. | [
{
"change_type": "MODIFY",
"old_path": "util/signer/ec_RW-manifest-dev.json",
"new_path": "util/signer/ec_RW-manifest-dev.json",
"diff": "\"timestamp\": 0,\n\"epoch\": 0, // FWR diversification contributor, 32 bits.\n\"major\": 0, // FW2_HIK_CHAIN counter.\n- \"minor\": 19, // Mostly harmless versio... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: prepare to release version 0.0.20
BRANCH=cr50
BUG=None
TEST=built an image, observed version number.
Change-Id: Iceec4cc72f0148966df0712d0b83a8680dbba686
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/511186
Reviewed-by: Mary Ruthven <mruthven@chromium.org> |
136,405 | 21.04.2017 16:24:56 | 25,200 | e42da5ace4393868a610a51bba89730fafd11157 | power_button_x86: Initialize to on if button is pressed
This change sets the initial power button state to init-on
if the power button is pressed.
BRANCH=none
TEST=Enter recovery mode by power+recovery button press. | [
{
"change_type": "MODIFY",
"old_path": "common/power_button_x86.c",
"new_path": "common/power_button_x86.c",
"diff": "@@ -227,6 +227,9 @@ static void set_initial_pwrbtn_state(void)\n*/\nCPRINTS(\"PB init-off\");\npower_button_pch_release();\n+ } else if (power_button_is_pressed()) {\n+ CPRINTS(\"PB ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | power_button_x86: Initialize to on if button is pressed
This change sets the initial power button state to init-on
if the power button is pressed.
BUG=b:37274183
BRANCH=none
TEST=Enter recovery mode by power+recovery button press.
Change-Id: I6ed849bc303e7cdbcb975ae2a6ff278093c86088
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486946
Reviewed-by: Duncan Laurie <dlaurie@google.com> |
136,405 | 24.05.2017 12:13:36 | 25,200 | abb8be8b64e3341e49dfc3be031a7e372126f37b | host_command: Add host_is_event_set
host_is_event_set checks whether a given event is set or not.
BRANCH=none
TEST=make buildall | [
{
"change_type": "MODIFY",
"old_path": "include/host_command.h",
"new_path": "include/host_command.h",
"diff": "@@ -161,6 +161,17 @@ void host_clear_events(uint32_t mask);\n* Return the raw event state.\n*/\nuint32_t host_get_events(void);\n+\n+/**\n+ * Check a single host event.\n+ *\n+ * @param ev... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | host_command: Add host_is_event_set
host_is_event_set checks whether a given event is set or not.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I7207fa75d155d5b9adc50430bc1ed703bea7c1b9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/514208
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 24.05.2017 16:24:03 | 25,200 | c78562ff602bd3026c02267650c020d61c87cee2 | Fizz: Power on ethernet port
This patch sets GPIO_LAN_PWR_EN to output/high to power on
the ethernet port at start.
BRANCH=none
TEST=Measured V3P3A_LAN is 3.3V. | [
{
"change_type": "MODIFY",
"old_path": "board/fizz/gpio.inc",
"new_path": "board/fizz/gpio.inc",
"diff": "@@ -41,7 +41,7 @@ GPIO(ENTERING_RW, PIN(7, 6), GPIO_OUTPUT) /* EC Entering RW */\nGPIO(PMIC_INT_L, PIN(6, 0), GPIO_INPUT) /* PMIC interrupt */\n/* Fizz specific pins */\n-GPIO(LAN_PWR_EN, PIN(8,... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Fizz: Power on ethernet port
This patch sets GPIO_LAN_PWR_EN to output/high to power on
the ethernet port at start.
BUG=b:37646105
BRANCH=none
TEST=Measured V3P3A_LAN is 3.3V.
Change-Id: I9629a72d1ffefd1ca2aeb8d2d1f5d74a953d7e58
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/514622
Reviewed-by: Duncan Laurie <dlaurie@google.com> |
136,274 | 22.05.2017 20:29:33 | 25,200 | 3219d9988b4816f5dbbacfda038aa448e6065f61 | tigertool: update pyusb calls
Update pyusb calling format to match chroot
version.
BRANCH=None
TEST=flash, control tigertail successfully
Commit-Ready: Nick Sanders
Tested-by: Nick Sanders | [
{
"change_type": "MODIFY",
"old_path": "extra/tigertool/ecusb/stm32usb.py",
"new_path": "extra/tigertool/ecusb/stm32usb.py",
"diff": "@@ -66,7 +66,7 @@ class Susb(object):\ndev = None\nif self._serialname:\nfor d in dev_list:\n- dev_serial = usb.util.get_string(d, d.iSerialNumber)\n+ dev_serial = us... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | tigertool: update pyusb calls
Update pyusb calling format to match chroot
version.
BRANCH=None
BUG=b:35849284
TEST=flash, control tigertail successfully
Change-Id: I27f34d63c8ddc09c903dcc1da39d18e7dbf15710
Reviewed-on: https://chromium-review.googlesource.com/511668
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,197 | 26.05.2017 18:12:29 | -28,800 | bff0a8093402790f3f58af80eb09509c27cafdaf | usb_update: Add support for INJECT_ENTROPY command (fixups)
Minor fixups on CL:513807.
BRANCH=none
TEST=none
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "common/usb_update.c",
"new_path": "common/usb_update.c",
"diff": "@@ -219,8 +219,9 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)\n}\nCPRINTS(\"Adding %db of entropy\", entropy_count);\n- /* Add the whole buffer to entropy. */\... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | usb_update: Add support for INJECT_ENTROPY command (fixups)
Minor fixups on CL:513807.
BRANCH=none
BUG=b:38487027
TEST=none
Change-Id: I8c17a21a13b6befc7ef305789930a321ac725204
Reviewed-on: https://chromium-review.googlesource.com/516868
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Mattias Nissler <mnissler@chromium.org> |
136,409 | 02.06.2017 06:54:07 | 25,200 | 1444ace29f0b3455a606e685b50085cd6d777a61 | eve: Swap volume up and down GPIO
The buton behavior is inverted if we follow the schematic, so swap the
GPIO on these inputs so they match the expected behavior.
BRANCH=none
TEST=manual test of side volume button behavior | [
{
"change_type": "MODIFY",
"old_path": "board/eve/gpio.inc",
"new_path": "board/eve/gpio.inc",
"diff": "@@ -18,8 +18,9 @@ GPIO_INT(PMIC_DPWROK, PIN(9, 7), GPIO_INT_BOTH, power_signal_interrupt)\nGPIO_INT(POWER_BUTTON_L, PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt)\nGPIO_INT(LID_O... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eve: Swap volume up and down GPIO
The buton behavior is inverted if we follow the schematic, so swap the
GPIO on these inputs so they match the expected behavior.
BUG=b:62120390
BRANCH=none
TEST=manual test of side volume button behavior
Change-Id: I0ad18b4a15fcc2832d97dfad3b03186180e4517a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/522410
Reviewed-by: Scott Collyer <scollyer@chromium.org> |
136,248 | 20.02.2017 16:15:09 | -28,800 | 9ca4586129844b86ca4b346860ab658754228d2b | common: Add support for flash with regions of different size
Add support to handle devices with flash regions of different sizes.
BRANCH=none
TEST=compile | [
{
"change_type": "MODIFY",
"old_path": "common/firmware_image.lds.S",
"new_path": "common/firmware_image.lds.S",
"diff": "@@ -14,7 +14,6 @@ MEMORY\n}\nSECTIONS\n{\n- . = ALIGN(CONFIG_FLASH_BANK_SIZE);\n#if defined(NPCX_RO_HEADER)\n/* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contain... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | common: Add support for flash with regions of different size
Add support to handle devices with flash regions of different sizes.
BRANCH=none
TEST=compile
BUG=b:38018926
Change-Id: I8f842abaa50de724df60dd7e19f9e97cb9660367
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/264031
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,340 | 03.04.2015 15:48:23 | 25,200 | 72afc55bd9d3f12fa62609b61dfbfe300a277dd3 | stm32: cleanup flash-f by using constant from register.h
Use constants from registers.h, to easily support other ECs.
Fix indentation in registers.h
BRANCH=none
TEST=compile + following patches tested on STM32F411 | [
{
"change_type": "MODIFY",
"old_path": "board/zinger/hardware.c",
"new_path": "board/zinger/hardware.c",
"diff": "@@ -465,7 +465,7 @@ void flash_physical_permanent_protect(void)\nwrite_optb(0, 0x11);\n/* Reset by using OBL_LAUNCH to take changes into account */\nasm volatile(\"cpsid i\");\n- STM32_F... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | stm32: cleanup flash-f by using constant from register.h
Use constants from registers.h, to easily support other ECs.
Fix indentation in registers.h
BRANCH=none
TEST=compile + following patches tested on STM32F411
BUG=None
Change-Id: Iecb3ce759a5c4ff13463e7df1cb7e03fc1ce6f69
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/264030
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,340 | 14.02.2015 12:09:57 | 28,800 | 09a7fa4aefc3b6f25642133aa36aedc8220f1ad9 | stm32mon: Add support for STM32F411
Add support for i2c boot protocol 1.1 and erase non-strech erase
command.
Add option to specify i2c slave address.
TEST=Read, Erase and Write SH on Ryu P4.
BRANCH=none | [
{
"change_type": "MODIFY",
"old_path": "util/stm32mon.c",
"new_path": "util/stm32mon.c",
"diff": "#define CMD_WRITEMEM 0x31 /* Writes memory (SRAM or Flash) */\n#define CMD_ERASE 0x43 /* Erases n pages of Flash memory */\n#define CMD_EXTERASE 0x44 /* Erases n pages of Flash memory */\n+#define CMD_N... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | stm32mon: Add support for STM32F411
Add support for i2c boot protocol 1.1 and erase non-strech erase
command.
Add option to specify i2c slave address.
TEST=Read, Erase and Write SH on Ryu P4.
BUG=chrome-os-partner:36018
BRANCH=none
Change-Id: Ib0649323fd8879fef6e2dc5e62001c891afe128a
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/250101
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,340 | 13.03.2015 16:09:24 | 25,200 | cc8fd2386f6ea1f888466a324c8c65cbade142b1 | stm32mon: Add offset/length parameter to read/write a particular memory region
Use that option to read a particular portion of the flash
BRANCH=none
TEST=Check data retrieved is correct. | [
{
"change_type": "MODIFY",
"old_path": "util/stm32mon.c",
"new_path": "util/stm32mon.c",
"diff": "struct stm32_def {\nuint16_t id;\nconst char *name;\n- uint32_t flash_start;\nuint32_t flash_size;\nuint32_t page_size;\nuint32_t cmds_len[2];\n} chip_defs[] = {\n- {0x416, \"STM32L15xxB\", 0x08000000, ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | stm32mon: Add offset/length parameter to read/write a particular memory region
Use that option to read a particular portion of the flash
BUG=None
BRANCH=none
TEST=Check data retrieved is correct.
Change-Id: Ib2bc98aa7352515c2e651443f322dd0250c72cdd
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/260886
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,396 | 06.06.2017 17:32:45 | 25,200 | 3639527eb47e73954abdd1c453b2b1dada7a9fd3 | bs: add missing codesigner command line argument
The recent change of the code signer is not backwards compatible, a
new command line parameter must be added.
BRANCH=cr50
TEST=verified that
H1_DEVIDS='xxxx yyyyy' ./util/signer/bs
succeeds again. | [
{
"change_type": "MODIFY",
"old_path": "util/signer/bs",
"new_path": "util/signer/bs",
"diff": "@@ -120,8 +120,7 @@ if [ -n \"${do_prod}\" -a -n \"${do_b1}\" ]; then\nexit 1\nfi\n-signer_command_params=''\n-signer_command_params=\" -x ${EC_BIN_ROOT}/fuses.xml\"\n+signer_command_params=\"--b -x ${EC_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | bs: add missing codesigner command line argument
The recent change of the code signer is not backwards compatible, a
new command line parameter must be added.
BRANCH=cr50
BUG=none
TEST=verified that
H1_DEVIDS='xxxx yyyyy' ./util/signer/bs
succeeds again.
Change-Id: I9a8e03c20aa4b7b689b1f5e4a1f786cf5857483f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/527317
Reviewed-by: Mary Ruthven <mruthven@chromium.org> |
136,274 | 07.06.2017 18:27:22 | 25,200 | f40e79b3f18d23c49418a6cbd91430e3d5e116a6 | servo_v4: enable usb port by default
Set the USB mux and power enable to default to route
the USB3 port to the DUT and enable VBUS.
BRANCH=None
TEST=ensure that blue port works on power on.
Commit-Ready: Nick Sanders
Tested-by: Nick Sanders | [
{
"change_type": "MODIFY",
"old_path": "board/servo_v4/board.c",
"new_path": "board/servo_v4/board.c",
"diff": "@@ -286,6 +286,17 @@ static void init_uservo_port(void)\nwrite_ioexpander(1, 0, 0);\n}\n+/* Enable blue USB port to DUT. */\n+static void init_usb3_port(void)\n+{\n+ /* Write USB3.0_TYPEA_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | servo_v4: enable usb port by default
Set the USB mux and power enable to default to route
the USB3 port to the DUT and enable VBUS.
BUG=b:38391443
BRANCH=None
TEST=ensure that blue port works on power on.
Change-Id: Ie46e422bc083e435379470132159df32f6d644d3
Reviewed-on: https://chromium-review.googlesource.com/527992
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,196 | 05.06.2017 19:30:00 | -28,800 | 0b5e3aa6428d135ff8ce638bc8a10f76fe9731f5 | hammer: initial commit for trackpad firmware updater
Tool to update the trackpad firmware over USB. Primarily borrowed from
extra/usb_console/usb_console.c
BRANCH=none
TEST=Manually executed with hammer
Commit-Ready: Chun-ta Lin
Tested-by: Chun-ta Lin | [
{
"change_type": "ADD",
"old_path": null,
"new_path": "extra/touchpad_updater/Makefile",
"diff": "+# Copyright 2017 The Chromium OS Authors. All rights reserved.\n+# Use of this source code is governed by a BSD-style license that can be\n+# found in the LICENSE file.\n+\n+PROGRAM := touchpad_updater... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | hammer: initial commit for trackpad firmware updater
Tool to update the trackpad firmware over USB. Primarily borrowed from
extra/usb_console/usb_console.c
BRANCH=none
BUG=b:35587174
TEST=Manually executed with hammer
Change-Id: Icad951d2478a3e231f293e11fb461eaae20e5042
Reviewed-on: https://chromium-review.googlesource.com/525192
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,197 | 07.06.2017 13:33:27 | -28,800 | 14a3a3ac23bc5b03a4d884106a8cb4a75d861fb7 | poppy: Adjust lid reference matrix
BRANCH=none
TEST=With this change, display rotates correctly when screen is rotated.
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "board/poppy/board.c",
"new_path": "board/poppy/board.c",
"diff": "@@ -719,8 +719,8 @@ const matrix_3x3_t mag_standard_ref = {\n};\nconst matrix_3x3_t lid_standard_ref = {\n- { 0, FLOAT_TO_FP(1), 0},\n{FLOAT_TO_FP(-1), 0, 0},\n+ { 0, FLOAT_TO_FP(-1), 0},\n{ 0, ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | poppy: Adjust lid reference matrix
BRANCH=none
BUG=b:62396794
TEST=With this change, display rotates correctly when screen is rotated.
Change-Id: I0dc2cd88ed36deef73c7e6d4d458e546fa0b254d
Reviewed-on: https://chromium-review.googlesource.com/526754
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,197 | 12.06.2017 08:31:56 | -28,800 | 3a8bba3bc3bfa5e52a368c89dd84cc25bea7fb16 | gpio: Move gpio_get_ternary to common gpio functions
Also, convert from usleep to udelay, as the calling site may not
necessarily be in task context.
BRANCH=none
TEST=make buildall -j
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "board/eve/board.c",
"new_path": "board/eve/board.c",
"diff": "@@ -685,28 +685,6 @@ void board_hibernate(void)\n;\n}\n-static int gpio_get_ternary(enum gpio_signal gpio)\n-{\n- int pd, pu;\n- int flags = gpio_get_default_flags(gpio);\n-\n- /* Read GPIO with int... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | gpio: Move gpio_get_ternary to common gpio functions
Also, convert from usleep to udelay, as the calling site may not
necessarily be in task context.
BRANCH=none
BUG=b:62242438
TEST=make buildall -j
Change-Id: I9f36f0de4259716a92183b28324c90d974a96239
Reviewed-on: https://chromium-review.googlesource.com/530884
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,197 | 02.06.2017 22:04:54 | -28,800 | aa15b8621d62b8926ca4853cdf9c336f0b892db9 | stm32: Add function to fetch unique id
BRANCH=none
TEST=Flash hammer
lsusb -d 18d1:5022 -v -v | grep iSerial
shows different chip IDs on different boards.
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "chip/stm32/registers.h",
"new_path": "chip/stm32/registers.h",
"diff": "@@ -2316,7 +2316,9 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;\n/* --- MISC --- */\n-#define STM32_UNIQUE_ID 0x1ffff7ac\n+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(0x1ffff... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | stm32: Add function to fetch unique id
BRANCH=none
BUG=b:62280271
TEST=Flash hammer
lsusb -d 18d1:5022 -v -v | grep iSerial
shows different chip IDs on different boards.
Change-Id: Id56b4509f184eb722d04fef94079c150dc2016e2
Reviewed-on: https://chromium-review.googlesource.com/523044
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org> |
136,197 | 02.06.2017 22:46:29 | -28,800 | d5bb8390a8f7b27d55d96b14dcaa928dfff4c59d | hammer: Use unique board ID to generate USB serial number
BRANCH=none
TEST=Flash hammer
lsusb -d 18d1:5022 -v -v | grep iSerial
shows different chip IDs on different boards.
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "board/hammer/board.c",
"new_path": "board/hammer/board.c",
"diff": "#include \"i2c.h\"\n#include \"keyboard_raw.h\"\n#include \"keyboard_scan.h\"\n+#include \"printf.h\"\n#include \"pwm.h\"\n#include \"pwm_chip.h\"\n#include \"registers.h\"\n#include \"rollbac... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | hammer: Use unique board ID to generate USB serial number
BRANCH=none
BUG=b:62280271
TEST=Flash hammer
lsusb -d 18d1:5022 -v -v | grep iSerial
shows different chip IDs on different boards.
Change-Id: I249967df133a8aa8a2b5c570fb940dd03fae4169
Reviewed-on: https://chromium-review.googlesource.com/523046
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,369 | 08.06.2017 17:06:16 | 25,200 | 01213a574f4d8ebe6cc295d1dc614feeb3a79adb | eve: Lower VCCIO from 975 to 850 mV
BRANCH=none
TEST=power consumption is lower | [
{
"change_type": "MODIFY",
"old_path": "board/eve/board.c",
"new_path": "board/eve/board.c",
"diff": "@@ -348,7 +348,7 @@ static void board_pmic_init(void)\ni2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x3e, 0x04);\n/* Set CSDECAYEN / VCCIO decays to 0V at assertion of SLP_S0# */\n- i2c_write8(I2C_PO... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eve: Lower VCCIO from 975 to 850 mV
BUG=b:62413556, b:62465979
BRANCH=none
TEST=power consumption is lower
Change-Id: I573ba2c68b97389a51a2524184a44c49e0eb692d
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528525
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,230 | 13.06.2017 17:42:58 | 25,200 | 9f37e4a655190d12c73bd5db3d7649e894a7d6be | scarlet: Turn on CONFIG_TABLET_MODE_SWITCH
BRANCH=scarlet
TEST=boot scarlet and confirm it's in tablet mode
Commit-Ready: Philip Chen
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "board/scarlet/board.h",
"new_path": "board/scarlet/board.h",
"diff": "#define CONFIG_TEMP_SENSOR\n#define CONFIG_TEMP_SENSOR_TMP432\n+/* To be able to indicate the device is in tablet mode. */\n+#define CONFIG_TABLET_MODE_SWITCH\n+\n/* FIFO size is in power of... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | scarlet: Turn on CONFIG_TABLET_MODE_SWITCH
BUG=b:62594071
BRANCH=scarlet
TEST=boot scarlet and confirm it's in tablet mode
Change-Id: I85cc53bb66d70acc9f5c77bd7c428447159dabb0
Reviewed-on: https://chromium-review.googlesource.com/534937
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org> |
136,197 | 14.06.2017 10:20:56 | -28,800 | 43391ca4157d37d934aa7ec041ded311b96720c2 | poppy: Increase base debounce time to 20ms
From our testing, 5ms seems a little short: 20ms is probably better.
BRANCH=none
TEST=Test that base is always detected.
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "board/poppy/board.c",
"new_path": "board/poppy/board.c",
"diff": "@@ -142,7 +142,7 @@ void anx74xx_cable_det_interrupt(enum gpio_signal signal)\n*\n* TODO(b/35585396): Fine-tune these values.\n*/\n-#define BASE_DETECT_DEBOUNCE_US (5 * MSEC)\n+#define BASE_DETE... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | poppy: Increase base debounce time to 20ms
From our testing, 5ms seems a little short: 20ms is probably better.
BRANCH=none
BUG=b:62393957
BUG=b:35586668
TEST=Test that base is always detected.
Change-Id: I8d0041fc387568cfa0983584ca1d68711c70d9cf
Reviewed-on: https://chromium-review.googlesource.com/535214
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,197 | 13.06.2017 10:27:35 | -28,800 | b9b431557e0b5d4c97af56f640f627533296373c | rollback: Add function to fetch secret
BRANCH=none
TEST=Flash hammer
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "common/rollback.c",
"new_path": "common/rollback.c",
"diff": "@@ -106,6 +106,32 @@ int32_t rollback_get_minimum_version(void)\nreturn data.rollback_min_version;\n}\n+#ifdef CONFIG_ROLLBACK_SECRET_SIZE\n+int rollback_get_secret(uint8_t *secret)\n+{\n+ struct ro... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | rollback: Add function to fetch secret
BRANCH=none
BUG=b:38486828
TEST=Flash hammer
Change-Id: I50088a78e75d6ea8d62e439fdc8bf18d46319462
Reviewed-on: https://chromium-review.googlesource.com/532474
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,197 | 10.06.2017 10:44:46 | -28,800 | c5b31e3868079b50d3f0db72632271d2b1eedea8 | sha256: add support for hmac_sha256, and add test for sha256
BRANCH=none
TEST=make run-sha256
TEST=make buildall -j
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "common/sha256.c",
"new_path": "common/sha256.c",
"diff": "@@ -188,6 +188,23 @@ void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)\nctx->tot_len += (block_nb + 1) << 6;\n}\n+/*\n+ * Specialized SHA256_init + SHA256_update that takes t... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | sha256: add support for hmac_sha256, and add test for sha256
BRANCH=none
BUG=b:38486828
TEST=make run-sha256
TEST=make buildall -j
Change-Id: I4c5b5d81ae5650ebfbdc989a0d860eeb0a60f68b
Reviewed-on: https://chromium-review.googlesource.com/530207
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,228 | 09.06.2017 11:36:50 | 25,200 | c860bc15c5a2250956dcedb5d8bdf76378b7fe7d | poppy: Add LED support for sysrq debug mode
BRANCH=None
TEST=Verified that LED blinks when in debug mode and stops blinking on
exit from debug mode. | [
{
"change_type": "MODIFY",
"old_path": "board/poppy/led.c",
"new_path": "board/poppy/led.c",
"diff": "@@ -143,9 +143,12 @@ DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);\nvoid led_control(enum ec_led_id led_id, enum ec_led_state state)\n{\n- if (led_id == EC_LED_ID_RECOVERY_HW_REINIT_LED) {\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | poppy: Add LED support for sysrq debug mode
BUG=b:37970194,b:36394093
BRANCH=None
TEST=Verified that LED blinks when in debug mode and stops blinking on
exit from debug mode.
Change-Id: I536d0eeffdc59bef940ea1f0f01d7c595320d9c4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/529766
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,455 | 14.06.2017 11:53:01 | 25,200 | 520f1aff7742afbeba5fb1720d27ac01de728968 | coral: Remove unused / unassigned variables
Defects reported by Coverity.
BRANCH=None
TEST=`make buildall -j`
Commit-Ready: Shawn N
Tested-by: Shawn N | [
{
"change_type": "MODIFY",
"old_path": "board/coral/board.c",
"new_path": "board/coral/board.c",
"diff": "@@ -824,9 +824,9 @@ const matrix_3x3_t mag_standard_ref = {\n};\n/* sensor private data */\n+/* TODO(crbug.com/733352): Remove useless externs and declare these static. */\nstruct kionix_accel_d... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | coral: Remove unused / unassigned variables
Defects reported by Coverity.
BUG=None
BRANCH=None
TEST=`make buildall -j`
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I083ef9e499076f7009717ccbe0a3ab0a055e1bed
Reviewed-on: https://chromium-review.googlesource.com/535836
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org> |
136,228 | 11.06.2017 17:36:24 | 25,200 | 94a9cfc02fa2aae6bfde6afc3454bf9089019bdf | eve/fizz/poppy: Enable panic backup/restore
BRANCH=None
TEST=make -j buildall | [
{
"change_type": "MODIFY",
"old_path": "board/eve/board.h",
"new_path": "board/eve/board.h",
"diff": "#define CONFIG_LID_SWITCH\n#define CONFIG_LOW_POWER_IDLE\n#define CONFIG_LTO\n+#define CONFIG_CHIP_PANIC_BACKUP\n#define CONFIG_PWM\n#define CONFIG_PWM_KBLIGHT\n#define CONFIG_SPI_FLASH_REGS\n"
},... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eve/fizz/poppy: Enable panic backup/restore
BUG=b:62076222
BRANCH=None
TEST=make -j buildall
Change-Id: Id1482cc959233b41b0d917e8650866651d9a61fe
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/530137
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,455 | 15.06.2017 10:45:45 | 25,200 | 89b8ff1cba1f6399f2990a418b9846fa54187c50 | cleanup: motion_sense: Remove driver data structure externs
Driver data structs are now accessed through the drv_data pointer.
BRANCH=None
TEST=`make buildall -j`
Commit-Ready: Shawn N
Tested-by: Shawn N | [
{
"change_type": "MODIFY",
"old_path": "board/coral/board.c",
"new_path": "board/coral/board.c",
"diff": "@@ -824,10 +824,9 @@ const matrix_3x3_t mag_standard_ref = {\n};\n/* sensor private data */\n-/* TODO(crbug.com/733352): Remove useless externs and declare these static. */\n-struct kionix_accel... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cleanup: motion_sense: Remove driver data structure externs
Driver data structs are now accessed through the drv_data pointer.
BUG=chromium:733352
BRANCH=None
TEST=`make buildall -j`
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I8fedb425708a08ae6900ade6f17967fe2bc75ebf
Reviewed-on: https://chromium-review.googlesource.com/537217
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,396 | 15.06.2017 19:56:11 | 25,200 | 023a1cb2b3fd4a02bda1ac18783f260323424b8f | cr50: prepare to release version 0.0.21
BRANCH=cr50
TEST=built an image, observed version number. | [
{
"change_type": "MODIFY",
"old_path": "util/signer/ec_RW-manifest-dev.json",
"new_path": "util/signer/ec_RW-manifest-dev.json",
"diff": "\"timestamp\": 0,\n\"epoch\": 0, // FWR diversification contributor, 32 bits.\n\"major\": 0, // FW2_HIK_CHAIN counter.\n- \"minor\": 20, // Mostly harmless versio... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: prepare to release version 0.0.21
BRANCH=cr50
BUG=None
TEST=built an image, observed version number.
Change-Id: I2717530abb92383e1d0260580bed81e00f4f21bb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/538162
Reviewed-by: Nick Sanders <nsanders@chromium.org> |
136,313 | 16.06.2017 11:34:07 | 25,200 | deeb0ac7de3774b50c8468dfe281e0b9f03d2d46 | Use celes-pre-cq instead of strago-pre-cq
The stago build is not well kept after, as it is not used in production,
celes however is.
TEST=None
Commit-Ready: Bernie Thompson
Tested-by: Bernie Thompson | [
{
"change_type": "MODIFY",
"old_path": "COMMIT-QUEUE.ini",
"new_path": "COMMIT-QUEUE.ini",
"diff": "# chromeos-ec. We use the no-vmtest-pre-cq configs since the tests won't\n# actually test against our EC changes. (That's what FAFT is for)\npre-cq-configs: gru-no-vmtest-pre-cq reef-no-vmtest-pre-cq ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Use celes-pre-cq instead of strago-pre-cq
The stago build is not well kept after, as it is not used in production,
celes however is.
BUG=chromium:734103
TEST=None
Change-Id: Ie62a4729192fe63d18348f47105a2585c9e4f5be
Reviewed-on: https://chromium-review.googlesource.com/538571
Commit-Ready: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Yixiang Li <yixiang@google.com> |
136,405 | 14.04.2017 15:41:35 | 25,200 | 5ce3d325381f2f3bce0be4a83454944271c3b27c | Fizz: Verify and jump to RW image
BRANCH=none
TEST=Boot Fizz | [
{
"change_type": "MODIFY",
"old_path": "board/fizz/board.h",
"new_path": "board/fizz/board.h",
"diff": "/* I2C addresses */\n#define I2C_ADDR_TCPC0 0x16\n+/* Verify and jump to RW image on boot */\n+#define CONFIG_RWSIG\n+#define CONFIG_RWSIG_TYPE_RWSIG\n+#define CONFIG_RSA\n+#define CONFIG_SHA256\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Fizz: Verify and jump to RW image
BUG=b:37316498
BRANCH=none
TEST=Boot Fizz
Change-Id: Iaceb64bcf5d54145c26e86ce62a14d5732a22e78
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517406
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 26.05.2017 14:10:22 | 25,200 | cdaca7c97eaefe93ab3a0148a954b2f139f5caad | Add system_can_boot_ap API
This API checks battery charge level and current power supply
to determine whether the AP has enough power to boot or not.
BRANCH=none
TEST=make buildall | [
{
"change_type": "MODIFY",
"old_path": "common/system.c",
"new_path": "common/system.c",
"diff": "*/\n/* System module for Chrome EC : common functions */\n+#include \"battery.h\"\n+#include \"charge_manager.h\"\n#include \"clock.h\"\n#include \"common.h\"\n#include \"console.h\"\n@@ -1290,3 +1292,3... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Add system_can_boot_ap API
This API checks battery charge level and current power supply
to determine whether the AP has enough power to boot or not.
BUG=b:38462249
BRANCH=none
TEST=make buildall
Change-Id: I489f7ea92f230701b8f18c94d3e698aad90b4a03
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517272 |
136,197 | 03.06.2017 13:41:29 | -28,800 | 1442cbdebb85f5fbd501feeabd3d85ac5ab0af5f | hammer: Adjust trackpad dimensions
BRANCH=none
TEST=Flash and boot hammer, no more trackpad dimension mismatch error.
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "board/hammer/board.h",
"new_path": "board/hammer/board.h",
"diff": "#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1020 /* tenth of mm */\n#define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 584 /* tenth of mm */\n#elif defined(BOARD_HAMMER)\n-/* TODO(b:35582031): ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | hammer: Adjust trackpad dimensions
BRANCH=none
BUG=b:35582031
TEST=Flash and boot hammer, no more trackpad dimension mismatch error.
Change-Id: If4bd9db456617a52d1890543e7cae34a563122dd
Reviewed-on: https://chromium-review.googlesource.com/523502
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,409 | 17.06.2017 23:11:29 | 25,200 | ced1b4f90a1e1c28f45b152c3f17675f32233623 | ec_commands: Fix portability issues
Recent changes broke the portability of this header file.
Fix the ACPI guards so it can be used in coreboot.
BRANCH=none
TEST=make -j buildall (as usual many haven boards fail) | [
{
"change_type": "MODIFY",
"old_path": "include/ec_commands.h",
"new_path": "include/ec_commands.h",
"diff": "#ifndef __CROS_EC_EC_COMMANDS_H\n#define __CROS_EC_EC_COMMANDS_H\n+#ifndef __ACPI__\n#include <stdint.h>\n+#endif\n/*\n* Include common.h for CONFIG_HOSTCMD_ALIGNED, if it's defined. This\n@... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | ec_commands: Fix portability issues
Recent changes broke the portability of this header file.
Fix the ACPI guards so it can be used in coreboot.
BUG=b:36024430
BRANCH=none
TEST=make -j buildall (as usual many haven boards fail)
Change-Id: I0d737e7aad7ead90289b43db09352092ef7e3e98
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539135
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,439 | 19.06.2017 15:33:14 | 25,200 | c6a8c03ac92f189aee428895f0c03eb23acd4566 | Add fizz-no-vmtest-pre-cq to the pre-cq set
Because ec is used by the fizz board
TEST='cbuildbot --remote fizz-no-vmtest-pre-cq' passes
BRANCH=None
Tested-by: Prathmesh Prabhu | [
{
"change_type": "MODIFY",
"old_path": "COMMIT-QUEUE.ini",
"new_path": "COMMIT-QUEUE.ini",
"diff": "# chromeos-ec. We use the no-vmtest-pre-cq configs since the tests won't\n# actually test against our EC changes. (That's what FAFT is for)\npre-cq-configs: gru-no-vmtest-pre-cq reef-no-vmtest-pre-cq ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Add fizz-no-vmtest-pre-cq to the pre-cq set
Because ec is used by the fizz board
BUG=chromium:734783
TEST='cbuildbot --remote fizz-no-vmtest-pre-cq' passes
BRANCH=None
Change-Id: Ib3f7cf5b798e805ed197c79999ff6fc61b07f561
Reviewed-on: https://chromium-review.googlesource.com/540287
Tested-by: Prathmesh Prabhu <pprabhu@chromium.org>
Reviewed-by: Aviv Keshet <akeshet@chromium.org> |
136,405 | 21.06.2017 13:28:31 | 25,200 | 79a5a035eafe3a9caa5184e0df73fb2de31f5b72 | eCTS: Close tty
This patch makes cts.py close tty files explicitly.
BRANCH=none
TEST=cts.py -m meta | [
{
"change_type": "MODIFY",
"old_path": "cts/common/board.py",
"new_path": "cts/common/board.py",
"diff": "@@ -81,8 +81,7 @@ class Board(object):\nList of serials\n\"\"\"\nusb_args = ['lsusb', '-v', '-d', '0x0483:0x374b']\n- usb_process = sp.Popen(usb_args, stdout=sp.PIPE, shell=False)\n- st_link_inf... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eCTS: Close tty
This patch makes cts.py close tty files explicitly.
BUG=none
BRANCH=none
TEST=cts.py -m meta
Change-Id: Ifebfdd9607a603075492a59b5fb588e3cbc4ab12
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/544106
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 21.06.2017 11:25:35 | 25,200 | 9069d0ff28b2a77dc5b8db3d8e968df12b9f275f | eCTS: Add script to run tests and publish results
This script will run nightly in the lab and publish the results.
Publishing results will be implemented later.
BRANCH=none
TEST=Run run_ects.sh inside & outside chroot and verify all tests pass. | [
{
"change_type": "ADD",
"old_path": null,
"new_path": "util/run_ects.sh",
"diff": "+#!/bin/bash\n+#\n+# Copyright 2017 The Chromium OS Authors. All rights reserved.\n+# Use of this source code is governed by a BSD-style license that can be\n+# found in the LICENSE file.\n+#\n+# Run all eCTS tests an... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eCTS: Add script to run tests and publish results
This script will run nightly in the lab and publish the results.
Publishing results will be implemented later.
BUG=chromium:735546
BRANCH=none
TEST=Run run_ects.sh inside & outside chroot and verify all tests pass.
Change-Id: I405ea601eff33f1a4328f2606c8bb4050ff8d253
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/543681 |
136,455 | 14.06.2017 13:21:50 | 25,200 | 7632f7c4ee958706a868b588985877a77976fd59 | genvif: Fix uninitialized variable access
Defects reported by Coverity.
TEST=`make buildall -j`
BRANCH=None
Commit-Ready: Shawn N
Tested-by: Shawn N | [
{
"change_type": "MODIFY",
"old_path": "util/genvif.c",
"new_path": "util/genvif.c",
"diff": "@@ -232,7 +232,7 @@ static uint32_t bcddevice_sop(void)\nstatic uint32_t write_pdo_to_vif(FILE *vif, uint32_t pdo,\nenum dtype type, uint32_t pnum)\n{\n- uint32_t power;\n+ uint32_t power = 0;\nif ((pdo & P... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | genvif: Fix uninitialized variable access
Defects reported by Coverity.
BUG=None
TEST=`make buildall -j`
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I15e0809f8d97e75be522b6160346de6b59316395
Reviewed-on: https://chromium-review.googlesource.com/535837
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,405 | 23.06.2017 17:41:50 | 25,200 | de36e33ecf8d7e376d36b68c4be0229d306006ad | eCTS: Add I2C suite to run_ects.py
This patch adds i2c suite to run_ects.py. It also adds checks for
return values from i2c_read and i2c_write functions.
BRANCH=none
TEST=Run run_ects.py and verify all test pass. | [
{
"change_type": "MODIFY",
"old_path": "cts/i2c/cts.testlist",
"new_path": "cts/i2c/cts.testlist",
"diff": "* found in the LICENSE file.\n*/\n-/* Currently tests will execute in the order they are listed here */\n-\n-/* Test whether sync completes successfully */\n+/*\n+ * Test i2c write for 8, 16, ... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eCTS: Add I2C suite to run_ects.py
This patch adds i2c suite to run_ects.py. It also adds checks for
return values from i2c_read and i2c_write functions.
BUG=chromium:653183
BRANCH=none
TEST=Run run_ects.py and verify all test pass.
Change-Id: Ie3d6e1e6f131235e2b28f39e1546c9cb4c3b92f6
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/547024
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 28.06.2017 16:07:02 | 25,200 | 75efd78a59486cbcfb111ef314bafca67bc8d993 | eCTS: Expedite flashing time
eCTS tests are small. We can use smaller flash size to expedite
tests. This patch reduces flashing time for stm32l476 from 24 sec
to 6 sec.
BRANCH=none
TEST=python util/run_ects.py | [
{
"change_type": "MODIFY",
"old_path": "board/stm32l476g-eval/board.h",
"new_path": "board/stm32l476g-eval/board.h",
"diff": "#ifndef __CROS_EC_BOARD_H\n#define __CROS_EC_BOARD_H\n+#ifdef CTS_MODULE\n+/* CTS tests are small. We can use smaller size to expedite flash time. */\n+#undef CONFIG_FLASH_SI... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eCTS: Expedite flashing time
eCTS tests are small. We can use smaller flash size to expedite
tests. This patch reduces flashing time for stm32l476 from 24 sec
to 6 sec.
BUG=chromium:736020
BRANCH=none
TEST=python util/run_ects.py
Change-Id: I829ee2c947664f2d7ed373f52ff336e9a9580817
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/553580
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 26.06.2017 18:23:38 | 25,200 | c4157673b909896884f594052ac2e19b0cfc2280 | eCTS: Use proper methods to reset boards
This patch makes cts.py call reset_halt and resume instead of calling
send_openocd_commands directly.
BRANCH=none
TEST=Run util/run_ects.py. | [
{
"change_type": "MODIFY",
"old_path": "cts/common/board.py",
"new_path": "cts/common/board.py",
"diff": "@@ -96,7 +96,7 @@ class Board(object):\n\"\"\"Subclass should implement this.\"\"\"\npass\n- def send_open_ocd_commands(self, commands):\n+ def send_openocd_commands(self, commands):\n\"\"\"Send... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eCTS: Use proper methods to reset boards
This patch makes cts.py call reset_halt and resume instead of calling
send_openocd_commands directly.
BUG=none
BRANCH=none
TEST=Run util/run_ects.py.
Change-Id: I179fb73d41842b927fda81c153848887bb2dff57
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/553581
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 26.05.2017 14:27:03 | 25,200 | 9eca99983175784a0cc5e17a65e67498b9cfc8b1 | Fizz: Enable vboot EC
This patch enables vboot ec for Fizz.
BRANCH=none
TEST=Boot Fizz | [
{
"change_type": "MODIFY",
"old_path": "board/fizz/board.h",
"new_path": "board/fizz/board.h",
"diff": "#define CONFIG_SPI_FLASH_REGS\n#define CONFIG_SPI_FLASH_W25X40\n#define CONFIG_UART_HOST 0\n-#define CONFIG_VBOOT_HASH\n-#define CONFIG_VSTORE\n-#define CONFIG_VSTORE_SLOT_COUNT 1\n#define CONFIG_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Fizz: Enable vboot EC
This patch enables vboot ec for Fizz.
BUG=b:38462249
BRANCH=none
TEST=Boot Fizz
Change-Id: Ie20f7bab92e45849171a2db545459b40fe7b1c88
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517274
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 30.05.2017 13:41:13 | 25,200 | 031dccad78b9d4df6b970bc36ef2f9d469239708 | vboot_ec:Read try slot from BBRAM
This patch makes EC read the slot to verify and jump to from the
battery backed up RAM (BBRAM).
BRANCH=none
TEST=Boot Fizz | [
{
"change_type": "MODIFY",
"old_path": "chip/npcx/system.c",
"new_path": "chip/npcx/system.c",
"diff": "@@ -184,6 +184,10 @@ static int bbram_idx_lookup(enum system_bbram_idx idx)\nreturn BBRM_DATA_INDEX_PD0;\nif (idx == SYSTEM_BBRAM_IDX_PD1)\nreturn BBRM_DATA_INDEX_PD1;\n+#endif\n+#ifdef CONFIG_VBO... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | vboot_ec:Read try slot from BBRAM
This patch makes EC read the slot to verify and jump to from the
battery backed up RAM (BBRAM).
BUG=b:38462249
BRANCH=none
TEST=Boot Fizz
Change-Id: I0c78861ea3ccdc45d0aa08e690e3a68f53658409
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/518255 |
136,403 | 21.06.2017 14:40:23 | 25,200 | 2e3b42610b1239e8643d58396b7471b73e3989f6 | common: Add base32 encoding
Base32 encoding is used to turn the RMA reset binary
challenge/response into less-typo-prone text, at 5 bits per character.
BRANCH=none
TEST=make runtests | [
{
"change_type": "ADD",
"old_path": null,
"new_path": "common/base32.c",
"diff": "+/* Copyright 2017 The Chromium OS Authors. All rights reserved.\n+ * Use of this source code is governed by a BSD-style license that can be\n+ * found in the LICENSE file.\n+ */\n+\n+/* Base-32 encoding/decoding */\n+... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | common: Add base32 encoding
Base32 encoding is used to turn the RMA reset binary
challenge/response into less-typo-prone text, at 5 bits per character.
BUG=b:37952913
BRANCH=none
TEST=make runtests
Change-Id: I474750a20204ba353cea1e91982aa03e8071c0c2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/544177
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> |
136,403 | 21.06.2017 13:10:57 | 25,200 | 282765fdd409fd16ed1e092e5d7fee8de5af7a5a | common: Add RMA reset auth challenge-response crypto
RMA auth uses X25519 to generate a relatively small challenge and
response.
Currently, nothing calls the rma_auth code. We'll need console and
TPM vendor commands to do so.
BRANCH=none
TEST=make buildall | [
{
"change_type": "MODIFY",
"old_path": "common/build.mk",
"new_path": "common/build.mk",
"diff": "@@ -81,6 +81,7 @@ common-$(CONFIG_POWER_BUTTON_X86)+=power_button_x86.o\ncommon-$(CONFIG_PSTORE)+=pstore_commands.o\ncommon-$(CONFIG_PWM)+=pwm.o\ncommon-$(CONFIG_PWM_KBLIGHT)+=pwm_kblight.o\n+common-$(C... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | common: Add RMA reset auth challenge-response crypto
RMA auth uses X25519 to generate a relatively small challenge and
response.
Currently, nothing calls the rma_auth code. We'll need console and
TPM vendor commands to do so.
BUG=b:37952913
BRANCH=none
TEST=make buildall
Change-Id: Iec7f2d0e3dc8243f79b009ead16bb3ba9f1bef9d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/544184 |
136,405 | 30.06.2017 12:02:33 | 25,200 | d33618ce9f9a6b95632d0de3ebed1eca196cd982 | system: Allow sysjump command to jump to RW_B
This patch also removes an extra newline character from the printf
in system_can_boot_ap.
BRANCH=none
TEST=make buildall | [
{
"change_type": "MODIFY",
"old_path": "common/system.c",
"new_path": "common/system.c",
"diff": "@@ -989,6 +989,12 @@ static int command_sysjump(int argc, char **argv)\n* updated to use \"RW\".\n*/\nreturn system_run_image_copy(SYSTEM_IMAGE_RW);\n+ } else if (!strcasecmp(argv[1], \"B\")) {\n+#ifdef... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | system: Allow sysjump command to jump to RW_B
This patch also removes an extra newline character from the printf
in system_can_boot_ap.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I4143a687e0643328583ebf6cb14fc303da7f6a40
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/558211
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,407 | 07.07.2017 15:28:52 | 25,200 | 7903342436bfef4941b20a3c839f14b5398b9119 | power: Add Cannonlake chipset support.
BRANCH=None
TEST=`make -j buildall`
Commit-Ready: Aseda Aboagye
Tested-by: Aseda Aboagye | [
{
"change_type": "MODIFY",
"old_path": "include/config.h",
"new_path": "include/config.h",
"diff": "/* AP chipset support; pick at most one */\n#undef CONFIG_CHIPSET_APOLLOLAKE/* Intel Apollolake (x86) */\n#undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */\n+#undef CONFIG_CHIPSET_CANNONLAKE /... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | power: Add Cannonlake chipset support.
BUG=b:63508740
BRANCH=None
TEST=`make -j buildall`
Change-Id: I66e0e229c61c85af8f1f1c263e107e9990399e6a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/564798
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 11.07.2017 09:28:08 | 25,200 | bd8536454210b712637aa25bf76decb6a24b3685 | Define load addresses using macros
This patch defines load addresses of regions using macros to increase
readability.
BRANCH=none
TEST=Diff firmware_image.lds before and after the change. | [
{
"change_type": "MODIFY",
"old_path": "common/firmware_image.lds.S",
"new_path": "common/firmware_image.lds.S",
"diff": "#include \"config.h\"\n#include \"rwsig.h\"\n+#ifdef NPCX_RO_HEADER\n+/* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contains header\n+ * or some struture which do... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Define load addresses using macros
This patch defines load addresses of regions using macros to increase
readability.
BUG=none
BRANCH=none
TEST=Diff firmware_image.lds before and after the change.
Change-Id: I24a13f4676b194efb748522f03c3134d1568f5ae
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/566940
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,274 | 11.07.2017 15:14:37 | 25,200 | 1106dea40d3b18fbab2f42a2510d0a7899650db9 | servo_micro: add parity setting
Add a control interface to set parity
for USB-UART bridge.
BRANCH=None
TEST=parity settable on command line or by servod | [
{
"change_type": "MODIFY",
"old_path": "board/servo_micro/board.c",
"new_path": "board/servo_micro/board.c",
"diff": "/* Servo micro board configuration */\n#include \"common.h\"\n+#include \"console.h\"\n#include \"ec_version.h\"\n#include \"gpio.h\"\n#include \"hooks.h\"\n@@ -52,14 +53,15 @@ stati... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | servo_micro: add parity setting
Add a control interface to set parity
for USB-UART bridge.
BRANCH=None
BUG=b:37513705
TEST=parity settable on command line or by servod
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: Ib859a70981162be58edfa79c7cb267e0084e05e6
Reviewed-on: https://chromium-review.googlesource.com/564150
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,281 | 20.07.2017 09:52:50 | -28,800 | 31ceb6a6da0cef5fae59707203b453d2294371d6 | flash_ec: add nefario for support
BRANCH=none
TEST=utils/flash_ec --board=nefario | [
{
"change_type": "MODIFY",
"old_path": "util/flash_ec",
"new_path": "util/flash_ec",
"diff": "@@ -114,6 +114,7 @@ BOARDS_NPCX_SPI=(\nfizz\ngru\nkevin\n+ nefario\npoppy\nreef\nscarlet\n@@ -139,6 +140,7 @@ BOARDS_SPI_1800MV=(\ncoral\ngru\nkevin\n+ nefario\nreef\nscarlet\n)\n@@ -149,6 +151,7 @@ BOARDS_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | flash_ec: add nefario for support
BUG=b:63408169
BRANCH=none
TEST=utils/flash_ec --board=nefario
Change-Id: Ic13d6257a548d6c759542f3e8e679b0ce2b4de51
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/578694
Reviewed-by: Philip Chen <philipchen@chromium.org> |
136,314 | 11.05.2017 16:24:05 | 25,200 | 2ef78186c980120560123b149d7092a51edbeb98 | kevin: disable reporting of unneeded host events
Disable reporting of EC events to the linux kernel that are not used
by kevin's kernel.
BRANCH=none
TEST=make buildall passes, lid close puts AP into suspend, lid open
turns on display | [
{
"change_type": "MODIFY",
"old_path": "board/kevin/board.h",
"new_path": "board/kevin/board.h",
"diff": "EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\\\nEC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))\n+/*\n+ * Define the host events which are to be reported to the kernel.\n+ *\n+ * Linux 4.4 kernel uses... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | kevin: disable reporting of unneeded host events
Disable reporting of EC events to the linux kernel that are not used
by kevin's kernel.
BRANCH=none
BUG=chromium:637061
TEST=make buildall passes, lid close puts AP into suspend, lid open
turns on display
Change-Id: I7841294aec0853f4820a262ec14e8ad6037e1060
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/503536
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,228 | 20.07.2017 15:03:32 | 25,200 | 3968c95e124c6a84ef57881a2058db3b754ab365 | button: Add recovery button to mkbp button state
Pass in recovery button press/release information to AP using MKBP
button driver.
BRANCH=None
TEST=Behavior verified by Shelley. | [
{
"change_type": "MODIFY",
"old_path": "common/keyboard_mkbp.c",
"new_path": "common/keyboard_mkbp.c",
"diff": "@@ -247,6 +247,11 @@ void keyboard_update_button(enum keyboard_button_type button, int is_pressed)\nmkbp_button_state |= (is_pressed << EC_MKBP_VOL_DOWN);\nbreak;\n+ case KEYBOARD_BUTTON_R... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | button: Add recovery button to mkbp button state
Pass in recovery button press/release information to AP using MKBP
button driver.
BUG=b:63893483
BRANCH=None
TEST=Behavior verified by Shelley.
Change-Id: I7a6e50ec8595d99327b5fc8e822bf762e0ce13e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580539
Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
136,274 | 17.07.2017 21:14:39 | 25,200 | a6c34e183a70aabcef1cd4362303df475afc173e | tigertail: support button toggle
Tigertail Rev. C has a button, we'll use it to toggle
between A, B and off.
BRANCH=None
TEST=ran on tigertail w/rework, mux muxed. | [
{
"change_type": "MODIFY",
"old_path": "board/tigertail/board.c",
"new_path": "board/tigertail/board.c",
"diff": "@@ -312,6 +312,7 @@ static void set_led_b(int r, int g, int b)\n/* State we intend the mux GPIOs to be set. */\nstatic int mux_state = MUX_OFF;\n+static int last_mux_state = MUX_OFF;\n/*... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | tigertail: support button toggle
Tigertail Rev. C has a button, we'll use it to toggle
between A, B and off.
BRANCH=None
BUG=b:35849284
TEST=ran on tigertail w/rework, mux muxed.
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I2a2a9ce0ba713c47e6f1196fac62a3804a78bf94
Reviewed-on: https://chromium-review.googlesource.com/575893
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,230 | 19.07.2017 23:11:48 | 25,200 | 1339fff8535e1378f5b34022075bb5b63ca0e522 | flash_ec: Add servo support for Scarlet rev1
This will also kill the servo support for Scarlet rev0.
BRANCH=none
TEST=none
Commit-Ready: Philip Chen
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "util/flash_ec",
"new_path": "util/flash_ec",
"diff": "@@ -74,6 +74,7 @@ BOARDS_STM32=(\nplankton\nryu\nsamus_pd\n+ scarlet\nsnoball\nstaff\nstrago_pd\n@@ -117,7 +118,6 @@ BOARDS_NPCX_SPI=(\nnefario\npoppy\nreef\n- scarlet\nsoraka\nwheatley\nkahlee\n@@ -142,7 +... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | flash_ec: Add servo support for Scarlet rev1
This will also kill the servo support for Scarlet rev0.
BUG=b:62269890
BRANCH=none
TEST=none
Change-Id: Ibacd8905bf0a07e3787adb7fe1a1daaf2ff98943
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/578927
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,274 | 17.07.2017 22:18:31 | 25,200 | 15819d06c89ac7c2c245b3d0eea3f2f4116aaaf7 | tigertail: support vref on uart
Support a level shifter for both 1.8v and 3.3v
uarts on SBU.
BRANCH=None
TEST=ran on tigertail, both 1.8v and 3.3v detected. | [
{
"change_type": "MODIFY",
"old_path": "board/tigertail/board.c",
"new_path": "board/tigertail/board.c",
"diff": "@@ -122,27 +122,63 @@ static int uart_state = UART_OFF;\n/* State to indicate current autodetect mode. */\nstatic int uart_detect = UART_DETECT_AUTO;\n+const char *const uart_state_names... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | tigertail: support vref on uart
Support a level shifter for both 1.8v and 3.3v
uarts on SBU.
BRANCH=None
BUG=b:35849284
TEST=ran on tigertail, both 1.8v and 3.3v detected.
Change-Id: I76d545b582c6ed15086941513d5de4cd6783ac16
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575595
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,409 | 19.07.2017 23:26:00 | 25,200 | 192be4327fac83f10b754ef69f25fdcdf574cec5 | eve: Enable active discharge on V3.3A and V1.8A
Enable 100ohm discharge on the V3.3A and V1.8A rails.
TEST=verify power down sequence on scope | [
{
"change_type": "MODIFY",
"old_path": "board/eve/board.c",
"new_path": "board/eve/board.c",
"diff": "@@ -350,6 +350,9 @@ static void board_pmic_init(void)\nif (system_jumped_to_this_image())\nreturn;\n+ /* DISCHGCNT2 - enable 100 ohm discharge on V3.3A and V1.8A */\n+ i2c_write8(I2C_PORT_PMIC, I2C_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eve: Enable active discharge on V3.3A and V1.8A
Enable 100ohm discharge on the V3.3A and V1.8A rails.
BUG=b:35581264
TEST=verify power down sequence on scope
Change-Id: Ibdfff5a60bddd9da0d950dae619346d7a3dccd8b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/578756
Reviewed-on: https://chromium-review.googlesource.com/579903
Reviewed-by: Furquan Shaikh <furquan@chromium.org> |
136,197 | 22.07.2017 06:39:34 | -28,800 | fef7e102f606654cb72b5bd25555ffe90aab4f7f | chip/stm32/usb_hid_touchpad: Move all finger data to a macro
Reduces code duplication, makes changes easier.
BRANCH=none
TEST=Flash hammer, touchpad works
Commit-Ready: Nicolas Boichat
Tested-by: Nicolas Boichat | [
{
"change_type": "MODIFY",
"old_path": "chip/stm32/usb_hid_touchpad.c",
"new_path": "chip/stm32/usb_hid_touchpad.c",
"diff": "@@ -53,7 +53,28 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = {\n.bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */\n};\n-#de... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | chip/stm32/usb_hid_touchpad: Move all finger data to a macro
Reduces code duplication, makes changes easier.
BRANCH=none
BUG=b:63936194
TEST=Flash hammer, touchpad works
Change-Id: I14539fa2611cdc0151c05bc83470265a2bb9faec
Reviewed-on: https://chromium-review.googlesource.com/583296
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Chun-ta Lin <itspeter@chromium.org> |
136,230 | 16.07.2017 17:16:07 | 25,200 | 2fe0acefdd8293ca7e7f34ff6da5811b76e01c7d | scarlet: Add rt946x charger for the new board
BRANCH=none
TEST=build scarlet
Commit-Ready: Philip Chen
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "board/scarlet/battery.c",
"new_path": "board/scarlet/battery.c",
"diff": "#include \"battery_smart.h\"\n#include \"charge_state.h\"\n#include \"console.h\"\n+#include \"driver/charger/rt946x.h\"\n#include \"ec_commands.h\"\n#include \"extpower.h\"\n#include \"... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | scarlet: Add rt946x charger for the new board
BUG=b:63739819
BRANCH=none
TEST=build scarlet
Change-Id: I8710412a591170d077dc217c192ec3b231e54659
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/573585
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,350 | 27.07.2017 16:28:15 | 25,200 | 84a952e0e867d2e862aefb72dd12efaf832a8fa8 | npcx: Drop unused cmd_params from lpc.c
cmd_params is static, const and unused. Drop it.
BRANCH=none
TEST=USE=coreboot-sdk emerge-fizz chromeos-ec succeeds.
Commit-Ready: Stefan Reinauer
Tested-by: Stefan Reinauer | [
{
"change_type": "MODIFY",
"old_path": "chip/npcx/lpc.c",
"new_path": "chip/npcx/lpc.c",
"diff": "@@ -70,8 +70,6 @@ static uint8_t shm_memmap[256] __aligned(8);\nstatic uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);\nstatic int init_done;\n-static uint8_t * const cmd_params = (uint8_t *)... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | npcx: Drop unused cmd_params from lpc.c
cmd_params is static, const and unused. Drop it.
BUG=none
BRANCH=none
TEST=USE=coreboot-sdk emerge-fizz chromeos-ec succeeds.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Change-Id: I62444d81affde9e3e0d4da1d1ee2d5d51a337bb6
Reviewed-on: https://chromium-review.googlesource.com/590676
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> |
136,350 | 28.07.2017 13:11:53 | 25,200 | 25aa1c13dd0f46a3444673cffedffe4543404330 | eve: Move enums before declarations in led.c
BRANCH=none
TEST=USE=coreboot-sdk emerge-eve chromeos-ec compiles successfully
Commit-Ready: Stefan Reinauer
Tested-by: Stefan Reinauer | [
{
"change_type": "MODIFY",
"old_path": "board/eve/led.c",
"new_path": "board/eve/led.c",
"diff": "#define LED_FRAC_BITS 4\n#define LED_STEP_MSEC 45\n-static int led_debug;\n-static int double_tap;\n-static int double_tap_tick_count;\n-static int led_pattern;\n-static int led_ticks;\n-static enum led... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | eve: Move enums before declarations in led.c
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=USE=coreboot-sdk emerge-eve chromeos-ec compiles successfully
Change-Id: Ib068a935bd80ee57388ffcb707b4a2684f7b6d5a
Reviewed-on: https://chromium-review.googlesource.com/592270
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,403 | 27.07.2017 16:00:52 | 25,200 | 96173345e7c56f82f6c746f574285849893977dd | cr50: Rename uartn_enabled() to uartn_tx_is_connected()
Because that's what it means. That is, it reports the state of
uartn_tx_connect(), not uartn_enable().
No functional changes; just a rename.
BRANCH=cr50
TEST=make buildall -j | [
{
"change_type": "MODIFY",
"old_path": "board/cr50/board.c",
"new_path": "board/cr50/board.c",
"diff": "@@ -880,7 +880,7 @@ static int device_state_changed(enum device_type device,\n*/\nstatic int servo_state_unknown(void)\n{\n- if (uartn_enabled(UART_EC)) {\n+ if (uart_tx_is_connected(UART_EC)) {\n... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: Rename uartn_enabled() to uartn_tx_is_connected()
Because that's what it means. That is, it reports the state of
uartn_tx_connect(), not uartn_enable().
No functional changes; just a rename.
BUG=none
BRANCH=cr50
TEST=make buildall -j
Change-Id: Ie2273b277bd73a40307be7ec215417c1225cd567
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590859 |
136,230 | 26.07.2017 18:09:18 | 25,200 | a7b57ca84c3ee81fc51f46133f0d67abf65b10bb | nefario: Re-configure/Rename GPIOs for rev0
BRANCH=none
TEST=build nefario
Commit-Ready: Philip Chen
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "board/nefario/board.c",
"new_path": "board/nefario/board.c",
"diff": "@@ -77,8 +77,8 @@ const struct adc_t adc_channels[] = {\n\"BOARD_ID\", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },\n[ADC_PP900_AP] = {\n\"PP900_AP\", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_REA... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | nefario: Re-configure/Rename GPIOs for rev0
BUG=b:63408169
BRANCH=none
TEST=build nefario
Change-Id: I1a655c6af665f0b144504c266981049775c0d7ff
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/588333
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,230 | 25.07.2017 14:11:53 | 25,200 | 90a2060904f4b55f64c341ff985a6a5ee7c5210a | nefario: Enable battery LED control
BRANCH=none
TEST=build nefario (no boards to test yet)
Commit-Ready: Philip Chen
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "board/nefario/board.c",
"new_path": "board/nefario/board.c",
"diff": "@@ -90,8 +90,9 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);\n/******************************************************************************/\n/* PWM channels. Must be in the e... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | nefario: Enable battery LED control
BUG=b:63408169
BRANCH=none
TEST=build nefario (no boards to test yet)
Change-Id: I1c170803b9e174dd969259aa6a3d3e910e872ba5
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/584858
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> |
136,396 | 24.07.2017 15:08:14 | 25,200 | cb06c593b401b8879d8c89e38863789c7385af98 | cr50: prepare to release RW 0.0.22
This version will be bettter sutied for chip manufacturing environment
(no contention with the test rig GPIO settings and formal confirmation
of successful certificate installation).
BRANCH=cr50
TEST=none | [
{
"change_type": "MODIFY",
"old_path": "util/signer/ec_RW-manifest-dev.json",
"new_path": "util/signer/ec_RW-manifest-dev.json",
"diff": "\"timestamp\": 0,\n\"epoch\": 0, // FWR diversification contributor, 32 bits.\n\"major\": 0, // FW2_HIK_CHAIN counter.\n- \"minor\": 21, // Mostly harmless versio... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: prepare to release RW 0.0.22
This version will be bettter sutied for chip manufacturing environment
(no contention with the test rig GPIO settings and formal confirmation
of successful certificate installation).
BRANCH=cr50
BUG=b:63686091
TEST=none
Change-Id: I6d394493b824c9d79bca4785d3d44b33f322b899
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/583990
Reviewed-by: Mary Ruthven <mruthven@chromium.org> |
136,407 | 02.08.2017 18:08:07 | 25,200 | 55d1a89f1780f56d6b938ad1e85c89d4a439b833 | zoombini: Use common KB PWM backlight module.
BRANCH=none
TEST=`make -j BOARD=zoombini`
Commit-Ready: Aseda Aboagye
Tested-by: Aseda Aboagye | [
{
"change_type": "MODIFY",
"old_path": "board/zoombini/board.c",
"new_path": "board/zoombini/board.c",
"diff": "@@ -69,7 +69,7 @@ const struct adc_t adc_channels[] = {\nconst struct pwm_t pwm_channels[] = {\n[PWM_CH_LED_GREEN] = { 0, PWM_CONFIG_DSLEEP, 100 },\n[PWM_CH_LED_RED] = { 2, PWM_CONFIG_DSLE... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | zoombini: Use common KB PWM backlight module.
BUG=none
BRANCH=none
TEST=`make -j BOARD=zoombini`
Change-Id: I73a74066e926cb788ddbf0f258b6fe84ebc4a95f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/601427
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,405 | 02.06.2017 14:08:05 | 25,200 | bc23ce130567ac1fb71dfbfaf3596b8ef540af8e | Fizz: Disable PECI
This patch disables PECI so that GPIO81 can be used for PROCHOT.
BRANCH=NONE
TEST=Boot i7 and Celeron Fizz. | [
{
"change_type": "MODIFY",
"old_path": "board/fizz/board.h",
"new_path": "board/fizz/board.h",
"diff": "#define CONFIG_CHIPSET_SKYLAKE\n#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET\n#define CONFIG_CHIPSET_RESET_HOOK\n+#undef CONFIG_PECI\n#define CONFIG_ESPI\n/* Eve and Poppy all have wires from GP... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Fizz: Disable PECI
This patch disables PECI so that GPIO81 can be used for PROCHOT.
BUG=b:62092359
BRANCH=NONE
TEST=Boot i7 and Celeron Fizz.
Change-Id: I57f7ece6aa23f1f84a05d2570d71a44e43e7e1ef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/526035
Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
136,381 | 04.08.2017 14:21:40 | 25,200 | 0d385e7e5754327dae713415d3b931172514eae9 | Add uint_(least|fast)*_t types
This commit adds typedefs for signed and unsigned variants of the
_fast and _least integer types.
BRANCH=None
TEST=make buildall -J
Commit-Ready: Jeff Andersen
Tested-by: Jeff Andersen | [
{
"change_type": "MODIFY",
"old_path": "builtin/stdint.h",
"new_path": "builtin/stdint.h",
"diff": "@@ -18,10 +18,31 @@ typedef signed int int32_t;\ntypedef unsigned long long uint64_t;\ntypedef signed long long int64_t;\n-typedef int intptr_t;\ntypedef unsigned int uintptr_t;\n+typedef int intptr_t... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | Add uint_(least|fast)*_t types
This commit adds typedefs for signed and unsigned variants of the
_fast and _least integer types.
BUG=None
BRANCH=None
TEST=make buildall -J
Change-Id: Idefc8f9529d22f17af57859be3c25c36a7f8ec25
Reviewed-on: https://chromium-review.googlesource.com/602870
Commit-Ready: Jeff Andersen <jeffandersen@google.com>
Tested-by: Jeff Andersen <jeffandersen@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,453 | 08.08.2017 08:06:59 | -28,800 | 02aa4ee1e5d73d65b9aae5915e284a2ff6ceadc6 | chip/host/config_chip: Fix TASK_STACK_SIZE of the host board.
Define TASK_STACK_SIZE as standard value 512 for the host board.
BRANCH=none
TEST=make runtests | [
{
"change_type": "MODIFY",
"old_path": "chip/host/config_chip.h",
"new_path": "chip/host/config_chip.h",
"diff": "@@ -32,6 +32,9 @@ extern char __host_flash[CONFIG_FLASH_SIZE];\n/* Compute the rest of the flash params from these */\n#include \"config_std_internal_flash.h\"\n+/* Default task stack si... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | chip/host/config_chip: Fix TASK_STACK_SIZE of the host board.
Define TASK_STACK_SIZE as standard value 512 for the host board.
BUG=chromium:752923
BRANCH=none
TEST=make runtests
Change-Id: I3e5120847e9b14fbf96d00c428b2db9d59d38fe2
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/604850
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,234 | 05.06.2017 17:06:26 | 25,200 | 8bfde69fdd9b5feb4c47c8c714416c17afe00f78 | GLKRVP: Enable fast charging and battery cut-off
BRANCH=glkrvp
TEST=Fast charging & battery cut-off works
Commit-Ready: Vijay P Hiremath
Tested-by: Vijay P Hiremath | [
{
"change_type": "MODIFY",
"old_path": "board/glkrvp/battery.c",
"new_path": "board/glkrvp/battery.c",
"diff": "*/\n#include \"battery.h\"\n+#include \"charger_profile_override.h\"\n#include \"console.h\"\n#include \"ioexpander_pca9555.h\"\n+#include \"util.h\"\n#define CPRINTS(format, args...) cpri... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | GLKRVP: Enable fast charging and battery cut-off
BUG=b:64452259
BRANCH=glkrvp
TEST=Fast charging & battery cut-off works
Change-Id: Ica19ed11891ef5ac8b37140a5fcbb311333d5b5a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/604732
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,314 | 26.05.2017 12:29:14 | 25,200 | e656b970e204309c1a665f154a5972ed85305911 | sensors: add bmi160 & kionix orientation driver
BRANCH=none
TEST=make buildall -j works, orientation works when enabled on gru
and scarlet.
Tested-by: Nick Vaccaro | [
{
"change_type": "MODIFY",
"old_path": "common/motion_sense.c",
"new_path": "common/motion_sense.c",
"diff": "#include \"timer.h\"\n#include \"task.h\"\n#include \"util.h\"\n+#include \"accel_kionix.h\"\n/* Console output macros */\n#define CPUTS(outstr) cputs(CC_MOTION_SENSE, outstr)\n#define CPRIN... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | sensors: add bmi160 & kionix orientation driver
BRANCH=none
BUG=chromium:718919
TEST=make buildall -j works, orientation works when enabled on gru
and scarlet.
Change-Id: I16dcfa5d9dea39c082d98190fa1bb6e496168b17
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/540124
Tested-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org> |
136,234 | 05.06.2017 17:17:02 | 25,200 | 5dc101be09213f5f7414245da0b1bdfb94d7b534 | glkrvp: Enable board version identification
BRANCH=glkrvp
TEST='version' works on EC console.
Commit-Ready: Vijay P Hiremath
Tested-by: Vijay P Hiremath | [
{
"change_type": "MODIFY",
"old_path": "board/glkrvp/board.c",
"new_path": "board/glkrvp/board.c",
"diff": "#include \"gpio_list.h\"\n-#define I2C_PORT_PCA555_PMIC NPCX_I2C_PORT0_0\n-#define I2C_ADDR_PCA555_PMIC 0x42\n-#define PMIC_WRITE(reg, data) pca9555_write(I2C_PORT_PCA555_PMIC, \\\n- I2C_ADDR_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | glkrvp: Enable board version identification
BUG=b:64491133
BRANCH=glkrvp
TEST='version' works on EC console.
Change-Id: I7ed56870ec8fa817d55ab8acb362761c99f5bb29
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/606893
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,234 | 14.07.2017 16:20:47 | 25,200 | 76a64e7c826e0665d75327cf8d219f1a7a534dd4 | glkrvp: Enable S0iX support
BRANCH=glkrvp
TEST=EC console command powerindebug shows correct GPIO info
Commit-Ready: Vijay P Hiremath
Tested-by: Vijay P Hiremath | [
{
"change_type": "MODIFY",
"old_path": "board/glkrvp/board.c",
"new_path": "board/glkrvp/board.c",
"diff": "/* power signal list. Must match order of enum power_signal. */\nconst struct power_signal_info power_signal_list[] = {\n{GPIO_RSMRST_L_PGOOD, 1, \"RSMRST_L\"},\n+ {GPIO_PCH_SLP_S0_L, 1, \"SLP... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | glkrvp: Enable S0iX support
BUG=b:64559696
BRANCH=glkrvp
TEST=EC console command powerindebug shows correct GPIO info
Change-Id: Iee346f61bc0a0b26d612d2966350d308be596592
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/610304
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
136,234 | 20.04.2017 18:16:55 | 25,200 | 97fe22e8d559449cbd9df5cc2065f5ab5941830e | glkrvp: Enable switches
BRANCH=glkrvp
TEST=mmapinfo is updated when lidopen & lidclose are performed
SCI/SMI gpios toggle
Commit-Ready: Vijay P Hiremath
Tested-by: Vijay P Hiremath | [
{
"change_type": "MODIFY",
"old_path": "board/glkrvp/board.h",
"new_path": "board/glkrvp/board.h",
"diff": "#define CONFIG_POWER_COMMON\n#define CONFIG_POWER_S0IX\n#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE\n+#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L\n/* EC */\n#define CONFIG_BOARD_VERSION\n/* EC excl... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | glkrvp: Enable switches
BUG=b:64491401
BRANCH=glkrvp
TEST=mmapinfo is updated when lidopen & lidclose are performed
SCI/SMI gpios toggle
Change-Id: I93f1ae2cc8dbc389b3e870b49d5ee2bfff503451
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/606892
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,197 | 11.08.2017 11:58:56 | -28,800 | 1ba0395a18c02dfbdc66f8b0f5fa930353b26705 | usb_api.h: Stub usb_wake if CONFIG_USB_REMOTE_WAKEUP is not defined
Removes clutter in callers, so that they do not have to wrap
usb_wake calls around ifdefs.
BRANCH=none
TEST=make buildall -j | [
{
"change_type": "MODIFY",
"old_path": "chip/stm32/usb_hid_keyboard.c",
"new_path": "chip/stm32/usb_hid_keyboard.c",
"diff": "@@ -211,10 +211,8 @@ static void write_keyboard_report(void)\nEP_TX_VALID, 0);\n}\n-#ifdef CONFIG_USB_REMOTE_WAKEUP\n/* Wake up host, if required. */\nusb_wake();\n-#endif\n}... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | usb_api.h: Stub usb_wake if CONFIG_USB_REMOTE_WAKEUP is not defined
Removes clutter in callers, so that they do not have to wrap
usb_wake calls around ifdefs.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I8641cb7aff702920aaa119e644dc812d5c3e774b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/612220
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,197 | 14.08.2017 11:45:48 | -28,800 | 72ea1febb128b4a14ccab5a093bd9abd267b9946 | chip/stm32/usb: Split usb wake handler as a different function
Indentation is growing out of control, let's move to a separate
function so that we can return early.
BRANCH=none
TEST=Flash hammer, usb_wake works. | [
{
"change_type": "MODIFY",
"old_path": "chip/stm32/usb.c",
"new_path": "chip/stm32/usb.c",
"diff": "@@ -422,33 +422,28 @@ int usb_is_suspended(void)\n}\n#endif /* CONFIG_USB_SUSPEND */\n-void usb_interrupt(void)\n-{\n- uint16_t status = STM32_USB_ISTR;\n-\n- if (status & STM32_USB_ISTR_RESET)\n- usb... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | chip/stm32/usb: Split usb wake handler as a different function
Indentation is growing out of control, let's move to a separate
function so that we can return early.
BRANCH=none
BUG=b:35775048
TEST=Flash hammer, usb_wake works.
Change-Id: I9abf99ff55b3977dfc307fc99aac6f1ab7dd1f6a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/612922
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,420 | 31.07.2017 14:19:26 | -7,200 | f747f70816ca825a4ff4f9c6234f97e93611dbaa | coral: Add host command to fetch SKU ID
BRANCH=none
TEST=with the other sku-id related patches applied, coreboot obtains the
right SKU ID from EC
Commit-Ready: Patrick Georgi
Tested-by: Patrick Georgi | [
{
"change_type": "MODIFY",
"old_path": "board/coral/board.c",
"new_path": "board/coral/board.c",
"diff": "@@ -1101,6 +1101,17 @@ DECLARE_CONSOLE_COMMAND(board_id, command_board_id,\n\"<id|sku0|sku1>\",\n\"Get board id or sku\");\n+uint32_t system_get_sku_id(void)\n+{\n+ uint8_t sku_id_lower = board_... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | coral: Add host command to fetch SKU ID
BUG=b:64468585
BRANCH=none
TEST=with the other sku-id related patches applied, coreboot obtains the
right SKU ID from EC
Change-Id: Ibf307c6e46152b4b09e94d8dca6d49ae863cb3ad
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/608370
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
136,453 | 16.08.2017 12:25:43 | -28,800 | 79e3b1c5e29e45eb25a8b7ad8f0b1679d31776df | ec: Fix object comparison in the stack analyzer
Handle the case of comparing with different kinds of objects.
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py | [
{
"change_type": "MODIFY",
"old_path": "extra/stack_analyzer/stack_analyzer.py",
"new_path": "extra/stack_analyzer/stack_analyzer.py",
"diff": "@@ -76,6 +76,9 @@ class Task(object):\nReturns:\nTrue if equal, False if not.\n\"\"\"\n+ if not isinstance(other, Task):\n+ return False\n+\nreturn (self.na... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | ec: Fix object comparison in the stack analyzer
Handle the case of comparing with different kinds of objects.
BUG=none
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
Change-Id: I01056cd39e14d75442d4029b6c64d9843c49cf2a
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/616367
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,396 | 18.08.2017 14:20:50 | 25,200 | 60f8deccb1de072340c7b624f16149f84db2323b | cr50: prepare to release RW 0.0.23
New released images need higher version number.
BRANCH=none
TEST=built and ran an image, verified version number to be right. | [
{
"change_type": "MODIFY",
"old_path": "util/signer/ec_RW-manifest-dev.json",
"new_path": "util/signer/ec_RW-manifest-dev.json",
"diff": "\"timestamp\": 0,\n\"epoch\": 0, // FWR diversification contributor, 32 bits.\n\"major\": 0, // FW2_HIK_CHAIN counter.\n- \"minor\": 22, // Mostly harmless versio... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | cr50: prepare to release RW 0.0.23
New released images need higher version number.
BRANCH=none
BUG=none
TEST=built and ran an image, verified version number to be right.
Change-Id: I0b5b690d84b2f281752ad01b154efdebeba2e136
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/621296
Reviewed-by: Mary Ruthven <mruthven@chromium.org> |
136,230 | 18.08.2017 12:17:37 | 25,200 | 8e7bad04821fb7b288ab2d3b4e1e3551ee7d6e94 | battery/max17055: Specify desired charging voltage/current
CQ-DEPEND=CL:621777
BRANCH=none
TEST=plug in AC, and check 'charger' command on ec console
Commit-Ready: Philip Chen
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "driver/battery/max17055.c",
"new_path": "driver/battery/max17055.c",
"diff": "@@ -256,8 +256,8 @@ void battery_get_params(struct batt_params *batt)\nbatt->current = CURRENT_CONV((int16_t)reg);\n- /* Default to not desiring voltage and current */\n- batt->desir... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | battery/max17055: Specify desired charging voltage/current
BUG=b:64821815, b:63870414
CQ-DEPEND=CL:621777
BRANCH=none
TEST=plug in AC, and check 'charger' command on ec console
Change-Id: Ic60bcab7fd0ccc2ea73471ac46e9b0b887f251d9
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/621776
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,230 | 18.08.2017 12:25:00 | 25,200 | a438efab9c8a667743da8588bc32252ce617c517 | scarlet: Define BATTERY_DESIRED_CHARGING_CURRENT
CQ-DEPEND=CL:621776
BRANCH=none
TEST=plug in AC, and check 'charger' command on ec console
Commit-Ready: Philip Chen
Tested-by: Philip Chen | [
{
"change_type": "MODIFY",
"old_path": "board/scarlet/board.h",
"new_path": "board/scarlet/board.h",
"diff": "#define BATTERY_MAX17055_ICHGTERM 0x0220\n#define BATTERY_MAX17055_VEMPTY 0xa561\n#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */\n+#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */\n#def... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | scarlet: Define BATTERY_DESIRED_CHARGING_CURRENT
BUG=b:64821815
CQ-DEPEND=CL:621776
BRANCH=none
TEST=plug in AC, and check 'charger' command on ec console
Change-Id: I53681d21a5311ea58562acf2fae451ebc7f41d4d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/621777
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,350 | 16.08.2017 16:49:15 | 25,200 | e11682bc0143691c72cc3e08ff781587a954ea32 | BUILDCC fragments should include core/host
This will prevent userland code to pull in includes
from core/stm32 etc.
BRANCH=none
TEST=make buildall -j
Commit-Ready: Stefan Reinauer
Tested-by: Stefan Reinauer | [
{
"change_type": "MODIFY",
"old_path": "Makefile.toolchain",
"new_path": "Makefile.toolchain",
"diff": "@@ -58,7 +58,7 @@ CFLAGS_DEFINE=-DOUTDIR=$(out)/$(BLD) -DCHIP=$(CHIP) -DBOARD_TASKFILE=$(_tsk_lst_\nCPPFLAGS=$(CFLAGS_DEFINE) $(CFLAGS_INCLUDE) $(CFLAGS_TEST) \\\n$(EXTRA_CFLAGS) $(CFLAGS_COVERAGE... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | BUILDCC fragments should include core/host
This will prevent userland code to pull in includes
from core/stm32 etc.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I450b17baf579cbaee04c253c1e86d998f6e329da
Reviewed-on: https://chromium-review.googlesource.com/618270
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
136,234 | 19.04.2017 18:48:20 | 25,200 | 309289df45c35af0e935b1a965412e4dacaad036 | glkrvp: Enable TCPC using NXP PTN5110 AIC
BRANCH=glkrvp
TEST=TCPC can negotiate to 20V & 2.25A
Commit-Ready: Vijay P Hiremath
Tested-by: Vijay P Hiremath | [
{
"change_type": "MODIFY",
"old_path": "board/glkrvp/board.c",
"new_path": "board/glkrvp/board.c",
"diff": "@@ -56,7 +56,7 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);\n/* I2C ports */\nconst struct i2c_port_t i2c_ports[] = {\n{\"pmic\", NPCX_I2C_PORT0_0, 100, GPIO_I2C0_SCL0... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | glkrvp: Enable TCPC using NXP PTN5110 AIC
BUG=b:64531818
BRANCH=glkrvp
TEST=TCPC can negotiate to 20V & 2.25A
Change-Id: I16510a510133bbb1827634303a6b9d02dec4bbc6
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/614311
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,453 | 17.08.2017 17:12:03 | -28,800 | 00e022272938d3c3f8b5d60f11c960d9da5546ac | extra/stack_analyzer: Fix cbz/cbnz and addr2line parsing.
Fix the cbz/cbnz operands parsing.
Parse the discriminator output of addr2line.
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py | [
{
"change_type": "MODIFY",
"old_path": "extra/stack_analyzer/stack_analyzer.py",
"new_path": "extra/stack_analyzer/stack_analyzer.py",
"diff": "@@ -267,16 +267,20 @@ class ArmAnalyzer(object):\nCONDITION_CODES = ['', 'eq', 'ne', 'cs', 'hs', 'cc', 'lo', 'mi', 'pl', 'vs',\n'vc', 'hi', 'ls', 'ge', 'lt'... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | extra/stack_analyzer: Fix cbz/cbnz and addr2line parsing.
Fix the cbz/cbnz operands parsing.
Parse the discriminator output of addr2line.
BUG=none
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
Change-Id: Iade1c14db0dc63fa65ef0f5df778b4f4f1e4f802
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/625498
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> |
136,407 | 24.08.2017 14:19:25 | 25,200 | 88abd3ee7284862fd7b76d251aabc4d79a735831 | zoombini: Add USB-A charge control support.
BRANCH=None
TEST=make -j buildall
Commit-Ready: Aseda Aboagye
Tested-by: Aseda Aboagye | [
{
"change_type": "MODIFY",
"old_path": "board/zoombini/board.c",
"new_path": "board/zoombini/board.c",
"diff": "@@ -100,6 +100,11 @@ const struct i2c_port_t i2c_ports[] = {\n};\nconst unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);\n+/* GPIO to enable/disable the USB Type-A port. */\n+const int... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | zoombini: Add USB-A charge control support.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I8ee0ec01d06343a158f4271e1f9ecdb3d8895659
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/634275
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org> |
136,274 | 24.08.2017 18:52:24 | 25,200 | 4fc9cf4c116d06153f7ab4a02533d4b5406248d3 | sweetberry: converter tool for servo_ina
convert_servo_ina.py can convert power log config
files from hdctools/servo/data into sweetberry configs
BRANCH=None
TEST=compare kevin_r0_loc.py output with kevin.board | [
{
"change_type": "MODIFY",
"old_path": "extra/usb_power/board.README",
"new_path": "extra/usb_power/board.README",
"diff": "@@ -8,6 +8,18 @@ a \".board\" file, and one describing the particular rails you want to\nmonitor in this session, a \".scenario\" file.\n+Converting from servo_ina configs:\n+\... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | sweetberry: converter tool for servo_ina
convert_servo_ina.py can convert power log config
files from hdctools/servo/data into sweetberry configs
BRANCH=None
BUG=b:35578707
TEST=compare kevin_r0_loc.py output with kevin.board
Change-Id: Iadc57fe4eb1f5b220c6bffe3a3fe8a10b0d6b5a2
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/634486 |
136,405 | 26.08.2017 17:39:42 | 25,200 | ff87bfac4e4883dff6076887f28358e2ea51b11e | EFS: Add error codes
This patch defines more error codes to make the consle more
descriptive.
BRANCH=none
TEST=Boot Fizz.
Commit-Ready: Daisuke Nojiri
Tested-by: Daisuke Nojiri | [
{
"change_type": "MODIFY",
"old_path": "common/vboot/common.c",
"new_path": "common/vboot/common.c",
"diff": "@@ -40,10 +40,8 @@ int vboot_verify(const uint8_t *data, int len,\nuint32_t *workbuf;\nint err = EC_SUCCESS;\n- if (shared_mem_acquire(3 * RSANUMBYTES, (char **)&workbuf)) {\n- CPRINTS(\"Fai... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | EFS: Add error codes
This patch defines more error codes to make the consle more
descriptive.
BUG=none
BRANCH=none
TEST=Boot Fizz.
Change-Id: I84cc6cd7f309bb2f2e1f36dea6cf5a7f0f862f50
Reviewed-on: https://chromium-review.googlesource.com/639160
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,405 | 24.08.2017 18:15:19 | 25,200 | 3dc0eae365305c84947fff5d1976e74d950b04e3 | EFS: Rename CONFIG_VBOOT_EC to _EFS
This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also
adds the macro to config.h.
BRANCH=none
TEST=make buidlall | [
{
"change_type": "MODIFY",
"old_path": "board/fizz/board.h",
"new_path": "board/fizz/board.h",
"diff": "#define I2C_ADDR_TCPC0 0x16\n/* Verify and jump to RW image on boot */\n-#define CONFIG_VBOOT_EC\n+#define CONFIG_VBOOT_EFS\n#define CONFIG_VBOOT_HASH\n#define CONFIG_VSTORE\n#define CONFIG_VSTORE... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | EFS: Rename CONFIG_VBOOT_EC to _EFS
This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also
adds the macro to config.h.
BUG=none
BRANCH=none
TEST=make buidlall
Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/639955
Reviewed-by: Randall Spangler <rspangler@chromium.org> |
136,197 | 29.08.2017 08:44:13 | -28,800 | 2777b7771e788a7c2205c907710b703c48efedc5 | presubmit_check: Check unittests results on extra/stack_analyzer
BRANCH=none
TEST=util/presubmit_check.sh | [
{
"change_type": "ADD",
"old_path": null,
"new_path": "extra/stack_analyzer/run_tests.sh",
"diff": "+#!/bin/bash\n+#\n+# Copyright 2017 The Chromium OS Authors. All rights reserved.\n+# Use of this source code is governed by a BSD-style license that can be\n+# found in the LICENSE file.\n+\n+# Disco... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | presubmit_check: Check unittests results on extra/stack_analyzer
BRANCH=none
BUG=none
TEST=util/presubmit_check.sh
Change-Id: I6078377603719de1d633660c69ad3a40b29ffadf
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/640191
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Che-yu Wu <cheyuw@google.com> |
136,432 | 30.08.2017 18:28:11 | 25,200 | 2c9dea11720b96d866785f81c1e0dc3bd206183e | ISH: added sleep mask for UART port
added UART sleep mask not to allow to enter into deep sleep.
BRANCH=master
Test='make -j buildall'
Commit-Ready: Kyoung Il Kim
Tested-by: Kyoung Il Kim | [
{
"change_type": "MODIFY",
"old_path": "chip/ish/uart.c",
"new_path": "chip/ish/uart.c",
"diff": "@@ -63,6 +63,9 @@ void uart_tx_start(void)\nif ( REG8(IER(id) & IER_TDRQ) )\nreturn;\n+ /* Do not allow deep sleep while transmit in progress */\n+ disable_sleep(SLEEP_MASK_UART);\n+\n/* TODO: disable l... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | ISH: added sleep mask for UART port
added UART sleep mask not to allow to enter into deep sleep.
BUG=None
BRANCH=master
Test='make -j buildall'
Change-Id: I15e55c2c94276da99339465f2ea577b1f94e1ce4
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/644848
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
136,197 | 30.08.2017 14:30:46 | -28,800 | 463aead11bab59dd6c15dd6f2954be4a6197d531 | usb_updater2: Add code to fetch touchpad information
BRANCH=none
TEST=./usb_updater2 -t | [
{
"change_type": "MODIFY",
"old_path": "extra/usb_updater/usb_updater2.c",
"new_path": "extra/usb_updater/usb_updater2.c",
"diff": "@@ -72,7 +72,7 @@ static struct first_response_pdu targ;\nstatic uint16_t protocol_version;\nstatic uint16_t header_type;\nstatic char *progname;\n-static char *short_o... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | usb_updater2: Add code to fetch touchpad information
BRANCH=none
BUG=b:63418037
TEST=./usb_updater2 -t
Change-Id: Ibed7cfc1d706f0f0ff8072f3ec08997f40a89038
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/593001
Reviewed-by: Chun-ta Lin <itspeter@chromium.org> |
136,432 | 14.06.2017 19:29:33 | 25,200 | 17bb1fbaa914c9631ef1e6e300050d47d4a116c4 | ISH: added UART port selection
added uart port debug selection.
in board.h, add "#define CONFIG_ISH_UART_0" for UART Port 0.
For port1, use "#define CONFIG_ISH_UART_1"
BRANCH=None
Test='make -j buildall'
Commit-Ready: Kyoung Il Kim
Tested-by: Kyoung Il Kim | [
{
"change_type": "MODIFY",
"old_path": "chip/ish/registers.h",
"new_path": "chip/ish/registers.h",
"diff": "@@ -72,6 +72,16 @@ enum ish_i2c_port {\n#define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ)\n#define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ)\n+#ifdef CONFIG_ISH_UART_0\n+#define ISH_DEBUG_UAR... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | ISH: added UART port selection
added uart port debug selection.
in board.h, add "#define CONFIG_ISH_UART_0" for UART Port 0.
For port1, use "#define CONFIG_ISH_UART_1"
BUG=None
BRANCH=None
Test='make -j buildall'
Change-Id: I5426b1d228ac715574e2ff4f28526232d375221f
Reviewed-on: https://chromium-review.googlesource.com/566593
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
136,197 | 28.08.2017 11:11:39 | -28,800 | 72252db3425a88f404f6d76eb15d02ace06747b7 | touchpad_elan: Discard zero finger clicks
Do not report click events when no finger is present on the touchpad.
BRANCH=none
TEST=Bend case, hear click, but no event reported in evtest. | [
{
"change_type": "MODIFY",
"old_path": "driver/touchpad_elan.c",
"new_path": "driver/touchpad_elan.c",
"diff": "@@ -154,13 +154,6 @@ static int elan_tp_read_report(void)\ntouch_info = tp_buf[ETP_TOUCH_INFO_OFFSET];\nhover_info = tp_buf[ETP_HOVER_INFO_OFFSET];\n- if (touch_info & 0x01)\n- report.butt... | C | BSD 3-Clause New or Revised License | coreboot/chrome-ec | touchpad_elan: Discard zero finger clicks
Do not report click events when no finger is present on the touchpad.
BRANCH=none
BUG=b:65098167
TEST=Bend case, hear click, but no event reported in evtest.
Change-Id: I0385213102dab0775e1b6906cb3a45933deac757
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/637288
Reviewed-by: Vincent Palatin <vpalatin@chromium.org> |
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