Search is not available for this dataset
content stringlengths 0 376M |
|---|
<reponame>DanielTRYTRYLOOK/RDF-2020
name: i2c_master_top
clock_port: wb_clk_i
verilog:
- i2c_master_defines.v
- i2c_master_bit_ctrl.v
- i2c_master_byte_ctrl.v
- i2c_master_top.v
|
src_list:
rtl:
- i2c_master_ctrl.vhd
- i2c_master_data.vhd
- i2c_master_top.vhd
tb:
- tb_pkg.vhd
- tb.vhd
submodules: null
sim:
top_name: tb
pat_in: pat_in.txt
pat_out: pat_out.txt
dut_out: dut_out.txt
pat_comp_script: null
fixed_cases:
- '00'
pat_gen_script: null
gener... |
ePixHr10kT:
enable: True
ForceWrite: False
InitAfterConfig: False
EpixHR:
enable: True
PacketRegisters0:
enable: True
ResetCounters: False
asicDataReq: 0x123f
DisableLane: 0x0
EnumerateDisLane: 0x0
PacketRegisters1:
enable: True
ResetCounters: False
as... |
<filename>azure-pipelines.yml
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Azure Pipelines CI build configuration
# Documentation at https://aka.ms/yaml
variables:
- template: ci/vars.yml
trigger:
batch: true
... |
<reponame>ka7/bat
---
# Simple example
id: 3595
name: <NAME>
username: "testuser"
other_names: ['Bob', 'Bill', 'George']
hexa: 0x11c3 #inline comment
octa: 021131
lastseen: .NAN
enabled: true
locked: false
groups:
- administrators
- engineering
- sfa
address: >
123 Alphabet Way
San Francisco, CA
bio: |
I ... |
<filename>.github/workflows/docs.yml
name: docs
on:
push:
branches:
- master
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Build sphinx doc
uses: ammaraskar/sphinx-action@master
with:
docs-folder: "docs/"
pre-buil... |
package:
name: ariane
authors: [ "<NAME> <<EMAIL>>" ]
dependencies:
axi: { git: "<EMAIL>:sasa/axi.git", rev: master }
axi2per: { git: "<EMAIL>:pulp-open/axi2per.git", rev: master }
axi_mem_if: { git: "<EMAIL>:pulp-platform/axi_mem_if.... |
<filename>.travis.yml
language: bash
install:
- source ./.travis/setup.sh
script:
- git push <EMAIL>:build "$BRANCH_NAME"
notifications:
email:
- <EMAIL>
irc:
channels:
- "chat.freenode.net#hdmi2usb"
- "chat.freenode.net#timvideos"
template:
... |
package:
name: axi_mem_if
authors: [ "<NAME> <<EMAIL>>"]
dependencies:
axi: { git: "<EMAIL>:sasa/axi.git", rev: master }
sources:
- src/axi2mem.sv
- src/deprecated/axi_mem_if.sv
- src/deprecated/axi_mem_if_var_latency.sv
- src/deprecated/axi_mem_if_wrap.sv
|
<filename>src_files.yml
apb_spi_master:
files: [
apb_spi_master.sv,
spi_master_apb_if.sv,
spi_master_clkgen.sv,
spi_master_controller.sv,
spi_master_fifo.sv,
spi_master_rx.sv,
spi_master_tx.sv,
]
|
<filename>.github/workflows/riscv-arch-test.yml
# Run the RISC-V riscv-arch-test test framework port to check current NEORV32 version
name: 'riscv-arch-test'
on:
workflow_dispatch:
jobs:
build:
runs-on: ubuntu-latest
name: '🐧 Ubuntu-Latest'
steps:
- name: '🧰 Repository Checkout'
us... |
PROJECT:
dt: 0.1e-6
board_name: PYNQ_Z1
plugins: ['msdsl']
emu_clk_freq: 10e6
cpu_debug_mode: true
cpu_debug_hierarchies: [[0, 'top']] |
# This file defines single architecture set for tlut systolic array performance projection
- proj_16_16_bank4_block8
- proj_32_32_bank4_block8
- proj_64_64_bank4_block8
- proj_128_128_bank4_block8
|
runtime: nodejs12
service: log-me-in
env_variables:
DB_USER: ctf
DB_PASS: ""
DB_NAME: ctf
INSTANCE_CONNECTION_NAME: put your instance here
|
<reponame>DaveMcEwan/svdata
---
modules:
- identifier: TestModule
parameters: []
ports:
- identifier: a
direction: Inout
datakind: Net
datatype: Logic
classid: ~
nettype: Wire
signedness: Unsigned
- identifier: b
direction: Inout
data... |
ip:
name: "uvme_mio_cli_st"
version: "1.0.0 Beta 0"
full-name: "Moore.io CLI Testing Grounds UVM Environment"
type: "DV"
sub-type: "UVM Environment"
sub-sub-type: "Agent Self-Testing"
description: >
UVM Environment used for development of Moore.io CLI. NOT meant for use in actual DV work.
home-page... |
<reponame>icgrp/doblink
"3200":
arch: "artix7_200t"
device_family: "xc7a200t"
device_name: "fig2-3200"
device_speed: "ffg1156-1"
device: "xc7a200t-fig2-3200-roi-virt"
board: "nexys_video"
timeout: 400 |
<filename>hw/vendor/lowrisc_opentitan/uart/Bender.yml
package:
name: lowrisc_uart
description: "lowRISC UART"
authors: ["lowRISC Contributors"]
dependencies:
lowrisc_prim: {path: ../prim}
sources:
- rtl/uart_reg_pkg.sv
- rtl/uart_reg_top.sv
- rtl/uart_rx.sv
- rtl/uart_tx.sv
- rtl/uart_core.sv
- rtl/uart.sv
|
<filename>.github/workflows/test.yml
name: Test
on:
push:
branches:
- develop
pull_request:
env:
ARROW_VERSION: '3.0.0'
jobs:
cpp:
name: 'C++'
strategy:
fail-fast: false
matrix:
source:
- codegen/cpp/fletchgen
- runtime/cpp
- platforms/echo/runtime
... |
<gh_stars>100-1000
name: C/C++ CI
on:
push:
paths-ignore:
- '.github/workflows/trigger-update.yml'
branches: [master]
pull_request:
branches: [master]
paths-ignore:
- '.github/workflows/trigger-update.yml'
jobs:
build:
runs-on: ubuntu-20.04
strategy:
matrix:
buil... |
name: CVA6 Task
description: Create a CVA6-SDK Project Task
title: "[TASK] <title>"
labels: ["task"]
body:
- type: checkboxes
attributes:
label: Is there an existing CVA6-SDK task for this?
description: Please search to see if a task issue already exists for the task you need to create
options:
- labe... |
AWSTemplateFormatVersion: '2010-09-09'
Parameters:
KeyPairParameter: # EC2インスタンスにSSHでログインする時のキーペアの名前
Type: String
GitRepoURL:
Type: String
Default: https://github.com/aws/aws-fpga.git
Resources:
F1DevVPC: # VPCを作成して、F1インスタンス作業専用のCloud環境を作成する。
Type: AWS::EC2::VPC
Properties:
CidrBlock: 1... |
---
name: decimator
board: boards/red-pitaya
version: 0.1.1
cores:
- fpga/cores/redp_adc_v1_0
- fpga/cores/redp_dac_v1_0
- fpga/cores/axi_ctl_register_v1_0
- fpga/cores/axi_sts_register_v1_0
- fpga/cores/dna_reader_v1_0
memory:
- name: control
offset: '0x60000000'
range: 4K
- name: status
of... |
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: reqrsp_interface
authors:
- <NAME> <<EMAIL>>
- <NAME> <<EMAIL>>
dependencies:
common_cells: {path: ../../vendor/pulp_platform_common_c... |
runners:
AWS-runner:
image: ubuntu-vitis-2020-1
jobs:
build_run_sim:
runner: AWS-runner
type:
build: hardware
current_working_directory: /tools/Xilinx/Vivado/2020.1/workspace/project_ci_sim
output:
artifact:
- ./project_ci_sim.xpr
- ./project_ci_sim.cache
- ./project_ci_sim.hw
- ./... |
# Copyright 2021 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, ... |
<reponame>BearerPipelineTest/google-ctf<gh_stars>1000+
# Human readable task name
name: abc arm and amd
# Long form description.
description: |+
Provide a payload that prints the contents of the 'flag' file and runs on both
x86-64 and arm64v8.
The payload may only contain bytes in the range [0x20, 0x7F] and cann... |
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
<reponame>ess-dmsc/dmg-build-scripts
---
- hosts: data-generators
gather_facts: False
tasks:
- name: stop data generators
command: "killall datagen_multigrid.bash mggen_readouts"
ignore_errors: True
tags:
- multigrid
|
---
# Copyright 2021 Datum Technology Corporation
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
########################################################################################################################
# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file e... |
language: c
compiler: gcc
before_install:
- sudo apt-get update -qq
- sudo apt-get install -qq libpng-dev libjpeg-dev libatlas-base-dev libblas-dev libgsl0-dev
script:
- cd Design/Test/
# Simulatin Testing on remote centos qloud server
# - cd Simulation/ && make && make clean && make test
- cd U... |
sudo: false
language: java
jdk:
- openjdk7
- oraclejdk8
git:
submodules: false
script: ant build
|
<reponame>Koheron/koheron-sdk
---
name: peak_detector
board: boards/red-pitaya
control_registers:
- peak_address_low
- peak_address_high
- peak_address_reset
status_registers:
- peak_address
- peak_maximum
cores:
- fpga/cores/comparator_v1_0
parameters:
wfm_width: 8
|
<filename>.github/workflows/manylinux.yml
name: Manylinux
on:
push:
tags:
- 'v*.*.*'
jobs:
deploy:
strategy:
matrix:
os: [ubuntu-latest]
python-version: [3.7]
rust-version: [stable]
runs-on: ${{ matrix.os }}
steps:
- name: Checkout
uses: actions/chec... |
# RUN: lld -flavor darwin -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/libSystem.yaml && llvm-objdump -private-headers %t | FileCheck %s
# RUN: lld -flavor darwin -arch x86_64 -macosx_version_min 10.8 %s -o %t -dylib %p/Inputs/libSystem.yaml -static -data_in_code_info && llvm-objdump -private-headers... |
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: future
dependencies:
axi: {path: ../../vendor/pulp_platform_axi}
common_cells: {path: ../../vendor/pulp_platform_common_cells}
sources:
#... |
<reponame>Calculasians/HDC-Sensor-Fusion-Research
sim.inputs.top_module: "hdc_sensor_fusion"
sim.inputs.tb_dut: "dut"
sim.inputs.tb_name: "hdc_sensor_fusion_tb"
sim.inputs.input_files_meta: "append"
sim.inputs.input_files:
- "src/HDC_Sensor_Fusion_FoldedRule90/hdc_sensor_fusion.sv"
- "src/HDC_Sensor_Fusion_Folde... |
# This file defines single architecture set for tlut systolic array performance projection
- proj_16_16_bank16_block16
- proj_32_32_bank16_block16
- proj_64_64_bank16_block16
- proj_128_128_bank16_block16
|
<filename>rtl/generic_FLL/src_files.yml
fll:
flags: [
skip_synthesis,
]
files : [
fe/model/gf22_DCO_model.tc.vhd,
fe/model/gf22_FLL_model.vhd,
fe/rtl/FLLPkg.vhd,
fe/rtl/FLL_clk_divider.vhd,
fe/rtl/FLL_clk_period_quantizer.vhd,
fe/rtl/FLL_clock_gated.rtl.vhd,
fe/rtl/FLL_digital.vhd,... |
<filename>rtl/tb/src_files.yml
tb:
files: [
jtag_pkg.sv,
dbg_pkg.sv,
tb_clk_gen.sv,
tb_fs_handler.sv,
dev_dpi/dev_dpi.sv,
tb_pulp.sv,
]
|
udma_uart:
files: [
rtl/udma_uart_reg_if.sv,
rtl/udma_uart_top.sv,
rtl/udma_uart_rx.sv,
rtl/udma_uart_tx.sv,
]
|
stages:
- uhd
- gnuradio
- fpga
.conditionals: &conditionals
refs:
- master
- branches
- web
.uhd-build: &uhd-build
- mkdir build
- cd build
- cmake ../ -DENABLE_UHD=1 -DENABLE_GNURADIO=0
- make -j10
.gnuradio-build: &gnuradio-build
- mkdir build
- cd build
- cmake ../ -DENABLE_UHD=... |
sim.inputs.top_module: "hdc_sensor_fusion"
sim.inputs.tb_dut: "dut"
sim.inputs.tb_name: "hdc_sensor_fusion_tb"
sim.inputs.input_files_meta: "append"
sim.inputs.input_files:
- "src/HDC_Sensor_Fusion_SEFUAMFoldedRule90/hdc_sensor_fusion.sv"
- "src/HDC_Sensor_Fusion_SEFUAMFoldedRule90/hdc_sensor_fusion_tb.sv"
- ... |
<reponame>Calculasians/HDC-Sensor-Fusion-Research<gh_stars>0
sim.inputs.top_module: "hdc_sensor_fusion"
sim.inputs.tb_dut: "dut"
sim.inputs.tb_name: "hdc_sensor_fusion_tb"
sim.inputs.input_files_meta: "append"
sim.inputs.input_files:
- "src/SEFUAM_Channel_Count_Experiment/hdc_sensor_fusion.sv"
- "src/SEFUAM_Chan... |
<filename>examples/afe/clks.yaml
derived_clks:
tb_emu_io:
abspath: 'tb_i'
emu_clk: 'emu_clk'
emu_rst: 'emu_rst'
emu_dt: 'emu_dt'
dt_req: 'dt_req'
# ext_dt:
# abspath: 'tb_i'
# dt_req: 'ext_dt' |
jobs:
- smoke:
variables:
- GTEST_FILTER: TblinkRpcHdlTestBase.smoke
- single_time_cb:
variables:
- GTEST_FILTER: TblinkRpcHdlTestBase.single_time_cb
- dual_layer_time_cb:
variables:
- GTEST_FILTER: TblinkRpcHdlTestBase.dual_layer_time_cb
|
<reponame>Hog-CERN/Hog
# Copyright 2018-2021 The University of Birmingham
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Un... |
###############################################################################
## Configuration file for generation of Documentation of CTU CAN FD.
## This configuration file determines content of documentation that will be
## generated. Two types are possible:
## IP (skip_conditional = false)
## ASIC (skip_condit... |
sim.inputs.top_module: "hdc_sensor_fusion"
sim.inputs.tb_dut: "dut"
sim.inputs.tb_name: "hdc_sensor_fusion_tb"
sim.inputs.input_files_meta: "append"
sim.inputs.input_files:
- "src/HDC_Sensor_Fusion_3M1P/hdc_sensor_fusion.sv"
- "src/HDC_Sensor_Fusion_3M1P/memory_wrapper.sv"
- "src/HDC_Sensor_Fusion_3M1P/hdc_s... |
---
algorithm:
class: Alps
population_size: 2000
elite_size: 20
max_layers: 5
aging_scheme: :fibonacci
age_gap: 10
duplicate_elimination: true
layer_diagnostic: true
probabilities:
crossover: 0.9
mutation: 0.01
init:
method: grow # grow or full or random or ramped
random_len... |
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
<reponame>koenenwmn/optimsoc
---
title: '\protect{Open SoC Debug -- \\ Core Debug Module based on the Advanced Debug System}'
author:
date: work-in-progress
---
|
<reponame>hprice99/ENGG4811_code
---
charIo:
- name: char
direction: output
width: 8
- name: char_output_ready
direction: input
width: 8
peToNetworkIo:
ledIo:
- name: led
direction: output
width: 8
networkToPeIo:
nodeIo:
- name: matrix_init_from_file
direction: input
width: 8... |
#template_tql < $RDI_TEMPLATES/sdx/sdaccel/swhw/template.tql
description: testinfo generated using import_sdx_test.py script
level: 6
owner: soeren
user:
allowed_test_modes: [hw]
force_makefile: "--force"
host_args: {all: -k kernel.xclbin --jobs 1024 --seconds 1 --cus 8 --ert}
host_cflags: ' -DDSA64 -ldl -luuid... |
<filename>sample/pid/aht.yaml
---
algorithm:
class: AgeHierarchyTree
deme_size: 200
elite_size: 5
max_layers: 7
aging_scheme: :fibonacci
age_gap: 13
layer_diagnostic: true
probabilities:
crossover: 0.9
mutation: 0.01
init:
method: ramped # grow or full or random or ramped
sens... |
<gh_stars>0
# ////////////////////////////////////////////////////////////////////////////////////////
# Copyright (c) by
# Company: IDEA LAB, The University of Texas at Dallas
# Author : <NAME>
#
# Originally Create Date: Mar-5, 2020
# Project Name : DNN_Framework
# Tool Versions : Python +3
#
# Description ... |
<reponame>QuickLogic-Corp/tech_cells_generic<filename>src_files.yml
tech_cells_rtl:
flags: [
skip_synthesis,
]
files: [
src/deprecated/cluster_clk_cells.sv,
src/deprecated/cluster_pwr_cells.sv,
src/deprecated/generic_memory.sv,
src/deprecated/generic_rom.sv,
src/deprecated/pad_functional.s... |
<reponame>till-s/slac-dev-board-examples
- mmio/AmcCarrierCore/AmcCarrierTiming:
- TPGMiniCore/TxPolarity: !<value> 1
- TPGMiniCore/TxLoopback: !<value> 0
- i2c-2/Si5344:
- FORCE_HOLD: !<value> 0
- mmio/AmcCarrierCore/AmcCarrierTiming:
- EvrV2CoreTriggers:
- EvrV2ChannelReg/DestSelMode: !<value>... |
dist: focal
language: c
compiler: gcc
matrix:
include:
- script:
- mkdir .build && cd .build && cmake .. -DCMAKE_BUILD_TYPE=Debug -DOPAE_ENABLE_MOCK=ON -DOPAE_BUILD_TESTS=ON
- make
- ctest --timeout 180
before_script:
- sudo sysctl -w vm.nr_hugepages=8
cache: ccache
env:
- CTEST_OUTP... |
top_module: alu
repo_name: alu
core_dir: ../../examples/alu
working_dir: tb/verilator/
rtl_dirs:
- rtl
- rtl/unitblocks
parse_args: ''
verif_tools_path: ../../
verilator_args: ''
|
# Copyright 2021 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, ... |
<reponame>QueenField/MPSoC-WB-OR1K<filename>software/glip/src/common/logic/fifo/test/test_fifo_dualclock_standard.manifest.yaml
module: test_fifo_dualclock_standard
sources:
- ../verilog/fifo_dualclock_standard.sv
toplevel: fifo_dualclock_standard
simulators:
- vcs
parameters:
WIDTH: 16
DEPTH: 32
|
# Copyright 2020 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Build Docker image and publish to pulp-platform's GHCR.
name: build-docker
on:
push:
branches:
- master
jobs:
build-docker:
runs-on: ... |
ip:
name: "uvmt_mio_cli_st"
version: "1.0.0 Beta 0"
full-name: "Moore.io CLI Testing Grounds UVM Test Bench"
type: "DV"
sub-type: "UVM Test Bench"
sub-sub-type: "Agent Self-Testing"
description: >
UVM Test Bench used for development of Moore.io CLI. NOT meant for use in actual DV work.
home-page: "... |
language: c
before_install:
- sudo apt-get -qq update
# luajit
- sudo apt-get install luajit
# z3
- if [[ $TARGET = "verilatorSOC" ]] || [[ $TARGET = "terra" ]]; then wget https://github.com/Z3Prover/z3/releases/download/z3-4.7.1/z3-4.7.1-x64-ubuntu-14.04.zip; fi
- if [[ $TARGET = "verilatorSOC" ]] || [[... |
# Copyright 2020 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: publish-docs
on:
push:
branches:
- master
jobs:
deploy:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- u... |
quick_check:kc705_basex__2020.2:
extends: .template_vivado_quick_check
variables:
VIVADO_VERSION: "2020.2"
PROJ: kc705_basex
quick_check:kc705_basex__2019.2:
extends: .template_vivado_quick_check
variables:
VIVADO_VERSION: "2019.2"
PROJ: kc705_basex
quick_check:kc705_gmii__2020.2:
extends: .t... |
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
---
title: '\protect{Open SoC Debug -- \\ Memory Mapped I/O Bridge}'
author:
date: work-in-progress
---
|
# Test build the MoveIt! tutorials. Author: <NAME>
sudo: required
dist: trusty
language: ruby
rvm:
- 2.4
python:
- "2.7"
compiler:
- gcc
before_install: # Use this to prepare the system to install prerequisites or dependencies
# Define some config vars
- export NOKOGIRI_USE_SYSTEM_LIBRARIES=true
- export C... |
# Adapted from Garnet and ButterPHY
name: input_buffer
commands:
- |
mkdir -p outputs
tar -xzvf /home/sjkim85/dragonphy_tarballs/input_buffer-latest.tar.gz -C outputs
outputs:
- input_buffer.lef
- input_buffer.gds
- input_buffer.spi
- input_buffer.version
|
<reponame>rsarwar87/koheron-sdk
version: 2
jobs:
build:
docker:
- image: circleci/python:2.7-stretch-browsers
- image: circleci/node:10.11.0-stretch-browsers
steps:
- checkout
- run:
name: Append dev to source.list
command: sudo bash -c "echo deb http://archive.ubu... |
<reponame>ruck314/dev-board-misc-utils<gh_stars>0
##############################################################################
## This file is part of 'dev-board-misc-utils'.
## It is subject to the license terms in the LICENSE.txt file found in the
## top-level directory of this distribution and at:
## https://... |
<reponame>FelixLuciano/Elements-of-Computing-Systems
# This workflow will install Python dependencies, run tests and lint with a single version of Python
# For more information see: https://help.github.com/actions/language-and-framework-guides/using-python-with-github-actions
name: Teste
on:
push:
branches: [ ma... |
<gh_stars>10-100
soc_interconnect:
files: [
RTL/l2_tcdm_demux.sv,
RTL/lint_2_apb.sv,
RTL/lint_2_axi.sv,
RTL/axi_2_lint/axi64_2_lint32.sv,
RTL/axi_2_lint/axi_read_ctrl.sv,
RTL/axi_2_lint/axi_write_ctrl.sv,
RTL/axi_2_lint/lint64_to_32.sv,
RTL/XBAR_L2/AddressDecoder_Req_L2.sv,
RTL/XBA... |
cache_root_dir: /usr/scratch2/dolent1/gitlabci/buildcache/ara
artifacts:
tc-gcc:
inputs:
- Makefile
- toolchain/riscv-gnu-toolchain
outputs:
- install/riscv-gcc
tc-verilator:
inputs:
- Makefile
- toolchain/verilator
outputs:
- install/verilator
tc-isa-sim:
... |
package:
name: pytblink-rpc
version: None
deps:
- name: tblink-rpc-core
url: https://github.com/tblink-rpc/tblink-rpc-core.git
dev-deps:
- name: tblink-rpc-core
url: https://github.com/tblink-rpc/tblink-rpc-core.git
|
<filename>models/AI-Model-Zoo/model-list/pt_personreid-res18_market1501_176_80_1.1G_2.0/model.yaml<gh_stars>1-10
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
... |
<filename>2021/quals/pwn-atheris/challenge.yaml
apiVersion: kctf.dev/v1
kind: Challenge
metadata:
name: atheris
spec:
deployed: true
powDifficultySeconds: 0
network:
public: true
healthcheck:
# TIP: disable the healthcheck during development
enabled: true
|
<reponame>abs-tudelft/vhlib<gh_stars>1-10
resources:
repositories:
- repository: abs-tudelft
type: github
endpoint: github
name: abs-tudelft/azure-pipelines-templates
jobs:
- template: jobs/vhdeps.yml@abs-tudelft
parameters:
sources: ['sim', 'stream', 'util']
|
- Global:
Print : true
- Library:
Name : merge_sorter
Format : "#{File.basename(file_name,\".vhd\")}.o : #{file_name} #{@use_list.map{|u|File.basename(u.file_name,\".vhd\")+\".o\"}.join(\" \")}\n\tghdl -a -C $(GHDLFLAGS) --work=#{library_name} #{file_name}\n\n"
PathList :
- "../../..... |
package:
name: udma_camera
authors:
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
dependencies:
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
udma_core: { git: "https://githu... |
#template_tql < $RDI_TEMPLATES/sdx/sdaccel/swhw/template.tql
description: testinfo generated using import_sdx_test.py script
level: 6
owner: sonals
user:
allowed_test_modes: [sw_emu, hw_emu, hw]
force_makefile: "--force"
host_args: {all: -d acc}
host_cflags: ' -DDSA64'
host_exe: host.exe
host_src: main.cpp ... |
<filename>server/src/test/deployments/federated_basic_sql/provider1/configuration.yml
hosts:
provider1_machine:
processes:
main_instance:
components:
core:
config_file: core_config.py
type: core
experiment_dummy1:
class: experiments.dummy.Dummy... |
---
name: make release
on:
push:
tags: ["d*.*.*"]
jobs:
build:
runs-on: ubuntu-latest
timeout-minutes: 60
env:
BOOTSTRAP: https://github.com/modula3/cm3/releases/download/d5.11.4/cm3-boot-AMD64_LINUX-d5.11.4.tar.xz
steps:
- name: Install prerequisites
run: |
sudo apt... |
<filename>.travis.yml
dist: trusty
sudo: required
language: bash
before_install:
- sudo apt-add-repository "deb http://archive.ubuntu.com/ubuntu trusty-backports main restricted universe multiverse"
- sudo apt-get -qq update
- sudo apt-get install gperf -y
- wget https://sourceforge.net/projects/iverilog/fil... |
name: CI
on: [push]
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v1
- name: Install verilator
run: sudo apt-get install verilator
- name: Install fusesoc
run: |
sudo pip install fusesoc
fusesoc init -y
- name: Setup project
... |
<filename>models/AI-Model-Zoo/model-list/cf_face-quality_80_60_61.68M_2.0/model.yaml
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.or... |
<reponame>PrincetonUniversity/prga
context: ../../../../fpga/magic/grady18v2_N10_mem32Kb_42x34/ctx.pkl
compiler: vcs
app:
name: picorv32_axi
sources:
- ../../src/picorv32.v
parameters:
COMPRESSED_ISA: 1
ENABLE_MUL: 1
ENABLE_FAST_MUL: 1
ENABLE_DIV: 1
ENABLE_IRQ... |
---
algorithm:
class: MuLambda
comma_or_plus: comma
population_size: 500
lambda_size: 600
elite_size: 10
probabilities:
crossover: 0.9
mutation: 0.01
injection: 0.9
termination:
max_steps: 2000
on_individual: :stopping_condition
init:
method: ramped # grow or full or random... |
<reponame>bluetiger9/Vitis-AI
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicabl... |
main:
- title: GitHub
url: https://github.com/PrincetonUniversity/prga
- title: Documentation
url: https://prga.readthedocs.io
- title: Publications
url: /publications.html
|
<filename>.github/workflows/test.yml
name: Dynamic Scheduler Tests
on: push
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
with:
submodules: 'recursive'
fetch-depth: 0
clean: false
- name: Install dependencies
run: |
sudo apt-get... |
---
charIo:
- name: char
direction: output
width: 8
- name: char_output_ready
direction: input
width: 8
peToNetworkIo:
- name: message_out_ready
direction: input
width: 8
- name: x_coord
direction: output
width: 8
- name: y_coord
direction: output
width: 8
- name: mu... |
language: c
compiler: clang
before_script: cd code
script:
- make clean
- make
- ./test
|
<gh_stars>1-10
package:
name: cluster_interconnect
dependencies:
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 }
workspace:
checkout_dir: "./deps"
export_include_dirs:
- rtl/low_latency_interco
- rtl/peripheral_interco
sources:
# Source files grouped in levels... |
<filename>ultra96/ROOT_FS/app/fad/data/ConstraintGenerator/TrafficLightDetector/param.yaml
%YAML 1.2
---
TrafficLight:
opencv_tm_method: 5 # CV_TM_SQDIFF = 0, CV_TM_SQDIFF_NORMED = 1, CV_TM_CCORR = 2, CV_TM_CCORR_NORMED = 3, CV_TM_CCOEFF = 4, CV_TM_CCOEFF_NORMED = 5
red_tl_haar_like_cascade_file_path: "/data/Con... |
<filename>models/AI-Model-Zoo/model-list/pt_person-orientation_224_112_558M_2.0/model.yaml
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apa... |
<reponame>lavanyajagan/cocotb<filename>.github/workflows/lint.yml
# Copyright cocotb contributors
# Licensed under the Revised BSD License, see LICENSE for details.
# SPDX-License-Identifier: BSD-3-Clause
name: Lint
on:
pull_request:
branches:
- master
- 'stable/**'
jobs:
lint-pre-commit:
ru... |
hwpe-stream:
vlog_opts: [
+nowarnSVCHK,
]
incdirs: [
rtl,
]
files: [
rtl/hwpe_stream_package.sv,
rtl/hwpe_stream_interfaces.sv,
rtl/basic/hwpe_stream_assign.sv,
rtl/basic/hwpe_stream_mux_static.sv,
rtl/basic/hwpe_stream_demux_static.sv,
rtl/basic/hwpe_stream_buffer.sv,
rtl/... |
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