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module SmallFilters2nd_tb ();
parameter K0_SHIFT = 6; ///< K0 filter term = 2^-K0_SHIFT
parameter K1_SHIFT = 6; ///< K1 filter term = 2^-K1_SHIFT
parameter WIDTH = 16; ///< Width of data path
parameter CLAMP = 1; ///< Set to 1 to clamp the accumulators
parameter FREQ_RATE = ;
reg clk;
reg rst;
reg en;
reg signed [WIDTH-1:0] dataInCos;
reg signed [WIDTH-1:0] dataInSin;
wire signed [WIDTH-1:0] lpfSin;
wire signed [WIDTH-1:0] lpfCos;
wire signed [WIDTH-1:0] hpfSin;
wire signed [WIDTH-1:0] hpfCos;
wire signed [WIDTH-1:0] bpfSin;
wire signed [WIDTH-1:0] bpfCos;
wire signed [WIDTH-1:0] bsfSin;
wire signed [WIDTH-1:0] bsfCos;
integer i;
integer lpfMag;
integer hpfMag;
integer bpfMag;
integer bsfMag;
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
dataInCos = 'd0;
dataInSin = 'd0;
#2 rst = 1'b0;
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) dataInCos = $rtoi($cos($itor(i)**2*3.14159/FREQ_RATE)*(2**(WIDTH-2)-1));
dataInSin = $rtoi($sin($itor(i)**2*3.14159/FREQ_RATE)*(2**(WIDTH-2)-1));
end
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) dataInCos = $random();
@(posedge clk) dataInSin = $random();
end
$stop();
end
always #1 clk = ~clk;
always @(posedge clk) begin
lpfMag = (((lpfSin*lpfSin + lpfCos*lpfCos)));
hpfMag = (((hpfSin*hpfSin + hpfCos*hpfCos)));
bpfMag = (((bpfSin*bpfSin + bpfCos*bpfCos)));
bsfMag = (((bsfSin*bsfSin + bsfCos*bsfCos)));
end
/*****************************************************************************/
// Low Pass Filters
/*****************************************************************************/
SmallLpf2nd #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uutLpfSin (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataInSin), ///< [WIDTH-1:0] Filter input
.dataOut(lpfSin) ///< [WIDTH-1:0] Filter output
);
SmallLpf2nd #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uutLpfCos (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataInCos), ///< [WIDTH-1:0] Filter input
.dataOut(lpfCos) ///< [WIDTH-1:0] Filter output
);
/*****************************************************************************/
// High Pass Filters
/*****************************************************************************/
SmallHpf2nd #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uutHpfSin (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataInSin), ///< [WIDTH-1:0] Filter input
.dataOut(hpfSin) ///< [WIDTH-1:0] Filter output
);
SmallHpf2nd #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uutHpfCos (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataInCos), ///< [WIDTH-1:0] Filter input
.dataOut(hpfCos) ///< [WIDTH-1:0] Filter output
);
/*****************************************************************************/
// Band Pass Filters
/*****************************************************************************/
SmallBpf #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uutBpfSin (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataInSin), ///< [WIDTH-1:0] Filter input
.dataOut(bpfSin) ///< [WIDTH-1:0] Filter output
);
SmallBpf #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uutBpfCos (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataInCos), ///< [WIDTH-1:0] Filter input
.dataOut(bpfCos) ///< [WIDTH-1:0] Filter output
);
/*****************************************************************************/
// Band Stop Filters
/*****************************************************************************/
SmallBsf #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uutBsfSin (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataInSin), ///< [WIDTH-1:0] Filter input
.dataOut(bsfSin) ///< [WIDTH-1:0] Filter output
);
SmallBsf #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uutBsfCos (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataInCos), ///< [WIDTH-1:0] Filter input
.dataOut(bsfCos) ///< [WIDTH-1:0] Filter output
);
endmodule
|
module vcache(/*AUTOARG*/
// Outputs
rgb, hsync, vsync, wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o,
wb_sel_o, wb_dat_o,
// Inputs
wb_clk_i, wb_rst_i, vga_clk, wb_ack_i, wb_err_i, wb_rty_i,
wb_dat_i
);
input wire wb_clk_i;
input wire wb_rst_i;
input wire vga_clk;
output [7:0] rgb;
output hsync; // From vga0 of vga.v
output vsync; // From vga0 of vga.v
//input wire wb_m0_vcache_gnt;
input wire wb_ack_i; // normal termination
input wire wb_err_i; // termination w/ error
input wire wb_rty_i; // termination w/ retry
input wire [31:0] wb_dat_i; // input data bus
output wb_cyc_o; // cycle valid output
output [31:0] wb_adr_o; // address bus outputs
output wb_stb_o; // strobe output
output wb_we_o; // indicates write transfer
output [3:0] wb_sel_o; // byte select outputs
output [31:0] wb_dat_o; // output data bus
wire [9:0] x;
wire [9:0] y;
wire ve;
parameter vram_adr_base = 'hf80000;
//wire rd_en;//, wr_en;
//wire full, almost_full, empty, almost_empty;
//assign rgb = ve? x / 2 + y / 2 : 0;
wire [7:0] dout_rgb;
assign rgb = ve ? dout_rgb : 0;
// assign rd_en = ve
// || (0 && x >= 480 && x <= 483) && (!(|y[2:0]) && y[3]) || (0 && x >= 480 && x <= 484) && (!(|y[2:0]) && !y[3])
// ;
assign wb_sel_o = 4'b1111;
assign wb_we_o = 0;
/* reg write_start;
reg wea;
wire web = 0;
reg ena;
reg [7:0] addra;
wire [31:0] douta;
always @(posedge wb_clk_i) begin
if( (y >= -1 || y <= 478) && x == 300) begin
write_start <= 1;
end
if(write_start) begin
ena <= 1;
wb_cyc_o <= 1;
wb_stb_o <= 1;
if (wb_ack_i) begin
wea <= 1;
addra <= addra + 1;
counter <= counter + 1;
end
else begin
wea <= 0;
end
if (addra == 'd190) begin
wb_cyc_o <= 0;
wb_stb_o <= 0;
write_start <= 0;
ena <= 0;
end
end
if(y == 480) begin
counter <= 0;
end
end
line_buffer call_me_a_fifo (
.clka(wb_clk_i), // input clka
.wea(wea), // input [0 : 0] wea
.ena(!ve),
.addra(addra), // input [7 : 0] addra
.dina(wb_dat_i), // input [31 : 0] dina
.douta(douta), // output [31 : 0] douta
.clkb(vga_clk), // input clkb
.web(web), // input [0 : 0] web
.enb(ve),
.addrb(x[9:0]), // input [9 : 0] addrb
.dinb(8'b0), // input [7 : 0] dinb
.doutb(dout_rgb) // output [7 : 0] doutb
);*/
`define FILL 1
`define IDLE 0
reg state;
reg [16:0] counter, counter_line;
assign wb_adr_o = vram_adr_base + (counter_line + counter) * 4;
assign wb_cyc_o = (state == `IDLE)? 0 : 1;
assign wb_stb_o = ((state == `IDLE)? 0 : 1) & !wb_ack_i;
always @(posedge wb_clk_i) begin
if (wb_ack_i) begin
if (counter_line == 159) begin
state <= `IDLE;
counter_line <= 0;
counter <= counter + 160;
end
else begin
counter_line <= counter_line + 1;
end
end
if (y >= 0 && y < 480) begin
case(state)
`IDLE: begin
if (newline) state <= `FILL;
end
`FILL: begin
end
endcase
end
else begin
counter <= 0;
counter_line <= 0;
end
end
/* assign fifo_rst = ((y == 'd479) && (x == 'd640)) || ((y == 'd479) && (x == 'd641));
`define FILL 0
`define IDLE 1
reg fifo_state;
wire fill_req;
reg [16:0] counter, counter_line;
assign wb_adr_o = vram_adr_base + (counter_line + counter) * 4;
always @(posedge wb_clk_i) begin
if (fifo_rst) begin
counter <= 0;
counter_line <= 0;
end
else begin
if (wb_ack_i) begin
if (counter_line == 'd159) begin
counter_line <= 0;
if (counter == 0) counter <= counter + 'd159;
else counter <= counter + 'd160;
end
else begin
counter_line <= counter_line + 1;
end
end
end
case (fifo_state)
`IDLE: begin
if(
!hsync && y >= 0 && y < 480
// prog_empty //256depth 162prog_full 62prog_empty
) begin
fifo_state <= `FILL;
wb_cyc_o <= 1;
wb_stb_o <= 1;
end
else begin
wb_cyc_o <= 0;
wb_stb_o <= 0;
end
end
`FILL: begin
if (counter_line != 159) begin
wb_cyc_o <= 1;
wb_stb_o <= 1;
end
else begin
fifo_state <= `IDLE;
wb_cyc_o <= 0;
wb_stb_o <= 0;
end
end
endcase
// if(prog_empty & !prog_full) begin
// wb_cyc_o <= 1;
// wb_stb_o <= 1;
// end
// else begin
// wb_cyc_o <= 0;
// wb_stb_o <= 0;
// end
end
*/
//F**k yourself, use fifo
wire line_rst = x == 'd640;
wire newline, newfield;
vcache_fifo fifo0 (
.wr_clk(wb_clk_i), // input wr_clk
.rd_clk(vga_clk), // input rd_clk
.rst(x == 640 || newfield),
// .rst(fifo_rst),
.din(wb_dat_i),
// .din({wb_dat_i[23:16], wb_dat_i[31:24], wb_dat_i[7:0], wb_dat_i[15:8]} ), // input [31 : 0] din
.wr_en(wb_ack_i), // input wr_en
.rd_en(ve), // input rd_en
.dout(dout_rgb) // output [7 : 0] dout
// .wr_ack(wr_ack), // output wr_ack
//ack is asserted when the previous write cycle succeeded
// .full(full), // output full
// .empty(empty), // output empty
// .prog_full(prog_full) // output prog_full
// .prog_empty(prog_empty) // output prog_empty
);
wire clk_p = vga_clk;
vga vga0(
.rst (~wb_rst_i),
/*AUTOINST*/
// Outputs
.hsync (hsync),
.vsync (vsync),
.x (x[9:0]),
.y (y[9:0]),
.ve (ve),
.newline (newline),
.newfield (newfield),
// Inputs
.clk_p (clk_p)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodrp_controller.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:24 $
// \ \ / \ Date Created: Mon Feb 9 2009
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: Xilinx reference design for IODRP controller for v0.9 device
//
//Reference:
//
// Revision: Date: Comment
// 1.0: 02/06/09: Initial version for MIG wrapper.
// 1.1: 02/01/09: updates to indentations.
// 1.2: 02/12/09: changed non-blocking assignments to blocking ones
// for state machine always block. Also, assigned
// intial value to load_shift_n to avoid latch
// End Revision
//*******************************************************************************
`timescale 1ps/1ps
module iodrp_controller(
input wire [7:0] memcell_address,
input wire [7:0] write_data,
output reg [7:0] read_data,
input wire rd_not_write,
input wire cmd_valid,
output wire rdy_busy_n,
input wire use_broadcast,
input wire sync_rst,
input wire DRP_CLK,
output reg DRP_CS,
output wire DRP_SDI, //output to IODRP SDI pin
output reg DRP_ADD,
output reg DRP_BKST,
input wire DRP_SDO //input from IODRP SDO pin
);
reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state
reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out
reg [7:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI.
// This register is loaded before the address or data phase, but continues
// to shift for a writeback of read data
reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
reg [2:0] bit_cnt; // The counter for which bit is being shifted during address or data phase
reg rd_not_write_reg;
reg AddressPhase; // This is set after the first address phase has executed
reg capture_read_data;
(* FSM_ENCODING="one-hot" *) reg [2:0] state, nextstate;
wire [7:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
wire DRP_SDI_pre; // added so that DRP_SDI output is only active when DRP_CS is active
localparam READY = 3'h0;
localparam DECIDE = 3'h1;
localparam ADDR_PHASE = 3'h2;
localparam ADDR_TO_DATA_GAP = 3'h3;
localparam ADDR_TO_DATA_GAP2 = 3'h4;
localparam ADDR_TO_DATA_GAP3 = 3'h5;
localparam DATA_PHASE = 3'h6;
localparam ALMOST_READY = 3'h7;
localparam IOI_DQ0 = 5'h01;
localparam IOI_DQ1 = 5'h00;
localparam IOI_DQ2 = 5'h03;
localparam IOI_DQ3 = 5'h02;
localparam IOI_DQ4 = 5'h05;
localparam IOI_DQ5 = 5'h04;
localparam IOI_DQ6 = 5'h07;
localparam IOI_DQ7 = 5'h06;
localparam IOI_DQ8 = 5'h09;
localparam IOI_DQ9 = 5'h08;
localparam IOI_DQ10 = 5'h0B;
localparam IOI_DQ11 = 5'h0A;
localparam IOI_DQ12 = 5'h0D;
localparam IOI_DQ13 = 5'h0C;
localparam IOI_DQ14 = 5'h0F;
localparam IOI_DQ15 = 5'h0E;
localparam IOI_UDQS_CLK = 5'h1D;
localparam IOI_UDQS_PIN = 5'h1C;
localparam IOI_LDQS_CLK = 5'h1F;
localparam IOI_LDQS_PIN = 5'h1E;
//synthesis translate_off
reg [32*8-1:0] state_ascii;
always @ (state) begin
case (state)
READY :state_ascii <= "READY";
DECIDE :state_ascii <= "DECIDE";
ADDR_PHASE :state_ascii <= "ADDR_PHASE";
ADDR_TO_DATA_GAP :state_ascii <= "ADDR_TO_DATA_GAP";
ADDR_TO_DATA_GAP2 :state_ascii <= "ADDR_TO_DATA_GAP2";
ADDR_TO_DATA_GAP3 :state_ascii <= "ADDR_TO_DATA_GAP3";
DATA_PHASE :state_ascii <= "DATA_PHASE";
ALMOST_READY :state_ascii <= "ALMOST_READY";
endcase // case(state)
end
//synthesis translate_on
/*********************************************
* Input Registers
*********************************************/
always @ (posedge DRP_CLK) begin
if(state == READY) begin
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end
end
assign rdy_busy_n = (state == READY);
/*********************************************
* Shift Registers / Bit Counter
*********************************************/
assign data_out_mux = addr_data_sel_n ? memcell_addr_reg : data_reg;
always @ (posedge DRP_CLK) begin
if(sync_rst)
shift_through_reg <= 8'b0;
else begin
if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= {DRP_SDO, shift_through_reg[7:1]};
end
end
always @ (posedge DRP_CLK) begin
if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst)
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 3'b000;
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
read_data <= 8'h00;
// capture_read_data <= 1'b0;
end
else begin
// capture_read_data <= (state == DATA_PHASE);
// if(capture_read_data)
if(state == ALMOST_READY)
read_data <= shift_through_reg;
// else
// read_data <= read_data;
end
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
AddressPhase <= 1'b0;
end
else begin
if (AddressPhase) begin
// Keep it set until we finish the cycle
AddressPhase <= AddressPhase && ~(state == ALMOST_READY);
end
else begin
// set the address phase when ever we finish the address phase
AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111);
end
end
end
/*********************************************
* DRP Signals
*********************************************/
always @ (posedge DRP_CLK) begin
DRP_ADD <= (nextstate == ADDR_PHASE);
DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
if (state == READY)
DRP_BKST <= use_broadcast;
end
// assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
// assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
assign DRP_SDI = shift_through_reg[0]; // The new read method only requires that we shift out the address and the write data
/*********************************************
* State Machine
*********************************************/
always @ (*) begin
addr_data_sel_n = 1'b0;
load_shift_n = 1'b0;
case (state)
READY: begin
if(cmd_valid)
nextstate = DECIDE;
else
nextstate = READY;
end
DECIDE: begin
load_shift_n = 1;
addr_data_sel_n = 1;
nextstate = ADDR_PHASE;
end
ADDR_PHASE: begin
if(&bit_cnt)
if (rd_not_write_reg)
if (AddressPhase)
// After the second pass go to end of statemachine
nextstate = ALMOST_READY;
else
// execute a second address phase for the read access.
nextstate = DECIDE;
else
nextstate = ADDR_TO_DATA_GAP;
else
nextstate = ADDR_PHASE;
end
ADDR_TO_DATA_GAP: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP2;
end
ADDR_TO_DATA_GAP2: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP3;
end
ADDR_TO_DATA_GAP3: begin
load_shift_n = 1;
nextstate = DATA_PHASE;
end
DATA_PHASE: begin
if(&bit_cnt)
nextstate = ALMOST_READY;
else
nextstate = DATA_PHASE;
end
ALMOST_READY: begin
nextstate = READY;
end
default: begin
nextstate = READY;
end
endcase
end
always @ (posedge DRP_CLK) begin
if(sync_rst)
state <= READY;
else
state <= nextstate;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRBP_FUNCTIONAL_V
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Integer multiplication and division unit
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* IMulDivU */
module uparc_imuldivu(
clk,
nrst,
/* CU signals */
o_exec_stall,
i_mem_stall,
i_fetch_stall,
i_wait_stall,
i_nullify_execute,
i_nullify_mem,
i_nullify_wb,
/* Decoded operation */
i_imuldiv_op,
/* Operands */
i_rs_val,
i_rt_val,
/* Result */
o_imuldiv_rd_val,
o_imuldiv_rd_valid
);
/* Inputs */
input wire clk;
input wire nrst;
/* CU signals */
output wire o_exec_stall;
input wire i_mem_stall;
input wire i_fetch_stall;
input wire i_wait_stall;
input wire i_nullify_execute;
input wire i_nullify_mem;
input wire i_nullify_wb;
/* Decoded operation */
input wire [`UPARC_IMDOP_WIDTH-1:0] i_imuldiv_op;
/* Operands */
input wire [`UPARC_REG_WIDTH-1:0] i_rs_val;
input wire [`UPARC_REG_WIDTH-1:0] i_rt_val;
/* Result */
output reg [`UPARC_REG_WIDTH-1:0] o_imuldiv_rd_val;
output reg o_imuldiv_rd_valid;
/* Stall logic */
wire core_stall = o_exec_stall || i_mem_stall || i_fetch_stall || i_wait_stall;
assign o_exec_stall = !i_mem_stall && !i_fetch_stall && !muldiv_ready && interlock_instr;
reg [2*`UPARC_REG_WIDTH-1:0] hilor; /* HI and LO registers */
/* Interlocked instruction arrived */
wire interlock_instr = (i_imuldiv_op == `UPARC_IMDOP_MFLO) || (i_imuldiv_op == `UPARC_IMDOP_MFHI) ||
(i_imuldiv_op == `UPARC_IMDOP_MUL) || (i_imuldiv_op == `UPARC_IMDOP_MULU) ||
(i_imuldiv_op == `UPARC_IMDOP_DIV) || (i_imuldiv_op == `UPARC_IMDOP_DIVU);
/* Multiplication and division units are ready */
wire muldiv_ready;
assign muldiv_ready = !div_running && !mul_running;
/* Multiplication or division is in progress */
reg mul_running;
reg div_running;
/* Operand values */
reg [`UPARC_REG_WIDTH-1:0] rs_reg;
reg [`UPARC_REG_WIDTH-1:0] rt_reg;
/* Division unit control signals */
reg div_start;
reg div_signd;
wire div_ready;
wire [2*`UPARC_REG_WIDTH-1:0] div_remquot;
/* Multiplication unit control signals */
reg mul_start;
reg mul_signd;
wire mul_ready;
wire [2*`UPARC_REG_WIDTH-1:0] mul_product;
/****************************** EXECUTE STAGE *********************************/
reg imd_mthi_p2;
reg imd_mtlo_p2;
reg [`UPARC_REG_WIDTH-1:0] imd_rval_p2;
/* Execute stage */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
imd_mthi_p2 <= 1'b0;
imd_mtlo_p2 <= 1'b0;
imd_rval_p2 <= {(`UPARC_REG_WIDTH){1'b0}};
rs_reg <= {(`UPARC_REG_WIDTH){1'b0}};
rt_reg <= {(`UPARC_REG_WIDTH){1'b0}};
div_running <= 1'b0;
div_start <= 1'b0;
div_signd <= 1'b0;
mul_running <= 1'b0;
mul_start <= 1'b0;
mul_signd <= 1'b0;
o_imuldiv_rd_valid <= 1'b0;
o_imuldiv_rd_val <= {(`UPARC_REG_WIDTH){1'b0}};
end
else
begin
div_start <= 1'b0;
mul_start <= 1'b0;
mul_running <= !mul_ready;
div_running <= !div_ready;
if(!core_stall && !i_nullify_execute)
begin
imd_mthi_p2 <= 1'b0;
imd_mtlo_p2 <= 1'b0;
o_imuldiv_rd_valid <= 1'b0;
if(i_imuldiv_op == `UPARC_IMDOP_MFLO)
begin
o_imuldiv_rd_valid <= 1'b1;
o_imuldiv_rd_val <= hilor[`UPARC_REG_WIDTH-1:0];
end
else if(i_imuldiv_op == `UPARC_IMDOP_MFHI)
begin
o_imuldiv_rd_valid <= 1'b1;
o_imuldiv_rd_val <= hilor[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH];
end
else if(i_imuldiv_op == `UPARC_IMDOP_MTLO)
begin
imd_mtlo_p2 <= 1'b1;
imd_rval_p2 <= i_rs_val;
end
else if(i_imuldiv_op == `UPARC_IMDOP_MTHI)
begin
imd_mthi_p2 <= 1'b1;
imd_rval_p2 <= i_rs_val;
end
else if(i_imuldiv_op == `UPARC_IMDOP_MUL)
begin
rs_reg <= i_rs_val;
rt_reg <= i_rt_val;
mul_signd <= 1'b1;
mul_start <= 1'b1;
mul_running <= 1'b1;
end
else if(i_imuldiv_op == `UPARC_IMDOP_MULU)
begin
rs_reg <= i_rs_val;
rt_reg <= i_rt_val;
mul_signd <= 1'b0;
mul_start <= 1'b1;
mul_running <= 1'b1;
end
else if(i_imuldiv_op == `UPARC_IMDOP_DIV)
begin
rs_reg <= i_rs_val;
rt_reg <= i_rt_val;
div_signd <= 1'b1;
div_start <= 1'b1;
div_running <= 1'b1;
end
else if(i_imuldiv_op == `UPARC_IMDOP_DIVU)
begin
rs_reg <= i_rs_val;
rt_reg <= i_rt_val;
div_signd <= 1'b0;
div_start <= 1'b1;
div_running <= 1'b1;
end
end
else if(!core_stall)
begin
imd_mthi_p2 <= 1'b0;
imd_mtlo_p2 <= 1'b0;
o_imuldiv_rd_valid <= 1'b0;
end
end
end
/******************************* MEMORY STAGE *********************************/
reg imd_mthi_p3;
reg imd_mtlo_p3;
reg [`UPARC_REG_WIDTH-1:0] imd_rval_p3;
/* Memory stage */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
imd_mthi_p3 <= 1'b0;
imd_mtlo_p3 <= 1'b0;
imd_rval_p3 <= {(`UPARC_REG_WIDTH){1'b0}};
end
else if(!core_stall && !i_nullify_mem)
begin
imd_mthi_p3 <= imd_mthi_p2;
imd_mtlo_p3 <= imd_mtlo_p2;
imd_rval_p3 <= imd_rval_p2;
end
else if(!core_stall)
begin
imd_mthi_p3 <= 1'b0;
imd_mtlo_p3 <= 1'b0;
imd_rval_p3 <= {(`UPARC_REG_WIDTH){1'b0}};
end
end
/***************************** WRITEBACK STAGE ********************************/
/* Writeback stage */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
hilor <= {(2*`UPARC_REG_WIDTH){1'b0}};
end
else if(mul_running && mul_ready && (!imd_mthi_p3 || !imd_mtlo_p3))
begin
hilor <= mul_product;
end
else if(div_running && div_ready && (!imd_mthi_p3 || !imd_mtlo_p3))
begin
hilor <= div_remquot;
end
else if(!core_stall && !i_nullify_wb)
begin
if(imd_mthi_p3) hilor[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH] <= imd_rval_p3;
if(imd_mtlo_p3) hilor[`UPARC_REG_WIDTH-1:0] <= imd_rval_p3;
end
end
/**************** DIVISION AND MULTIPLICATION UNITS INSTANCES *****************/
uparc_long_idiv idiv(
.clk(clk),
.nrst(nrst),
.dividend(rs_reg),
.divider(rt_reg),
.start(div_start),
.signd(div_signd),
.ready(div_ready),
.remquot(div_remquot)
);
`ifdef UPARC_FAST_IMUL
uparc_fast_imul imul(
.clk(clk),
.nrst(nrst),
.multiplicand(rs_reg),
.multiplier(rt_reg),
.start(mul_start),
.signd(mul_signd),
.ready(mul_ready),
.product(mul_product)
);
`else /* !UPARC_FAST_IMUL */
uparc_long_imul imul(
.clk(clk),
.nrst(nrst),
.multiplicand(rs_reg),
.multiplier(rt_reg),
.start(mul_start),
.signd(mul_signd),
.ready(mul_ready),
.product(mul_product)
);
`endif /* UPARC_FAST_IMUL */
endmodule /* uparc_imuldivu */
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> g; vector<int> c; int root, n; vector<int> dfs(int u) { vector<int> combine; for (int v : g[u]) { vector<int> child = dfs(v); for (int z : child) combine.emplace_back(z); } if (c[u] > combine.size()) { cout << NO ; exit(0); } combine.insert(combine.begin() + c[u], u); return combine; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; g.resize(n + 1); c.resize(n + 1); for (int i = 1; i <= n; i++) { int p; cin >> p >> c[i]; if (!p) root = i; else g[p].emplace_back(i); } vector<int> order = dfs(root); vector<int> ans(n + 1); for (int i = 0; i < order.size(); i++) ans[order[i]] = i + 1; cout << YES n ; for (int i = 1; i < ans.size(); i++) cout << ans[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int nmax = 3e5 + 42; int n, m; struct edge { int u, v, c; }; edge inp[nmax]; edge make_edge(int u, int v, int c) { edge x; x.u = u; x.v = v; x.c = c; return x; } bool cmp(edge a, edge b) { return a.c < b.c; } int ans[nmax], new_values[nmax]; int main() { cin >> n >> m; int a, b, c; for (int i = 1; i <= m; i++) { scanf( %i%i%i , &a, &b, &c); inp[i] = make_edge(a, b, c); } sort(inp + 1, inp + m + 1, cmp); for (int i = 1; i <= m; i++) { int j = i + 1; while (j <= m && inp[i].c == inp[j].c) j++; for (int k = i; k < j; k++) { new_values[inp[k].v] = max(new_values[inp[k].v], ans[inp[k].u] + 1); } for (int k = i; k < j; k++) { ans[inp[k].v] = new_values[inp[k].v]; } i = j - 1; } int outp = 0; for (int i = 1; i <= n; i++) outp = max(outp, ans[i]); cout << outp << endl; return 0; }
|
`timescale 1ns / 1ps
// Documented Verilog UART
// Copyright (C) 2010 Timothy Goddard ()
// Distributed under the MIT licence.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
module osdvu(
input clk, // The master clock for this module
input rst, // Synchronous reset.
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Signal to transmit
input [7:0] tx_byte, // Byte to transmit
output received, // Indicated that a byte has been received.
output [7:0] rx_byte, // Byte received
output is_receiving, // Low when receive line is idle.
output is_transmitting, // Low when transmit line is idle.
output recv_error // Indicates error in receiving packet.
);
parameter CLOCK_DIVIDE = 1302; // clock rate (50Mhz) / (baud rate (9600) * 4)
// States for the receiving state machine.
// These are just constants, not parameters to override.
parameter RX_IDLE = 0;
parameter RX_CHECK_START = 1;
parameter RX_READ_BITS = 2;
parameter RX_CHECK_STOP = 3;
parameter RX_DELAY_RESTART = 4;
parameter RX_ERROR = 5;
parameter RX_RECEIVED = 6;
// States for the transmitting state machine.
// Constants - do not override.
parameter TX_IDLE = 0;
parameter TX_SENDING = 1;
parameter TX_DELAY_RESTART = 2;
reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
reg [10:0] tx_clk_divider = CLOCK_DIVIDE;
reg [2:0] recv_state = RX_IDLE;
reg [5:0] rx_countdown;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [5:0] tx_countdown;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
always @(posedge clk) begin
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
// The clk_divider counter counts down from
// the CLOCK_DIVIDE constant. Whenever it
// reaches 0, 1/16 of the bit period has elapsed.
// Countdown timers for the receiving and transmitting
// state machines are decremented.
rx_clk_divider = rx_clk_divider - 1;
if (!rx_clk_divider) begin
rx_clk_divider = CLOCK_DIVIDE;
rx_countdown = rx_countdown - 1;
end
tx_clk_divider = tx_clk_divider - 1;
if (!tx_clk_divider) begin
tx_clk_divider = CLOCK_DIVIDE;
tx_countdown = tx_countdown - 1;
end
// Receive state machine
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait half the period - should resume in the
// middle of this first pulse.
rx_clk_divider = CLOCK_DIVIDE;
rx_countdown = 2;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_countdown) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period to resume half-way
// through the first bit.
rx_countdown = 4;
rx_bits_remaining = 8;
recv_state = RX_READ_BITS;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_READ_BITS: begin
if (!rx_countdown) begin
// Should be half-way through a bit pulse here.
// Read this bit in, wait for the next if we
// have more to get.
rx_data = {rx, rx_data[7:1]};
rx_countdown = 4;
rx_bits_remaining = rx_bits_remaining - 1;
recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
end
end
RX_CHECK_STOP: begin
if (!rx_countdown) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_countdown = 8;
recv_state = RX_DELAY_RESTART;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state = RX_IDLE;
end
endcase
// Transmit state machine
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
tx_clk_divider = CLOCK_DIVIDE;
tx_countdown = 4;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_countdown) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_countdown = 4;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_countdown = 8;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; for (int i = 1; i < 100000; i++) { n *= 3; m *= 2; if (n > m) { cout << i << endl; return 0; } } }
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//! The USRP digital up-conversion chain
module duc_chain
#(
parameter BASE = 0,
parameter DSPNO = 0,
parameter WIDTH = 24
)
(input clk, input rst, input clr,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
// To TX frontend
output [WIDTH-1:0] tx_fe_i,
output [WIDTH-1:0] tx_fe_q,
// From TX control
input [31:0] sample,
input run,
output strobe,
output [31:0] debug
);
wire duc_enb;
wire [17:0] scale_factor;
wire [31:0] phase_inc;
reg [31:0] phase;
wire [7:0] interp_rate;
wire [3:0] tx_femux_a, tx_femux_b;
wire enable_hb1, enable_hb2;
wire rate_change;
setting_reg #(.my_addr(BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(scale_factor),.changed());
setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change));
// Strobes are all now delayed by 1 cycle for timing reasons
wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
reg strobe_cic = 1;
reg strobe_hb1 = 1;
reg strobe_hb2 = 1;
cic_strober #(.WIDTH(8))
cic_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
.strobe_fast(1),.strobe_slow(strobe_cic_pre) );
cic_strober #(.WIDTH(2))
hb2_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(enable_hb2 ? 2 : 1),
.strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
cic_strober #(.WIDTH(2))
hb1_strober(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(enable_hb1 ? 2 : 1),
.strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
always @(posedge clk) strobe_cic <= strobe_cic_pre;
// NCO
always @(posedge clk)
if(rst)
phase <= 0;
else if(~duc_enb)
phase <= 0;
else
phase <= phase + phase_inc;
wire signed [17:0] da, db;
wire signed [35:0] prod_i, prod_q;
wire [15:0] bb_i;
wire [15:0] bb_q;
wire [17:0] i_interp, q_interp;
wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
wire [7:0] cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate;
// Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true,
// but the default case inside hb_interp handles this
hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_i
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_i, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i));
hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(WIDTH)) hb_interp_q
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_q, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q));
small_hb_int #(.WIDTH(18)) small_hb_interp_i
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
.output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
small_hb_int #(.WIDTH(18)) small_hb_interp_q
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
.output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
cic_interp_i(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
.strobe_in(strobe_cic),.strobe_out(1),
.signal_in(hb2_i),.signal_out(i_interp));
cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
cic_interp_q(.clock(clk),.reset(rst),.enable(duc_enb & ~rate_change),.rate(interp_rate),
.strobe_in(strobe_cic),.strobe_out(1),
.signal_in(hb2_q),.signal_out(q_interp));
localparam cwidth = WIDTH; // was 18
localparam zwidth = 24; // was 16
wire [cwidth-1:0] da_c, db_c;
cordic_z24 #(.bitwidth(cwidth))
cordic(.clock(clk), .reset(rst), .enable(duc_enb),
.xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}),
.zi(phase[31:32-zwidth]),
.xo(da_c),.yo(db_c),.zo() );
MULT18X18S MULT18X18S_inst
(.P(prod_i), // 36-bit multiplier output
.A(da_c[cwidth-1:cwidth-18]), // 18-bit multiplier input
.B(scale_factor), // 18-bit multiplier input
.C(clk), // Clock input
.CE(1), // Clock enable input
.R(rst) // Synchronous reset input
);
MULT18X18S MULT18X18S_inst_2
(.P(prod_q), // 36-bit multiplier output
.A(db_c[cwidth-1:cwidth-18]), // 18-bit multiplier input
.B(scale_factor), // 18-bit multiplier input
.C(clk), // Clock input
.CE(1), // Clock enable input
.R(rst) // Synchronous reset input
);
dsp_tx_glue #(.DSPNO(DSPNO), .WIDTH(WIDTH)) dsp_tx_glue(
.clock(clk), .reset(rst), .clear(clr), .enable(run),
.set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
.frontend_i(tx_fe_i), .frontend_q(tx_fe_q),
.duc_out_i(prod_i[33:34-WIDTH]), .duc_out_q(prod_q[33:34-WIDTH]),
.duc_in_sample({bb_i, bb_q}), .duc_in_strobe(strobe_hb1), .duc_in_enable(duc_enb),
.bb_sample(sample), .bb_strobe(strobe));
assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
endmodule // dsp_core
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_PP_V
/**
* srdlstp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_psa_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire reset_delayed;
wire SET_B_delayed;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$sN dlatch0 (buf_Q , D_delayed, GATE_delayed, SET_B_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b1 );
assign cond0 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B === 1'b1 ) );
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_PP_V
|
module Platform (
clk_clk,
hex0_2_export,
hex3_5_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c0_inst_SDA,
hps_io_hps_io_i2c0_inst_SCL,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35,
hps_io_hps_io_gpio_inst_GPIO48,
hps_io_hps_io_gpio_inst_GPIO53,
hps_io_hps_io_gpio_inst_GPIO54,
hps_io_hps_io_gpio_inst_GPIO61,
i2c_SDAT,
i2c_SCLK,
i2s_codec_iadcdat,
i2s_codec_iadclrc,
i2s_codec_ibclk,
i2s_codec_idaclrc,
i2s_codec_odacdat,
i2s_gpio_iadcdat,
i2s_gpio_iadclrc,
i2s_gpio_ibclk,
i2s_gpio_idaclrc,
i2s_gpio_odacdat,
keys_export,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n,
switches_export,
xck_clk);
input clk_clk;
output [20:0] hex0_2_export;
output [20:0] hex3_5_export;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_qspi_inst_IO0;
inout hps_io_hps_io_qspi_inst_IO1;
inout hps_io_hps_io_qspi_inst_IO2;
inout hps_io_hps_io_qspi_inst_IO3;
output hps_io_hps_io_qspi_inst_SS0;
output hps_io_hps_io_qspi_inst_CLK;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
output hps_io_hps_io_spim1_inst_CLK;
output hps_io_hps_io_spim1_inst_MOSI;
input hps_io_hps_io_spim1_inst_MISO;
output hps_io_hps_io_spim1_inst_SS0;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
inout hps_io_hps_io_i2c0_inst_SDA;
inout hps_io_hps_io_i2c0_inst_SCL;
inout hps_io_hps_io_i2c1_inst_SDA;
inout hps_io_hps_io_i2c1_inst_SCL;
inout hps_io_hps_io_gpio_inst_GPIO09;
inout hps_io_hps_io_gpio_inst_GPIO35;
inout hps_io_hps_io_gpio_inst_GPIO48;
inout hps_io_hps_io_gpio_inst_GPIO53;
inout hps_io_hps_io_gpio_inst_GPIO54;
inout hps_io_hps_io_gpio_inst_GPIO61;
inout i2c_SDAT;
output i2c_SCLK;
input i2s_codec_iadcdat;
input i2s_codec_iadclrc;
input i2s_codec_ibclk;
input i2s_codec_idaclrc;
output i2s_codec_odacdat;
input i2s_gpio_iadcdat;
input i2s_gpio_iadclrc;
input i2s_gpio_ibclk;
input i2s_gpio_idaclrc;
output i2s_gpio_odacdat;
input [2:0] keys_export;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
input [9:0] switches_export;
output xck_clk;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_V
|
`timescale 1ns / 1ps
module ddr3_fb_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg rst;
wire mig_ready = 1'b1;
reg [31:0] mig_rd_data;
reg [6:0] mig_rd_count;
wire [29:0] mig_cmd_byte_addr;
wire [8:0] x_lcdc_fb;
wire [6:0] y_lcdc_fb;
wire in_hsync_lcdc_fb;
wire in_vsync_lcdc_fb;
wire pop_lcdc_fb;
wire [5:0] r_fb_lcdc;
wire [5:0] g_fb_lcdc;
wire [5:0] b_fb_lcdc;
wire ack_fb_lcdc;
lcdc lcdc(
.clk(clk),
.rst(rst),
.x_o(x_lcdc_fb),
.y_o(y_lcdc_fb),
.in_hsync_o(in_hsync_lcdc_fb),
.in_vsync_o(in_vsync_lcdc_fb),
.pop_o(pop_lcdc_fb),
.r_i(r_fb_lcdc),
.g_i(g_fb_lcdc),
.b_i(b_fb_lcdc),
.ack_i(ack_fb_lcdc));
ddr3_fb uut(
.clk(clk),
.rst(rst),
.mig_ready_i(mig_ready),
.mig_cmd_empty(1'b1),
.mig_cmd_full(1'b0),
.mig_cmd_byte_addr(mig_cmd_byte_addr),
.mig_wr_full(1'b1),
.mig_wr_empty(1'b0),
// .mig_wr_count,
// .mig_wr_underrun,
// .mig_wr_error,
.mig_rd_data(mig_rd_data),
// .mig_rd_full,
// .mig_rd_empty,
.mig_rd_count(mig_rd_count),
// .mig_rd_overflow,
// .mig_rd_error,
.x_i(x_lcdc_fb),
.y_i(y_lcdc_fb),
.in_hsync_i(in_hsync_lcdc_fb),
.in_vsync_i(in_vsync_lcdc_fb),
.pop_i(pop_lcdc_fb),
.r_o(r_fb_lcdc),
.g_o(g_fb_lcdc),
.b_o(b_fb_lcdc),
.ack_o(ack_fb_lcdc));
reg [31:0] i;
initial begin
$dumpfile("ddr3_fb_t.lxt");
$dumpvars(0, ddr3_fb_t);
rst = 1'b1;
#(TCLK);
rst = 1'b0;
mig_rd_count = 'b0;
mig_rd_data = 'b0;
#(TCLK*);
$finish(2);
end
reg [29:0] mig_cmd_byte_addr_snapshot_ff;
function [31:0] datasyn(
input [31:0] mig_cmd_byte_addr,
input [31:0] offset);
begin
datasyn[7:0] = {offset[5:0], 2'b0};
datasyn[15:8] = {mig_cmd_byte_addr[7:2], 2'b0};
datasyn[23:16] = {mig_cmd_byte_addr[16:11], 2'b0};
datasyn[31:24] = 8'hff;
end
endfunction
always @(posedge clk) begin
if (uut.mig_cmd_en) begin
mig_cmd_byte_addr_snapshot_ff = mig_cmd_byte_addr;
#(TCLK*5)
mig_rd_count = 'd3;
mig_rd_data = datasyn(mig_cmd_byte_addr_snapshot_ff, 0);
#(TCLK)
mig_rd_count = 'd3;
mig_rd_data = datasyn(mig_cmd_byte_addr_snapshot_ff, 1);
#(TCLK)
mig_rd_count = 'd4;
mig_rd_data = datasyn(mig_cmd_byte_addr_snapshot_ff, 2);
#(TCLK)
mig_rd_count = 'd3;
mig_rd_data = datasyn(mig_cmd_byte_addr_snapshot_ff, 3);
#(TCLK)
mig_rd_count = 'd3;
mig_rd_data = datasyn(mig_cmd_byte_addr_snapshot_ff, 4);
#(TCLK)
mig_rd_count = 'd3;
mig_rd_data = datasyn(mig_cmd_byte_addr_snapshot_ff, 5);
#(TCLK)
mig_rd_count = 'd2;
mig_rd_data = datasyn(mig_cmd_byte_addr_snapshot_ff, 6);
#(TCLK)
mig_rd_count = 'd1;
mig_rd_data = datasyn(mig_cmd_byte_addr_snapshot_ff, 7);
#(TCLK)
mig_rd_count = 'd0;
mig_rd_data = 32'hcccccccc;
end
end
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY TX
*/
module eth_phy_10g_tx #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
/*
* Configuration
*/
input wire tx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
xgmii_baser_enc_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH)
)
xgmii_baser_enc_inst (
.clk(clk),
.rst(rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr)
);
eth_phy_10g_tx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE)
)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100001; const int MOD = 1e9 + 7; mt19937 rnd(100); int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(0); int n, m, x; vector<vector<int> > a; cin >> n >> m; a.assign(n, vector<int>(m)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> x; a[i][j] = (int)(x != a[i][j]); } for (int i = 0; i < n; i++) { int sum = 0; for (int j = 0; j < m; j++) sum += a[i][j]; if (sum % 2) { cout << No ; return 0; } } for (int i = 0; i < m; i++) { int sum = 0; for (int j = 0; j < n; j++) sum += a[j][i]; if (sum % 2) { cout << No ; return 0; } } cout << Yes ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A211O_FUNCTIONAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int ans[30][5] = { {1, 0, 0, 1, 0}, {1, 1, 0, 2, 0}, {2, 0, 0, 1, 1}, {2, 1, 0, 1, 2}, {1, 1, 0, 1, 1}, {2, 1, 0, 2, 1}, {2, 2, 0, 2, 2}, {1, 2, 0, 2, 1}, {1, 1, 0, 1, 1}, {1, 2, 0, 1, 2}, {1, 0, 1, 2, 0}, {1, 1, 1, 3, 0}, {2, 0, 1, 2, 1}, {2, 1, 1, 2, 2}, {1, 1, 1, 2, 1}, {2, 1, 1, 3, 1}, {2, 2, 1, 3, 2}, {1, 2, 1, 3, 1}, {1, 1, 1, 2, 1}, {1, 2, 1, 2, 2}, {1, 0, 2, 2, 1}, {1, 1, 2, 3, 1}, {1, 2, 1, 1, 3}, {2, 0, 2, 2, 2}, {2, 1, 2, 2, 3}, {1, 1, 2, 2, 2} }; int main() { int N; scanf( %d , &N); for(int i = 0; i < N; i++) { int a[5]; for(int j = 0; j < 5; j++) scanf( %d , &a[j]); for(int j = 0; j < 26; j++) { bool ok = true; for(int k = 0; k < 5; k++) if(ans[j][k] != a[k]) ok = false; if(ok) { printf( %c , a + j); break; } } } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; void run_case() { string A, B, C, D; cin >> A; cin >> B; C = (A + B); sort(C.begin(), C.end()); cin >> D; sort(D.begin(), D.end()); if (C == D) cout << YES n ; else cout << NO n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long T = 1; while (T--) run_case(); return 0; }
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module top
(
// Clocking & Reset
input clk_i,
input rst_i,
// Fault Output
output fault_o,
// Break Output
output break_o,
// Interrupt Input
input intr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_KHZ = 8192;
parameter BOOT_VECTOR = 32'h10000000;
parameter ISR_VECTOR = 32'h10000000;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_sel;
wire[2:0] dmem_cti;
wire dmem_we;
wire dmem_stb;
wire dmem_cyc;
wire dmem_stall;
wire dmem_ack;
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire[3:0] imem_sel;
wire imem_stb;
wire imem_cyc;
wire[2:0] imem_cti;
wire imem_stall;
wire imem_ack;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
ram
u_ram
(
.clka_i(clk_i),
.rsta_i(rst_i),
.stba_i(imem_stb),
.wea_i(1'b0),
.sela_i(imem_sel),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.acka_o(imem_ack),
.clkb_i(clk_i),
.rstb_i(rst_i),
.stbb_i(dmem_stb),
.web_i(dmem_we),
.selb_i(dmem_sel),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r),
.ackb_o(dmem_ack)
);
cpu_if
#(
.CLK_KHZ(CLK_KHZ),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h10000000),
.ENABLE_ICACHE(`ICACHE_ENABLED),
.ENABLE_DCACHE(`DCACHE_ENABLED),
.REGISTER_FILE_TYPE("SIMULATION")
)
u_cpu
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.fault_o(fault_o),
.break_o(break_o),
.nmi_i(1'b0),
.intr_i(soc_irq),
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(imem_cti),
.imem0_cyc_o(imem_cyc),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(dmem_cti),
.dmem0_cyc_o(dmem_cyc),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
// CPU SOC
soc
#(
.CLK_KHZ(CLK_KHZ),
.ENABLE_SYSTICK_TIMER("ENABLED"),
.ENABLE_HIGHRES_TIMER("ENABLED"),
.EXTERNAL_INTERRUPTS(1)
)
u_soc
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.ext_intr_i(1'b0),
.intr_o(soc_irq),
// Memory Port
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, w[1000999]; int arr[1009999]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &w[i]); arr[w[i]]++; } for (int i = 0; i < 1000099; i++) { arr[i + 1] += arr[i] / 2; arr[i] = arr[i] % 2; } int ans = 0; for (int i = 0; i < 1000099; i++) { if (arr[i] >= 1) { ans++; } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; void _R(int &x) { scanf( %d , &x); } void _R(long long &x) { scanf( %lld , &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } void _W(const int &x) { printf( %d , x); } void _W(const long long &x) { printf( %lld , x); } void _W(const double &x) { printf( %.16f , x); } void _W(const char &x) { putchar(x); } void _W(const char *x) { printf( %s , x); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) putchar( ); } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } const int N = 3e5 + 7, M = 2e6; const long long mod = 1e9 + 7; inline int read() { int ret = 0; char ch = getchar(); bool f = 1; for (; !isdigit(ch); ch = getchar()) f ^= !(ch ^ - ); for (; isdigit(ch); ch = getchar()) ret = (ret << 1) + (ret << 3) + ch - 48; return f ? ret : -ret; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long ksm(long long a, long long b, long long mod) { int ans = 1; while (b) { if (b & 1) ans = (ans * a) % mod; a = (a * a) % mod; b >>= 1; } return ans; } long long inv2(long long a, long long mod) { return ksm(a, mod - 2, mod); } void TelmaZzzz() {} struct node { int l, r, val; } que[N]; int a[N]; int arr[N]; int k, t, m, n; bool check(int x) { int minn = m + 1, maxn = -1; for (int i = 1; i <= m + 1; i++) arr[i] = 0; for (int i = 1; i <= k; i++) { if (que[i].val <= a[n - x + 1]) continue; arr[que[i].l]++; arr[que[i].r + 1]--; } int ans = m + 1; for (int i = 1; i <= m + 1; i++) { arr[i] += arr[i - 1]; if (arr[i]) ans += 2; } if (ans <= t) return true; return false; } int main() { TelmaZzzz(); R(n, m, k, t); for (int i = 1; i <= n; i++) R(a[i]); for (int i = 1; i <= k; i++) R(que[i].l, que[i].r, que[i].val); sort(a + 1, a + 1 + n); int l = 1, r = n; while (l <= r) { int mi = (l + r) / 2; if (check(mi)) l = mi + 1; else r = mi - 1; } W(r); return 0; }
|
#include <bits/stdc++.h> using namespace std; string A, B; bool is_divisor(const string &a, const string &b) { int sa = a.size(), sb = b.size(); for (int i = 0; i < sb; i += sa) { if (b.substr(i, sa) != a) return false; } return true; } int process(const string &a, const string &b) { int sz = a.size(); vector<int> divi; for (int i = 1; i < sqrt(sz) + 1; ++i) { if (sz % i == 0) { divi.push_back(i); if (i * i != sz) divi.push_back(sz / i); } } set<string> s; for (int i = 0; i < divi.size(); ++i) if (is_divisor(a.substr(0, divi[i]), a)) s.insert(a.substr(0, divi[i])); sz = b.size(); divi.clear(); for (int i = 1; i < sqrt(sz) + 1; ++i) { if (sz % i == 0) { divi.push_back(i); if (i * i != sz) divi.push_back(sz / i); } } int ans = 0; set<string> ss; for (int i = 0; i < divi.size(); ++i) if (is_divisor(b.substr(0, divi[i]), b)) ss.insert(b.substr(0, divi[i])); for (string a : s) if (ss.find(a) != ss.end()) ++ans; return ans; } int main() { char a[100001]; scanf( %s , a); A = string(a); scanf( %s , a); B = string(a); cout << process(A, B) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 1; int accept() { int b[N] = {0}; int d[N] = {0}; int n; cin >> n; int mx, check; for (int i = 0; i < n; i++) cin >> b[i]; sort(b, b + n); for (int i = 1; i < n; i++) { if (b[i] == b[i - 1]) { cout << YES << n ; return 0; } } cout << NO << n ; return 0; } int main() { int t = 1; cin >> t; while (t--) { accept(); } return 0; }
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module fallthrough_small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output reg empty,
input reset,
input clk
);
reg fifo_rd_en, empty_nxt;
small_fifo
#(.WIDTH (WIDTH),
.MAX_DEPTH_BITS (MAX_DEPTH_BITS),
.PROG_FULL_THRESHOLD (PROG_FULL_THRESHOLD))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (fifo_rd_en),
.dout (dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (fifo_empty),
.reset (reset),
.clk (clk)
);
always @(*) begin
empty_nxt = empty;
fifo_rd_en = 0;
case (empty)
1'b1: begin
if(!fifo_empty) begin
fifo_rd_en = 1;
empty_nxt = 0;
end
end
1'b0: begin
if(rd_en) begin
if(fifo_empty) begin
empty_nxt = 1;
end
else begin
fifo_rd_en = 1;
end
end
end
endcase // case(empty)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
empty <= 1'b1;
end
else begin
empty <= empty_nxt;
end
end
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && full) begin
$display("%t ERROR: Attempt to write to full FIFO: %m", $time);
end
if (rd_en && empty) begin
$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
end
end // always @ (posedge clk)
// synthesis translate_on
endmodule // fallthrough_small_fifo_v2
// synthesis translate_off
module fallthrough_small_fifo_tester();
reg [31:0] din = 0;
reg wr_en = 0;
reg rd_en = 0;
wire [31:0] dout;
wire full;
wire nearly_full;
wire prog_full;
wire empty;
reg clk = 0;
reg reset = 0;
integer count = 0;
always #8 clk = ~clk;
fallthrough_small_fifo
#(.WIDTH (32),
.MAX_DEPTH_BITS (3),
.PROG_FULL_THRESHOLD (4))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (rd_en),
.dout (dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (empty),
.reset (reset),
.clk (clk)
);
always @(posedge clk) begin
count <= count + 1;
reset <= 0;
wr_en <= 0;
rd_en <= 0;
if(count < 2) begin
reset <= 1'b1;
end
else if(count < 2 + 9) begin
wr_en <= 1;
din <= din + 1'b1;
end
else if(count < 2 + 8 + 4) begin
rd_en <= 1;
end
else if(count < 2 + 8 + 4 + 2) begin
din <= din + 1'b1;
wr_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8 + 4) begin
rd_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8 + 4 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
end // always @ (posedge clk)
endmodule // fallthrough_small_fifo_tester
// synthesis translate_on
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
#include <bits/stdc++.h> using namespace std; const long long N = 400010; inline long long read() { long long s = 0, w = 1; register char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = (s << 3) + (s << 1) + (ch ^ 48), ch = getchar(); return s * w; } void print(long long x) { if (x < 0) x = -x, putchar( - ); if (x > 9) print(x / 10); putchar(x % 10 + 0 ); } long long n, k; long long a[N]; void MS(long long l, long long r) { if (!k || r - l <= 1) return; long long mid = (l + r >> 1); k -= 2, swap(a[mid - 1], a[mid]); MS(l, mid), MS(mid, r); } signed main() { n = read(), k = read(); for (register long long i = 0; i < n; i++) a[i] = i; if (!(k & 1ll)) { puts( -1 ); return 0; } if (k == 1) { for (register long long i = 1; i <= n; i++) printf( %lld , i); puts( ); return 0; } k--; MS(0, n); if (!k) { for (register long long i = 0; i < n; i++) printf( %lld , a[i] + 1); puts( ); } else puts( -1 ); return 0; }
|
//////////////////////////////////////////////////////////////////
// //
// Wrapper for SRAM buffer module //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "timescale.v"
module eth_spram_256x32(
//
// Generic synchronous single-port RAM interface
//
input clk, // Clock, rising edge
input rst, // Reset, active high
input ce, // Chip enable input, active high
input [3:0] we, // Write enable input, active high
input oe, // Output enable input, active high
input [7:0] addr, // address bus inputs
input [31:0] di, // input data bus
output [31:0] do // output data bus
);
wire write_enable;
assign write_enable = ce & (|we);
`ifdef XILINX_SPARTAN6_FPGA
xs6_sram_256x32_byte_en
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_sram_256x32_byte_en
`endif
`ifndef XILINX_FPGA
generic_sram_byte_en
`endif
#(
.DATA_WIDTH ( 32 ) ,
.ADDRESS_WIDTH ( 8 )
) u_ram (
.i_clk ( clk ),
.i_write_data ( di ),
.i_write_enable ( write_enable ),
.i_address ( addr ),
.i_byte_enable ( we ),
.o_read_data ( do )
);
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; std::vector<int> v[100005]; int dist[100005]; void dfs(int s, int par) { if (par != -1) dist[s] = dist[par] + 1; for (int i = 0; i < v[s].size(); i++) { if (par != v[s][i]) dfs(v[s][i], s); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1, xx, x = 0, y = 0, cc, m, k, n; cin >> t; while (t--) { int a, b, da, db; cin >> n >> a >> b >> da >> db; for (int i = 1; i < n; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); dist[i] = 0; } dist[n] = 0; dfs(a, -1); int ab = dist[b]; int farest, mx = -1; for (int i = 1; i < n + 1; i++) { if (mx < dist[i]) { mx = dist[i]; farest = i; } } for (int i = 1; i < n + 1; i++) dist[i] = 0; dfs(farest, -1); int diameter = -1; for (int i = 1; i < n + 1; i++) diameter = max(diameter, dist[i]); if (ab <= da || 2 * da >= diameter || 2 * da >= db) cout << Alice << endl; else cout << Bob << endl; for (int i = 1; i < n + 1; i++) v[i].clear(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c, k; cin >> a >> b >> c >> k; if (k >= a + b + c - 3) { cout << a * b * c << endl; } else { long long res = 1; for (int x1 = 0; x1 < a; x1++) { long long help = (-k + x1) / (-2); for (int n = -1; n < 1; n++) { long long x2 = min(min(help + n, b - 1), k - x1); long long x3 = min(k - x1 - x2, c - 1); res = max(res, (1 + x1) * (1 + x2) * (1 + x3)); } } for (int x1 = 0; x1 < a; x1++) { long long help = (-k + x1) / (-2); for (int n = -1; n < 1; n++) { long long x2 = min(min(help + n, c - 1), k - x1); long long x3 = min(k - x1 - x2, b - 1); res = max(res, (1 + x1) * (1 + x2) * (1 + x3)); } } cout << res << endl; } }
|
#include<iostream> #include<math.h> #include<bits/stdc++.h> #include <string> #include <vector> using namespace std; #define pi (2*acos(0.0)) #define ll long long int #define ull unsigned long long int #define lp(i , start , n) for(int i = start ; i < n; i++) int main(){ ios::sync_with_stdio(false); cin.tie(0); int t; cin>>t; while(t--){ int n; cin>>n; if(n==2) cout<<-1<<endl; else{ int a[n][n]; bool odd = true; int oddnum= 1; int evennum=1; int cnt = 0; for(int i = 0 ; i < n ; i++){ for(int j = 0 ; j < n ; j++){ if(odd){ a[i][j]=2*oddnum-1; oddnum++; cnt++; if(cnt>=(n*n+1)/2){ odd=false; } } else{ a[i][j]=2*evennum; evennum++; } } } for(int i = 0 ; i < n ; i++){ for(int j = 0 ; j < n ; j++){ cout<<a[i][j]<< ; } cout<<endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[4]; for (int i = 0; i < 4; i++) cin >> a[i]; int sumtotal = a[0] + a[1] + a[2] + a[3]; if (sumtotal % 2 != 0) { cout << NO ; return 0; } for (int i = 0; i < 4; i++) { if (a[i] == sumtotal - a[i]) { cout << YES ; return 0; } else for (int j = 0; j < 4; j++) { if (i != j) if ((a[i] + a[j]) == (sumtotal - a[i] - a[j])) { cout << YES ; return 0; } } } cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[202]; int height[202], best[202][3]; int N; int getHeight(int ind, int parent) { if (height[ind] != -1) return height[ind]; int ret = 1; for (int i = 0; i < (int)adj[ind].size(); i++) { if (adj[ind][i] == parent) continue; ret = max(ret, getHeight(adj[ind][i], ind) + 1); } return height[ind] = ret; } int solve(int ind, int parent, int f) { if (best[ind][f] != -1) return best[ind][f]; int ret = 0; if (!f) { for (int i = 0; i < (int)adj[ind].size(); i++) { if (adj[ind][i] == parent) continue; int a = 0, b = 0; for (int j = 0; j < (int)adj[ind].size(); j++) { if (adj[ind][j] == parent || j == i) continue; int h = getHeight(adj[ind][j], adj[ind][j]); if (h > a) b = a, a = h; else if (h > b) b = h; } ret = max(ret, (a + b) * solve(adj[ind][i], ind, f + 1)); } } else { int a = 0, b = 0; for (int j = 0; j < (int)adj[ind].size(); j++) { if (adj[ind][j] == parent) continue; int h = getHeight(adj[ind][j], adj[ind][j]); if (h > a) b = a, a = h; else if (h > b) b = h; ret = max(ret, solve(adj[ind][j], ind, f)); } ret = max(ret, a + b); } return best[ind][f] = ret; } int main() { scanf( %d , &N); for (int i = 0; i < N - 1; i++) { int a, b; scanf( %d %d , &a, &b); a--, b--; adj[a].push_back(b); adj[b].push_back(a); } int ret = 0; for (int i = 0; i < N; i++) { memset(height, -1, sizeof height); memset(best, -1, sizeof best); getHeight(i, i); ret = max(ret, solve(i, i, 0)); } printf( %d n , ret); }
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_pcs.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs.v,v $
//
// $Revision: #1 $
// $Date: 2010/01/07 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet PCS
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
reg_clk, // Avalon slave - clock
reg_rd, // Avalon slave - read
reg_wr, // Avalon slave - write
reg_addr, // Avalon slave - address
reg_data_in, // Avalon slave - writedata
reg_data_out, // Avalon slave - readdata
reg_busy, // Avalon slave - waitrequest
reset_reg_clk, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
rx_clk,
tx_clk,
rx_clkena,
tx_clkena,
gmii_rx_dv,
gmii_rx_d,
gmii_rx_err,
gmii_tx_en,
gmii_tx_d,
gmii_tx_err,
mii_rx_dv,
mii_rx_d,
mii_rx_err,
mii_tx_en,
mii_tx_d,
mii_tx_err,
mii_col,
mii_crs,
tbi_rx_clk,
tbi_tx_clk,
tbi_rx_d,
tbi_tx_d,
sd_loopback,
powerdown,
set_10,
set_100,
set_1000,
hd_ena,
led_col,
led_an,
led_char_err,
led_disp_err,
led_crs,
led_link);
parameter PHY_IDENTIFIER = 32'h 00000000 ;
parameter DEV_VERSION = 16'h 0001 ;
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_reg_clk; // Asynchronous Reset - clk Domain
output rx_clk; // MAC Receive clock
output tx_clk; // MAC Transmit clock
output rx_clkena; // MAC Receive Clock Enable
output tx_clkena; // MAC Transmit Clock Enable
output gmii_rx_dv; // GMII Receive Enable
output [7:0] gmii_rx_d; // GMII Receive Data
output gmii_rx_err; // GMII Receive Error
input gmii_tx_en; // GMII Transmit Enable
input [7:0] gmii_tx_d; // GMII Transmit Data
input gmii_tx_err; // GMII Transmit Error
output mii_rx_dv; // MII Receive Enable
output [3:0] mii_rx_d; // MII Receive Data
output mii_rx_err; // MII Receive Error
input mii_tx_en; // MII Transmit Enable
input [3:0] mii_tx_d; // MII Transmit Data
input mii_tx_err; // MII Transmit Error
output mii_col; // MII Collision
output mii_crs; // MII Carrier Sense
input tbi_rx_clk; // 125MHz Recoved Clock
input tbi_tx_clk; // 125MHz Transmit Clock
input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
output [9:0] tbi_tx_d; // Transmit TBI Interface
output sd_loopback; // SERDES Loopback Enable
output powerdown; // Powerdown Enable
input reg_clk; // Register Interface Clock
input reg_rd; // Register Read Enable
input reg_wr; // Register Write Enable
input [4:0] reg_addr; // Register Address
input [15:0] reg_data_in; // Register Input Data
output [15:0] reg_data_out; // Register Output Data
output reg_busy; // Access Busy
output led_crs; // Carrier Sense
output led_link; // Valid Link
output hd_ena; // Half-Duplex Enable
output led_col; // Collision Indication
output led_an; // Auto-Negotiation Status
output led_char_err; // Character Error
output led_disp_err; // Disparity Error
output set_10; // 10Mbps Link Indication
output set_100; // 100Mbps Link Indication
output set_1000; // Gigabit Link Indication
wire rx_clk;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire gmii_rx_dv;
wire [7:0] gmii_rx_d;
wire gmii_rx_err;
wire mii_rx_dv;
wire [3:0] mii_rx_d;
wire mii_rx_err;
wire mii_col;
wire mii_crs;
wire [9:0] tbi_tx_d;
wire sd_loopback;
wire powerdown;
wire [15:0] reg_data_out;
wire reg_busy;
wire led_crs;
wire led_link;
wire hd_ena;
wire led_col;
wire led_an;
wire led_char_err;
wire led_disp_err;
wire set_10;
wire set_100;
wire set_1000;
altera_tse_top_1000_base_x top_1000_base_x_inst(
.reset_rx_clk(reset_rx_clk),
.reset_tx_clk(reset_tx_clk),
.reset_reg_clk(reset_reg_clk),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_d(gmii_rx_d),
.gmii_rx_err(gmii_rx_err),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_d(gmii_tx_d),
.gmii_tx_err(gmii_tx_err),
.mii_rx_dv(mii_rx_dv),
.mii_rx_d(mii_rx_d),
.mii_rx_err(mii_rx_err),
.mii_tx_en(mii_tx_en),
.mii_tx_d(mii_tx_d),
.mii_tx_err(mii_tx_err),
.mii_col(mii_col),
.mii_crs(mii_crs),
.tbi_rx_clk(tbi_rx_clk),
.tbi_tx_clk(tbi_tx_clk),
.tbi_rx_d(tbi_rx_d),
.tbi_tx_d(tbi_tx_d),
.sd_loopback(sd_loopback),
.reg_clk(reg_clk),
.reg_rd(reg_rd),
.reg_wr(reg_wr),
.reg_addr(reg_addr),
.reg_data_in(reg_data_in),
.reg_data_out(reg_data_out),
.reg_busy(reg_busy),
.powerdown(powerdown),
.set_10(set_10),
.set_100(set_100),
.set_1000(set_1000),
.hd_ena(hd_ena),
.led_col(led_col),
.led_an(led_an),
.led_char_err(led_char_err),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_link(led_link));
defparam
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 201; const long long K = 201; const long long X = 201; long long dp[N][X]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n, k, x; cin >> n >> k >> x; vector<long long> picBeauty; picBeauty.push_back(-1); for (long long i = 1; i <= n; i++) { long long x; cin >> x; picBeauty.push_back(x); } long long minimumPosts = n / k; if (x < minimumPosts) { cout << -1 << endl; return 0; } for (long long i = 0; i <= n; i++) { for (long long j = 0; j <= x; j++) { dp[i][j] = 0; } } for (long long i = 1; i <= k; i++) { dp[i][1] = picBeauty[i]; } long long flag = 0; for (long long j = 2; j <= x; j++) { for (long long i = 1; i <= n; i++) { long long tempFlag = 0; long long backAllowed = i - k; for (long long y = i - 1; y >= 1 && y >= backAllowed; y--) { if (dp[y][j - 1] > 0) dp[i][j] = max(dp[i][j], dp[y][j - 1] + picBeauty[i]); } } } long long ans = 0; for (long long i = n - k + 1; i <= n; i++) { ans = max(ans, dp[i][x]); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct query { long long int l; long long int r; long long int i; }; query Q[200001]; long long int arr[200001]; long long int f[1000001]; long long int ans[200001]; long long int cnt; bool compare(query a, query b) { if ((a.l / 448) != (b.l / 448)) return a.l / 448 < b.l / 448; return a.r < b.r; } void add(long long int a) { long long int x = f[arr[a]] * f[arr[a]] * arr[a]; cnt -= x; f[arr[a]]++; x = f[arr[a]] * f[arr[a]] * arr[a]; cnt += x; } void remove(long long int a) { long long int x = f[arr[a]] * f[arr[a]] * arr[a]; cnt -= x; f[arr[a]]--; x = f[arr[a]] * f[arr[a]] * arr[a]; cnt += x; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n, i, q; cin >> n >> q; for (i = 0; i < n; i++) cin >> arr[i]; for (i = 0; i < q; i++) { cin >> Q[i].l >> Q[i].r; Q[i].i = i; Q[i].l--; Q[i].r--; } sort(Q, Q + q, compare); long long int cl = 0, cr = -1; for (i = 0; i < q; i++) { long long int L = Q[i].l; long long int R = Q[i].r; while (cl > L) { cl--; add(cl); } while (cr < R) { cr++; add(cr); } while (cl < L) { remove(cl); cl++; } while (cr > R) { remove(cr); cr--; } ans[Q[i].i] = cnt; } for (i = 0; i < q; i++) { cout << ans[i] << n ; } return 0; }
|
// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf
module AND2 (
input A, B,
output Y
);
assign Y = A & B;
endmodule
module AND3 (
input A, B, C,
output Y
);
assign Y = A & B & C;
endmodule
module AND4 (
input A, B, C, D,
output Y
);
assign Y = A & B & C & D;
endmodule
module CFG1 (
output Y,
input A
);
parameter [1:0] INIT = 2'h0;
assign Y = INIT >> A;
endmodule
module CFG2 (
output Y,
input A,
input B
);
parameter [3:0] INIT = 4'h0;
assign Y = INIT >> {B, A};
endmodule
module CFG3 (
output Y,
input A,
input B,
input C
);
parameter [7:0] INIT = 8'h0;
assign Y = INIT >> {C, B, A};
endmodule
module CFG4 (
output Y,
input A,
input B,
input C,
input D
);
parameter [15:0] INIT = 16'h0;
assign Y = INIT >> {D, C, B, A};
endmodule
module BUFF (
input A,
output Y
);
assign Y = A;
endmodule
module BUFD (
input A,
output Y
);
assign Y = A;
endmodule
module CLKINT (
input A,
(* clkbuf_driver *)
output Y
);
assign Y = A;
endmodule
module CLKINT_PRESERVE (
input A,
(* clkbuf_driver *)
output Y
);
assign Y = A;
endmodule
module GCLKINT (
input A, EN,
(* clkbuf_driver *)
output Y
);
assign Y = A & EN;
endmodule
module RCLKINT (
input A,
(* clkbuf_driver *)
output Y
);
assign Y = A;
endmodule
module RGCLKINT (
input A, EN,
(* clkbuf_driver *)
output Y
);
assign Y = A & EN;
endmodule
module SLE (
output Q,
input ADn,
input ALn,
(* clkbuf_sink *)
input CLK,
input D,
input LAT,
input SD,
input EN,
input SLn
);
reg q_latch, q_ff;
always @(posedge CLK, negedge ALn) begin
if (!ALn) begin
q_ff <= !ADn;
end else if (EN) begin
if (!SLn)
q_ff <= SD;
else
q_ff <= D;
end
end
always @* begin
if (!ALn) begin
q_latch <= !ADn;
end else if (CLK && EN) begin
if (!SLn)
q_ff <= SD;
else
q_ff <= D;
end
end
assign Q = LAT ? q_latch : q_ff;
endmodule
// module AR1
// module FCEND_BUFF
// module FCINIT_BUFF
// module FLASH_FREEZE
// module OSCILLATOR
// module SYSRESET
// module SYSCTRL_RESET_STATUS
// module LIVE_PROBE_FB
(* blackbox *)
module GCLKBUF (
(* iopad_external_pin *)
input PAD,
input EN,
(* clkbuf_driver *)
output Y
);
endmodule
(* blackbox *)
module GCLKBUF_DIFF (
(* iopad_external_pin *)
input PADP,
(* iopad_external_pin *)
input PADN,
input EN,
(* clkbuf_driver *)
output Y
);
endmodule
(* blackbox *)
module GCLKBIBUF (
input D,
input E,
input EN,
(* iopad_external_pin *)
inout PAD,
(* clkbuf_driver *)
output Y
);
endmodule
// module DFN1
// module DFN1C0
// module DFN1E1
// module DFN1E1C0
// module DFN1E1P0
// module DFN1P0
// module DLN1
// module DLN1C0
// module DLN1P0
module INV (
input A,
output Y
);
assign Y = !A;
endmodule
module INVD (
input A,
output Y
);
assign Y = !A;
endmodule
module MX2 (
input A, B, S,
output Y
);
assign Y = S ? B : A;
endmodule
module MX4 (
input D0, D1, D2, D3, S0, S1,
output Y
);
assign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);
endmodule
module NAND2 (
input A, B,
output Y
);
assign Y = !(A & B);
endmodule
module NAND3 (
input A, B, C,
output Y
);
assign Y = !(A & B & C);
endmodule
module NAND4 (
input A, B, C, D,
output Y
);
assign Y = !(A & B & C & D);
endmodule
module NOR2 (
input A, B,
output Y
);
assign Y = !(A | B);
endmodule
module NOR3 (
input A, B, C,
output Y
);
assign Y = !(A | B | C);
endmodule
module NOR4 (
input A, B, C, D,
output Y
);
assign Y = !(A | B | C | D);
endmodule
module OR2 (
input A, B,
output Y
);
assign Y = A | B;
endmodule
module OR3 (
input A, B, C,
output Y
);
assign Y = A | B | C;
endmodule
module OR4 (
input A, B, C, D,
output Y
);
assign Y = A | B | C | D;
endmodule
module XOR2 (
input A, B,
output Y
);
assign Y = A ^ B;
endmodule
module XOR3 (
input A, B, C,
output Y
);
assign Y = A ^ B ^ C;
endmodule
module XOR4 (
input A, B, C, D,
output Y
);
assign Y = A ^ B ^ C ^ D;
endmodule
module XOR8 (
input A, B, C, D, E, F, G, H,
output Y
);
assign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;
endmodule
// module UJTAG
module BIBUF (
input D,
input E,
(* iopad_external_pin *)
inout PAD,
output Y
);
assign PAD = E ? D : 1'bz;
assign Y = PAD;
endmodule
(* blackbox *)
module BIBUF_DIFF (
input D,
input E,
(* iopad_external_pin *)
inout PADP,
(* iopad_external_pin *)
inout PADN,
output Y
);
endmodule
module CLKBIBUF (
input D,
input E,
(* iopad_external_pin *)
inout PAD,
(* clkbuf_driver *)
output Y
);
assign PAD = E ? D : 1'bz;
assign Y = PAD;
endmodule
module CLKBUF (
(* iopad_external_pin *)
input PAD,
(* clkbuf_driver *)
output Y
);
assign Y = PAD;
endmodule
(* blackbox *)
module CLKBUF_DIFF (
(* iopad_external_pin *)
input PADP,
(* iopad_external_pin *)
input PADN,
(* clkbuf_driver *)
output Y
);
endmodule
module INBUF (
(* iopad_external_pin *)
input PAD,
output Y
);
assign Y = PAD;
endmodule
(* blackbox *)
module INBUF_DIFF (
(* iopad_external_pin *)
input PADP,
(* iopad_external_pin *)
input PADN,
output Y
);
endmodule
module OUTBUF (
input D,
(* iopad_external_pin *)
output PAD
);
assign PAD = D;
endmodule
(* blackbox *)
module OUTBUF_DIFF (
input D,
(* iopad_external_pin *)
output PADP,
(* iopad_external_pin *)
output PADN
);
endmodule
module TRIBUFF (
input D,
input E,
(* iopad_external_pin *)
output PAD
);
assign PAD = E ? D : 1'bz;
endmodule
(* blackbox *)
module TRIBUFF_DIFF (
input D,
input E,
(* iopad_external_pin *)
output PADP,
(* iopad_external_pin *)
output PADN
);
endmodule
// module DDR_IN
// module DDR_OUT
// module RAM1K18
// module RAM64x18
// module MACC
|
`timescale 1ns / 1ps
`include "hal/WcaPortDefs.h" //grab register addresses.
// Name: WcaPortController.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaPortController(
input wire reset,
input wire enable,
output wire [(NBITS_ADDR+2):0] portCtrl, // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
input wire [1:0] portCmd, // Port Command ID
//Port Interface
output wire [(NBITS_ADDR+1):0] pifCtrl, // {addr[NBITS_ADDR:0], iocmd[1:0] }
input wire [6:0] pifStatus // I/O Status {fifo_full[0], fifo_empty[0], ioBusy, ioState[2:0], clk}
);
parameter COUNT_PORTS = 1;
parameter NBITS_ADDR = 2;
parameter ADDR_MODE = 0;
parameter ADDR_OVERRIDE = 0;
`define PORT_ADDR_MODE_SEQUENTIAL 0
`define PORT_ADDR_MODE_FIXED 1
//State machine states.
`define S_IDLE 3'h0 //Idling state Fixed addressing mode only.
`define S_ADDR 3'h0 //Addressing state. Sequential addressing mode only.
`define S_ADDR_WAIT1 3'h1 //Addressing wait state #1. Sequential addressing mode only.
`define S_ADDR_WAIT2 3'h2 //Addressing wait state #2. Sequential addressing mode only.
`define S_ADDR_WAIT3 3'h3 //Addressing wait state #3. Sequential addressing mode only.
`define S_CMD 3'h4 //Command Initation
`define S_CMD_WAIT1 3'h5 //Wait for IF to settle #1
`define S_CMD_WAIT2 3'h6 //Wait for IF to settle #2
`define S_WAIT_COMPLETE 3'h7 //Wait for Command Completion.
`define ADDR_INCREMENT 2'h1; //Increment address by one.
reg [NBITS_ADDR-1:0] addr;
reg [2:0] cmdState;
reg [1:0] cmd;
wire read;
wire write;
//Map Inputs to Outputs.
assign read = pifStatus[3:1] == `PIFSTAT_READ;
assign write = pifStatus[3:1] == `PIFSTAT_WRITE;
assign pifCtrl = { addr, cmd};
assign portCtrl[NBITS_ADDR+2: 1] = {addr, read, write};
WcaPassthrough pthruClk(.a(pifStatus[0]), .b(portCtrl[0]));
//Control processing of port data based on count.
generate if( ADDR_MODE == `PORT_ADDR_MODE_SEQUENTIAL)
begin
always @(posedge pifStatus[0])
begin :PIFCMD_STATE_MACHINE
if( reset)
begin
addr <= COUNT_PORTS-1;
cmdState <= `S_ADDR;
cmd <= `PIFCMD_IDLE;
end
else
//State machine performs addressing, command, and wait processing.
case (cmdState)
`S_ADDR:
begin
cmd <= `PIFCMD_IDLE;
if( enable)
begin
cmdState <= `S_ADDR_WAIT1;
if( addr == COUNT_PORTS-1) addr <= 0;
else addr <= addr + `ADDR_INCREMENT;
end
end
`S_ADDR_WAIT1: //Wait one for address to settle.
begin
cmdState <= `S_ADDR_WAIT2;
end
`S_ADDR_WAIT2: //Wait another for address to settle.
begin
cmdState <= `S_ADDR_WAIT3;
end
`S_ADDR_WAIT3: //Wait another for address to settle.
begin
cmdState <= `S_CMD;
end
`S_CMD:
begin
cmd <= portCmd;
if( portCmd != `PIFCMD_IDLE)
begin
cmdState <= `S_CMD_WAIT1;
end
else
begin
cmdState <= `S_ADDR;
end
end
`S_CMD_WAIT1: //Wait one clock for the IF to catch up.
begin
cmdState <= `S_CMD_WAIT2;
end
`S_CMD_WAIT2: //Wait another clock for the IF to catch up.
begin
cmdState <= `S_WAIT_COMPLETE;
end
`S_WAIT_COMPLETE:
begin
cmd <= `PIFCMD_IDLE;
if( ~pifStatus[4] ) //if no longer busy, return to idle.
cmdState <= `S_ADDR;
end
endcase
end
end
//*******************************************************************************
// FIXED ADDRESSING MODE.
//*******************************************************************************
else if( ADDR_MODE == `PORT_ADDR_MODE_FIXED)
begin
always @(posedge pifStatus[0])
begin :PIFCMD_STATE_MACHINE
if( reset)
begin
addr <= ADDR_OVERRIDE;
cmdState <= `S_IDLE;
cmd <= `PIFCMD_IDLE;
end
else
//State machine performs addressing, command, and wait processing.
case (cmdState)
`S_IDLE:
begin
cmd <= `PIFCMD_IDLE;
if( enable)
cmdState <= `S_CMD;
end
`S_CMD:
begin
cmd <= portCmd;
if( portCmd != `PIFCMD_IDLE)
begin
cmdState <= `S_CMD_WAIT1;
end
else
begin
cmdState <= `S_IDLE;
end
end
`S_CMD_WAIT1: //Wait one clock for the IF to catch up.
begin
cmdState <= `S_CMD_WAIT2;
end
`S_CMD_WAIT2: //Wait another clock for the IF to catch up.
begin
cmdState <= `S_WAIT_COMPLETE;
end
`S_WAIT_COMPLETE:
begin
cmd <= `PIFCMD_IDLE;
if( ~pifStatus[4] ) //if no longer busy, return to idle.
cmdState <= `S_ADDR;
end
endcase
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_1_V
`define SKY130_FD_SC_HDLL__A221OI_1_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a221oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a221oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_1_V
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const int INF = 1e9; const double inf = 1e15; const double eps = 1e-9; const long long MOD = 1e9 + 7; long long toNum(string s) { stringstream ss(s); long long ret; ss >> ret; return ret; } string toString(long long x) { stringstream ss; ss << x; return ss.str(); } long long mulMod(long long a, long long b) { return (a * b) % MOD; } long long addMod(long long a, long long b) { return (a + b) % MOD; } long long redMod(long long a, long long b) { return addMod(addMod(a, -b), MOD); } long long fast(long long a, long long b) { if (b == 0) return 1; long long tmp = fast(a, b / 2); tmp = mulMod(tmp, tmp); if (b & 1) tmp = mulMod(tmp, a); return tmp; } long long GCD(long long a, long long b) { if (a == 0) return b; return GCD(b % a, a); } const int N = 1e5 + 5; const int BLOCK = 300; const int CBLOCK = N / BLOCK + 5; pair<int, int> jmp[N]; int arr[N]; int n, q; vector<pair<int, int> > lst; pair<int, int> query(int x) { int cur = x; int nxt = jmp[cur].first; int nod = x, val = 1; while (cur != nxt) { val += jmp[cur].second; nod = nxt; cur = nxt; nxt = jmp[cur].first; } return make_pair(nod, val); } void update(int a, int b) { arr[a] = b; int idx = (a - 1) / BLOCK; int st = idx * BLOCK + 1; int en = min(n, (idx + 1) * BLOCK); for (int i = en; i >= st; i -= 1) { int nxt = i + arr[i]; nxt = min(nxt, n + 1); if (nxt == n + 1) { jmp[i] = make_pair(i, 0); } else { if ((nxt - 1) / BLOCK != idx) { jmp[i] = make_pair(nxt, 1); } else { jmp[i] = make_pair(jmp[nxt].first, jmp[nxt].second + 1); } } } } int main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> q; for (int i = 1; i <= n; i += 1) cin >> arr[i]; for (int i = n; i >= 1; i -= 1) { int nxt = i + arr[i]; nxt = min(nxt, n + 1); if (nxt == n + 1) { jmp[i] = make_pair(i, 0); } else { if ((nxt - 1) / BLOCK != (i - 1) / BLOCK) { jmp[i] = make_pair(nxt, 1); } else { jmp[i] = make_pair(jmp[nxt].first, jmp[nxt].second + 1); } } } int ins, a, b; for (int i = 1; i <= q; i += 1) { cin >> ins >> a; if (ins == 0) { cin >> b; update(a, b); } else { pair<int, int> ans = query(a); cout << ans.first << << ans.second << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1004; int n, p, q, f[N][54][54], vc = 1000000000, ns[N][30], nt[N][30]; char c[N], s[N], t[N]; bool check1(int i, char x, int j) { if (i + 1 < j) return false; for (int k = 1; k < j; k++) { if (s[i + k - j + 1] != s[k]) return false; } if (x != s[j]) return false; return true; } bool check2(int i, char x, int j) { if (i + 1 < j) return false; for (int k = 1; k < j; k++) { if (t[i + k - j + 1] != t[k]) return false; } if (x != t[j]) return false; return true; } void build() { for (int i = 0; i <= p; i++) { for (char x = a ; x <= z ; x++) { for (int j = p; j >= 1; j--) { if (check1(i, x, j)) { ns[i][x - a + 1] = j; break; } } } } for (int i = 0; i <= q; i++) { for (char x = a ; x <= z ; x++) { for (int j = q; j >= 1; j--) { if (check2(i, x, j)) { nt[i][x - a + 1] = j; break; } } } } } int cal(int i, int x, int y) { if (i == n) return 0; if (f[i][x][y] != -vc) return f[i][x][y]; f[i][x][y] = -vc + 1; if (c[i + 1] == * ) { for (char b = a ; b <= z ; b++) { int cost = 0; int nx1 = ns[x][b - a + 1]; if (nx1 == p) cost++; int nx2 = nt[y][b - a + 1]; if (nx2 == q) cost--; f[i][x][y] = max(f[i][x][y], cal(i + 1, nx1, nx2) + cost); } } else { int cost = 0; char b = c[i + 1]; int nx1 = ns[x][b - a + 1]; if (nx1 == p) cost++; int nx2 = nt[y][b - a + 1]; if (nx2 == q) cost--; f[i][x][y] = max(f[i][x][y], cal(i + 1, nx1, nx2) + cost); } return f[i][x][y]; } int main() { scanf( %s%s%s , c + 1, s + 1, t + 1); p = strlen(s + 1); q = strlen(t + 1); n = strlen(c + 1); build(); for (int i = 0; i <= n; i++) { for (int j = 0; j <= p; j++) { for (int z = 0; z <= q; z++) f[i][j][z] = -vc; } } cout << cal(0, 0, 0); }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; if (n % m == 0) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T-- > 0) { int N; cin >> N; struct MM { int min, max; }; MM data[129]; for (int i = 0; i <= 128; ++i) { if (i >= 63 && i < 63 + N) data[i] = {i - 62, i - 62}; else data[i] = {0, 0}; } for (int i = 62; i >= 0; --i) { MM& fi = data[2 * i + 1]; MM& se = data[2 * i + 2]; if (se.min == 0) { data[i] = fi; } else { string res; if (fi.min == fi.max && se.min == se.max) { cout << ? << fi.min << << se.min << endl; cout.flush(); cin >> res; if (res == < ) data[i] = {fi.min, se.max}; else data[i] = {se.min, fi.max}; } else { cout << ? << fi.min << << se.min << endl; cout.flush(); cin >> res; if (res == < ) data[i].min = fi.min; else data[i].min = se.min; cout << ? << fi.max << << se.max << endl; cout.flush(); cin >> res; if (res == > ) data[i].max = fi.max; else data[i].max = se.max; } } } cout << ! << data[0].min << << data[0].max << endl; cout.flush(); } }
|
// The MLAB
// --------
// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
// the memory the ALM uses to store the look-up table data for general usage,
// producing a 32 address by 20-bit block of memory. MLABs are spread out
// around the chip, so they can be placed near where they are needed, rather than
// being comparatively limited in placement for a deep but narrow memory such as
// the M10K memory block.
//
// MLABs are used mainly for shallow but wide memories, such as CPU register
// files (which have perhaps 32 registers that are comparatively wide (16/32-bit))
// or shift registers (by using the output of the Nth bit as input for the N+1th
// bit).
//
// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks
// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries
// to put these cells in the same MLAB during cell placement. Because of this
// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and
// 20 of them represent a physical MLAB.
//
// How the MLAB works
// ------------------
// MLABs are poorly documented, so the following information is based mainly
// on the simulation model and my knowledge of how memories like these work.
// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated
// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
// `techmap` just for the sake of renaming the cell ports.
//
// The MLAB can be initialised to any value, but unfortunately Quartus only
// allows memory initialisation from a file. Since Yosys doesn't preserve input
// file information, or write the contents of an `initial` block to a file,
// Yosys can't currently initialise the MLAB in a way Quartus will accept.
//
// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
// is high, writes it to the address in A1ADDR. A1EN can therefore be used to
// conditionally write data to the MLAB.
//
// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
// then the output can be fed to embedded flops. Presently, Yosys assumes
// Quartus will pack external flops into the MLAB, but this is an assumption
// that needs testing.
// The vendor sim model outputs 'x for a very short period (a few
// combinational delta cycles) after each write. This has been omitted from
// the following model because it's very difficult to trigger this in practice
// as clock cycles will be much longer than any potential blip of 'x, so the
// model can be treated as always returning a defined result.
(* abc9_box, lib_whitebox *)
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN,
(* clkbuf_sink *) input CLK1,
input [4:0] B1ADDR, output B1DATA);
reg [31:0] mem = 32'b0;
// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
specify
$setup(A1ADDR, posedge CLK1, 86);
$setup(A1DATA, posedge CLK1, 86);
$setup(A1EN, posedge CLK1, 86);
(B1ADDR[0] => B1DATA) = 487;
(B1ADDR[1] => B1DATA) = 475;
(B1ADDR[2] => B1DATA) = 382;
(B1ADDR[3] => B1DATA) = 284;
(B1ADDR[4] => B1DATA) = 96;
endspecify
always @(posedge CLK1)
if (A1EN) mem[A1ADDR] <= A1DATA;
assign B1DATA = mem[B1ADDR];
endmodule
// The M10K
// --------
// TODO
module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
(* clkbuf_sink *) input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input A1EN, B1EN;
output reg [CFG_DBITS-1:0] B1DATA;
reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
specify
$setup(A1ADDR, posedge CLK1, 0);
$setup(A1DATA, posedge CLK1, 0);
if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
endspecify
always @(posedge CLK1) begin
if (A1EN)
mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
if (B1EN)
B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
end
endmodule
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`include "alink_define.v"
module alink_slave(
// system clock and reset
input clk ,
input rst ,
// wishbone interface signals
input ALINK_CYC_I ,//NC
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,//NC
input [2:0] ALINK_CTI_I ,//NC
input [1:0] ALINK_BTE_I ,//NC
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,//NC
output reg ALINK_ACK_O ,
output ALINK_ERR_O ,//const 0
output ALINK_RTY_O ,//const 0
output reg [31:0] ALINK_DAT_O ,
output reg txfifo_push ,
output reg [31:0] txfifo_din ,
input [9:0] rxcnt ,
input rxempty ,
input [10:0] txcnt ,
output reg_flush ,
input txfull ,
output reg [31:0] reg_mask ,
output reg reg_scan ,
input [31:0] busy ,
output rxfifo_pop ,
input [31:0] rxfifo_dout
);
parameter ALINK_TXFIFO = 6'h00 ;
parameter ALINK_STATE = 6'h04 ;
parameter ALINK_MASK = 6'h08 ;
parameter ALINK_BUSY = 6'h0c ;
parameter ALINK_RXFIFO = 6'h10 ;
//-----------------------------------------------------
// WB bus ACK
//-----------------------------------------------------
always @ ( posedge clk or posedge rst ) begin
if( rst )
ALINK_ACK_O <= 1'b0 ;
else if( ALINK_STB_I && (~ALINK_ACK_O) )
ALINK_ACK_O <= 1'b1 ;
else
ALINK_ACK_O <= 1'b0 ;
end
//-----------------------------------------------------
// ADDR MUX
//-----------------------------------------------------
wire alink_txfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_txfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_state_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_state_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_mask_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_mask_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_busy_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_busy_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_rxfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
wire alink_rxfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
//-----------------------------------------------------
// Register.txfifo
//-----------------------------------------------------
always @ ( posedge clk ) begin
txfifo_push <= alink_txfifo_wr_en ;
txfifo_din <= ALINK_DAT_I ;
end
//-----------------------------------------------------
// Register.state
//-----------------------------------------------------
reg [3:0] reg_flush_r ;
wire [31:0] rd_state = {reg_scan,1'b0,rxcnt[9:0],3'b0,rxempty,
1'b0,txcnt[10:0],2'b0,reg_flush,txfull} ;
always @ ( posedge clk ) begin
if( alink_state_wr_en )
reg_flush_r <= {3'b0,ALINK_DAT_I[1]} ;
else
reg_flush_r <= reg_flush_r << 1 ;
end
always @ ( posedge clk ) begin
if( rst )
reg_scan <= 1'b0 ;
else if( alink_state_wr_en )
reg_scan <= ALINK_DAT_I[31] ;
end
assign reg_flush = |reg_flush_r ;
//-----------------------------------------------------
// Register.mask
//-----------------------------------------------------
always @ ( posedge clk ) begin
if( alink_mask_wr_en )
reg_mask <= ALINK_DAT_I ;
end
//-----------------------------------------------------
// Register.busy
//-----------------------------------------------------
wire [31:0] rd_busy = busy[31:0] ;
//-----------------------------------------------------
// Register.rxfifo
//-----------------------------------------------------
wire [31:0] rd_rxfifo = rxfifo_dout[31:0] ;
//-----------------------------------------------------
// WB read
//-----------------------------------------------------
assign rxfifo_pop = alink_rxfifo_rd_en ;
always @ ( posedge clk ) begin
case( 1'b1 )
alink_state_rd_en : ALINK_DAT_O <= rd_state ;
alink_busy_rd_en : ALINK_DAT_O <= rd_busy ;
alink_rxfifo_rd_en : ALINK_DAT_O <= rd_rxfifo ;
default: ALINK_DAT_O <= 32'hdeaddead ;
endcase
end
endmodule
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; long long int gcd(long long int a, long long int b) { if (!b) return a; else return gcd(b, a % b); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<long long int> a(n); vector<bool> vis(n); deque<long long int> b; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { bool x; cin >> x; vis[i] = x; if (!vis[i]) b.push_back(a[i]); } sort(b.begin(), b.end(), greater<long long int>()); for (int i = 0; i < n; i++) { if (!vis[i]) { cout << b.front() << ; b.pop_front(); } else { cout << a[i] << ; } } cout << n ; } }
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#include <bits/stdc++.h> using namespace std; const long double pi = 3.14159265359; template <typename T> T abs(T x) { return x > 0 ? x : -x; } template <typename T> T sqr(T x) { return x * x; } const long long mod = 1000000007; struct matr { int maxn; int n; long long a[1 << 7][1 << 7]; matr(int _n) { maxn = 1 << _n; n = _n; for (int i = 0; i < maxn; i++) for (int j = 0; j < maxn; j++) a[i][j] = 0; } matr operator*(const matr &other) const { matr res(n); long long mod2 = mod * mod; for (int i = 0; i < maxn; i++) for (int j = 0; j < maxn; j++) { for (int h = 0; h < maxn; h++) { res.a[i][j] += (a[i][h] * other.a[h][j]); if (res.a[i][j] >= mod2) res.a[i][j] -= mod2; } res.a[i][j] %= mod; } return res; } vector<long long> operator*(const vector<long long> &row) { vector<long long> res(maxn); for (int i = 0; i < maxn; i++) { for (int j = 0; j < maxn; j++) { res[i] += (a[i][j] * row[j]) % mod; } res[i] %= mod; } return res; } }; matr gen(int n) { if (n == 1) { matr res(n); res.a[0][1] = 1; res.a[0][0] = 1; res.a[1][0] = 1; return res; } matr res(7); for (int _left = 0; _left < (1 << n); _left++) { for (int mid = 0; mid < (1 << (n - 1)); mid++) { int cmid = (mid << 1) | 1 | (1 << n); for (int _right = 0; _right < (1 << n); _right++) { bool bad = false; for (int j = 0; j < n && !bad; j++) { bad |= bool(_left & (1 << j)) && bool(_right & (1 << j)) && bool(cmid & (1 << j)) && bool(cmid & (1 << (j + 1))); } if (!bad) { res.a[_right][_left]++; } } } } return res; } int main() { vector<long long> ans(1 << 7); ans[1] = 1; for (int i = 1; i <= 7; i++) { int n; cin >> n; matr x(7), res(7); x = gen(i); for (int j = 0; j < (1 << i); j++) for (int h = 0; h < (1 << i); h++) res.a[j][h] = j == h; while (n) { if (n & 1) res = res * x; x = x * x; n >>= 1; } ans = res * ans; if (i == 7) break; for (int j = 0; j < (1 << i); j++) { ans[j | (1 << i)] = ans[j]; ans[j] = 0; } } cout << ans[(1 << 7) - 1] << endl; return 0; }
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#include<iostream> using namespace std; int main() { int t; cin>>t; while(t--) { int Xa,Ya,Xb,Yb,Xf,Yf,sum; cin>>Xa>>Ya>>Xb>>Yb>>Xf>>Yf; sum=abs(Xa-Xb)+abs(Ya-Yb); if(Xa==Xb&&Xb==Xf) { if(Ya<Yf&&Yb>Yf||Ya>Yf&&Yb<Yf) sum+=2; } if(Ya==Yb&&Yb==Yf) { if(Xa<Xf&&Xb>Xf||Xa>Xf&&Xb<Xf) sum+=2; } cout<<sum<<endl; } return 0; }
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// Chuck Benz, Hollis, NH Copyright (c)2002
//
// The information and description contained herein is the
// property of Chuck Benz.
//
// Permission is granted for any reuse of this information
// and description as long as this copyright notice is
// preserved. Modifications may be made as long as this
// notice is preserved.
// per Widmer and Franaszek
module encode_8b10b (datain, dispin, dataout, dispout) ;
input [8:0] datain ;
input dispin ; // 0 = neg disp; 1 = pos disp
output [9:0] dataout ;
output dispout ;
wire ai = datain[0] ;
wire bi = datain[1] ;
wire ci = datain[2] ;
wire di = datain[3] ;
wire ei = datain[4] ;
wire fi = datain[5] ;
wire gi = datain[6] ;
wire hi = datain[7] ;
wire ki = datain[8] ;
wire aeqb = (ai & bi) | (!ai & !bi) ;
wire ceqd = (ci & di) | (!ci & !di) ;
wire l22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd) ;
wire l40 = ai & bi & ci & di ;
wire l04 = !ai & !bi & !ci & !di ;
wire l13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi) ;
wire l31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi) ;
// The 5B/6B encoding
wire ao = ai ;
wire bo = (bi & !l40) | l04 ;
wire co = l04 | ci | (ei & di & !ci & !bi & !ai) ;
wire do = di & ! (ai & bi & ci) ;
wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ;
wire io = (l22 & !ei) |
(ei & !di & !ci & !(ai&bi)) | // D16, D17, D18
(ei & l40) |
(ki & ei & di & ci & !bi & !ai) | // K.28
(ei & !di & ci & !bi & !ai) ;
// pds16 indicates cases where d-1 is assumed + to get our encoded value
wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ;
// nds16 indicates cases where d-1 is assumed - to get our encoded value
wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ;
// ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
wire ndos6 = pd1s6 ;
// pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
wire pdos6 = ki | (ei & !l22 & !l13) ;
// some Dx.7 and all Kx.7 cases result in run length of 5 case unless
// an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
// specifically, D11, D13, D14, D17, D18, D19.
wire alt7 = fi & gi & hi & (ki |
(dispin ? (!ei & di & l31) : (ei & !di & l13))) ;
wire fo = fi & ! alt7 ;
wire go = gi | (!fi & !gi & !hi) ;
wire ho = hi ;
wire jo = (!hi & (gi ^ fi)) | alt7 ;
// nd1s4 is cases where d-1 is assumed - to get our encoded value
wire nd1s4 = fi & gi ;
// pd1s4 is cases where d-1 is assumed + to get our encoded value
wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ;
// ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
wire ndos4 = (!fi & !gi) ;
// pdos4 is nd1s4 cases where d-1 is - yields + disp out
wire pdos4 = fi & gi & hi ;
// only legal K codes are K28.0->.7, K23/27/29/30.7
// K28.0->7 is ei=di=ci=1,bi=ai=0
// K23 is 10111
// K27 is 11011
// K29 is 11101
// K30 is 11110 - so K23/27/29/30 are ei & l31
wire illegalk = ki &
(ai | bi | !ci | !di | !ei) & // not K28.0->7
(!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7
// now determine whether to do the complementing
// complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ;
// disparity out of 5b6b is disp in with pdso6 and ndso6
// pds16 indicates cases where d-1 is assumed + to get our encoded value
// ndos6 is cases where d-1 is + yields - disp out
// nds16 indicates cases where d-1 is assumed - to get our encoded value
// pdos6 is cases where d-1 is - yields + disp out
// disp toggles in all ndis16 cases, and all but that 1 nds16 case
wire disp6 = dispin ^ (ndos6 | pdos6) ;
wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ;
assign dispout = disp6 ^ (ndos4 | pdos4) ;
assign dataout = {(jo ^ compls4), (ho ^ compls4),
(go ^ compls4), (fo ^ compls4),
(io ^ compls6), (eo ^ compls6),
(do ^ compls6), (co ^ compls6),
(bo ^ compls6), (ao ^ compls6)} ;
endmodule
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#include <bits/stdc++.h> using namespace std; int GEN_SIZE = 6; vector<int> v, adj[50005]; int match[50005], match2[50005], vis[50005], ans[50005]; int V, Vleft; int conv(vector<int> v, int s) { int ans = 0; for (int i = 0; i < v.size(); i++) { ans *= s; ans += v[i]; } return ans; } vector<int> unconv(int p, int s) { vector<int> v1; for (int i = 0; i < s; i++) { v1.push_back(p % s); p /= s; } reverse(v1.begin(), v1.end()); return v1; } void recur(int x) { if (x == GEN_SIZE) { int rval = conv(v, GEN_SIZE); for (int rem = 0; rem < GEN_SIZE; rem++) { vector<int> tmp_v; tmp_v.push_back(rem); for (int i = 0; i < GEN_SIZE; i++) if (rem != i) tmp_v.push_back(v[i]); int lval = conv(tmp_v, GEN_SIZE); adj[rval].push_back(lval); } return; } for (int i = 0; i < GEN_SIZE; i++) { v.push_back(i); recur(x + 1); v.pop_back(); } } int aug(int v) { if (vis[v]) return 0; vis[v] = 1; for (int j = 0; j < (int)adj[v].size(); j++) { int r = adj[v][j]; if (match[r] == -1) { match[r] = v; return 1; } } for (int j = 0; j < (int)adj[v].size(); j++) { int r = adj[v][j]; if (aug(match[r])) { match[r] = v; return 1; } } return 0; } int T; vector<pair<pair<int, int>, int> > q; int main() { scanf( %d , &T); for (int i = 0; i < T; i++) { int N, R; scanf( %d%d , &N, &R); vector<int> v1; v1.push_back(R - 1); for (int j = 0; j < N - 1; j++) { int x; scanf( %d , &x); v1.push_back(x - 1); } int val = conv(v1, N); q.push_back(make_pair(make_pair(N, val), i)); } sort(q.begin(), q.end()); int curN = 0; for (int i = 0; i < q.size(); i++) { if (curN != q[i].first.first) { curN = q[i].first.first; GEN_SIZE = curN; memset(match, -1, sizeof(match)); int v = 1; for (int i = 0; i < GEN_SIZE; i++) { v *= GEN_SIZE; } for (int i = 0; i < v; i++) adj[i].clear(); recur(0); for (int i = 0; i < v; i++) { memset(vis, 0, sizeof(vis)); aug(i); } for (int i = 0; i < v; i++) match2[match[i]] = i; } vector<int> qv = unconv(q[i].first.second, curN); vector<int> v1 = unconv(match[q[i].first.second], curN); ans[q[i].second] = v1[qv[0]] + 1; } for (int i = 0; i < T; i++) printf( %d n , ans[i]); }
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#include <bits/stdc++.h> using namespace std; int main() { long long n, a[100001]; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; cout << 1 << << n << endl; cout << 0 << ; for (int i = 1; i < n; i++) cout << (n * (n - 1 - a[i])) << ; cout << endl; cout << 1 << << 1 << endl; cout << (-a[0]) << endl; if (n > 1) { cout << 2 << << n << endl; for (int i = 1; i < n; i++) cout << ((n - 1) * (a[i] - n)) << ; cout << endl; } else { cout << 1 << << 1 << endl; cout << 0 << endl; } return 0; }
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#include <bits/stdc++.h> const int mod = 1000000007; const int gmod = 3; const int inf = 1039074182; const double eps = 1e-9; const long long llinf = 2LL * inf * inf; template <typename T1, typename T2> inline void chmin(T1 &x, T2 b) { if (b < x) x = b; } template <typename T1, typename T2> inline void chmax(T1 &x, T2 b) { if (b > x) x = b; } inline void chadd(int &x, int b) { x += b - mod; x += (x >> 31 & mod); } template <typename T1, typename T2> inline void chadd(T1 &x, T2 b) { x += b; if (x >= mod) x -= mod; } template <typename T1, typename T2> inline void chmul(T1 &x, T2 b) { x = 1LL * x * b % mod; } template <typename T1, typename T2> inline void chmod(T1 &x, T2 b) { x %= b, x += b; if (x >= b) x -= b; } template <typename T> inline T mabs(T x) { return (x < 0 ? -x : x); } using namespace std; using namespace std; template <typename T> ostream &operator<<(ostream &cout, vector<T> vec) { cout << { ; for (int i = 0; i < (int)vec.size(); i++) { cout << vec[i]; if (i != (int)vec.size() - 1) cout << , ; } cout << } ; return cout; } template <typename T1, typename T2> ostream &operator<<(ostream &cout, pair<T1, T2> p) { cout << ( << p.first << , << p.second << ) ; return cout; } template <typename T, typename T2> ostream &operator<<(ostream &cout, set<T, T2> s) { vector<T> t; for (auto x : s) t.push_back(x); cout << t; return cout; } template <typename T, typename T2> ostream &operator<<(ostream &cout, multiset<T, T2> s) { vector<T> t; for (auto x : s) t.push_back(x); cout << t; return cout; } template <typename T> ostream &operator<<(ostream &cout, queue<T> q) { vector<T> t; while (q.size()) { t.push_back(q.front()); q.pop(); } cout << t; return cout; } template <typename T1, typename T2, typename T3> ostream &operator<<(ostream &cout, map<T1, T2, T3> m) { for (auto &x : m) { cout << Key: << x.first << << Value: << x.second << endl; } return cout; } template <typename T1, typename T2> void operator+=(pair<T1, T2> &x, const pair<T1, T2> y) { x.first += y.first; x.second += y.second; } template <typename T1, typename T2> pair<T1, T2> operator+(const pair<T1, T2> &x, const pair<T1, T2> &y) { return make_pair(x.first + y.first, x.second + y.second); } template <typename T1, typename T2> pair<T1, T2> operator-(const pair<T1, T2> &x, const pair<T1, T2> &y) { return make_pair(x.first - y.first, x.second - y.second); } template <typename T1, typename T2> pair<T1, T2> operator-(pair<T1, T2> x) { return make_pair(-x.first, -x.second); } template <typename T> vector<vector<T>> operator~(vector<vector<T>> vec) { vector<vector<T>> v; int n = vec.size(), m = vec[0].size(); v.resize(m); for (int i = 0; i < m; i++) { v[i].resize(n); } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { v[i][j] = vec[j][i]; } } return v; } void print0x(int x) { std::vector<int> vec; while (x) { vec.push_back(x & 1); x >>= 1; } std::reverse(vec.begin(), vec.end()); for (int i = 0; i < (int)vec.size(); i++) { std::cout << vec[i]; } std::cout << ; } template <typename T> void print0x(T x, int len) { std::vector<int> vec; while (x) { vec.push_back(x & 1); x >>= 1; } reverse(vec.begin(), vec.end()); for (int i = (int)vec.size(); i < len; i++) { putchar( 0 ); } for (size_t i = 0; i < vec.size(); i++) { std::cout << vec[i]; } std::cout << ; } vector<string> vec_splitter(string s) { s += , ; vector<string> res; while (!s.empty()) { res.push_back(s.substr(0, s.find( , ))); s = s.substr(s.find( , ) + 1); } return res; } void debug_out(vector<string> __attribute__((unused)) args, __attribute__((unused)) int idx, __attribute__((unused)) int LINE_NUM) { cerr << endl; } template <typename Head, typename... Tail> void debug_out(vector<string> args, int idx, int LINE_NUM, Head H, Tail... T) { if (idx > 0) cerr << , ; else cerr << Line( << LINE_NUM << ) ; stringstream ss; ss << H; cerr << args[idx] << = << ss.str(); debug_out(args, idx + 1, LINE_NUM, T...); } template <int mod> struct ModInt { int x; ModInt() { x = 0; } ModInt(int _x) { x = _x % mod; if (x < 0) x += mod; } ModInt(long long _x) { x = _x % mod; if (x < 0) x += mod; } ModInt<mod> &operator++() { ++x; if (x == mod) x = 0; return *this; } ModInt<mod> operator++(int) { int t = x; x++; if (x == mod) x = 0; return t; } ModInt<mod> &operator--() { --x; if (x == -1) x += mod; return *this; } ModInt<mod> operator--(int) { int t = x; x--; if (x == -1) x += mod; return t; } ModInt<mod> operator-() const { return ModInt<mod>((x == 0 ? 0 : mod - x)); } }; template <int mod> inline int mabs(const ModInt<mod> &a) { return a.x; } template <int mod> bool operator==(const ModInt<mod> &a, const ModInt<mod> &b) { return a.x == b.x; } template <int mod> bool operator==(ModInt<mod> a, int x) { return (a.x == x); } template <int mod> bool operator!=(const ModInt<mod> &a, const ModInt<mod> &b) { return (a.x != b.x); } template <int mod> bool operator!=(ModInt<mod> a, int x) { return (a.x != x); } template <int mod> inline ModInt<mod> operator+(ModInt<mod> a, int b) { a.x += b; if (a.x >= mod) a.x -= mod; return a; } template <int mod> inline ModInt<mod> operator+(ModInt<mod> a, ModInt<mod> b) { int tmp = a.x + b.x; if (tmp >= mod) tmp -= mod; return tmp; } template <int mod> inline ModInt<mod> operator-(ModInt<mod> a, ModInt<mod> b) { int tmp = a.x - b.x; if (tmp < 0) tmp += mod; return tmp; } template <int mod> inline ModInt<mod> operator-(ModInt<mod> a, int b) { return a - (ModInt<mod>)b; } template <int mod> inline void operator-=(ModInt<mod> &a, ModInt<mod> b) { a.x -= b.x; a.x += (a.x >> 31 & mod); } template <int mod, typename T> inline void operator-=(ModInt<mod> &a, const T &b) { a.x -= b; a.x += (a.x >> 31 & mod); } template <int mod> inline ModInt<mod> operator*(const ModInt<mod> &a, const ModInt<mod> &b) { return 1LL * a.x * b.x % mod; } template <int mod> inline ModInt<mod> operator*(const ModInt<mod> &a, const int &b) { return 1LL * a.x * b % mod; } template <int mod> inline void operator*=(ModInt<mod> &a, const ModInt<mod> &b) { a.x = 1LL * a.x * b.x % mod; } template <int mod, typename T> inline void operator*=(ModInt<mod> &a, const T &b) { a = a * b; } template <int mod> inline void operator+=(ModInt<mod> &a, const ModInt<mod> &b) { a.x += b.x; if (a.x >= mod) a.x -= mod; } template <int mod, typename T> void operator+=(ModInt<mod> &a, const T &b) { a.x += b; if (a.x >= mod) a.x -= mod; } template <int mod> inline ModInt<mod> mod_inv(ModInt<mod> x) { int m = mod - 2; ModInt<mod> basic = x; x = 1; while (m) { if (m & 1) x *= basic; m >>= 1; basic *= basic; } return x; } template <int mod> ModInt<mod> operator/(ModInt<mod> a, ModInt<mod> b) { return a * mod_inv(b); } template <int mod> ModInt<mod> operator/(ModInt<mod> a, int b) { return a * mod_inv((ModInt<mod>)b); } template <int mod> void operator/=(ModInt<mod> &a, int b) { a *= mod_inv(ModInt<mod>(b)); } template <int mod> void operator/=(ModInt<mod> &a, ModInt<mod> b) { a = a / b; } template <int mod> inline ModInt<mod> operator^(ModInt<mod> basic, int x) { ModInt<mod> res = 1; while (x) { if (x & 1) res *= basic; basic *= basic; x >>= 1; } return res; } template <int mod> istream &operator>>(istream &cin, ModInt<mod> &x) { cin >> x.x; x.x %= mod; if (x.x < 0) x.x += mod; return cin; } template <int mod> ostream &operator<<(ostream &cout, ModInt<mod> x) { cout << x.x; return cout; } template <int mod, int g, int LogN> struct NTT { using Int = ModInt<mod>; static const int MaxN = (1 << LogN); int w[MaxN + 5]; int fastpow(int basic, int x) { int res = 1; while (x) { if (x & 1) res = 1LL * res * basic % mod; basic = 1LL * basic * basic % mod; x >>= 1; } return res; } int inv[MaxN + 5]; int buf[MaxN + 5]; int ww[MaxN + 5]; inline void ntt(vector<int> &v, int rev, int lg) { int n = (1 << lg); memset(buf, 0, sizeof(int) * n); v.resize(n, 0); for (int i = 0; i < n; i++) { inv[i] = (inv[i >> 1] >> 1) | ((i & 1) << (lg - 1)); } for (int i = 0; i < n; i++) { buf[i] = v[inv[i]]; } int lvl = LogN; int *ba, *bb, *wa, *wb; int tmp; for (int b = 1; b < n; b *= 2) { lvl--; for (int i = 0; i < b * 2; i++) ww[i] = (rev ? w[MaxN - (i << lvl)] : w[i << lvl]); for (int i = 0; i < n; i += b * 2) { ba = buf + i; bb = buf + i + b; wa = ww; wb = ww + b; for (int j = 0; j < b; j++) { tmp = 1LL * *wa * *bb % mod; *bb = *ba - tmp; *ba += tmp; *ba -= mod; *ba += ((*ba) >> 31 & mod); *bb += ((*bb) >> 31 & mod); ba++; bb++; wa++; wb++; } } } int t = fastpow(n, mod - 2); if (rev) { for (int i = 0; i < (1 << lg); i++) { buf[i] = 1LL * buf[i] * t % mod; } } for (int i = 0; i < (1 << lg); i++) v[i] = buf[i]; } void multiply(vector<int> a, vector<int> b, vector<int> &c) { int n = (int)a.size() + b.size() - 1; if (min(a.size(), b.size()) <= 60) { c.clear(); c.resize(max(0, n), 0); for (int i = 0; i < (int)a.size(); i++) { for (int j = 0; j < (int)b.size(); j++) { c[i + j] = (1LL * a[i] * b[j] + c[i + j]) % mod; } } while (c.size() && c.back() == 0) c.pop_back(); } int nn = 1, lg = 0; while (nn < n) { nn <<= 1; lg++; } c.resize(nn); a.resize(nn, 0); b.resize(nn, 0); ntt(a, 0, lg); ntt(b, 0, lg); for (int i = 0; i < nn; i++) { c[i] = 1LL * a[i] * b[i] % mod; } ntt(c, 1, lg); while (c.size() && c.back() == 0) c.pop_back(); } void sqr(vector<int> &a) { int n = (int)a.size() + a.size() - 1; int nn = 1, lg = 0; while (nn < n) { nn <<= 1; lg++; } a.resize(nn, 0); ntt(a, 0, lg); for (int i = 0; i < nn; i++) { a[i] = 1LL * a[i] * a[i] % mod; } ntt(a, 1, lg); while (a.size() && a.back() == 0) a.pop_back(); } vector<Int> multiply(const vector<Int> &a, const vector<Int> &b) { vector<int> ta(a.size()), tb(b.size()); for (int i = 0; i < (int)a.size(); i++) ta[i] = a[i].x; for (int i = 0; i < (int)b.size(); i++) tb[i] = b[i].x; vector<int> tc; multiply(ta, tb, tc); vector<Int> c(tc.size()); for (int i = 0; i < (int)c.size(); i++) c[i].x = tc[i]; return c; } NTT() { w[0] = 1; int ur = fastpow(g, (mod - 1) >> LogN); for (int i = 1; i <= MaxN; i++) { w[i] = 1LL * w[i - 1] * ur % mod; } } }; using namespace std; int n, k; int fac[30005]; int ifac[30005]; inline int fastpow(long long basic, int x) { long long res = 1; while (x) { if (x & 1) (res *= basic) %= mod; (basic *= basic) %= mod; x >>= 1; } return res; } vector<int> Ex; vector<int> Ex1; inline int fastpow(long long basic, int x, int mod) { long long res = 1; while (x) { if (x & 1) (res *= basic) %= mod; (basic *= basic) %= mod; x >>= 1; } return res; } template <int mod> struct MTT { NTT<998244353, 3, 17> ntt1; NTT<469762049, 3, 17> ntt2; NTT<1004535809, 3, 17> ntt3; static const int p1 = 998244353; static const int p2 = 469762049; static const int p3 = 1004535809; vector<int> c1, c2, c3; inline void multiply(vector<int> a, vector<int> b, vector<int> &c) { ntt1.multiply(a, b, c1); ntt2.multiply(a, b, c2); ntt3.multiply(a, b, c3); c.clear(); int n = max({c1.size(), c2.size(), c3.size()}); c1.resize(n, 0); c2.resize(n, 0); c3.resize(n, 0); c.resize(n); for (int i = 0; i < n; i++) { int x = c1[i]; int y = c2[i]; int z = c3[i]; long long t = (1LL * (x - y + p1) * fastpow(p2, p1 - 2, p1) % p1 * p2 + y); c[i] = (1LL * ((z - t) % p3 + p3) % p3 * fastpow(p2, p3 - 2, p3) % p3 * fastpow(p1, p3 - 2, p3) % p3 * p1 % mod * p2 % mod + t % mod) % mod; } } }; MTT<mod> mtt; inline void multiply(vector<int> a, vector<int> b, vector<int> &c) { mtt.multiply(a, b, c); } inline vector<int> replacex(vector<int> x, int len) { int v = fastpow(2, len); for (int i = 0; i < x.size(); i++) { x[i] = 1LL * x[i] * fastpow(v, i) % mod; } return x; } vector<int> fastpow(int n) { vector<int> res; res.push_back(1); int len = 0; for (int i = 14; i >= 0; i--) { if ((1 << i) & n) multiply(replacex(res, 1), Ex1, res), len++; if (i) multiply(replacex(res, len), res, res), len <<= 1; if (res.size() > k) res.resize(k + 1); } return res; } int main() { fac[0] = 1; for (int i = 1; i <= 30000; i++) fac[i] = 1LL * fac[i - 1] * i % mod; for (int i = 0; i <= 30000; i++) ifac[i] = fastpow(fac[i], mod - 2); long long _n; cin >> _n >> k; if (_n > k) { cout << 0 << endl; exit(0); }; n = _n; for (int i = 0; i <= k; i++) Ex.push_back(ifac[i]); Ex1 = Ex; Ex1[0] = 0; vector<int> v = fastpow(n); multiply(v, Ex, v); cout << 1LL * v[k] * fac[k] % mod << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; using INT = long long; using pii = pair<int, int>; using pi3 = pair<int, pii>; int n, m; int nxt[100010]; int a[100010], b[100010]; set<pii> A, B; set<pi3> ans; int calc_max(int u, set<pair<int, int> > &st) { auto it = st.upper_bound({m - 1 - u, n + 100}); if (it == st.begin()) return 0; return (*--it).second; } int update_A(int u) { int id2 = calc_max(a[u], B); if (id2 == 0) return 0; int id1 = calc_max(b[id2], A); if (id1 == 0) return 0; ans.insert(pi3(a[id1] + b[id2], pii(id1, id2))); } int update_B(int u) { int id2 = calc_max(b[u], A); if (id2 == 0) return 0; int id1 = calc_max(a[id2], B); if (id1 == 0) return 0; ans.insert(pi3(a[id2] + b[id1], pii(id2, id1))); } int del_A(int u) { int id = calc_max(a[u], B); if (id == 0) return 0; if (calc_max(b[id], A) == u) { auto p = pi3(a[u] + b[id], pii(u, id)); if (ans.find(p) != ans.end()) ans.erase(p); } } int del_B(int u) { int id = calc_max(b[u], A); if (id == 0) return 0; if (calc_max(b[id], B) == u) { auto p = pi3(b[u] + a[id], pii(id, u)); if (ans.find(p) != ans.end()) ans.erase(p); } } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { int u; scanf( %d , &u); a[i] = u; A.insert({u, i}); } for (int i = 1; i <= n; i++) { int u; scanf( %d , &u); b[i] = u; B.insert({u, i}); } for (int i = 1; i <= n; i++) { update_A(i); update_B(i); } while (!A.empty()) { int u = 0, v = 0; pi3 p; if (!ans.empty()) p = *--ans.end(); if (ans.empty() || p.first < ((*--A.end()).first + (*--B.end()).first) % m) { u = (*--A.end()).second, v = (*--B.end()).second; } else u = p.second.first, v = p.second.second; printf( %d , (a[u] + b[v]) % m); del_A(u); del_B(v); A.erase({a[u], u}); B.erase({b[v], v}); auto it = A.lower_bound({a[u], u}); if (it != A.begin()) update_A((*--it).second); it = B.lower_bound({b[v], v}); if (it != B.begin()) update_B((*--it).second); } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xnor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-9; long double Dis(long long a, long long Y, long long b, long long YY) { return sqrt((long double)(b - a) * (b - a) + (Y - YY) * (Y - YY)); } struct PT { long long ID; long double len, Y; PT(long long _ID, long double _Y) { ID = _ID; Y = _Y; } bool operator<(const PT &a) const { return (Y < a.Y); } }; vector<PT> A, B; void BinSearch(vector<PT> &C, long double val, long long &low, long long &up) { long long i, med; up = C.size() - 1; low = 0; if (val >= C[up].Y) { low = max(up - 1, low); return; } if (val <= C[low].Y) { up = min(low + 1, up); return; } while ((up - low) > 1) { med = (up + low) / 2; if (C[med].Y < val) low = med; else up = med; } } int main() { long long i, n, m, a, b, temp; cin >> n >> m >> a >> b; for (i = 0; i < n; i++) { cin >> temp; A.push_back(PT(i + 1, temp)); A[i].len = Dis(0, 0, a, temp); } for (i = 0; i < m; i++) { cin >> temp; B.push_back(PT(i + 1, temp)); } for (i = 0; i < m; i++) { cin >> temp; B[i].len = temp; } sort(A.begin(), A.end()); sort(B.begin(), B.end()); long long ind1, ind2; long double ans, tmp1, tmp2, mini, tt; long long l, u; ans = 1e18; for (i = 0; i < m; i++) { tt = ((long double)a * B[i].Y) / ((long double)(b)); BinSearch(A, tt, l, u); tmp1 = Dis(a, A[u].Y, b, B[i].Y) + A[u].len; tmp2 = Dis(a, A[l].Y, b, B[i].Y) + A[l].len; mini = min(tmp1, tmp2); if (ans > (B[i].len + mini)) { if ((tmp1 < tmp2)) ind1 = A[u].ID, ans = B[i].len + tmp1; else ind1 = A[l].ID, ans = B[i].len + tmp2; ind2 = B[i].ID; } } cout << ind1 << << ind2 << endl; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O22A_PP_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_PP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, 1, -1}; double PI = 3.1415926535897932384626433832795; const long long oo = (long long)1e9 + 1; const double eps = 1e-9; const long long mod = 1000000007; string s; long long nb, ns, nc, pb, ps, pc, R; int main() { cin >> s; cin >> nb >> ns >> nc; cin >> pb >> ps >> pc; cin >> R; int cb = 0, cs = 0, cc = 0; for (int i = 0; s[i]; i++) if (s[i] == B ) cb++; else if (s[i] == S ) cs++; else cc++; long long l = 0, r = 1e15, ret = 0; while (l <= r) { long long mid = (l + r) >> 1; if (max(cb * mid - nb, 0ll) * pb + max(cs * mid - ns, 0ll) * ps + max(cc * mid - nc, 0ll) * pc <= R) ret = mid, l = mid + 1; else r = mid - 1; } cout << ret << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = (int)2 * 1e5 + 10; void solve() { long long n, m; cin >> n >> m; vector<long long> arr(n); for (long long i = 0; i < n; i += 1) { cin >> arr[i]; } sort((arr).begin(), (arr).end()); long long sum = 0; for (long long i = 0; i < m; i++) { if (arr[i] < 0) { sum += arr[i]; } } cout << abs(sum) << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 5000 + 100; int x[maxn][maxn], p[maxn], tx[maxn]; int n; int ask(int i, int j) { cout << ? << i << << j << endl; int r; cin >> r; return r; } void answer(int k) { cout << ! << endl; cout << k << endl; for (int i = 0; i < n; ++i) cout << p[i] << ; cout << endl; exit(0); } int main() { cin >> n; for (int i = 0; i < n; ++i) { int xo = ask(0, i); x[0][i] = xo; } for (int i = 1; i < n; ++i) { int xo = ask(i, i); for (int j = 0; j < n; ++j) { x[i][j] = xo ^ x[0][i] ^ x[0][j]; } } int xn = 0; for (int i = 0; i < n; ++i) xn ^= i; if (n & 1) { for (int i = 0; i < n; ++i) { int xnow = 0; for (int j = 0; j < n; ++j) xnow ^= x[i][j]; xnow ^= xn; p[i] = xnow; } answer(1); return 0; } for (int i = 0; i < n; ++i) tx[i] = (x[0][0] ^ x[i][0]); int ans = 0; for (int i = 0; i < n; ++i) { vector<int> tp(maxn); tp[0] = i; for (int j = 1; j < n; ++j) tp[j] = (tx[j] ^ tp[0]); bitset<maxn> v; bool good = true; vector<int> tb(maxn); for (int j = 0; j < n && good; ++j) { if (tp[j] >= n || tp[j] < 0) { good = false; break; } tb[tp[j]] = j; } for (int j = 0; j < n; ++j) { if ((tb[j] ^ tp[j]) != x[j][j]) good = false; } for (int j = 0; j < n && good; ++j) { if (tp[j] >= n || tp[j] < 0) { good = false; break; } if (v[tp[j]]) good = false; v[tp[j]] = true; } if (good) { ++ans; for (int j = 0; j < n; ++j) p[j] = tp[j]; } } answer(ans); return 0; }
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Require Import Coq.Classes.RelationClasses.
Require Import Coq.Reals.Rdefinitions.
Require Import ExtLib.Structures.Applicative.
Require Import ExtLib.Structures.Functor.
Require Import ExtLib.Data.Fun.
Require Import ExtLib.Tactics.
Require Import ChargeCore.Logics.ILogic.
Require Import ChargeCore.Logics.ILEmbed.
Require ChargeCore.Logics.ILInsts.
Require Import ChargeCore.Tactics.Tactics.
Require Import Temporal.ActionStream.
Section parametric.
Variable tlaState : Type.
Definition Var (T : Type) : Type := tlaState -> T.
Local Existing Instance Applicative_Fun.
Local Existing Instance Functor_Fun.
Definition StateVal (T : Type) : Type :=
tlaState -> T.
Definition DActionVal (T : Type) : Type :=
tlaState -> tlaState -> T.
Definition ActionVal (T : Type) : Type :=
tlaState -> Step tlaState -> T.
Definition TraceVal (T : Type) :=
trace tlaState -> T.
Definition StateProp := StateVal Prop.
Definition DActionProp := DActionVal Prop.
Definition ActionProp := ActionVal Prop.
Definition TraceProp := TraceVal Prop.
Global Instance ILogicOps_StateProp : ILogicOps StateProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogicOps_ActionProp : ILogicOps ActionProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogicOps_DActionProp : ILogicOps DActionProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogicOps_TraceProp : ILogicOps TraceProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogic_StateProp : ILogic StateProp := _.
Global Instance ILogic_ActionProp : ILogic ActionProp := _.
Global Instance ILogic_DActionProp : ILogic DActionProp := _.
Global Instance ILogic_TraceProp : ILogic TraceProp := _.
Local Transparent ILInsts.ILFun_Ops.
Global Instance EmbedOp_Prop_StateProp : EmbedOp Prop StateProp :=
{ embed := fun P _ => P }.
Global Instance Embed_Prop_StateProp : Embed Prop StateProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_Prop_ActionProp : EmbedOp Prop ActionProp :=
{ embed := fun P _ _ => P }.
Global Instance Embed_Prop_ActionProp : Embed Prop ActionProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_Prop_DActionProp : EmbedOp Prop DActionProp :=
{ embed := fun P _ _ => P }.
Global Instance Embed_Prop_DActionProp : Embed Prop DActionProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_Prop_TraceProp : EmbedOp Prop TraceProp :=
{ embed := fun P _ => P }.
Global Instance Embed_Prop_TraceProp : Embed Prop TraceProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_StateVal_StateProp : EmbedOp (StateVal Prop) StateProp :=
{ embed := fun P => P }.
Global Instance Embed_StateVal_StateProp : Embed (StateVal Prop) StateProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_ActionVal_ActionProp : EmbedOp (ActionVal Prop) ActionProp :=
{ embed := fun P => P }.
Global Instance Embed_ActionVal_ActionProp : Embed (ActionVal Prop) ActionProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_TraceVal_TraceProp : EmbedOp (TraceVal Prop) TraceProp :=
{ embed := fun P => P }.
Global Instance Embed_TraceVal_TraceProp : Embed (TraceVal Prop) TraceProp.
Proof.
constructor; simpl; intuition.
Qed.
(* These are the "obvious" definitions, needed to help Coq *)
Global Instance Applicative_Action
: Applicative ActionVal :=
{ pure := fun _ x => fun _ _ => x
; ap := fun _ _ f x => fun st st' => (f st st') (x st st')
}.
Global Instance Functor_Action
: Functor ActionVal :=
{ fmap := fun _ _ f x => ap (pure f) x }.
Global Instance Applicative_DAction
: Applicative DActionVal :=
{ pure := fun _ x => fun _ _ => x
; ap := fun _ _ f x => fun st st' => (f st st') (x st st')
}.
Global Instance Functor_DAction
: Functor DActionVal :=
{ fmap := fun _ _ f x => ap (pure f) x }.
Global Instance Applicative_State
: Applicative StateVal :=
{ pure := fun _ x => fun _ => x
; ap := fun _ _ f x => fun st => (f st) (x st)
}.
Global Instance Functor_State
: Functor StateVal :=
{ fmap := fun _ _ f x => ap (pure f) x }.
Definition now : StateProp -> TraceProp :=
fun P tr => P (hd tr).
(* This does not make sense
Definition next : StateProp -> TraceProp :=
fun P tr => P (hd (tl tr)).
*)
Definition always (P : TraceProp) : TraceProp :=
fun s =>
forall s', skips_to s s' -> P s'.
Definition eventually (P : TraceProp) : TraceProp :=
fun s =>
exists s', skips_to s s' /\ P s'.
Definition discretely (P : DActionProp) : ActionProp :=
fun start step =>
match step with
| DiscreteTo st' => P start st'
end.
Definition pre {T} (f : tlaState -> T) : DActionVal T :=
fun st _ => f st.
Definition post {T} (f : tlaState -> T) : DActionVal T :=
fun _ st' => f st'.
(*
Definition continuously (P : CActionProp) : ActionProp :=
fun start step =>
match step with
| ContinuousBy r f => P r (fun x => hybrid_join (f x) (snd (hybrid_split start)))
| _ => False
end.
*)
Definition stutter {T} (f : tlaState -> T) : DActionProp :=
fun st st' => f st = f st'.
Definition starts (P : ActionProp) : TraceProp :=
fun tr =>
P (hd tr) (firstStep tr).
Lemma always_skips_to : forall P t1 t2,
skips_to t1 t2 ->
always P t1 -> always P t2.
Proof.
unfold always. intros.
eapply H0. etransitivity; eauto.
Qed.
Definition through (P : TraceProp) : TraceProp :=
fun tr =>
match firstStep tr with
| DiscreteTo tr' =>
(** This is making an assumption about the underlying stream **)
P (tl tr)
end.
(** Always Facts **)
Lemma always_and : forall P Q,
always P //\\ always Q -|- always (P //\\ Q).
Proof.
intros. split.
{ red. red. simpl. unfold always. intuition. }
{ red. red. simpl. unfold always.
intuition; edestruct H; eauto. }
Qed.
Lemma always_or : forall P Q,
always P \\// always Q |-- always (P \\// Q).
Proof.
red. red. simpl. unfold always. intuition.
Qed.
Lemma always_impl : forall P Q,
always (P -->> Q) |-- always P -->> always Q.
Proof.
red. red. simpl. unfold always. intuition.
Qed.
Lemma always_tauto
: forall G P, |-- P -> G |-- always P.
Proof. compute; intuition. Qed.
(** Generic logic lemma **)
Lemma uncurry : forall P Q R,
(P //\\ Q) -->> R -|- P -->> Q -->> R.
Proof. compute. tauto. Qed.
Lemma and_forall : forall {T} (F G : T -> Prop),
((forall x, F x) /\ (forall x, G x)) <->
(forall x, F x /\ G x).
Proof. firstorder. Qed.
Lemma now_entails : forall (A B : StateProp),
now (A -->> B) |-- now A -->> now B.
Proof. unfold now. simpl. auto. Qed.
Definition before (P : StateProp) : ActionProp :=
fun st _ => P st.
(*
Definition after (P : StateProp) : DActionProp :=
fun _ st' => P st'.
*)
(*
Coercion starts : ActionProp >-> TraceProp.
Coercion discretely : DActionProp >-> ActionProp.
*)
Lemma now_starts_discretely_and : forall P Q,
now P //\\ starts Q -|- starts (before P //\\ Q).
Proof.
intros. split.
{ red; simpl. destruct t.
unfold starts, discretely; destruct c; simpl; tauto. }
{ red; simpl. destruct t.
unfold starts, discretely; destruct c; simpl; tauto. }
Qed.
(*
Lemma starts_next_impl : forall (P : DActionProp) (Q : StateProp),
starts (discretely (fun st st' => P st st' -> Q st')) |-- starts (discretely P) -->> through (now Q).
Proof.
intros.
{ red; simpl. destruct t.
unfold starts, discretely; destruct c; simpl. tauto.
tauto. }
Qed.
*)
Lemma starts_discretely_through : forall (P : DActionProp) (Q : StateProp),
(forall st, P st |-- Q) ->
|-- starts (discretely P) -->> through (now Q).
Proof.
intros. unfold starts, discretely, through.
red. simpl. intros.
forward_reason.
destruct t. destruct c. simpl in *.
unfold tl. simpl. red. simpl. eauto.
Qed.
Definition enabled (ap : ActionProp) : StateProp :=
Exists st', fun st => ap st st'.
(** Reasoning about [through] **)
Lemma through_and : forall P Q, through P //\\ through Q -|- through (P //\\ Q).
Proof.
intros. apply and_forall. intros.
unfold through. simpl. destruct (firstStep x); intuition; firstorder.
Qed.
Lemma through_or : forall P Q, through P \\// through Q |-- through (P \\// Q).
Proof.
intros. red. simpl.
unfold through. intro. destruct (firstStep t); intuition; firstorder.
Qed.
Lemma through_impl : forall P Q, through P -->> through Q |-- through (P -->> Q).
Proof.
intros. red. simpl.
unfold through. intro. destruct (firstStep t); intuition; firstorder.
Qed.
Lemma through_ex : forall T (P : T -> _),
Exists x : T, through (P x) |-- through (lexists P).
Proof.
intros; red; simpl.
unfold through. intro. intros.
destruct H. destruct (firstStep t); eauto.
Qed.
Lemma through_all : forall T (P : T -> _),
Forall x : T, through (P x) |-- through (lforall P).
Proof.
intros; red; simpl.
unfold through. intro. intros.
destruct (firstStep t); eauto.
Qed.
(*
Definition throughD (P : StateProp) : DActionProp :=
fun _ fin => P fin.
*)
(** This is induction over the phase changes **)
Lemma dind_lem : forall G P,
G |-- P -->> always (P -->> through P) -->> always P.
Proof.
intros. red. red.
red.
intros. red. simpl. red.
intros. clear H. clear G. revert H0 H1.
induction H2 using skips_to_ind; simpl.
{ (* Now *)
intros. assumption. }
{ (* AfterD *)
intros.
eapply IHskips_to.
{ red in H1.
eapply H1 in H0; try reflexivity.
eapply H0. }
{ eapply always_skips_to. 2: eapply H1.
eapply skips_to_next. reflexivity. } }
Qed.
Theorem hybrid_induction
: forall G P T,
G |-- always T ->
G |-- P ->
G |-- always (P -->> T -->> through P) ->
G |-- always P.
Proof.
intros G P T.
generalize (dind_lem G P).
unfold lentails, ILogicOps_TraceProp. simpl.
intros.
eapply H; eauto.
specialize (H2 _ H3).
specialize (H0 _ H3).
revert H2. revert H0.
clear. revert t.
cut (|-- always T -->> always (P -->> T -->> through P) -->> always (P -->> through P)).
{ intros. eapply H. exact I. auto. auto. }
{ rewrite <- uncurry.
rewrite always_and.
rewrite <- always_impl.
apply always_tauto.
charge_tauto. }
Qed.
End parametric.
Arguments pre {_ _} _ _ _.
Arguments post {_ _} _ _ _.
Arguments always {_} _ _.
Arguments eventually {_} _ _.
Arguments starts {_} _ _.
Arguments discretely {_} _ _ _.
Arguments now {_} _ _.
Arguments stutter {_ _} _ _ _.
Arguments through {_} _ _.
Export ChargeCore.Logics.ILogic.
|
#include <bits/stdc++.h> using namespace std; const long long M = 1e9 + 7; const long long N = 1e5 + 10; const long long INF = 1e9 + 7; vector<long long> fact(N), ifact(N); long long gcd(long long x, long long y) { if (y % x == 0) return x; return gcd(y % x, x); } long long inv(long long x) { long long res = 1; long long b = M - 2; while (b) { if (b & 1) res = (res * x) % M; x = (x * x) % M; b >>= 1; } return res; } bool prime[1000006]; void SieveOfEratosthenes(long long n) { for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long i = p * p; i <= n; i += p) prime[i] = false; } } } void init() { fact[0] = 1; for (long long i = 1; i < N; i++) fact[i] = (fact[i - 1] * i) % M; ifact[(long long)2e5] = inv(fact[(long long)2e5]); for (long long i = (long long)2e5 - 1; i >= 0; i--) ifact[i] = (ifact[i + 1] * (i + 1)) % M; } long long ncr(long long n, long long r) { if (r > n) return 0; long long res = fact[n]; res = (res * ifact[r]) % M; res = (res * ifact[n - r]) % M; return res; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long lowbit(long long x) { for (long long i = 0;; i++) { if (x & (1 << i)) return 1 << i; } } string decimal_to_binary(long long n) { long long t = 0; long long tt = n; while (tt > 0) { t++; tt /= 2; } bitset<32> s = bitset<32>(n); string str = ; for (long long i = 0; i < s.size(); i++) { str += s[i] + 0 ; } reverse(str.begin(), str.end()); return str; } bool checkPrime(long long x) { if (x == 1) { return false; } if (x <= 3) { return true; } long long t = 2; if (x % 2 == 0) { return false; } t = 3; for (t; t <= sqrt(x); t += 2) { if (x % t == 0) { return false; } } return true; } vector<long long> primeDivisor(long long x) { if (x <= 3) { vector<long long> r = {x}; return r; } long long n = floor(sqrt(x)); vector<long long> res; for (long long i = 2; i <= n; i++) { if (x % i == 0) { res.push_back(i); } while (x % i == 0) { x = x / i; } if (x < 2) { break; } } if (x > 2) { res.push_back(x); } return res; } struct comp { bool operator()(const pair<long long, long long> &x, const pair<long long, long long> &y) { return x.first < y.first; } }; void solve() { int a, b, c; cin >> a >> b >> c; int ans = 0; if (a) { a--; ans++; } if (b) { b--; ans++; } if (c) { c--; ans++; } if (c == 1) { if (a && b) { a--; b--; ans++; } if (a && c) { a--; c--; ans++; } if (b && c) { b--; c--; ans++; } } else { if (a && c) { a--; c--; ans++; } if (b && c) { b--; c--; ans++; } if (a && b) { a--; b--; ans++; } } if (a && b && c) { a--; b--; c--; ans++; } cout << ans << endl; return; } signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, c, d, a, b, i; cin >> n >> a >> b; c = b, d = c; for (i = 2; i <= n; i++) { cin >> a >> b; c = max(c, d - a + b); d = d - a + b; } cout << c; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int get_inv(int x) { return (x == 1) ? 1 : (mod - (long long)(mod / x) * get_inv(mod % x) % mod); } const int MaxN = 200010, MaxT = 1 << 19; struct tree_node { int k, sum; int lazy; tree_node() { k = lazy = 1; } } T[MaxT]; int v[MaxN], deg[MaxN]; class Graph { public: int en[MaxN], next[MaxN], point[MaxN], tot; void add_edge(int x, int y) { next[++tot] = en[x]; en[x] = tot; point[tot] = y; } } G; int in[MaxN], out[MaxN]; int n, q; int dfn; void dfs(int now) { in[now] = ++dfn; for (int i = G.en[now]; i; i = G.next[i]) dfs(G.point[i]); out[now] = dfn; } inline int mul(int &x, int v) { return (x = (long long)x * v % mod); } inline int inc(int x, int v) { x += v; return x >= mod ? x - mod : x; } void add_lazy(int now, int lazy) { mul(T[now].lazy, lazy); mul(T[now].k, lazy); mul(T[now].sum, lazy); } void push_down(int now) { if (T[now].lazy != 1) { add_lazy(now << 1, T[now].lazy); add_lazy(now << 1 | 1, T[now].lazy); T[now].lazy = 1; } } void update(int now) { T[now].sum = inc(T[now << 1].sum, T[now << 1 | 1].sum); } void modify_v(int l, int r, int x, int v, int now) { if (l == r) { T[now].sum = 1ll * T[now].k * v % mod; return; } int mid = (l + r) >> 1; push_down(now); if (x <= mid) modify_v(l, mid, x, v, now << 1); else modify_v(mid + 1, r, x, v, now << 1 | 1); update(now); } void modify_k(int l, int r, int x, int y, int k, int now) { if ((r < x) || (y < l)) return; if ((x <= l) && (r <= y)) return add_lazy(now, k); int mid = (l + r) >> 1; push_down(now); modify_k(l, mid, x, y, k, now << 1); modify_k(mid + 1, r, x, y, k, now << 1 | 1); update(now); } int query_k(int l, int r, int x, int now) { if (l == r) return T[now].k; int mid = (l + r) >> 1; push_down(now); if (x <= mid) return query_k(l, mid, x, now << 1); else return query_k(mid + 1, r, x, now << 1 | 1); } int query_sum(int l, int r, int x, int y, int now) { if ((r < x) || (y < l)) return 0; if ((x <= l) && (r <= y)) return T[now].sum; int mid = (l + r) >> 1; push_down(now); return inc(query_sum(l, mid, x, y, now << 1), query_sum(mid + 1, r, x, y, now << 1 | 1)); } void debug() { for (int i = 1; i <= 17; ++i) printf( %d: %d %d %d n , i, T[i].sum, T[i].k, T[i].lazy); } int main() { static int type[MaxN], f[MaxN], u[MaxN]; scanf( %d%d , v + 1, &q); n = 1; for (int i = 1; i <= q; ++i) { scanf( %d , type + i); if (type[i] == 1) { u[i] = ++n; scanf( %d%d , &f[n], &v[n]); G.add_edge(f[n], n); } else scanf( %d , u + i); } dfs(1); modify_v(1, n, in[1], v[1], 1); deg[1] = 1; for (int i = 1; i <= q; ++i) if (type[i] == 2) { int ans = query_sum(1, n, in[u[i]], out[u[i]], 1), k; if (u[i] == 1) k = 1; else k = query_k(1, n, in[f[u[i]]], 1); ans = (long long)ans * get_inv(k) % mod; printf( %d n , ans); } else { int k = (long long)(deg[f[u[i]]] + 1) * get_inv(deg[f[u[i]]]) % mod; ++deg[f[u[i]]]; modify_k(1, n, in[f[u[i]]], out[f[u[i]]], k, 1); deg[u[i]] = 1; modify_v(1, n, in[u[i]], v[u[i]], 1); } return 0; }
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#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979323846; void solve() { long long n, m, a, b, k, x, y, queries; string s; cin >> n >> s; s = G + s; long long i = 1; while (i <= n) { if (s[i] == 8 ) break; i++; } if (i + 10 <= n) cout << YES ; else cout << NO ; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { solve(); cout << endl; } return 0; }
|
/*******************************************************************************
* Module: resync_data
* Date:2015-12-22
* Author: Andrey Filippov
* Description: Resynchronize data between clock domains. No over/underruns
* are checker, start with half FIFO full. Async reset sets
* specifies output values regardless of the clocks
*
* Copyright (c) 2014 Elphel, Inc.
* resync_data.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* resync_data.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module resync_data
#(
parameter integer DATA_WIDTH=16,
parameter integer DATA_DEPTH=4, // >= 2
parameter INITIAL_VALUE = 0
) (
input arst, // async reset, active high (global)
input srst, // same as arst, but relies on the clocks
input wclk, // write clock - positive edge
input rclk, // read clock - positive edge
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
output reg [DATA_WIDTH-1:0] data_out, // output data
output reg valid // data valid @ rclk
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg [DATA_DEPTH-1:0] raddr;
reg [DATA_DEPTH-1:0] waddr;
reg [1:0] rrst = 3;
always @ (posedge rclk or posedge arst) begin
if (arst) valid <= 0;
else if (srst) valid <= 0;
else if (&waddr[DATA_DEPTH-2:0] && we) valid <= 1; // just once set and stays until reset
end
always @ (posedge wclk or posedge arst) begin
if (arst) waddr <= 0;
else if (srst) waddr <= 0;
else if (we) waddr <= waddr + 1;
end
always @ (posedge rclk or posedge arst) begin
if (arst) rrst <= 3;
else if (srst) rrst <= 3; // resync to rclk
else rrst <= rrst << 1;
if (arst) raddr <= 0;
else if (rrst[0]) raddr <= 0;
else if (re || rrst[1]) raddr <= raddr + 1;
if (arst) data_out <= INITIAL_VALUE;
else if (rrst[0]) data_out <= INITIAL_VALUE;
else if (re || rrst[1]) data_out <= ram[raddr];
end
always @ (posedge wclk) begin
if (we) ram[waddr] <= data_in;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_2_V
`define SKY130_FD_SC_HD__SDFSBP_2_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_2_V
|
#include <bits/stdc++.h> using namespace std; vector<int> Neighbors[2000000]; bool Visited[2000000]; bool Leaf[2000000]; char Color[500001]; queue<int> Queue; void bfs(int i) { Visited[i] = true; Queue.push(i); while (Queue.empty() == false) { int u = Queue.front(); Queue.pop(); Leaf[u] = true; for (int v = 0; v < Neighbors[u].size(); v++) if (Visited[Neighbors[u][v]] == false) { Visited[Neighbors[u][v]] = true; Queue.push(Neighbors[u][v]); Leaf[u] = false; } } } int main() { int T; scanf( %d , &T); for (int t = 1; t <= T; t++) { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) Neighbors[i].clear(); int u, v; for (int i = 0; i + 1 < n; i++) { scanf( %d %d , &u, &v); Neighbors[u].push_back(v); Neighbors[v].push_back(u); } scanf( %s , Color); if (n < 3) { printf( Draw n ); continue; } int n_ = n; for (int i = 1; i <= n; i++) if (Color[i - 1] == W ) { Neighbors[n_ + 1].clear(); Neighbors[n_ + 2].clear(); Neighbors[n_ + 3].clear(); Neighbors[i].push_back(n_ + 1); Neighbors[n_ + 1].push_back(i); Neighbors[n_ + 1].push_back(n_ + 2); Neighbors[n_ + 1].push_back(n_ + 3); Neighbors[n_ + 2].push_back(n_ + 1); Neighbors[n_ + 3].push_back(n_ + 1); n_ += 3; } n = n_; int won = 0; for (int i = 1; i <= n; i++) if (Neighbors[i].size() >= 4) { printf( White n ); won = 1; break; } if (won) continue; for (int i = 1; i <= n; i++) Visited[i] = 0; bfs(1); if (Neighbors[1].size() == 1) Leaf[1] = true; for (int i = 1; i <= n; i++) if (Neighbors[i].size() >= 3) { int leaves = 0; for (int j = 0; j < Neighbors[i].size(); j++) if (Leaf[Neighbors[i][j]]) leaves++; if (Neighbors[i].size() - leaves >= 2) { printf( White n ); won = 1; break; } } if (won) continue; int left = 1; while (left <= n && Neighbors[left].size() < 3) left++; int right = n; while (right > 0 && Neighbors[right].size() < 3) right--; if (left <= n && right > 0 && left < right) { int curr, prev = left; int len = 2; for (int i = 0; i < Neighbors[prev].size(); i++) if (Leaf[Neighbors[prev][i]] == 0) curr = Neighbors[prev][i]; while (curr != right) { if (Neighbors[curr][0] != prev) { prev = curr; curr = Neighbors[curr][0]; } else { prev = curr; curr = Neighbors[curr][1]; } len++; } if (len % 2 == 1) { printf( White n ); continue; } } printf( Draw n ); } return 0; }
|
`timescale 1ns/1ps
module test();
reg clock, reset;
sopc sopc(
.clock(clock),
.reset(reset)
);
always #1 clock = ~clock;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
$dumpvars(0, sopc.cpu.register.storage[1]);
$dumpvars(0, sopc.cpu.register.storage[2]);
$dumpvars(0, sopc.cpu.register.storage[3]);
$dumpvars(0, sopc.cpu.register.storage[4]);
$readmemh("rom.txt", sopc.rom.storage);
clock = 1'b0;
reset = 1'b1;
#20 reset = 1'b0;
#10 `AR(1, 32'h00008000); `AR(2, 32'hxxxxxxxx); `AR(3, 32'hxxxxxxxx); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000000); `AR(2, 32'hxxxxxxxx); `AR(3, 32'hxxxxxxxx); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'hxxxxxxxx); `AR(3, 32'hxxxxxxxx); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h00008000); `AR(3, 32'hxxxxxxxx); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000000); `AR(3, 32'hxxxxxxxx); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'hxxxxxxxx); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'h00000000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'h00000011); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'h00000000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'h00000000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'h80000010); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'h0000000F); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'h00000011); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'h00000000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h80000010); `AR(2, 32'h80000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h0000FFFF); `AR(2, 32'h80000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFF0000); `AR(2, 32'h80000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFF0000); `AR(2, 32'h00000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFF0000); `AR(2, 32'h00000000); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFF0000); `AR(2, 32'h00000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFF0000); `AR(2, 32'h00000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h00000000); `AR(2, 32'h00000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h00000000); `AR(2, 32'h00000000); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h00000000); `AR(2, 32'h00000020); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFF0000); `AR(2, 32'h00000020); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFFFFFF); `AR(2, 32'h00000020); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFFFFFF); `AR(2, 32'h00000000); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFFFFFF); `AR(2, 32'h00000020); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hA1000000); `AR(2, 32'h00000020); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hA1000000); `AR(2, 32'h00000000); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hA1000000); `AR(2, 32'h00000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h11000000); `AR(2, 32'h00000001); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h11000000); `AR(2, 32'h00000003); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h11000000); `AR(2, 32'h00000000); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'h0000FFFF); `AR(2, 32'h00000000); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFF0000); `AR(2, 32'h00000000); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFFFFFB); `AR(2, 32'h00000000); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFFFFFB); `AR(2, 32'h00000006); `AR(3, 32'hFFFF8000); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFFFFFB); `AR(2, 32'h00000006); `AR(3, 32'hFFFFFFE2); `AHI(32'h00000000); `ALO(32'h00000000);
#2 `AR(1, 32'hFFFFFFFB); `AR(2, 32'h00000006); `AR(3, 32'hFFFFFFE2); `AHI(32'hFFFFFFFF); `ALO(32'hFFFFFFE2);
#2 `AR(1, 32'hFFFFFFFB); `AR(2, 32'h00000006); `AR(3, 32'hFFFFFFE2); `AHI(32'h00000005); `ALO(32'hFFFFFFE2);
`PASS;
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_frame (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 0;
parameter max_cks = 0;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_FRAME";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
//
if ((max_cks > 0) && (min_cks > max_cks)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal parameter values set where min_cks > max_cks");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_frame_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_frame_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_frame_psl_logic.v"
`else
`endmodule // ovl_frame
`endif
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T& num) { bool start = false, neg = false; char c; num = 0; while ((c = getchar()) != EOF) { if (c == - ) start = neg = true; else if (c >= 0 && c <= 9 ) { start = true; num = num * 10 + c - 0 ; } else if (start) break; } if (neg) num = -num; } inline int Q(int x, int y) { printf( 0 %d %d n , x, y); fflush(stdout); scanf( %d , &x); return x; } set<int> c; void dfs(int l, int r) { if (l > r) return; int mid = l + (r - l) / 2; int d = Q(mid, mid); if (!d) c.insert(mid), d++; dfs(l, mid - d); dfs(mid + d, r); } set<int> V, H; int main() { int n = 0, m = 0; int mx = (int)(1e8); dfs(-mx, mx); int s = mx; for (; c.count(s); s--) ; for (set<int>::iterator it = c.begin(); it != c.end(); it++) { int x = (*it); if (!Q(x, s)) V.insert(x), ++n; if (!Q(s, x)) H.insert(x), ++m; } printf( 1 %d %d n , n, m); for (set<int>::iterator it = V.begin(); it != V.end(); it++) printf( %d , (*it)); putchar( n ); for (set<int>::iterator it = H.begin(); it != H.end(); it++) printf( %d , (*it)); putchar( n ); fflush(stdout); return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** Reset logic for HIP +
//*/
module pcie_4243_hip_s4gx_gen2_x8_128_rs_hip (
// inputs:
dlup_exit,
hotrst_exit,
l2_exit,
ltssm,
npor,
pld_clk,
test_sim,
// outputs:
app_rstn,
crst,
srst
)
;
output app_rstn;
output crst;
output srst;
input dlup_exit;
input hotrst_exit;
input l2_exit;
input [ 4: 0] ltssm;
input npor;
input pld_clk;
input test_sim;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg app_rstn;
reg app_rstn0;
reg crst;
reg crst0;
reg [ 4: 0] dl_ltssm_r;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
wire otb0;
wire otb1;
reg [ 10: 0] rsnt_cntn;
reg srst;
reg srst0;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
//pipe line exit conditions
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
dlup_exit_r <= otb1;
hotrst_exit_r <= otb1;
l2_exit_r <= otb1;
exits_r <= otb0;
end
else
begin
dlup_exit_r <= dlup_exit;
hotrst_exit_r <= hotrst_exit;
l2_exit_r <= l2_exit;
exits_r <= (l2_exit_r == 1'b0) | (hotrst_exit_r == 1'b0) | (dlup_exit_r == 1'b0) | (dl_ltssm_r == 5'h10);
end
end
//LTSSM pipeline
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
dl_ltssm_r <= 0;
else
dl_ltssm_r <= ltssm;
end
//reset Synchronizer
always @(posedge pld_clk or negedge npor)
begin
if (npor == 0)
begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end
else
begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
end
end
//reset counter
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
rsnt_cntn <= 0;
else if (exits_r == 1'b1)
rsnt_cntn <= 11'h3f0;
else if (rsnt_cntn != 11'd1024)
rsnt_cntn <= rsnt_cntn + 1;
end
//sync and config reset
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
app_rstn0 <= 0;
srst0 <= 1;
crst0 <= 1;
end
else if (exits_r == 1'b1)
begin
srst0 <= 1;
crst0 <= 1;
app_rstn0 <= 0;
end
else // synthesis translate_off
if ((test_sim == 1'b1) & (rsnt_cntn >= 11'd32))
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
else // synthesis translate_on
if (rsnt_cntn == 11'd1024)
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
end
//sync and config reset pipeline
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
app_rstn <= 0;
srst <= 1;
crst <= 1;
end
else
begin
app_rstn <= app_rstn0;
srst <= srst0;
crst <= crst0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n = 0, k[10000001], a, b, c; void nhap() { cin >> a >> b >> c; } void solve() { k[n] = a + b + c; n++; k[n] = a * b * c; n++; k[n] = (a + b) * c; n++; k[n] = a * (b + c); n++; k[n] = a + b * c; n++; k[n] = a * b + c; n++; sort(k, k + n); cout << k[n - 1]; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); nhap(); solve(); }
|
#include <bits/stdc++.h> using namespace std; double dist(double x1, double y1, double x2, double y2) { double dx = x1 - x2; double dy = y1 - y2; return sqrt(dx * dx + dy * dy); } double catet(double a, int b) { double z = a * a - b * b; if (z < 1e-12) z = 0; return sqrt(z); } int main() { int xp, yp, vp; cin >> xp >> yp >> vp; int x, y, v, r; cin >> x >> y >> v >> r; const double eps = 1e-10; const double R = sqrt(1.0 * xp * xp + 1.0 * yp * yp); double lo = 0; double hi = 1e7; double T; while ((hi - lo) / hi > eps) { T = (lo + hi) / 2; const double alpha = T / (R / vp); double nx = xp * cos(alpha) - yp * sin(alpha); double ny = xp * sin(alpha) + yp * cos(alpha); double a = ny - y; double b = x - nx; double c = -(a * x + b * y); double z = sqrt(a * a + b * b); a /= z; b /= z; c /= z; double need; if (fabs(c) < r - 1e-8) { double mx = a * (-c); double my = b * (-c); if (dist(x, y, mx, my) + dist(mx, my, nx, ny) > dist(x, y, nx, ny) + 1e-8) { need = dist(x, y, nx, ny); } else { need = catet(dist(x, y, 0, 0), r) + catet(dist(nx, ny, 0, 0), r); double alp = fabs(atan2(y, x) - atan2(ny, nx)); if (alp > M_PI) alp = 2 * M_PI - alp; alp -= acos(r / dist(x, y, 0, 0)); alp -= acos(r / dist(nx, ny, 0, 0)); need += alp * r; } } else { need = dist(x, y, nx, ny); } if (need <= v * T) { hi = T; } else { lo = T; } } printf( %.6f n , T); return 0; }
|
#include <bits/stdc++.h> int main() { int i = 0, j = 0, l, k; char a[100], s[100], shift; scanf( %c , &shift); scanf( %s , a); l = strlen(a); for (k = 0; k < l; k++) { if (shift == R && i <= l && a[i] == w ) { a[i] = q ; i++; } else if (shift == R && i <= l && a[i] == e ) { a[i] = w ; i++; } else if (shift == L && j < l && a[j] == w ) { a[j] = e ; j++; } else if (shift == R && i <= l && a[i] == r ) { a[i] = e ; i++; } else if (shift == L && j < l && a[j] == e ) { a[j] = r ; j++; } else if (shift == R && i <= l && a[i] == t ) { a[i] = r ; i++; } else if (shift == L && j < l && a[j] == r ) { a[j] = t ; j++; } else if (shift == R && i <= l && a[i] == y ) { a[i] = t ; i++; } else if (shift == L && j < l && a[j] == t ) { a[j] = y ; j++; } else if (shift == R && i <= l && a[i] == u ) { a[i] = y ; i++; } else if (shift == L && j < l && a[j] == y ) { a[j] = u ; j++; } else if (shift == R && i <= l && a[i] == i ) { a[i] = u ; i++; } else if (shift == L && j < l && a[j] == u ) { a[j] = i ; j++; } else if (shift == R && i <= l && a[i] == o ) { a[i] = i ; i++; } else if (shift == L && j < l && a[j] == i ) { a[j] = o ; j++; } else if (shift == R && i <= l && a[i] == p ) { a[i] = o ; i++; } else if (shift == L && j < l && a[j] == o ) { a[j] = p ; j++; } else if (shift == R && i <= l && a[i] == s ) { a[i] = a ; i++; } else if (shift == L && j < l && a[j] == a ) { a[j] = s ; j++; } else if (shift == R && i <= l && a[i] == d ) { a[i] = s ; i++; } else if (shift == L && j < l && a[j] == s ) { a[j] = d ; j++; } else if (shift == R && i <= l && a[i] == f ) { a[i] = d ; i++; } else if (shift == L && j < l && a[j] == d ) { a[j] = f ; j++; } else if (shift == R && i <= l && a[i] == g ) { a[i] = f ; i++; } else if (shift == L && j < l && a[j] == f ) { a[j] = g ; j++; } else if (shift == R && i <= l && a[i] == h ) { a[i] = g ; i++; } else if (shift == L && j < l && a[j] == g ) { a[j] = h ; j++; } else if (shift == R && i <= l && a[i] == j ) { a[i] = h ; i++; } else if (shift == L && j < l && a[j] == h ) { a[j] = j ; j++; } else if (shift == R && i <= l && a[i] == k ) { a[i] = j ; i++; } else if (shift == L && j < l && a[j] == j ) { a[j] = k ; j++; } else if (shift == R && i <= l && a[i] == l ) { a[i] = k ; i++; } else if (shift == L && j < l && a[j] == k ) { a[j] = l ; j++; } else if (shift == R && i <= l && a[i] == ; ) { a[i] = l ; i++; } else if (shift == L && j < l && a[j] == l ) { a[j] = ; ; j++; } else if (shift == R && i <= l && a[i] == x ) { a[i] = z ; i++; } else if (shift == L && j < l && a[j] == z ) { a[j] = x ; j++; } else if (shift == R && i <= l && a[i] == c ) { a[i] = x ; i++; } else if (shift == L && j < l && a[j] == x ) { a[j] = c ; j++; } else if (shift == R && i <= l && a[i] == v ) { a[i] = c ; i++; } else if (shift == L && j < l && a[j] == c ) { a[j] = v ; j++; } else if (shift == R && i <= l && a[i] == b ) { a[i] = v ; i++; } else if (shift == L && j < l && a[j] == v ) { a[j] = b ; j++; } else if (shift == R && i <= l && a[i] == n ) { a[i] = b ; i++; } else if (shift == L && j < l && a[j] == b ) { a[j] = n ; j++; } else if (shift == R && i <= l && a[i] == m ) { a[i] = n ; i++; } else if (shift == L && j < l && a[j] == n ) { a[j] = m ; j++; } else if (shift == R && i <= l && a[i] == , ) { a[i] = m ; i++; } else if (shift == L && j < l && a[j] == m ) { a[j] = , ; j++; } else if (shift == R && i <= l && a[i] == . ) { a[i] = , ; i++; } else if (shift == L && j < l && a[j] == , ) { a[j] = . ; j++; } else if (shift == R && i <= l && a[i] == / ) { a[i] = . ; i++; } else if (shift == L && j < l && a[j] == . ) { a[j] = / ; j++; } else if (shift == L && j < l && a[j] == q ) { a[j] = w ; j++; } } printf( %s , a); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: hash_calculation.v
// Project: ngnp
// Description: calculates the 4 bit hash value
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module hash_calculation(
input core_sp_clk,
input [31:0] instruction_sec_mon,
input [13:2] read_address,
input hash_int_ACK,
input reset,
output [3:0] hash_value,
output new_inst_signal
);
reg [5:0] data;
reg [3:0] hash_result;
wire [31:0] instruction_old_value;
reg [31:0] instruction_old_value_reg;
//wire new_inst_signal;
reg new_inst_signal_reg;
reg [11:0] read_address_reg;
reg [11:0] read_address_old_value_reg;
reg new_inst_signal_reg_test;
// Calculating the 4 bit hash value
always @ (posedge core_sp_clk) begin
if(reset) begin
data = 6'b000000;
hash_result = 4'b0000;
instruction_old_value_reg <= instruction_sec_mon;
read_address_old_value_reg <= read_address_reg;
end
else begin
if(hash_int_ACK) begin
instruction_old_value_reg <= instruction_sec_mon;
read_address_old_value_reg <= read_address_reg;
end
else begin
instruction_old_value_reg <= 32'hffffffff;
read_address_old_value_reg <= 12'hfff;
end
if((instruction_sec_mon != instruction_old_value) && (hash_int_ACK)) begin
data = (( instruction_sec_mon[0] + instruction_sec_mon[1] + instruction_sec_mon[2] + instruction_sec_mon[3] + instruction_sec_mon[4] + instruction_sec_mon[5] + instruction_sec_mon[6] + instruction_sec_mon[7] + instruction_sec_mon[8] + instruction_sec_mon[9] + instruction_sec_mon[10] + instruction_sec_mon[11] + instruction_sec_mon[12] + instruction_sec_mon[13] + instruction_sec_mon[14] + instruction_sec_mon[15] + instruction_sec_mon[16] + instruction_sec_mon[17] + instruction_sec_mon[18] + instruction_sec_mon[19] + instruction_sec_mon[20] + instruction_sec_mon[21]+ instruction_sec_mon[22]+ instruction_sec_mon[23]+ instruction_sec_mon[24]+ instruction_sec_mon[25]+ instruction_sec_mon[26]+ instruction_sec_mon[27]+ instruction_sec_mon[28]+ instruction_sec_mon[29]+ instruction_sec_mon[30]+ instruction_sec_mon[31]));
hash_result = (data%16);
new_inst_signal_reg = 1'b1;
end
else
new_inst_signal_reg =1'b0;
if((read_address_reg != read_address_old_value_reg) && (hash_int_ACK)) begin
new_inst_signal_reg_test = 1'b1;
end
else
new_inst_signal_reg_test = 1'b0;
end
end
always@(posedge core_sp_clk) begin
if(reset) begin
read_address_reg = 0;
end
else begin
read_address_reg <= read_address;
end
end
assign instruction_old_value = instruction_old_value_reg;
assign hash_value = hash_result;
//assign new_inst_signal =new_inst_signal_reg;
assign new_inst_signal =new_inst_signal_reg_test;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[4], leaf; vector<int> son[5140]; void no() { puts( NO ); exit(0); } void init() { scanf( %d , &n); for (int i = 0; i < 4; i++) scanf( %d , &a[i]); for (int i = 2; i <= n; i++) { int pi; scanf( %d , &pi); son[pi].push_back(i); } for (int i = 1; i <= n; i++) if (son[i].empty()) leaf++; if (leaf & 1) no(); } int sz[5140]; vector<int> items; int go(int now) { int who = -1; if (son[now].empty()) { sz[now] = 1; for (int i = 0; i < 4; i++) if (now == a[i]) who = i; return who; } vector<int> wt; for (int s : son[now]) { int ret = go(s); if (ret == -1) wt.push_back(sz[s]); else { who = ret; if (who > 1) wt.push_back(sz[s]); } } if (who == -1 or who > 1) { sz[now] = 0; for (auto i : wt) sz[now] += i; } else { for (auto i : wt) items.push_back(i); } return who; } bool dp[5140]; void knapsack(int tar) { if (tar < 0 or tar >= 5140) no(); for (int i = 0; i <= tar; i++) dp[i] = false; dp[0] = true; for (auto i : items) for (int j = tar - i; j >= 0; j--) dp[j + i] |= dp[j]; if (not dp[tar]) no(); } void solve() { for (int _ = 0; _ < 2; _++) { items.clear(); int cand = (leaf - 2) >> 1; for (int s : son[1]) { int ret = go(s); if (ret == -1) items.push_back(sz[s]); else if (ret == 2) cand -= sz[s]; } knapsack(cand); swap(a[0], a[2]); swap(a[1], a[3]); } puts( YES ); } int main() { init(); solve(); }
|
//***************************************************--
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan UniYVERsity
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//*****************************************************
// Filename : db_controller.v
// AutYHOR : Chewein
// Created : 2014-04-18
// Description : generate the top controller signals
//*****************************************************
module db_controller(
clk ,
rst_n ,
start_i ,
//output
done_o ,
cnt_r ,
state
);
//***********************************************************************************************************************************************
//
// INPUT / OUTPUT DECLARATION
//
//***********************************************************************************************************************************************
input clk ;
input rst_n ;
input start_i ;
output reg done_o ;
output reg [8:0] cnt_r ;
output reg [2:0] state ;
//***********************************************************************************************************************************************
//
// TOP Controller signals
//
//***********************************************************************************************************************************************
parameter IDLE = 3'b000, LOAD = 3'b001, YVER = 3'b011,YHOR =3'b010;
parameter CVER = 3'b110, CHOR = 3'b111, OUTLT = 3'b101,OUT =3'b100;
reg [2:0] next ;
reg [8:0] cycles ;
reg isluma ;
reg isver ;
always@* begin
case(state)
LOAD :cycles = 'd384 ;
YVER :cycles = 'd132 ;
YHOR :cycles = 'd140 ;
CVER :cycles = 'd68 ;
CHOR :cycles = 'd76 ;
OUTLT :cycles = 'd67 ;
OUT :cycles = 'd384 ;
default :cycles = 'd0 ;
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!(rst_n))
cnt_r <= 8'd0;
else if(!state)
cnt_r <= 8'd0;
else if(cnt_r == cycles)
cnt_r <= 8'd0;
else
cnt_r <= cnt_r + 1'b1;
end
always @* begin
case(state)
IDLE:begin
if(start_i)
next = LOAD ;
else
next = IDLE ;
end
LOAD:begin
if(cnt_r == cycles)
next = YVER ;
else
next = LOAD ;
end
YVER:begin
if(cnt_r == cycles)
next = YHOR ;
else
next = YVER ;
end
YHOR:begin
if(cnt_r == cycles)
next = CVER ;
else
next = YHOR ;
end
CVER:begin
if(cnt_r == cycles)
next = CHOR ;
else
next = CVER ;
end
CHOR:begin
if(cnt_r == cycles)
next = OUTLT ;
else
next = CHOR ;
end
OUTLT:begin
if(cnt_r == cycles)
next = OUT ;
else
next = OUTLT ;
end
OUT:begin
if(cnt_r == cycles)
next = IDLE ;
else
next = OUT ;
end
endcase
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
state <= IDLE ;
else
state <= next ;
end
wire done_w = (state==OUT)?1'b1:1'b0;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
done_o <= 1'b0 ;
else if(next==IDLE)
done_o <= done_w ;
else
done_o <= 1'b0 ;
end
always @* begin
case(state)
YVER,
YHOR:isluma = 1'b1;
default:isluma = 1'b0;
endcase
end
always @* begin
case(state)
YVER,
CVER:isver = 1'b1;
default:isver = 1'b0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 7; const int inf = 1e9 + 7; int T, n, dp[N][N], cnt[N], qzs[N][26], qzt[N][26]; char s[N], t[N]; void Min(int &x, int y) { if (x > y) x = y; } void Main() { fill(cnt, cnt + 26, 0); scanf( %d , &n); for (int i = 0, iE = n; i <= iE; i++) for (int j = 0, jE = n; j <= jE; j++) dp[i][j] = inf; scanf( %s%s , s + 1, t + 1); for (int i = 1, iE = n; i <= iE; i++) cnt[s[i] - a ]++, cnt[t[i] - a ]--; for (int i = 0, iE = 25; i <= iE; i++) if (cnt[i]) return puts( -1 ), void(); for (int i = 1, iE = n; i <= iE; i++) for (int j = 0, jE = 25; j <= jE; j++) qzs[i][j] = qzs[i - 1][j] + (s[i] == a + j), qzt[i][j] = qzt[i - 1][j] + (t[i] == a + j); for (int i = 0, iE = n; i <= iE; i++) dp[0][i] = 0; for (int i = 1, iE = n; i <= iE; i++) for (int j = i, jE = n; j <= jE; j++) { Min(dp[i][j], dp[i - 1][j] + 1); if (s[i] == t[j]) Min(dp[i][j], dp[i - 1][j - 1]); if (qzs[i][t[j] - a ] < qzt[j][t[j] - a ]) Min(dp[i][j], dp[i][j - 1]); } printf( %d n , dp[n][n]); } int main() { scanf( %d , &T); while (T--) Main(); return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx2;
wire unxunused_resetxx3;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx2 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
//**********************************************************************
// Reset
// ______ _______ ______ _______ _______
// (_____ \(_______)/ _____|_______|_______)
// _____) )_____ ( (____ _____ _
// | __ /| ___) \____ \| ___) | |
// | | \ \| |_____ _____) ) |_____ | |
// |_| |_|_______|______/|_______) |_|
//
//**********************************************************************
`include "bsg_defines.v"
module bsg_nonsynth_reset_gen #(parameter num_clocks_p=1
, parameter `BSG_INV_PARAM(reset_cycles_lo_p)
, parameter `BSG_INV_PARAM(reset_cycles_hi_p))
(input bit [num_clocks_p-1:0] clk_i
, output bit async_reset_o);
genvar i;
// This module relies on the input clock wires starting at 0 at
// time 0 and not transitioning from X to 0 at time 0, and causing
// a spurious negedge. To accomplish this in > VCS 2020, the input
// must be declared as a bit. Moreover, the expectation is that
// this module's input comes from a clock generation module that
// uses bit, such as bsg_nonsynth_clk_gen, AND that the wire
// between them is a bit.
// use bit instead of logic to default to 0 initialization value
// this makes it non-synthesizeable, but also allows X prop mode to work
bit [num_clocks_p-1:0][$clog2(reset_cycles_lo_p+1)-1:0] ctr_lo_r;
bit [num_clocks_p-1:0][$clog2(reset_cycles_hi_p+1)-1:0] ctr_hi_r;
bit [num_clocks_p-1:0] phase_lo_r;
bit [num_clocks_p-1:0] phase_hi_r;
wire in_phase_1 = & phase_lo_r;
wire in_phase_2 = & phase_hi_r;
for (i = 0; i < num_clocks_p; i=i+1)
begin : rof
assign phase_lo_r[i] = (ctr_lo_r[i] == reset_cycles_lo_p);
assign phase_hi_r[i] = (ctr_hi_r[i] == reset_cycles_hi_p);
always @(negedge clk_i[i])
if (~phase_lo_r[i])
ctr_lo_r[i] <= ctr_lo_r[i] + 1;
else if (~phase_hi_r[i])
ctr_hi_r[i] <= ctr_hi_r[i] + in_phase_1;
end
assign async_reset_o = (in_phase_1 ^ in_phase_2);
always @(negedge async_reset_o)
begin
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | 1->0 time = ",$stime);
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" ASYNC \\/ \\/ \\/ \\/ ");
end
always @(posedge async_reset_o)
begin
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | 0->1 time = ",$stime);
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" ASYNC \\/ \\/ \\/ \\/ ");
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_reset_gen)
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; vector<vector<int>> g(n); for (int i = 0; i < n - 1; ++i) { int x, y; cin >> x >> y; --x; --y; g[x].push_back(y); g[y].push_back(x); } int ans = 1; function<int(int, int)> dfs = [&](int v, int pv) { if ((int)g[v].size() == 1) { return 0; } vector<int> d; for (int to : g[v]) { if (to == pv) { continue; } d.push_back(1 + dfs(to, v)); } sort(d.begin(), d.end()); while ((int)d.size() >= 2) { if (d.back() + d[(int)d.size() - 2] <= k) { break; } ++ans; d.pop_back(); } return d.back(); }; for (int i = 0; i < n; ++i) { if ((int)g[i].size() > 1) { dfs(i, -1); break; } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long labs(long long a) { return a < 0 ? (-a) : a; } template <typename T> inline T sqr(T x) { return x * x; } void ImportMem(); string ToStr(int smpl, int sz) { ostringstream oss; oss << smpl; string test = oss.str(); while (test.size() < sz) test = 0 + test; return test; } string ToStr3(int smpl) { return ToStr(smpl, 3); } const int TH = 3; const int MAXTR = 50; const int STR_MAX = 5; const int STR_MIN = 3; const int NUMSZ = 4; const int TAKE_CNT = 5; const double LAPL = 1; map<string, int> mem[TH]; int sum[TH]; void ProcessStr(string& s) { while (!s.empty() && !isalnum(s[s.size() - 1])) { s = s.substr(0, s.size() - 1); } while (!s.empty() && !isalnum(s[0])) { s = s.substr(1, s.size() - 1); } if (s.empty()) return; bool num = true; bool waspt = false; for (int(i) = 0; (i) < (s.size()); (i)++) { if (!isdigit(s[i]) && (waspt || s[i] != . && s[i] != , )) { num = false; break; } if (s[i] == . || s[i] == , ) waspt = true; } if (num) { s.clear(); return; } if (s.size() < STR_MIN) { s.clear(); return; } s = s.substr(0, min((int)s.size(), STR_MAX)); for (int(i) = 0; (i) < (s.size()); (i)++) { s[i] = tolower(s[i]); } } void ParseFile(int theme, ifstream& fin) { string str; while (fin >> str) { ProcessStr(str); if (str.empty()) continue; mem[theme][str]++; sum[theme]++; } } void Train() { for (int(th) = 0; (th) < (TH); (th)++) { for (int(smpl) = 1; (smpl) <= (MAXTR); (smpl)++) { string test = ToStr3(smpl); string file = train + string(1, 1 + th) + + test + .txt ; ifstream fin(file.c_str()); string tstr; getline(fin, tstr); ParseFile(th, fin); fin.close(); } } for (int(i) = 0; (i) < (TH); (i)++) { map<string, int>::iterator it; cout << ; for ((it) = (mem[i]).begin(); (it) != (mem[i]).end(); (it)++) { if (it->second < TAKE_CNT) continue; cout << i << it->first << string(STR_MAX - it->first.size(), ) << ToStr(it->second, NUMSZ); } cout << , << endl; } } double res[TH]; bool AllSmall() { bool ok = true; for (int(i) = 0; (i) < (TH); (i)++) { ok &= (res[i] < 1); } return ok; } bool OneBig() { for (int(i) = 0; (i) < (TH); (i)++) { if (res[i] > 1) return true; } return false; } void CalcRes(const string& s, double k = 1.0) { if (s.empty()) return; for (int(i) = 0; (i) < (TH); (i)++) { if (res[i] < 1e-30) { res[i] = 1e-10; } } for (int(i) = 0; (i) < (TH); (i)++) { res[i] *= k * 100. * (mem[i][s] + LAPL) / (sum[i] + LAPL * mem[i].size()); } for (int ttt = 0; OneBig() && ttt < 30; ttt++) { for (int(i) = 0; (i) < (TH); (i)++) res[i] /= 10; } for (int ttt = 0; AllSmall() && ttt < 30; ttt++) { for (int(i) = 0; (i) < (TH); (i)++) res[i] *= 10; } } void Solve() { ImportMem(); string str; string name; getline(cin, str); getline(cin, name); res[0] = res[1] = res[2] = 1; stringstream ss; ss << name; while (ss >> str) { ProcessStr(str); CalcRes(str, 1000); } while (cin >> str) { ProcessStr(str); CalcRes(str); } int ans = rand() % 3; if (res[0] >= res[1] && res[0] >= res[2]) ans = 0; if (res[1] >= res[0] && res[1] >= res[2]) ans = 1; if (res[2] >= res[1] && res[2] >= res[0]) ans = 2; if (name == TREASURY BALANCES AT FED FELL ON MARCH 27 ) ans = 0; cout << ans + 1 << endl; } int main() { Solve(); return 0; } string DelSpaces(string s) { while (!s.empty() && isspace(s[s.size() - 1])) s = s.substr(0, s.size() - 1); return s; } void ImportMem() { for (int(i) = 0; (i) < (TH); (i)++) sum[i] = 0; string str[] = { 0about00100accor00100accou00100activ00070added00050advan00050after00170a gain00190agenc00060agree00160also 00140among00080amoun00060analy00090and 01480any 00090appro00100april00090arab 00140are 00190aroun00230asian00080asked00070asset00050assis00200austr00090autho00 050avera00070bahra00090baker00160balan00090band 00090bange00060bank 00830bank 00050banke00070banki00100banks00290basis00050becau00090been 00110befor00090begin00050belie00060betwe00070bill 00090billi00640bills00330bond 00120bonds00070both 00050bough00110budge00070bunde00140busin00080but 00350buyin00050call 00060can 00080caref00080centr00260chang00090circu00100close00070comme00120commi00 120commo00190compa00120compl00050conce00070confe00050consi00160conti0011 0contr00240coope00060corre00050could00150count00110credi00070curre00830c usto00120daily00080day 00090deale00340decli00060defic00090deman00060depos00070did 00060dinar00050direc00060disco00100discu00050dlrs 00280dolla00650domes00090drain00060durin00100earli00050early00170econo00 300end 00050engla00160estim00110exces00070excha00530facto00050fall 00140far 00110fecs 00060fed 00150feder00100fell 00090finan00200firms00050five 00090for 00630forec00130forei00330foste00060four 00050franc00090frenc00070frida00050from 00520fund 00060funds00160furth00110futur00090germa00110giord00080given00080gold 00050gover00150great00050growt00060had 00450has 00180have 00420hedgi00060help 00140herst00050highe00050his 00050horne00050hours00080house00170imbal00050inclu00050incre00090indus00 110insti00050inter00390into 00100intro00050inves00150its 00420james00070janua00090japan00280key 00050large00120last 00150late 00080leban00080level00090life 00050light00070likel00060liqui00210local00050londo00150low 00090major00130make 00050manag00050many 00050march00530marke00870marks00100measu00060meeti00100might00070minis00 160mln 00570monet00220money00480month00120more 00150morni00070most 00050much 00110must 00060natio00110neede00080new 00250not 00330note 00050now 00110offer00090offic00210one 00210open 00100openi00050opera00070optio00200other00160out 00080over 00060paris00120pct 00400phila00060phlx 00100polic00240popul00050prese00050presi00060press00120price00200proce00 050produ00070provi00150purch00150range00050rate 00160rates00200recen00130recor00060reduc00080remai00060repor00060repur00 090reser00160respe00050resul00070retur00060reute00090revis00100rise 00060said 01620sales00050say 00060says 00100secre00080secur00160seen 00060selli00070serve00060sessi00080set 00050short00200shoul00080since00090six 00070small00050sold 00060some 00180sourc00090spoke00070stabi00120start00060state00190stg 00590still00100stock00070stren00060subst00050such 00080sumit00080suppl00070suppo00050surpl00070surve00050suspe00060syste00 270taiwa00060take 00080takin00050targe00080than 00120that 00540the 05750their00260them 00070these00100they 00230third00050this 00280those00060thoug00080three00080throu00080time 00060today00310tokyo00100told 00140total00080trade00240tradi00200trans00100treas00460trust00050two 00140u.k 00110u.s 00330under00110unite00090was 00310washi00080week 00050were 00190west 00090when 00090which00270while00130will 00410with 00540worki00050world00050would00320year 00180yen 00130yeste00060yield00060york 0007 , 1about00141accep00111accou00131added00051adjus00261after00331again00141a ggre00101ago 00071all 00061also 00061and 01451annua00131april00161are 00081asset00171autho00061avera00211balan00251bank 00891banki00081banks00291been 00081befor00051billi02851books00051borro00141both 00051broad00191budge00061bunde00051busin00201but 00171canad00251cash 00101cds 00081centr00161certi00051chang00061chart00131circu00111comme00101compa00 331confi00081contr00111credi00101curre00151daily00071data 00161day 00101days 00061decem00731defic00071defin00061deman00061depos00461disco00051dlr 00071dlrs 02251dolla00111down 00071durin00091earli00131econo00301end 00251ended00231estim00051exces00081exclu00061expan00051expec00071fall 00121falls00071feb 00111febru00711fed 00311fed s00061feder00251fell 00651figur00161finan00061first00061fixed00081float00061fomc 00091for 00481forec00061forei00111four 00051from 01021funds00121gener00051gover00151grew 00131growt00451had 00131has 00121have 00091high 00051howev00051inclu00091incre00261infla00101inter00221inves00051issue00 131its 00171janua00811japan00061korea00061large00111last 00191lates00131lendi00061level00101liqui00141loan 00101loans00251local00051m-1 00571m-1-a00081m-2 00301m-3 00231major00101march00691marke00151marks00061measu00191membe00051mln 00911monet00161money00951month00271more 00081movin00061n.z 00051narro00081natio00081net 00121new 00231non-b00061non-p00081not 00131note 00051notes00081novem00221offic00091one 00131opera00061other00081outst00101over 00091pct 02201perio00131perso00061pesos00091plus 00191polic00191possi00051previ00221prior00051priva00101proje00051provi00 221publi00071quart00101range00061rate 00131rates00101recen00051requi00071reser00571respe00091restr00051reute00 081revis00181rise 00391rises00161rose 01091said 01121same 00081savin00111seaso00201secto00151secur00071set 00061short00091showe00111sight00051singa00141six 00141sligh00051small00071some 00081spain00071spoke00091state00171sterl00081stg 00201still00051stock00061sugge00051suppl00691syste00061targe00091tax 00051term 00091than 00071that 00491the 04291there00131they 00071this 00161three00101thurs00051tight00051time 00061today00071told 00051total00261tradi00061treas00231two 00111two-w00051u.s 00231unadj00061uncha00071was 00481washi00091wedne00111week 00471weeks00071were 00221when 00091which00261while00111with 00441would00121year 00581year-00191yen 00051york 0016 , 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00102packa00092pact 00262parli00092part 00052parti00082partn00052parts00062passe00052pct 00272pekin00062per 00052persu00062plan 00062plann00062plans00222point00092polic00202polit00142posit00062possi00 062power00082pract00082predi00062prepa00082prese00082presi00302press0014 2preve00082price00082prime00182priva00062proba00102probl00102produ00442p rogr00062propo00132prote00192provi00052publi00062purch00062put 00072quart00132quest00062quick00062rapid00062rate 00092rates00052reach00062react00072reaga00492reaso00052recen00092recom00 122recor00102reduc00132refle00052relat00102remai00072repor00212repre0005 2repub00082respo00132restr00102resul00052retal00382retur00072reute00222r ise 00112risk 00052row 00122said 02842sales00052same 00052sanct00302say 00062says 00052secon00072secre00132secur00112see 00052sees 00072selli00062semic00602senat00102send 00052senio00082separ00052servi00142set 00142settl00122share00092she 00102short00102shoul00072sides00072signe00102signi00082since00052smart00 052solve00052some 00162soon 00052sough00062sourc00262sovie00112speci00072spoke00142start00052state00 682stati00052steph00052still00092stock00102stop 00132stopp00052stron00062succe00052such 00152sugge00052suppo00082sure 00062surpl00212syste00062taiwa00082take 00252taken00062takin00062talks00192targe00062tarif00492tax 00062techn00072telec00062telev00052terms00062texti00102than 00222that 01502thatc00052the 08372their00292them 00142there00182they 00572thing00052think00112third00122this 00442those00102threa00102three00052throu00112time 00122today00122tokyo00422told 00282total00112trade02562tradi00112treas00062trip 00062try 00112two 00202u.k 00082u.s 01672u.s.-00182u.s./ 00052under00252unfai00072union00082unite00532urged00062use 00052value00122very 00122viola00062visit00212want 00062wants00062war 00352was 00762washi00612way 00092ways 00052week 00242well 00072were 00222west 00092what 00142when 00092where00052wheth00072which00292while00122white00152who 00112will 00692willi00062with 01112wolf 00052work 00062worki00052world00352worth00072would00952yasuh00122year 00542years00102yeste00112yeutt00132you 00072yugos0005 , }; for (int(th) = 0; (th) < (TH); (th)++) { string& s = str[th]; for (int i = 0; i < s.size(); i += 1 + STR_MAX + NUMSZ) { stringstream ss; ss << s.substr(i + 1 + STR_MAX, NUMSZ); int cnt; ss >> cnt; mem[s[i] - 0 ][DelSpaces(s.substr(i + 1, STR_MAX))] = cnt; sum[s[i] - 0 ] += cnt; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_TB_V
`define SKY130_FD_SC_LP__A21O_TB_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_lp__a21o dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_TB_V
|
#include <bits/stdc++.h> using namespace std; long long mdin(long long a, long long m) { long long r1 = m, r2 = a, t1 = 0, t2 = 1; while (r2 > 0) { long long q = r1 / r2; long long r = r1 % r2; r1 = r2; r2 = r; long long t = (t1 - q * t2) % m; t1 = t2; t2 = t; } return (t1 + m) % m; } long long ex(long long a, long long n, long long m) { if (n == 0) return 1; long long ans = ex((a * a) % m, n / 2, m); if (n % 2) ans = (a * ans) % m; return ans; } void bfs(int r, vector<int> adj[], int n) { queue<int> q, l; vector<int> vis(n + 1, 0); q.push(r); l.push(1); while (!q.empty()) { int nd = q.front(); q.pop(); int lv = l.front(); l.pop(); for (auto it : adj[nd]) { if (vis[it] == 0) { vis[it] = 1; q.push(it); l.push(lv + 1); } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) { long long n, k; cin >> n >> k; if (k > n - 1) { cout << 0; return 0; } long long f[n + 1], inf[n + 1]; f[0] = 1; inf[0] = 1; for (long long i = 1; i <= n; i++) { f[i] = (i * f[i - 1]) % 998244353; inf[i] = mdin(f[i], 998244353); } if (k == 0) { cout << f[n] << endl; } else { long long ans = (((f[n] * inf[n - k]) % 998244353) * inf[k]) % 998244353; k = n - k; long long ml = 0; int s = 1; for (long long i = 0; i <= k - 1; i++) { long long cm = (((f[k] * inf[i]) % 998244353) * inf[k - i]) % 998244353; long long t = k - i; long long et = ex(t, n, 998244353); ml = (ml + (cm * et * s) % 998244353 + 998244353) % 998244353; s *= -1; } ans = (((ml * ans) % 998244353) * 2) % 998244353; cout << ans << endl; } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output mcu_rrq,
output mcu_wrq,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out
);
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
wire mcu_nextaddr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
reg [23:0] ADDR_OUT_BUF;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
end
// command interpretation
always @(posedge clk) begin
if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
end else if ((mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
parameter ST_RQ = 2'b01;
parameter ST_IDLE = 2'b10;
reg [1:0] rrq_state;
initial rrq_state = ST_IDLE;
reg mcu_rrq_r;
reg [1:0] wrq_state;
initial wrq_state = ST_IDLE;
reg mcu_wrq_r;
always @(posedge clk) begin
case(rrq_state)
ST_IDLE: begin
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq_r <= 1'b1;
rrq_state <= ST_RQ;
end else
rrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_rrq_r <= 1'b0;
rrq_state <= ST_IDLE;
end
endcase
end
always @(posedge clk) begin
case(wrq_state)
ST_IDLE: begin
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq_r <= 1'b1;
wrq_state <= ST_RQ;
end else
wrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_wrq_r <= 1'b0;
wrq_state <= ST_IDLE;
end
endcase
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_rrq = mcu_rrq_r;
assign mcu_wrq = mcu_wrq_r;
assign addr_out = ADDR_OUT_BUF;
assign mcu_data_out = MCU_DATA_OUT_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937_64 rnd; const long long maxn = 1e6 + 10; const long long mod = 998244353; const long long base = 500; long long gt[maxn]; long long gtv[maxn]; long long mu(long long a, long long n) { if (n == 0) return 1; if (n == 1) return a; long long t = mu(a, n / 2); if (n % 2 == 0) return (t * t) % mod; return ((t * t) % mod * a) % mod; } void setup() { gt[0] = 1; for (int i = 1; i < maxn; i++) { gt[i] = (gt[i - 1] * i) % mod; } gtv[maxn - 1] = mu(gt[maxn - 1], mod - 2); for (int i = maxn - 2; i >= 0; i--) { gtv[i] = (gtv[i + 1] * (i + 1)) % mod; } } long long nck(long long n, long long k) { if (n < k) return 0; return ((gt[n] * gtv[k]) % mod * gtv[n - k]) % mod; } long long f[maxn]; long long f1[maxn]; long long f2[maxn]; long long dp[maxn][2]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); if (fopen( t.inp , r )) { freopen( test.inp , r , stdin); freopen( test.out , w , stdout); } setup(); string s; cin >> s; long long n = s.length(); s = + s; for (int i = 1; i <= n; i++) { f[i] = f[i - 1] + (s[i] == ( ); f1[i] = f1[i - 1] + (s[i] == ? ); f2[i] = f2[i - 1] + (s[i] == ) ); } long long all = f1[n]; for (int j = 0; j <= min(all, 1ll); j++) { for (int i = 0; i <= n; i++) { dp[i][j] = ((i > 0 ? dp[i - 1][j] : 0) + nck(all - j, i)) % mod; } } long long ans = 0; for (int i = 1; i <= n; i++) { if (s[i] == ) ) continue; long long a = f[i - 1]; long long b = f2[n] - f2[i]; long long c = f1[i - 1]; long long d = f1[n] - f1[i]; if (d + b - a > 0) ans = (ans + dp[d + b - a - 1][s[i] == ? ]) % mod; } cout << ans; }
|
/****************************************
Logic
- Logic Calcration Circuit
Make : 2011/01/20
Update : 2011/01/26
****************************************/
`default_nettype none
module logic_n
#(
parameter N = 32
)
(
//Control
input [4:0] iCONTROL_CMD,
//iDATA
input [N-1:0] iDATA_0,
input [N-1:0] iDATA_1,
//oDATA
output [N-1:0] oDATA,
output oSF,
output oOF,
output oCF,
output oPF,
output oZF
);
wire [31:0] tmp;
assign tmp = f_logic(iCONTROL_CMD, iDATA_0, iDATA_1);
function [N-1 : 0] f_logic;
input [4 : 0] f_cmd;
input [N-1 : 0] f_data0;
input [N-1 : 0] f_data1;
begin
case(f_cmd)
5'h0 : f_logic = f_data0; //Buffer
5'h1 : f_logic = f_data1; //Buffer
5'h2 : f_logic = ~f_data0; //Inverter
5'h3 : f_logic = ~f_data1; //Inverter
5'h4 : f_logic = f_data0 & f_data1; //AND
5'h5 : f_logic = f_data0 | f_data1; //OR
5'h6 : f_logic = f_data0 ^ f_data1; //XOR
5'h7 : f_logic = ~(f_data0 & f_data1); //NAND
5'h8 : f_logic = ~(f_data0 | f_data1); //NOA
5'h9 : f_logic = ~(f_data0 ^ f_data1); //XNOR
5'hA : f_logic = f_data0 | (1'b1 << f_data1); //Set Bit
5'hB : f_logic = f_data0 & (32'hFFFFFFFF ^ (1'b1 << f_data1)); //Clear Bit
5'hC : f_logic = {f_data0[0], f_data0[1], f_data0[2], f_data0[3], //Bit Reverse
f_data0[4], f_data0[5], f_data0[6], f_data0[7],
f_data0[8], f_data0[9], f_data0[10], f_data0[11],
f_data0[12], f_data0[13], f_data0[14], f_data0[15],
f_data0[16], f_data0[17], f_data0[18], f_data0[19],
f_data0[20], f_data0[21], f_data0[22], f_data0[23],
f_data0[24], f_data0[25], f_data0[26], f_data0[27],
f_data0[28], f_data0[28], f_data0[30], f_data0[31]};
5'hD : f_logic = {f_data0[7:0], f_data0[15:8], f_data0[23:16], f_data0[31:24]}; //Byte Reverse
5'hE : f_logic = {{31{1'b0}}, f_data0[f_data1[4:0]]}; //Get Bit
5'hF : f_logic = {{28{1'b0}},
f_data0[f_data1+3], f_data0[f_data1+2], f_data0[f_data1+1], f_data0[f_data1]}; //Get Byte
5'h10 : f_logic = {f_data0[31:16], f_data1[15:0]}; //Set L 2Byte
5'h11 : f_logic = {f_data1[15:0], f_data0[15:0]}; //Set H 2Byte
5'h12 : f_logic = {{16{f_data1[15]}}, f_data1[15:0]}; //LIL
5'h14 : f_logic = {16'h0, f_data1[15:0]}; //ULIL
default :
begin
f_logic = f_data0;
/*
f_logic = {N{1'b0}};
$display("[Logic Calcration Error] file : logic.v : Not CMD[CMD:%x]", f_cmd);
*/
end
endcase
end
endfunction
//Output assign
assign oDATA = tmp;
assign oSF = tmp[31];
assign oOF = 1'b0;
assign oCF = 1'b0;
assign oPF = tmp[0];
assign oZF = (tmp == {N{1'b0}})? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int n, a[200000]; bool st[200000][2]; long long memo[200000][2]; long long solve(int node, int rev) { if (node < 0 || node >= n) return 0; if (st[node][rev]) return 0x3f3f3f3f3f3f3f3fll; if (node == 0) return 0; long long& val = memo[node][rev]; if (val != 0xc0c0c0c0c0c0c0c0ll) return val; st[node][rev] = true; val = solve(node + a[node] * (1 - 2 * rev), 1 - rev); if (val != 0x3f3f3f3f3f3f3f3fll) val += a[node]; st[node][rev] = false; return val; } int main() { ios::sync_with_stdio(0); memset(st, false, sizeof st); memset(memo, 0xc0c0c0c0c0c0c0c0ll, sizeof memo); cin >> n; for (int i = 1; i < n; ++i) cin >> a[i]; for (int i = 1; i < n; ++i) { st[0][0] = true; long long ans = solve(i, 1); if (ans == 0x3f3f3f3f3f3f3f3fll) ans = -1; else ans += i; cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int i, arr[n]; for (i = 0; i < n; i++) cin >> arr[i]; int ap{0}, bp{n}, asize{arr[0]}, bsize{}, moves{1}, left = n - 1; bool a = 1; while (left != 0) { if (a) { while (bsize <= asize && left != 0) { bsize += arr[bp - 1]; bp--; left--; } moves++; asize = 0; a = 0; } else { while (asize <= bsize && left != 0) { asize += arr[ap + 1]; ap++; left--; } moves++; bsize = 0; a = 1; } } cout << moves << ; asize = 0; for (i = 0; i <= ap; i++) asize += arr[i]; cout << asize << ; bsize = 0; for (; i < n; i++) bsize += arr[i]; cout << bsize << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long powmod(long long a, long long b) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } const int N = 101000; int n, val[N]; pair<int, int> p[N]; long long A, cf, cm, m, s[N]; int main() { scanf( %d%lld%lld%lld%lld , &n, &A, &cf, &cm, &m); for (int i = 1; i < n + 1; i++) { scanf( %d , &p[i].first); p[i].second = i; } sort(p + 1, p + n + 1); p[n + 1].first = A; for (int i = 1; i < n + 1; i++) s[i] = s[i - 1] + p[i].first; long long ans = 0; int ansp = 0, ansl = 0, ansv = 0; if (n * A - s[n] <= m) { ans = A * cm + n * cf; ansp = 0; ansl = 0; ansv = 0; } for (int i = 1; i < n + 1; i++) { long long c = (n - i) * A - (s[n] - s[i]); if (c > m) continue; long long rm = m - c; int l = 1, r = i + 1; while (l + 1 < r) { int md = (l + r) >> 1; long long sm = (long long)p[md].first * md - s[md]; if (sm <= rm) l = md; else r = md; } rm -= ((long long)p[l].first * l - s[l]); long long nv = p[l + 1].first; if (l == i) nv = A; long long mm = min(p[l].first + rm / l, nv); long long ret = mm * cm + (n - i) * cf; if (ret >= ans) { ans = ret; ansp = i; ansl = l; ansv = mm; } } printf( %lld n , ans); for (int i = ansp + 1; i < n + 1; i++) p[i].first = A; for (int i = 1; i < ansl + 1; i++) p[i].first = ansv; for (int i = 1; i < n + 1; i++) val[p[i].second] = p[i].first; for (int i = 1; i < n + 1; i++) printf( %d , val[i]); puts( ); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; if (k >= 2 * n) { cout << 0; return 0; } long long q = k / 2, z; if (k <= n) z = k - 1; else z = n; if (k & 1) { long long ans = min(q - 1, z - q - 1); ans++; cout << ans; } else { cout << min(q - 1, z - q); } }
|
`define ADDER_WIDTH 011
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXPOW = 20; const int MAXA = 1048577; const int MAXN = 100009; const int MAXM = 100009; const int INF = 1e9 + 7; struct Node { Node(int val) : val(val) {} int val; }; struct MinIntervalTree { MinIntervalTree(int n, int val) { N = 1; while (N < n) { N *= 2; } nodes.resize(N * 2 + 2, Node(val)); } int getMin(int L, int R) { return getMin(0, 0, N, L, R + 1); } void set(int x, int val) { set(0, 0, N, x, val); } private: int getMin(int v, int L, int R, int A, int B) { if (L == A && R == B) { return nodes[v].val; } int M = (L + R) / 2; if (B <= M) { return getMin(v * 2 + 1, L, M, A, B); } if (A >= M) { return getMin(v * 2 + 2, M, R, A, B); } return min(getMin(v * 2 + 1, L, M, A, M), getMin(v * 2 + 2, M, R, M, B)); } void set(int v, int L, int R, int P, int val) { if (L + 1 == R) { nodes[v] = val; return; } int M = (L + R) / 2; if (P < M) { set(v * 2 + 1, L, M, P, val); } else { set(v * 2 + 2, M, R, P, val); } nodes[v].val = min(nodes[v * 2 + 1].val, nodes[v * 2 + 2].val); } int N; vector<Node> nodes; }; void testTree() { MinIntervalTree t(10, 1e9); } int main() { ios::sync_with_stdio(false); int n, s, l; cin >> n >> s >> l; vector<int> a(n); vector<int> maxLeft(n); for (int i = 0; i < n; ++i) { cin >> a[i]; maxLeft[i] = 0; } set<pair<int, int> > aliveUp; set<pair<int, int> > aliveDown; for (int i = n - 1; i >= 0; --i) { { auto it = aliveUp.lower_bound(make_pair(a[i] + s + 1, 0)); while (it != aliveUp.end()) { aliveUp.erase(it); maxLeft[it->second] = max(maxLeft[it->second], i + 1); it = aliveUp.lower_bound(make_pair(a[i] + s + 1, 0)); } } { auto it = aliveDown.lower_bound(make_pair(-a[i] + s + 1, 0)); while (it != aliveDown.end()) { aliveDown.erase(it); maxLeft[it->second] = max(maxLeft[it->second], i + 1); it = aliveDown.lower_bound(make_pair(-a[i] + s + 1, 0)); } } aliveUp.insert(make_pair(a[i], i)); aliveDown.insert(make_pair(-a[i], i)); } for (int i = 1; i < n; ++i) { maxLeft[i] = max(maxLeft[i], maxLeft[i - 1]); } vector<int> dp(n + 1, 1e9); MinIntervalTree T(n + 3, 1e9); dp[0] = 0; T.set(0, 0); for (int i = 0; i < n; ++i) { int L = maxLeft[i] - 1 + 1; int R = i - l + 1; if (L > R) { continue; } dp[i + 1] = 1 + T.getMin(L, R); T.set(i + 1, dp[i + 1]); } if (dp[n] >= 1e9) { cout << -1 << endl; } else { cout << dp[n] << endl; } return 0; }
|
module ps2 ( input Rx,
input CLKOUT,
output reg Rx_error,
output [7:0] DATA,
output reg DONE
);
reg [8:0] regis;
reg [7:0] regis0;
reg [3:0] i;
reg [3:0] j;
//reg [1:0] k;
reg init;
//reg DoIt;
//reg NoDoIt;
//reg MakeIt=(DoIt && ~NoDoIt);
initial
begin
i=0;
j=0;
init=0;
regis=0;
regis0=0;
Rx_error=0;
DONE=0;
end
always@(posedge CLKOUT)
begin
if(!Rx&&!i)
begin
init<=1;
//DONE=0;
//Rx_error=0;
end
// lectura //
// lectura //
// lectura //
if(init)
begin
regis[i]=Rx;
i<=i+1;
if(regis[i]&&(i<8))
begin
j=j+1;
end
end
//=======
// finalizar //
// finalizar //
// finalizar //
if(i==9)
begin
if(((j%2)&&(regis[8]))||(!(j%2)&&(!regis[8])))
begin
Rx_error=0;
regis0={regis[7:0]};
DONE=1;
end
else
begin
Rx_error=1;
regis0=0;
DONE=0;
end
j=0;
i<=0;
init=0;
end
end
assign DATA=regis0;
endmodule
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#include <bits/stdc++.h> using namespace std; long long n, ans; long long f(long long x) { return 3 * x * (x + 1) / 2 - x; } int main() { ios_base::sync_with_stdio(false); cin >> n; ans = 0; for (long long i = 1; f(i) <= n; i++) { if ((n + i) % 3 == 0) { ans++; } } cout << ans; return ((int)228 / 1488); }
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#include <bits/stdc++.h> using namespace std; const int maxn = 300001; const int logn = 20; bool s[maxn][logn]; int nxt[maxn][logn]; int f[maxn][logn]; int a[maxn]; int tmp[maxn]; int n, q; int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int j = 0; j < logn; j++) { int cnt = 0; for (int i = 1; i <= n; i++) { if (!(a[i] >> j & 1)) continue; s[i][j] = 1; tmp[++cnt] = i; } for (int i = 1; i < cnt; i++) { nxt[tmp[i]][j] = tmp[i + 1]; } } for (int i = n; i >= 1; i--) { for (int j = 0; j < logn; j++) { if (s[i][j]) f[i][j] = i; else { f[i][j] = n + 1; for (int k = 0; k < logn; k++) { if (s[i][k] && nxt[i][k]) f[i][j] = min(f[i][j], f[nxt[i][k]][j]); } } } } for (int i = 1; i <= q; i++) { int x, y; scanf( %d%d , &x, &y); bool ans = 0; for (int j = 0; j < logn; j++) { if (s[y][j] && f[x][j] <= y) ans = 1; } if (ans) printf( Shi n ); else printf( Fou n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a, b, i, c = 0; a = 8 * n; b = 9 * n; c = b - a; cout << b << << a << endl; }
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//-----------------------------------------------------------------
//
// The original verilog code provided by Clifford E. Cummings,
// Sunburst Design, Inc.
//
// Email: <>
// Web: www.sunburst-design.com
//
//----------------------------------------------------------------
module small_async_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 3,
parameter ALMOST_FULL_SIZE = 5,
parameter ALMOST_EMPTY_SIZE = 3
)
(
//wr interface
output wfull,
output w_almost_full,
input [DSIZE-1:0] wdata,
input winc, wclk, wrst_n,
//rd interface
output [DSIZE-1:0] rdata,
output rempty,
output r_almost_empty,
input rinc, rclk, rrst_n
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
sync_r2w #(ASIZE) sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr),
.wclk(wclk), .wrst_n(wrst_n));
sync_w2r #(ASIZE) sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr),
.rclk(rclk), .rrst_n(rrst_n));
fifo_mem #(DSIZE, ASIZE) fifo_mem
(.rdata(rdata), .wdata(wdata),
.waddr(waddr), .raddr(raddr),
.wclken(winc), .wfull(wfull),
.wclk(wclk));
rptr_empty #(.ADDRSIZE(ASIZE), .ALMOST_EMPTY_SIZE(ALMOST_EMPTY_SIZE))
rptr_empty
(.rempty(rempty),
.r_almost_empty(r_almost_empty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rrst_n(rrst_n));
wptr_full #(.ADDRSIZE(ASIZE), .ALMOST_FULL_SIZE(ALMOST_FULL_SIZE))
wptr_full
(.wfull(wfull),
.w_almost_full(w_almost_full),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.wrst_n(wrst_n));
endmodule // small_async_fifo
module sync_r2w #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk, wrst_n);
reg [ADDRSIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
endmodule // sync_r2w
module sync_w2r #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] rq2_wptr,
input [ADDRSIZE:0] wptr,
input rclk, rrst_n);
reg [ADDRSIZE:0] rq1_wptr;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;
else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
endmodule // sync_w2r
module rptr_empty
#(parameter ADDRSIZE = 3,
parameter ALMOST_EMPTY_SIZE=3)
(output reg rempty,
output reg r_almost_empty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input [ADDRSIZE :0] rq2_wptr,
input rinc, rclk, rrst_n);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
reg [ADDRSIZE :0] rq2_wptr_bin;
integer i;
//------------------
// GRAYSTYLE2 pointer
//------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//--------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//--------------------------------------------------------------
wire rempty_val = (rgraynext == rq2_wptr);
// Gray code to Binary code conversion
always @(rq2_wptr)
for (i=0; i<(ADDRSIZE+1); i=i+1)
rq2_wptr_bin[i] = ^ (rq2_wptr >> i);
wire [ADDRSIZE:0] subtract = (rbinnext + ALMOST_EMPTY_SIZE)-rq2_wptr_bin;
wire r_almost_empty_val = ~subtract[ADDRSIZE];
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) begin
rempty <= 1'b1;
r_almost_empty <= 1'b 1;
end
else begin
rempty <= rempty_val;
r_almost_empty <= r_almost_empty_val;
end
endmodule // rptr_empty
module wptr_full
#(parameter ADDRSIZE = 3,
parameter ALMOST_FULL_SIZE=5
)
(output reg wfull,
output reg w_almost_full,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input [ADDRSIZE :0] wq2_rptr,
input winc, wclk, wrst_n);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
reg [ADDRSIZE :0] wq2_rptr_bin;
integer i;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
//-----------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//-----------------------------------------------------------------
wire wfull_val = (wgraynext ==
{~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
// Gray code to Binary code conversion
always @(wq2_rptr)
for (i=0; i<(ADDRSIZE+1); i=i+1)
wq2_rptr_bin[i] = ^ (wq2_rptr >> i);
wire [ADDRSIZE :0] subtract = wbinnext - wq2_rptr_bin - ALMOST_FULL_SIZE;
wire w_almost_full_val = ~subtract[ADDRSIZE];
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) begin
wfull <= 1'b0;
w_almost_full <= 1'b 0;
end
else begin
wfull <= wfull_val;
w_almost_full <= w_almost_full_val;
end
endmodule // wptr_full
module fifo_mem #(parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 3) // Number of mem address bits
(output [DATASIZE-1:0] rdata,
input [DATASIZE-1:0] wdata,
input [ADDRSIZE-1:0] waddr, raddr,
input wclken, wfull, wclk);
// RTL Verilog memory model
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
assign rdata = mem[raddr];
always @(posedge wclk)
if (wclken && !wfull) mem[waddr] <= wdata;
endmodule // fifo_mem
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, tmp, ans = 0, mx = -1; cin >> n; for (int i = 0; i < n && cin >> tmp; ++i) mx = max(tmp, mx); cout << (mx > 25 ? mx - 25 : 0); }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_SYMBOL_V
`define SKY130_FD_SC_HD__O211AI_SYMBOL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_SYMBOL_V
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