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#include <bits/stdc++.h> using namespace std; void rr(vector<vector<long long>> &m, long long r, long long nr, long long nc) { long long t = m[r - 1][nc - 1]; for (long long i = nc - 2; i >= 0; i--) m[r - 1][i + 1] = m[r - 1][i]; m[r - 1][0] = t; return; } void rc(vector<vector<long long>> &m, long long c, long long nr, long long nc) { long long t = m[nr - 1][c - 1]; for (long long i = nr - 2; i >= 0; i--) m[i + 1][c - 1] = m[i][c - 1]; m[0][c - 1] = t; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m, q, t; cin >> n >> m >> q; vector<vector<long long>> mat(n, vector<long long>(m, 0)); vector<vector<long long>> op; for (long long i = 0; i < q; i++) { cin >> t; if (t == 1 || t == 2) { long long roc; cin >> roc; op.push_back({t, roc}); } else { long long r, c, x; cin >> r >> c >> x; op.push_back({t, r, c, x}); } } bool f3 = false; for (long long i = op.size() - 1; i >= 0; i--) { if (!f3) { if (op[i][0] == 3) { f3 = true; mat[op[i][1] - 1][op[i][2] - 1] = op[i][3]; } } else { if (op[i][0] == 1) { rr(mat, op[i][1], n, m); } else if (op[i][0] == 2) { rc(mat, op[i][1], n, m); } else { mat[op[i][1] - 1][op[i][2] - 1] = op[i][3]; } } } for (auto i : mat) { for (auto j : i) cout << j << ; cout << endl; } return 0; }
|
module crc_parallel
#(
parameter CRC_SIZE = 8, // Define the size of CRC Code
parameter FRAME_SIZE = 8 // Number of bits in the data block
)(
//OUTPUTS
output [CRC_SIZE - 1 : 0] crc_out,
//INPUTS
input [FRAME_SIZE - 1 : 0] data_in,
input [CRC_SIZE - 1 : 0] crc_init,
input [CRC_SIZE - 1 : 0] crc_poly,
input [CRC_SIZE - 1 : 0] crc_poly_size
);
localparam ENABLE = {CRC_SIZE{1'b1}};
localparam DISABLE = {CRC_SIZE{1'b0}};
wire [CRC_SIZE - 1 : 0] crc_comb_out[0 : FRAME_SIZE];
wire [CRC_SIZE - 1 : 0] poly_sel [1 : CRC_SIZE - 1];
wire [CRC_SIZE - 1 : 0] sel_out [0 : CRC_SIZE - 1];
wire [CRC_SIZE - 1 : 0] crc_init_sel[0 : CRC_SIZE - 1];
wire [CRC_SIZE - 1 : 0] poly_mux;
wire [CRC_SIZE - 1 : 0] crc_poly_size_reversed;
wire [CRC_SIZE - 1 : 0] crc_init_justified;
assign poly_mux[0] = crc_poly[0];
generate
genvar k;
for(k = 1; k < CRC_SIZE; k = k + 1)
begin
assign poly_sel[CRC_SIZE - k] = crc_poly_size >> (k - 1);
assign poly_mux[k] = |(crc_poly & poly_sel[k]);
end
endgenerate
generate
genvar l;
for(l = 0; l < CRC_SIZE; l = l + 1)
begin
assign crc_poly_size_reversed[l] = crc_poly_size[CRC_SIZE - 1 - l];
assign sel_out[l] = crc_poly_size_reversed << l;
assign crc_out[l] = |(sel_out[l] & crc_comb_out[FRAME_SIZE]);
end
endgenerate
generate
genvar m;
for(m = CRC_SIZE - 1; m >= 0; m = m - 1)
begin
assign crc_init_sel[m] = crc_poly_size >> (CRC_SIZE - 1 - m);
assign crc_init_justified[m] = |(crc_init & crc_init_sel[m]);
end
endgenerate
assign crc_comb_out[0] = crc_init_justified;
generate
genvar i;
for(i = 0; i < FRAME_SIZE; i = i + 1)
begin
crc_comb
#(
.CRC_SIZE ( CRC_SIZE ),
.MASK ( ENABLE )
) CRC_COMB
(
.crc_out ( crc_comb_out[i + 1] ),
.data_in ( data_in[FRAME_SIZE - 1 - i] ),
.crc_in ( crc_comb_out[i] ),
.crc_poly ( poly_mux ),
.crc_poly_size ( crc_poly_size[CRC_SIZE - 2:0] )
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using i8 = std::int8_t; using i16 = std::int16_t; using i32 = std::int32_t; using i64 = std::int64_t; using u8 = std::uint8_t; using u16 = std::uint16_t; using u32 = std::uint32_t; using u64 = std::uint64_t; auto SolveTest() -> void { int n; std::cin >> n; std::vector<int> a(n); for (auto &elem : a) { std::cin >> elem; } std::set<int> numbers(std::begin(a), std::end(a)); for (auto it = std::begin(numbers); std::next(it) != std::end(numbers); ++it) { if (std::abs(*it - *std::next(it)) > 1) { std::cout << NO n ; return; } } std::cout << YES n ; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); std::cout.tie(nullptr); i32 test_count; std::cin >> test_count; for (i32 t = 0; t < test_count; ++t) { SolveTest(); } }
|
#include <bits/stdc++.h> using namespace std; int n, m; int dmap[45][45]; int ans[45]; int dans[45]; int nans, zans; void dfs(int dn) { if (dn == n + 1) { if (nans > zans) { zans = nans; } return; } int mark = 0; for (int i = 1; i < dn; i++) if (ans[i] == 1 && dmap[i][dn] == 0) mark = 1; if (mark == 0) { ans[dn] = 1; nans++; dfs(dn + 1); nans--; } if (nans + n - dn > zans) { ans[dn] = 0; dfs(dn + 1); } return; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &dmap[i][j]); nans = 0; zans = 0; dfs(1); double zzans = zans; printf( %lf n , (zzans - 1) / zzans / 2 * m * m); return 0; }
|
#include <bits/stdc++.h> using namespace std; int Mod; const int Nmax = 1005, Kmax = 105; int Dp[Nmax][Kmax]; int main() { ios::sync_with_stdio(false); int N, K; cin >> N >> K >> Mod; for (int i = 1; i < 10; ++i) Dp[1][i % K]++; if (N > 1) Dp[1][K] = 1; for (int i = 2, pw = 10 % K; i <= N; ++i) { for (int j = 1; j <= K; ++j) { for (int k = i == N ? 1 : 0; k < 10; ++k) { int nj = (1LL * pw * k + j) % K; Dp[i][nj] = (Dp[i][nj] + Dp[i - 1][j]) % Mod; } } Dp[i][K] = 1; pw = 10LL * pw % K; } int ans = 0, pw = 1; for (int i = 1; i < N; ++i) { pw = 10LL * pw % Mod; } pw = 9LL * pw % Mod; for (int i = 1; i < K; ++i) ans = (ans + Dp[N][i]) % Mod; ans = (pw - ans + Mod) % Mod; cout << ans << n ; }
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#include <bits/stdc++.h> using namespace std; inline int nxt() { int x; scanf( %d , &x); return x; } int main() { mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long n; cin >> n; vector<long long> ps; for (long long i = 2; i * i <= n; ++i) { if (n % i) { continue; } ps.push_back(i); while (n % i == 0) { n /= i; } } if (n > 1) { ps.push_back(n); } cout << (ps.size() == 1 ? ps[0] : 1) << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int N, K, D[1010], S[1010], ans, tt, crtMax; int main() { int i; scanf( %i %i , &N, &K); for (i = 1; i <= N; i++) scanf( %i , &D[i]); for (i = 1; i <= N; i++) scanf( %i , &S[i]); for (i = 1; i <= N; i++) { crtMax = max(crtMax, S[i]); ans += S[i]; while (ans < D[i]) { ans += crtMax; tt += K; } tt += D[i]; ans -= D[i]; } printf( %i n , tt); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; const long long inf = 10000005; int nsize, root, n, tot, nedge, hed[maxn], father[maxn], maxson[maxn], sz[maxn], vis[maxn]; long long M, pw[maxn]; map<int, int> up[maxn], cst[maxn]; vector<int> dist[maxn], down[maxn]; struct Edge { int todot, nex; long long cost; } edge[maxn << 1]; inline int read() { int x = 0; int w = 0; char ch = 0; while (ch < 0 || ch > 9 ) w |= ch == - , ch = getchar(); while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + (ch ^ 48), ch = getchar(); return w ? -x : x; } void addedge(int a, int b, long long c) { edge[nedge].todot = b; edge[nedge].nex = hed[a]; edge[nedge].cost = c; hed[a] = nedge++; } void getsize(int k, int fa) { ++nsize; for (int i = hed[k]; i != -1; i = edge[i].nex) { int v = edge[i].todot; if ((v == fa) || (vis[v])) continue; getsize(v, k); } } void getroot(int k, int fa) { maxson[k] = 0; sz[k] = 1; for (int i = hed[k]; i != -1; i = edge[i].nex) { int v = edge[i].todot; if ((v == fa) || (vis[v])) continue; getroot(v, k); sz[k] += sz[v]; maxson[k] = max(maxson[k], sz[v]); } maxson[k] = max(maxson[k], nsize - sz[k]); if (maxson[k] < maxson[root]) root = k; } void ex_gcd(long long a, long long b, long long c, long long &x, long long &y) { if (!b) { x = c / a; y = 0; return; } if (!(a % b)) { x = 0; y = c / b; return; } ex_gcd(b, a % b, c, y, x); y -= (a / b) * x; } void Merge(int k, int fa, int gf, int f, int dis, long long nowdown) { for (int i = hed[k]; i != -1; i = edge[i].nex) { int v = edge[i].todot; if ((vis[v]) || (v == fa)) continue; ++tot; father[tot - 1] = f ? f : v; dist[gf].push_back(dis + 1); down[gf].push_back((nowdown * 10 + edge[i].cost) % M); if (!f) Merge(v, k, gf, v, dis + 1, (nowdown * 10 + edge[i].cost) % M); else Merge(v, k, gf, f, dis + 1, (nowdown * 10 + edge[i].cost) % M); } } void getup(int k, int fa, int gf, long long nowup, int dis) { for (int i = hed[k]; i != -1; i = edge[i].nex) { int v = edge[i].todot; if ((vis[v]) || (v == fa)) continue; up[gf][(pw[dis] * edge[i].cost + nowup) % M]++; getup(v, k, gf, (pw[dis] * edge[i].cost + nowup) % M, dis + 1); } } long long calc(int k) { int t = dist[k].size(); long long ret = 0; for (int i = 0; i <= t - 1; i++) { long long x, y; ex_gcd(M, pw[dist[k][i]], 1, x, y); y = ((y % M) + M) % M; y = (y * (-down[k][i]) % M + M) % M; long long tx, ty; ex_gcd(M, 10 % M, 1, tx, ty); ty = ((ty % M) + M) % M; ty = (((y - cst[k][father[i]]) * ty) % M + M) % M; ret += up[k][y] - up[father[i]][ty] - (cst[k][father[i]] % M == y); if (!down[k][i]) ret++; } ret += up[k][0]; up[k].clear(); dist[k].clear(); down[k].clear(); for (int i = hed[k]; i != -1; i = edge[i].nex) { int v = edge[i].todot; if (vis[v]) continue; dist[v].clear(); up[v].clear(); down[v].clear(); } return ret; } long long getans(int k) { vis[k] = 1; tot = 0; dist[k].clear(); down[k].clear(); Merge(k, k, k, 0, 0, 0); up[k].clear(); getup(k, k, k, 0, 0); for (int i = hed[k]; i != -1; i = edge[i].nex) { int v = edge[i].todot; if (vis[v]) continue; up[v].clear(); getup(v, k, v, 0, 0); } long long ret = calc(k); for (int i = hed[k]; i != -1; i = edge[i].nex) { int v = edge[i].todot; if (vis[v]) continue; nsize = 0; getsize(v, k); root = 0; getroot(v, k); ret += getans(root); } return ret; } int main() { n = read(); M = read(); pw[0] = 1 % M; for (int i = 1; i <= n; i++) pw[i] = (pw[i - 1] * 10) % M; nedge = 0; memset(hed, -1, sizeof(hed)); for (int i = 1; i <= n - 1; i++) { int a, b; long long c; a = read(); b = read(); c = read(); ++a; ++b; addedge(a, b, c); addedge(b, a, c); cst[a][b] = cst[b][a] = c; } maxson[0] = inf; root = 0; nsize = n; getroot(1, 1); long long ans = getans(root); printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 100000 + 10; const double PI = M_PI; const double eps = 1e-8; int dcmp(double a) { if (fabs(a) < eps) return 0; if (a > 0) return 1; return -1; } struct Point { double x, y; Point operator+(const Point &A) { return (Point){A.x + x, A.y + y}; } Point operator-(const Point &A) { return (Point){x - A.x, y - A.y}; } } P, Poly[Maxn]; int n; struct Line { Point P; Point V; } Line[Maxn]; double CalDJ(Point A, Point B) { return A.x * B.x + A.y * B.y; } double CalCJ(Point A, Point B) { return A.x * B.y - A.y * B.x; } double CalLen(Point A) { return sqrt(CalDJ(A, A)); } double CalDIS(Point P, Point A, Point B) { Point v1 = B - A, v2 = P - A, v3 = P - B; if (dcmp(CalDJ(v1, v2)) < 0) return CalLen(v2); if (dcmp(CalDJ(v1, v3)) > 0) return CalLen(v3); return fabs(CalCJ(v1, v2) / CalLen(v1)); } double Getdis(Point Q) { long long dx = Q.x - P.x, dy = Q.y - P.y; long long ret = dx * dx + dy * dy; return ret; } double Max, Min; void solve() { scanf( %d , &n); scanf( %lf%lf , &P.x, &P.y); for (int i = 1; i <= n; i++) scanf( %lf%lf , &Poly[i].x, &Poly[i].y); Min = Getdis(Poly[1]); for (int i = 1; i <= n; i++) { double di = Getdis(Poly[i]); if (di > Max) Max = di; if (di < Min) Min = di; } Poly[n + 1] = Poly[1]; for (int i = 1; i <= n; i++) { double dis = CalDIS(P, Poly[i], Poly[i + 1]); dis = dis * dis; if (dis < Min) Min = dis; } double ans = PI * (Max - Min); printf( %lf n , ans); } int main() { solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_1_V
`define SKY130_FD_SC_HD__DLRTP_1_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.06.2017 18:58:49
// Design Name:
// Module Name: VGA_driver
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module driver_vga_640x480(clk_vga, hs, vs,hc_visible,vc_visible);
input clk_vga; // 25 MHz !
output hs, vs;
output [9:0]hc_visible;
output [9:0]vc_visible;
//640x480 original
parameter hpixels = 10'd800; // --Value of pixels in a horizontal line
parameter vlines = 10'd500; // --Number of horizontal lines in the display
parameter hfp = 10'd16; // --Horizontal front porch
parameter hsc = 10'd64; // --Horizontal sync
parameter hbp = 10'd80; // --Horizontal back porch
parameter vfp = 10'd3; // --Vertical front porch
parameter vsc = 10'd4; // --Vertical sync
parameter vbp = 10'd13; // --Vertical back porch
reg [9:0] hc, hc_next, vc, vc_next; // --These are the Horizontal and Vertical counters
assign hc_visible = ((hc < (hpixels - hfp)) && (hc > (hsc + hbp)))?(hc -(hsc + hbp)):10'd0;
assign vc_visible = ((vc < (vlines - vfp)) && (vc > (vsc + vbp)))?(vc - (vsc + vbp)):10'd0;
// --Runs the horizontal counter
always@(*)
if(hc == hpixels) // --If the counter has reached the end of pixel count
hc_next = 10'd0; // --reset the counter
else
hc_next = hc + 10'd1; // --Increment the horizontal counter
// --Runs the vertical counter
always@(*)
if(hc == 10'd0)
if(vc == vlines)
vc_next = 10'd0;
else
vc_next = vc + 10'd1;
else
vc_next = vc;
always@(posedge clk_vga)
{hc, vc} <= {hc_next, vc_next};
assign hs = (hc < hsc) ? 1'b0 : 1'b1; // --Horizontal Sync Pulse
assign vs = (vc < vsc) ? 1'b0 : 1'b1; // --Vertical Sync Pulse
endmodule
module driver_vga_1024x768(clk_vga, hs, vs,hc_visible,vc_visible);
input clk_vga; // 82 MHz !
output hs, vs;
output [10:0]hc_visible;
output [10:0]vc_visible;
parameter hpixels = 11'd1360; // --Value of pixels in a horizontal line
parameter vlines = 11'd805; // --Number of horizontal lines in the display
parameter hfp = 11'd64; // --Horizontal front porch
parameter hsc = 11'd104; // --Horizontal sync
parameter hbp = 11'd168; // --Horizontal back porch
parameter vfp = 11'd3; // --Vertical front porch
parameter vsc = 11'd4; // --Vertical sync
parameter vbp = 11'd30; // --Vertical back porch
reg [10:0] hc, hc_next, vc, vc_next; // --These are the Horizontal and Vertical counters
assign hc_visible = ((hc < (hpixels - hfp)) && (hc > (hsc + hbp)))?(hc -(hsc + hbp)):10'd0;
assign vc_visible = ((vc < (vlines - vfp)) && (vc > (vsc + vbp)))?(vc - (vsc + vbp)):10'd0;
// --Runs the horizontal counter
always@(*)
if(hc == hpixels) // --If the counter has reached the end of pixel count
hc_next = 11'd0; // --reset the counter
else
hc_next = hc + 11'd1; // --Increment the horizontal counter
// --Runs the vertical counter
always@(*)
if(hc == 11'd0)
if(vc == vlines)
vc_next = 11'd0;
else
vc_next = vc + 11'd1;
else
vc_next = vc;
always@(posedge clk_vga)
{hc, vc} <= {hc_next, vc_next};
assign hs = (hc < hsc) ? 1'b0 : 1'b1; // --Horizontal Sync Pulse
assign vs = (vc < vsc) ? 1'b0 : 1'b1; // --Vertical Sync Pulse
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__OR3_PP_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long ar[5000005]; int main() { string s; cin >> s; long long sz = s.size(); long long cnt = 0; for (int i = 0; i < sz; i++) { long long l = 0, w = 0; for (int j = i; j < sz; j++) { if (s[j] == ( ) l++; else if (s[j] == ) ) l--; else w++; if (w > l && w != 0) { w--; l++; } if (l < 0) break; if (w == l) cnt++; } } cout << cnt << endl; }
|
#include <bits/stdc++.h> const double eps = 1e-06; int main() { double t, s, q; scanf( %lf%lf%lf , &t, &s, &q); double v = (q - 1.0) / q; int cnt = 1; while (true) { s = s / (1 - v); if (s > t - eps) break; cnt++; } printf( %d n , cnt); return 0; }
|
`timescale 1 ns / 100 ps
module top_tb #(parameter CLOCK_FREQ = 12000000, parameter BAUD_RATE = 1200) ();
reg [3:0] lpc_ad;
reg lpc_clock;
reg lpc_frame;
reg lpc_reset;
reg ext_clock;
wire uart_tx_pin;
wire lpc_clock_led;
wire lpc_frame_led;
wire lpc_reset_led;
wire uart_tx_led;
wire overflow_led;
always
#3 ext_clock = ~ext_clock;
always
#1 lpc_clock = ~lpc_clock;
initial begin
$dumpfile ("top_tb.vcd");
$dumpvars (0, top_tb);
# $finish;
end
initial begin
ext_clock = 0;
lpc_clock = 0;
lpc_frame = 1;
#10;
lpc_reset = 0;
#10;
lpc_reset = 1;
#10;
/* writing LPC: io write 0x12 to 0x60 */
@(posedge lpc_clock);
/* start condition */
lpc_frame = 0;
lpc_ad = 'b0000;
@(posedge lpc_clock);
/* direction */
lpc_frame = 1;
lpc_ad = 'b0010;
@(posedge lpc_clock);
/* address 0x0060 */
/* 00 = 1 byte */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h6;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* data */
lpc_ad = 'h1;
@(posedge lpc_clock);
lpc_ad = 'hf;
@(posedge lpc_clock);
/* turn around time */
@(posedge lpc_clock);
@(posedge lpc_clock);
/* sync */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* turn around time */
@(posedge lpc_clock);
@(posedge lpc_clock);
#100;
/* writing LPC: io read 0x12 to 0x60 */
@(posedge lpc_clock);
/* start condition */
lpc_frame = 0;
lpc_ad = 'b0000;
@(posedge lpc_clock);
/* direction */
lpc_frame = 1;
lpc_ad = 'b0000;
@(posedge lpc_clock);
/* address 0x0060 */
/* 00 = 1 byte */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h6;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* turn around time */
@(posedge lpc_clock);
@(posedge lpc_clock);
/* sync */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* data */
lpc_ad = 'h1;
@(posedge lpc_clock);
lpc_ad = 'hf;
@(posedge lpc_clock);
/* turn around time */
@(posedge lpc_clock);
@(posedge lpc_clock);
#100;
/* writing LPC: mem read 0x12 to 0x60 */
@(posedge lpc_clock);
/* start condition */
lpc_frame = 0;
lpc_ad = 'b0000;
@(posedge lpc_clock);
/* cycle + direction */
lpc_frame = 1;
lpc_ad = 'b0100;
@(posedge lpc_clock);
/* address 0x12345678 */
/* 00 = 1 byte */
lpc_ad = 'h1;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h2;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h3;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h4;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h5;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h6;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h7;
@(posedge lpc_clock);
/* 00 = 1 byte */
lpc_ad = 'h8;
@(posedge lpc_clock);
/* turn around time */
@(posedge lpc_clock);
@(posedge lpc_clock);
/* sync */
lpc_ad = 'h0;
@(posedge lpc_clock);
/* byte */
lpc_ad = 'h1;
@(posedge lpc_clock);
lpc_ad = 'hf;
@(posedge lpc_clock);
/* turn around time */
@(posedge lpc_clock);
@(posedge lpc_clock);
@(posedge lpc_clock);
$finish;
end
top #(.CLOCK_FREQ(CLOCK_FREQ), .BAUD_RATE(BAUD_RATE))
TOP (
.lpc_ad(lpc_ad),
.lpc_clock(lpc_clock),
.lpc_frame(lpc_frame),
.lpc_reset(lpc_reset),
.ext_clock(ext_clock),
.uart_tx_pin(uart_tx_pin),
.lpc_clock_led(lpc_clock_led),
.lpc_frame_led(lpc_frame_led),
.lpc_reset_led(lpc_reset_led),
.overflow_led(overflow_led));
endmodule
|
`timescale 1ns / 1ps
module VGA(
input CLK_25MH,
input CLK_50MH,
output reg [5:0] RGB,
output reg hsync,
output reg vsync,
output [9:0] hor_count,
output [9:0] ver_count,
input [2:0] rgb_in,
input [9:0] paddle_pos,
input [9:0] ball_x,
input [9:0] ball_y,
input reset,
input active_write_enable,
input [5:0] active_position,
input [1:0] active_data
);
parameter
BALL_SIZE = 7,
BLOCK_SPACING_X = 10'd40,
BLOCK_WIDTH = 10'd80,
BLOCK_HEIGHT = 10'd30,
FIRST_ROW_Y = 10'd40,
SECOND_ROW_Y = 10'd90,
THIRD_ROW_Y = 10'd140,
FOURTH_ROW_Y = 10'd190,
FIFTH_ROW_Y = 10'd240;
reg [9:0] hcount;
reg [9:0] vcount;
assign hor_count = hcount;
assign ver_count = vcount;
reg [9:0] data_x [19:0];
reg [9:0] data_y [19:0];
reg [2:0] active [19:0];
reg [4:0] i;
reg [5:0] block_colors [24:0];
always @ (posedge CLK_50MH) begin
if(active_write_enable)
active[active_position] = active_data;
if (reset) begin
//initialize rows and columns of block
for (i = 0; i < 20; i = i + 1) begin
if(i < 5) begin
data_x[i] = BLOCK_SPACING_X + (BLOCK_SPACING_X + BLOCK_WIDTH) * i;
data_y[i] = FIRST_ROW_Y;
block_colors[i] = 6'b001001;
active[i] = 0;
end
else if (i < 10) begin
data_x[i] = BLOCK_SPACING_X + ((BLOCK_SPACING_X + BLOCK_WIDTH) * (i-5));
data_y[i] = SECOND_ROW_Y;
block_colors[i] = 6'b110101;
active[i] = 0;
end
else if (i < 15) begin
data_x[i] = BLOCK_SPACING_X + ((BLOCK_SPACING_X + BLOCK_WIDTH) * (i-10));
data_y[i] = THIRD_ROW_Y;
block_colors[i] = 6'b011111;
active[i] = 0;
end
else if (i < 20) begin
data_x[i] = BLOCK_SPACING_X + ((BLOCK_SPACING_X + BLOCK_WIDTH) * (i-15));
data_y[i] = FOURTH_ROW_Y;
block_colors[i] = 6'b100101;
active[i] = 0;
end
else if (i < 25) begin
data_x[i] = BLOCK_SPACING_X + ((BLOCK_SPACING_X + BLOCK_WIDTH) * (i-20));
data_y[i] = FIFTH_ROW_Y;
block_colors[i] = 6'b000010;
active[i] = 0;
end
end
end
end
always @ ( posedge CLK_25MH)
begin
if (hcount == 799) begin
hcount = 0;
if (vcount == 524) begin
vcount = 0;
end
else begin
vcount = vcount + 1;
end
end
else begin
hcount = hcount + 1;
end
if (vcount >= 490 && vcount < 492) begin
vsync = 0;
end
else begin
vsync = 1;
end
if (hcount >= 656 && hcount < 752) begin
hsync = 0;
end
else begin
hsync = 1;
end
if (hcount < 640 && vcount < 480) begin
RGB = 6'b000;//'
if(vcount >= ball_y && vcount <= (ball_y + BALL_SIZE)//ball
&& hcount >= ball_x && hcount <= (ball_x + BALL_SIZE) )
RGB = 6'b111000;//'
if(vcount > 440 && vcount < 450 &&
hcount > paddle_pos && hcount < paddle_pos + 100)begin//paddle
RGB = 6'b100001;//'
end
else begin
for (i = 0; i < 20; i = i + 1) begin
//first row of blocks (upper)
//if(i < 5)begin
if(active[i] != 2'b11 && (vcount >= data_y[i] && vcount <= (data_y[i] + BLOCK_HEIGHT))
&& hcount >= data_x[i] && hcount <= (data_x[i] + BLOCK_WIDTH))
begin
RGB = block_colors[i] + active[i] + 6'b000001;
end
/*
end
else begin
//second row of blocks
if(active[i] != 2'b11 && (vcount >= data_y[i] && vcount <= (data_y[i] + BLOCK_HEIGHT))
&& hcount >= data_x[i] && hcount <= (data_x[i] + BLOCK_WIDTH))
begin
RGB = block_colors[i] + active[i] + 6'b000001;
end
end
*/
end
end
end
else begin
RGB = 6'b000;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, k; const int N = 5050; int a[N]; int dp[N][N]; int cnt[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.setstate(ios_base::failbit); cin >> n >> k; for (int i = 1; i < (n + 1); i++) cin >> a[i]; sort(a + 1, a + n + 1); int j = n; for (int i = (n + 1) - 1; i >= 1; i--) { while (j > 0 && abs(a[j] - a[i]) <= 5) j--; cnt[i] = i - j; } for (int i = 1; i < (n + 1); i++) for (int j = 1; j < (k + 1); j++) { int &ans = dp[i][j]; ans = max(ans, dp[i - 1][j]); ans = max(ans, dp[i - cnt[i]][j - 1] + cnt[i]); } cout << dp[n][k] << n ; }
|
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module pll (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t, sum; cin >> s >> t; string n = to_string(stoi(s) + stoi(t)); s.erase(remove(s.begin(), s.end(), 0 ), s.end()); t.erase(remove(t.begin(), t.end(), 0 ), t.end()); n.erase(remove(n.begin(), n.end(), 0 ), n.end()); if (stoi(s) + stoi(t) == stoi(n)) cout << YES << endl; else cout << NO << endl; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; int n; int x[300010]; int y[300010]; pair<int, int> izq, der, down, up; int ereccion(int i, int j, int k) { vector<int> pito, ura; pito.push_back(x[i]); pito.push_back(x[j]); pito.push_back(x[k]); ura.push_back(y[i]); ura.push_back(y[j]); ura.push_back(y[k]); sort(pito.begin(), pito.end()); sort(ura.begin(), ura.end()); return pito.back() - pito[0] + ura.back() - ura[0]; } int triangulo() { set<int> pingo; pingo.insert(der.second); pingo.insert(izq.second); pingo.insert(up.second); pingo.insert(down.second); if (pingo.size() != 4) { return 2 * (der.first - izq.first) + 2 * (up.first - down.first); } vector<int> concha; for (auto pito : pingo) { concha.push_back(pito); } int ans = -1; for (int i = 0; i < 4; i++) { for (int j = i + 1; j < 4; j++) { int u = concha[i]; int v = concha[j]; for (int k = 0; k < n; k++) { if (k != u && k != v) { ans = max(ans, ereccion(u, v, k)); } } } } return 2 * ans; } int main() { scanf( %d , &n); izq = make_pair(INF, 0); down = make_pair(INF, 0); der = make_pair(-INF, 0); up = make_pair(-INF, 0); for (int i = 0; i < n; i++) { scanf( %d %d , &x[i], &y[i]); down = min(down, make_pair(y[i], i)); up = max(up, make_pair(y[i], i)); der = max(der, make_pair(x[i], i)); izq = min(izq, make_pair(x[i], i)); } printf( %d , triangulo()); int anss = 2 * (der.first - izq.first) + 2 * (up.first - down.first); for (int i = 4; i <= n; i++) { printf( %d , anss); } puts( ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_32_V
`define SKY130_FD_SC_HVL__BUF_32_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 32 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_32 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_32 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_32_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_1_V
`define SKY130_FD_SC_LS__OR2B_1_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or2b_1 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or2b_1 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__FAH_BEHAVIORAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; template <class S, class T> ostream &operator<<(ostream &os, const pair<S, T> v) { os << ( << v.first << , << v.second << ) ; return os; } template <class T> ostream &operator<<(ostream &os, const vector<T> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << ; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const vector<vector<T>> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << endl; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const vector<set<T>> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << endl; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const set<T> &v) { int i = 0; for (auto it : v) { if (i > 0) { os << ; } os << it; i++; } return os; } using Graph = vector<vector<int>>; const ll MAX_S = 2e5; vector<ll> check(vector<ll> &x) { vector<ll> anss(x.size()); for (int i = 0; i < int(x.size()) - 1; ++i) { anss[i + 1] = x[i + 1] - x[i]; } anss[0] = x[0]; return anss; } using Value = ll; const Value ini = ll(1e18); Value connect(Value al, const Value ar) { return min(al, ar); } Value dat[1100001]; struct segtree { int N; segtree() {} segtree(int n) { N = 1; while (N < n) N *= 2; for (int x = 0; x < N; ++x) { dat[x + N - 1] = ini; } for (int x = N - 2; x >= 0; --x) { dat[x] = connect(dat[x * 2 + 1], dat[x * 2 + 2]); } } void update(int k, const Value &a) { k += N - 1; dat[k] = a; while (k > 0) { k = (k - 1) >> 1; dat[k] = connect(dat[k * 2 + 1], dat[k * 2 + 2]); } } Value query(int a, int b) { return query(a, b, 0, 0, N); } Value query(int a, int b, int k, int l, int r) { if (r <= a || b <= l) return ini; if (a <= l && r <= b) return dat[k]; const int m = (l + r) / 2; return connect(query(a, b, k * 2 + 1, l, m), query(a, b, k * 2 + 2, m, r)); } }; vector<int> nums(int(3e5)); ll to_n(string st) { ll num = 0; for (auto c : st) { num *= 2; num += c - 0 ; } return num; } string to_s(int sz, ll num) { string st; for (int i = 0; i < sz; ++i) { st.push_back( 0 + (num % 2)); num /= 2; } reverse(st.begin(), st.end()); return st; } const int mod = 998244353; struct Mod { public: int num; Mod() : Mod(0) { ; } Mod(long long int n) : num((n % mod + mod) % mod) {} Mod(int n) : Mod(static_cast<long long int>(n)) { ; } operator int() { return num; } }; Mod operator+(const Mod a, const Mod b) { return Mod((a.num + b.num) % mod); } Mod operator+(const long long int a, const Mod b) { return Mod(a) + b; } Mod operator+(const Mod a, const long long int b) { return b + a; } Mod operator++(Mod &a) { return a + Mod(1); } Mod operator-(const Mod a, const Mod b) { return Mod((mod + a.num - b.num) % mod); } Mod operator-(const long long int a, const Mod b) { return Mod(a) - b; } Mod operator--(Mod &a) { return a - Mod(1); } Mod operator*(const Mod a, const Mod b) { return Mod(((long long)a.num * b.num) % mod); } Mod operator*(const long long int a, const Mod b) { return Mod(a) * b; } Mod operator*(const Mod a, const long long int b) { return Mod(b) * a; } Mod operator*(const Mod a, const int b) { return Mod(b) * a; } Mod operator+=(Mod &a, const Mod b) { return a = a + b; } Mod operator+=(long long int &a, const Mod b) { return a = a + b; } Mod operator-=(Mod &a, const Mod b) { return a = a - b; } Mod operator-=(long long int &a, const Mod b) { return a = a - b; } Mod operator*=(Mod &a, const Mod b) { return a = a * b; } Mod operator*=(long long int &a, const Mod b) { return a = a * b; } Mod operator*=(Mod &a, const long long int &b) { return a = a * b; } Mod operator^(const Mod a, const int n) { if (n == 0) return Mod(1); Mod res = (a * a) ^ (n / 2); if (n % 2) res = res * a; return res; } Mod mod_pow(const Mod a, const long long n) { if (n == 0) return Mod(1); Mod res = mod_pow((a * a), (n / 2)); if (n % 2) res = res * a; return res; } Mod inv(const Mod a) { return a ^ (mod - 2); } Mod operator/(const Mod a, const Mod b) { assert(b.num != 0); return a * inv(b); } Mod operator/(const long long int a, const Mod b) { return Mod(a) / b; } Mod operator/=(Mod &a, const Mod b) { return a = a / b; } Mod fact[1024000], factinv[1024000]; void init(const int amax = 1024000) { fact[0] = Mod(1); factinv[0] = 1; for (int i = 0; i < amax - 1; ++i) { fact[i + 1] = fact[i] * Mod(i + 1); factinv[i + 1] = factinv[i] / Mod(i + 1); } } Mod comb(const int a, const int b) { return fact[a] * factinv[b] * factinv[a - b]; } int main() { int N; cin >> N; vector<Mod> pers(int(1e6)); vector<int> cnts(int(1e6)); for (int i = 0; i < N; ++i) { int k; scanf( %d , &k); for (int j = 0; j < k; ++j) { int a; scanf( %d , &a); a--; cnts[a]++; pers[a] += Mod(1) / Mod(N) / Mod(k); } } Mod answer = Mod(0); for (int i = 0; i < int(1e6); ++i) { answer += pers[i] * Mod(cnts[i]) / Mod(N); } cout << answer.num << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int a[60000], x, mn = 0x3f3f3f3f; int main() { int n, m; cin >> m >> n; for (int i = 1; i <= n; i++) { cin >> x; a[x]++; } sort(a + 1, a + m + 1); cout << a[1]; return 0; }
|
/*
* schoolMIPS - small MIPS CPU for "Young Russian Chip Architects"
* summer school ( )
*
* originally based on Sarah L. Harris MIPS CPU
*
* Copyright(c) 2017 Stanislav Zhelnio
* Alexander Romanov
*/
`include "sm_cpu.vh"
module sm_cpu
(
input clk, // clock
input rst_n, // reset
input [ 4:0] regAddr, // debug access reg address
output [31:0] regData, // debug access reg data
output [31:0] imAddr, // instruction memory address
input [31:0] imData, // instruction memory data
input [7:0] exData // External data from GPIOs
);
//control wires
wire pcSrc;
wire regDst;
wire regWrite;
wire aluSrc;
wire aluZero;
wire [ 3:0] aluControl;
wire exControl;
//program counter
wire [31:0] pc;
wire [31:0] pcBranch;
wire [31:0] pcNext = pc + 1;
wire [31:0] pc_new = ~pcSrc ? pcNext : pcBranch;
sm_register r_pc(clk, rst_n, pc_new, pc);
//program memory access
assign imAddr = pc;
wire [31:0] instr = imData;
//debug register access
wire [31:0] rd0;
assign regData = (regAddr != 0) ? rd0 : pc;
//register file
wire [ 4:0] a3 = regDst ? instr[15:11] : instr[20:16];
wire [31:0] rd1;
wire [31:0] rd2;
wire [31:0] wd3;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instr[25:21] ),
.a2 ( instr[20:16] ),
.a3 ( a3 ),
.rd0 ( rd0 ),
.rd1 ( rd1 ),
.rd2 ( rd2 ),
.wd3 ( wd3 ),
.we3 ( regWrite )
);
//sign extension
wire signExtend;
wire [31:0] signImm = (exControl) ? {{24 { exData[7] }}, exData[7:0] }
: (~signExtend) ? { {16 { instr[15] }}, instr[15:0] } : { {16 {1'b0}}, instr[15:0] };
assign pcBranch = pcNext + signImm;
//alu
wire [31:0] srcB = aluSrc ? signImm : rd2;
sm_alu alu
(
.srcA ( (exControl) ? 32'b0: rd1 ),
.srcB ( srcB ),
.oper ( aluControl ),
.shift ( instr[10:6 ] ),
.sign ( aluZero ),
.result ( wd3 )
);
//control
sm_control sm_control
(
.cmdOper ( instr[31:26] ),
.cmdFunk ( instr[ 5:0 ] ),
.aluZero ( aluZero ),
.pcSrc ( pcSrc ),
.regDst ( regDst ),
.regWrite ( regWrite ),
.aluSrc ( aluSrc ),
.aluControl ( aluControl ),
.exControl ( exControl )
);
endmodule
module sm_control
(
input [5:0] cmdOper,
input [5:0] cmdFunk,
input aluZero,
output pcSrc,
output reg regDst,
output reg regWrite,
output reg aluSrc,
output reg [3:0] aluControl,
output reg exControl
);
reg branch;
reg condZero;
assign pcSrc = branch & (aluZero == condZero);
always @ (*) begin
branch = 1'b0;
condZero = 1'b0;
regDst = 1'b0;
regWrite = 1'b0;
aluSrc = 1'b0;
aluControl = `ALU_ADD;
exControl = 1'b0;
casez( {cmdOper,cmdFunk} )
default : ;
{ `C_SPEC, `F_ADDU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD; end
{ `C_SPEC, `F_OR } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR; end
{ `C_SPEC, `F_AND } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_AND; end
{ `C_SPEC, `F_SRL } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL; end
{ `C_SPEC, `F_SLTU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
{ `C_SPEC, `F_SUBU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end
{ `C_SPEC, `F_SRLV } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRLV; end
{ `C_ADDIU, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; end
{ `C_LUI, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI; end
{ `C_BEQ, `F_ANY } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
{ `C_BNE, `F_ANY } : begin branch = 1'b1; aluControl = `ALU_SUBU; end
{ `C_BGEZ, `F_ANY } : begin branch = 1'b1; aluControl = `ALU_NOTNEG; end
{ `C_EXT, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; exControl = 1'b1; aluControl = `ALU_ADD; end
endcase
end
endmodule
module sm_alu
(
input [31:0] srcA,
input [31:0] srcB,
input [ 3:0] oper,
input [ 4:0] shift,
output sign,
output reg [31:0] result
);
always @ (*) begin
case (oper)
default : result = srcA + srcB;
`ALU_ADD : result = srcA + srcB;
`ALU_OR : result = srcA | srcB;
`ALU_AND : result = srcA & srcB;
`ALU_LUI : result = (srcB << 16);
`ALU_SRL : result = srcB >> shift;
`ALU_SRLV : result = srcB >> srcA;
`ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
`ALU_SUBU : result = srcA - srcB;
`ALU_NOR : result = ~(srcA | srcB);
`ALU_NOTNEG : result = srcB >=0;
endcase
end
assign sign = (result == 0);
endmodule
module sm_register_file
(
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf [31:0];
assign rd0 = (a0 != 0) ? rf [a0] : 32'b0;
assign rd1 = (a1 != 0) ? rf [a1] : 32'b0;
assign rd2 = (a2 != 0) ? rf [a2] : 32'b0;
always @ (posedge clk)
if(we3) rf [a3] <= wd3;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e3 + 5; int n, a[N][N]; char s[N]; bool vis[N]; void dfs(int x, int fa) { vis[x] = 1; for (int i = 1; i <= n; i++) { if (!a[x][i] || i == fa || i == x) continue; if (a[i][fa]) printf( %d %d %d n , x, i, fa), exit(0); if (!vis[i]) dfs(i, x); } } signed main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); for (int j = 1; j <= n; j++) a[i][j] = s[j] - 0 ; } for (int i = 1; i <= n; i++) if (!vis[i]) dfs(i, 0); puts( -1 ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_P_TB_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_P_TB_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dlatch_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hdll__udp_dlatch$P dut (.D(D), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_P_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int tc = 1; tc <= t; tc++) { int n; cin >> n; pair<pair<int, int>, int> arr[2 * n - 1]; for (int i = 0; i < 2 * n - 1; i++) { cin >> arr[i].first.first >> arr[i].first.second; arr[i].second = i; } sort(arr, arr + 2 * n - 1); long long odd = 0, even = 0; for (int i = 0; i < 2 * n - 1; i++) { if (i & 1) even += arr[i].first.second; else odd += arr[i].first.second; } if (odd >= even) { cout << YES n ; int ans[n]; for (int i = 0; i < 2 * n - 1; i += 2) ans[i / 2] = arr[i].second + 1; sort(ans, ans + n); for (int i = 0; i < n - 1; i++) cout << ans[i] << ; cout << ans[n - 1] << n ; } else { cout << YES n ; int ans[n]; for (int i = 1; i < 2 * n - 1; i += 2) ans[i / 2] = arr[i].second + 1; ans[n - 1] = arr[2 * n - 2].second + 1; sort(ans, ans + n); for (int i = 0; i < n - 1; i++) cout << ans[i] << ; cout << ans[n - 1] << n ; } } }
|
// megafunction wizard: %ALTSYNCRAM%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: altera_spram_256x32.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 216 03/06/2006 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_spram_256x32 (
address,
byteena_a,
clock,
data,
wren,
q);
input [7:0] address;
input [3:0] byteena_a;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena_a),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.q_b (),
.clocken1 (1'b1),
.clocken0 (1'b1),
.data_b (1'b1),
.rden_b (1'b1),
.address_b (1'b1),
.wren_b (1'b0),
.byteena_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.clock1 (1'b1));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32_bb.v TRUE
|
#include <bits/stdc++.h> using namespace std; long long int power(int b, int pw) { long long int res = 1; for (int i = 1; i <= pw; i++) { res = res * b; } return res; } long long int typ[1000000]; int main() { ios_base::sync_with_stdio(false); long long int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> typ[i]; } set<int> prev; vector<pair<int, int> > ns; long long int cnt = 0; long long int from = 1; for (int i = 1; i <= n; i++) { if (prev.find(typ[i]) != prev.end()) { ns.push_back(make_pair(from, i)); prev.clear(); from = i + 1; } else { prev.insert(typ[i]); } } if (ns.size() == 0) { printf( -1 n ); return 0; } cout << ns.size() << endl; int temp = ns.size(); for (int i = 0; i < ns.size(); i++) { if (i == temp - 1) { cout << ns[i].first << << n << endl; return 0; } cout << ns[i].first << << ns[i].second << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int incoming[110]; int outgoing[110]; int main(int argc, const char* argv[]) { int n, m; cin >> n >> m; int a, b, c; for (int i = 0; i < m; i++) { cin >> a >> b >> c; incoming[b] += c; outgoing[a] += c; } int ans = 0; for (int i = 1; i <= n; i++) { if (outgoing[i] - incoming[i] > 0) ans += outgoing[i] - incoming[i]; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int pos, neg, tmp, x, y, len; int main() { scanf( %d%d , &n, &m); pos = 0; neg = 0; for (int i = 0; i < n; ++i) { scanf( %d , &tmp); if (tmp > 0) ++pos; else ++neg; } while (m--) { scanf( %d%d , &x, &y); len = y - x + 1; if (len & 1) printf( 0 n ); else { if (len / 2 <= min(pos, neg)) printf( 1 n ); else printf( 0 n ); } } return 0; }
|
//-------------------------------------------------------------------
//-- scicad1_tb
//-- Banco de pruebas para el ejemplo de transmision continua de
//-- cadenas
//-------------------------------------------------------------------
//-- BQ September 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`include "baudgen.vh"
module scicad1_tb();
//-- Baudios con los que realizar la simulacion
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
localparam FRAME = (BITRATE * 11);
//-- Tiempo entre dos bits enviados
localparam FRAME_WAIT = (BITRATE * 4);
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente
scicad1 #(.BAUD(BAUD))
dut(
.clk(clk),
.dtr(dtr),
.tx(tx)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("scicad1_tb.vcd");
$dumpvars(0, scicad1_tb);
#1 dtr <= 0;
//-- Comenzar primer envio
#FRAME_WAIT dtr <= 1;
#(BITRATE * 2) dtr <=0;
//-- Segundo envio (2 caracteres mas)
#(FRAME * 11) dtr <=1;
#(BITRATE * 1) dtr <=0;
#(FRAME * 11) $display("FIN de la simulacion");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
module VIDEO_FETCHER(
input RST_I,
input CLK_I_25MHZ,
input VSYNC_I,
input VFEN_I,
output [12:0] RAM_ADR_O,
output RAM_CYC_O,
output RAM_STB_O,
input RAM_ACK_I,
input [15:0] RAM_DAT_I,
output [ 5:0] LB_ADR_O,
output [15:0] LB_DAT_O,
output LB_WE_O
);
reg [12:0] bitmap_ptr;
reg bitmap_fetch_in_progress;
reg [12:0] n_bitmap_ptr;
reg n_bitmap_fetch_in_progress;
reg last_transfer;
reg start_transfer;
reg [ 5:0] fetch_counter;
reg [ 5:0] n_fetch_counter;
reg o_vfen;
reg rst_fetch_ctr;
reg inc_fetch_ctr;
reg line_buffer_write;
assign RAM_ADR_O = bitmap_ptr;
assign RAM_CYC_O = bitmap_fetch_in_progress;
assign RAM_STB_O = bitmap_fetch_in_progress;
assign LB_ADR_O = fetch_counter;
assign LB_WE_O = line_buffer_write;
assign LB_DAT_O = RAM_DAT_I;
always @(posedge CLK_I_25MHZ) begin
bitmap_ptr <= n_bitmap_ptr;
bitmap_fetch_in_progress <= n_bitmap_fetch_in_progress;
fetch_counter <= n_fetch_counter;
o_vfen <= VFEN_I;
end
always @(*) begin
start_transfer <= VFEN_I & !o_vfen;
last_transfer <= (fetch_counter == 40);
rst_fetch_ctr <= (RST_I | last_transfer);
line_buffer_write <= RAM_CYC_O & RAM_STB_O & RAM_ACK_I;
inc_fetch_ctr <= (bitmap_fetch_in_progress & line_buffer_write);
case({VSYNC_I, line_buffer_write})
2'b10: n_bitmap_ptr <= bitmap_ptr;
2'b11: n_bitmap_ptr <= bitmap_ptr+1;
default: n_bitmap_ptr <= 0;
endcase
case({rst_fetch_ctr, inc_fetch_ctr})
2'b01: n_fetch_counter <= fetch_counter+1;
2'b10: n_fetch_counter <= 0;
2'b11: n_fetch_counter <= 0;
default: n_fetch_counter <= fetch_counter;
endcase
case({start_transfer, last_transfer})
3'b01: n_bitmap_fetch_in_progress <= 0;
3'b10: n_bitmap_fetch_in_progress <= !RST_I;
default: n_bitmap_fetch_in_progress <= (RST_I)? 0 : bitmap_fetch_in_progress;
endcase
end
endmodule
|
/**
\file "channel-ledr-source-sink.v"
Chain a source and sink in prsim to verilog.
$Id: channel-source-sink.v,v 1.4 2010/04/06 00:08:26 fang Exp $
*/
`timescale 1ns/1ps
`include "standard.v"
`define inv_delay 0.020
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg l0, l1;
wire r0, r1;
DELAY #(.delay(`inv_delay)) d0(l0, r0);
DELAY #(.delay(`inv_delay)) d1(l1, r1);
// prsim stuff
initial
begin
// @haco@ channel-ledr-source-sink.haco-c
$prsim("channel-ledr-source-sink.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("echo-commands on");
$from_prsim("L.d","TOP.l0");
$from_prsim("L.r","TOP.l1");
$to_prsim("TOP.r0", "R.d");
$to_prsim("TOP.r1", "R.r");
$prsim_cmd("breaks");
$prsim_cmd("watchall");
// $prsim_cmd("watchall-queue");
$prsim_cmd("channel-ledr L : :0 d:0 r:0");
$prsim_cmd("channel-ledr R : :0 d:0 r:0");
$prsim_cmd("channel-source-args-loop L 0 1 1 0");
$prsim_cmd("channel-expect-args-loop R 0 1 1 0");
$prsim_cmd("channel-watchall");
$prsim_cmd("channel-ignore-all");
$prsim_cmd("channel-reset-all");
$prsim_cmd("channel-show-all");
// $prsim_cmd("breaks");
#2 $prsim_cmd("channel-release-all");
$prsim_cmd("channel-heed-all");
$prsim_cmd("channel-show-all");
#1 $prsim_cmd("nowatchall");
#2 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void debug(T a, T b) { ; } template <class T> void chmin(T& a, const T& b) { if (a > b) a = b; } template <class T> void chmax(T& a, const T& b) { if (a < b) a = b; } namespace std { template <class S, class T> ostream& operator<<(ostream& out, const pair<S, T>& a) { out << ( << a.first << , << a.second << ) ; return out; } } // namespace std const int INF = 7e8; int n; int ar[300005]; int sum[300005]; vector<int> Tpos, Opos; int solve1(int a, int b, int A, int B) { if (B == INF) return INF; if (b == INF) return INF; int Tlen = B - b; int tmp = sum[b] * 1000; int pt = sum[b] * 100; int Trange = Tlen * 2000; tmp += max(0, Trange - pt); pt -= min(Trange, pt); tmp += 1000; pt += 100; int rest = (sum[n] - sum[B + 1]) * 1000; tmp += max(0, rest - pt); return tmp; } int solve2(int a, int b, int A, int B) { if (a == -1) return INF; if (A == -1) return INF; int Tlen = a - A; int tmp = sum[A] * 1000; int pt = sum[A] * 100; tmp += max(0, 1000 - pt); pt -= min(pt, 1000); int Trange = Tlen * 2000; tmp += Trange; pt += Tlen * 200; int rest = (sum[n] - sum[a + 1]) * 1000; tmp += max(0, rest - pt); return tmp; } int main() { cin >> n; Opos.push_back(-1); Tpos.push_back(-1); for (int i = 0; i < (n); ++i) { int a; scanf( %d , &a); ar[i] = a / 1000; if (ar[i] == 1) Opos.push_back(i); else Tpos.push_back(i); } Tpos.push_back(INF); Opos.push_back(INF); for (int i = 0; i < (n); ++i) sum[i + 1] = sum[i] + ar[i]; int res = INF; for (int i = 0; i < (n + 1); ++i) { int tmp = sum[i] * 1000; int pt = sum[i] * 100; int rest = (sum[n] - sum[i]) * 1000; tmp += max(0, rest - pt); chmin(res, tmp); } int prev = res; for (int i = 0; i < ((int)Tpos.size() - 1); ++i) { int a = Tpos[i], b = Tpos[i + 1]; int B = *lower_bound((Opos).begin(), (Opos).end(), b); int A = *(--lower_bound((Opos).begin(), (Opos).end(), a)); int X = solve1(a, b, A, B); int Y = solve2(a, b, A, B); chmin(res, X); chmin(res, Y); } cout << res << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
integer p_i;
reg [7*8:1] p_str;
string sv_str;
reg [7*8:1] p_in;
string sv_in;
initial begin
if ($test$plusargs("PLUS")!==1) $stop;
if ($test$plusargs("PLUSNOT")!==0) $stop;
if ($test$plusargs("PL")!==1) $stop;
//if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer
if ($test$plusargs("NOTTHERE")!==0) $stop;
p_i = 10;
if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop;
if (p_i !== 10) $stop;
p_i = 0;
if ($value$plusargs("INT=%d", p_i)!==1) $stop;
if (p_i !== 32'd1234) $stop;
p_i = 0;
if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also
if (p_i !== 32'h1234) $stop;
p_i = 0;
// Check octal and WIDTH
if (!$value$plusargs("INT=%o", p_i)) $stop;
if (p_i !== 32'o1234) $stop;
p_str = "none";
if ($value$plusargs("IN%s", p_str)!==1) $stop;
$display("str='%s'",p_str);
if (p_str !== "T=1234") $stop;
sv_str = "none";
if ($value$plusargs("IN%s", sv_str)!==1) $stop;
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
sv_str = "none";
$value$plusargs("IN%s", sv_str);
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
p_in = "IN%s";
`ifdef VERILATOR
p_in = $c(p_in); // Prevent constant propagation
`endif
sv_str = "none";
if ($value$plusargs(p_in, sv_str)!==1) $stop;
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
sv_in = "INT=%d";
`ifdef VERILATOR
if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation
`endif
p_i = 0;
if ($value$plusargs(sv_in, p_i)!==1) $stop;
$display("i='%d'",p_i);
if (p_i !== 32'd1234) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int fx[] = {1, 0, 0, -1}; int fy[] = {0, -1, 1, 0}; int n, m; int data[1002][1002], dist[1002][1002]; void bfs(int sx, int sy) { for (int i = 0; i < 1002; i++) { for (int j = 0; j < 1002; j++) dist[i][j] = INT_MAX; } queue<int> q; q.push(sx); q.push(sy); dist[sx][sy] = 0; while (!q.empty()) { int u = q.front(); q.pop(); int v = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int x = u + fx[i]; int y = v + fy[i]; if (x >= 0 && x < n && y >= 0 && y < m && data[x][y] == 0 && dist[x][y] > dist[u][v] + 1) { dist[x][y] = dist[u][v] + 1; q.push(x); q.push(y); } } } } int main() { int k; scanf( %d , &n); scanf( %d , &m); scanf( %d , &k); int sx, sy; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char ch; cin >> ch; if (ch == * ) data[i][j] = 1; else if (ch == X ) { sx = i; sy = j; } } } if (k % 2 != 0) { cout << IMPOSSIBLE n ; return 0; } bfs(sx, sy); vector<char> res; while (k > 0) { if (sx < n - 1 && dist[sx + 1][sy] < k) { sx++; res.push_back( D ); } else if (sy > 0 && dist[sx][sy - 1] < k) { sy--; res.push_back( L ); } else if (sy < m - 1 && dist[sx][sy + 1] < k) { sy++; res.push_back( R ); } else if (sx > 0 && dist[sx - 1][sy] < k) { sx--; res.push_back( U ); } else { cout << IMPOSSIBLE n ; return 0; } k--; } for (int i = 0; i < res.size(); i++) { cout << res[i]; } printf( n ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_hd__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int T, n, i, j, l, m, x, y, z, a, b, c, d, flag, count; cin >> a >> b >> c >> d; long long int sum1, sum2; sum1 = std::max((3 * a / 10), (a - ((a / 250) * c))); sum2 = std::max((3 * b / 10), (b - ((b / 250) * d))); if (sum1 > sum2) cout << Misha << endl; else if (sum1 < sum2) cout << Vasya << endl; else cout << Tie << endl; return 0; }
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#include <bits/stdc++.h> std::vector<long long> G[100001]; std::vector<long long> psn[100001]; std::vector<long long> arr[100001][20]; long long par[100001], lvl[100001]; long long P[100001][20]; void dfs_visit(long long s, long long p) { if (p != -1) { par[s] = p; lvl[s] = 1 + lvl[p]; } for (long long i = 0, j = (long long)G[s].size(); i < j; i++) { if (G[s][i] != p) dfs_visit(G[s][i], s); } return; } std::vector<long long> merger(std::vector<long long> left, std::vector<long long> right) { std::vector<long long> res; long long n1 = (long long)left.size(), n2 = (long long)right.size(); long long i = 0, j = 0, k = 0; while (i != n1 && j != n2 && k != 10) { if (left[i] < right[j]) { res.push_back(left[i]); i++; } else if (left[i] > right[j]) { res.push_back(right[j]); j++; } else { res.push_back(left[i]); i++; j++; } k++; } while (i != n1 && k != 10) { res.push_back(left[i]); i++; k++; } while (j != n2 && k != 10) { res.push_back(right[j]); j++; k++; } return res; } void ST_build(long long n) { for (long long i = 1; i <= n; i++) { for (long long j = 0; (1 << j) <= n; j++) P[i][j] = -1; } for (long long i = 1; i <= n; i++) { P[i][0] = par[i]; arr[i][0] = merger(psn[i], psn[par[i]]); } for (long long j = 1; (1 << j) <= n; j++) { for (long long i = 1; i <= n; i++) { if (P[i][j - 1] != -1) { P[i][j] = P[P[i][j - 1]][j - 1]; arr[i][j] = merger(arr[i][j - 1], arr[P[i][j - 1]][j - 1]); } } } return; } std::vector<long long> LCA_find(long long p, long long q) { std::vector<long long> res = merger(psn[p], psn[q]); if (lvl[p] < lvl[q]) { long long tmp = p; p = q; q = tmp; } long long lx = 0; for (lx = 1; (1 << lx) <= lvl[p]; lx++) ; lx--; for (long long i = lx; i >= 0; i--) { if ((lvl[p] - (1 << i)) >= lvl[q]) { res = merger(res, arr[p][i]); p = P[p][i]; } } if (p == q) return res; for (long long i = lx; i >= 0; i--) { if ((P[p][i] != -1) && (P[p][i] != P[q][i])) { res = merger(res, arr[p][i]); res = merger(res, arr[q][i]); p = P[p][i]; q = P[q][i]; } } res = merger(res, arr[p][0]); res = merger(res, arr[q][0]); return res; } int main(void) { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); std::cout.tie(NULL); long long n, m, q; std::cin >> n >> m >> q; for (long long i = 0; i < n - 1; i++) { long long s, d; std::cin >> s >> d; G[s].push_back(d); G[d].push_back(s); } for (long long i = 1; i <= m; i++) { long long t; std::cin >> t; if ((long long)psn[t].size() < 10) psn[t].push_back(i); } dfs_visit(1, -1); ST_build(n); while (q--) { long long v, u, a; std::cin >> v >> u >> a; std::vector<long long> ans = LCA_find(v, u); a = std::min(a, (long long)ans.size()); std::cout << a << ; for (long long i = 0; i < a; i++) std::cout << ans[i] << ; std::cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; struct xy { int x, y; }; int a[1212121], par[1212121], depth[1212121]; vector<int> C[1212121]; void dfs(int w, int dep) { depth[w] = dep; for (int nxt : C[w]) dfs(nxt, dep + 1); } int Hn = 0, myH[1212121], sz[1212121], root[1212121], ppar[1212121]; int find(int x) { if (ppar[x] == x) return x; return ppar[x] = find(ppar[x]); } multiset<int> S[1212121], ansS; void push(int x) { sz[x] = 1; int mx = 0, mxw; for (int child : C[x]) { sz[x] += sz[child]; if (mx < sz[child] && S[myH[child]].size() > 0) mx = sz[child], mxw = child; } if (mx == 0) { int hIdx = ++Hn; myH[x] = hIdx; root[hIdx] = x; S[hIdx].insert(depth[x]); ppar[hIdx] = hIdx; ansS.insert(0); } else { int hIdx = myH[x] = myH[mxw]; root[hIdx] = x; int dep = (*S[hIdx].rbegin()) - depth[mxw]; ansS.erase(ansS.find(dep)); S[hIdx].insert(depth[x]); for (int child : C[x]) if (child != mxw) { if (!S[myH[child]].empty()) { for (auto &v : S[myH[child]]) S[hIdx].insert(v); ppar[myH[child]] = hIdx; int dep = (*S[myH[child]].rbegin()) - depth[child]; ansS.erase(ansS.find(dep)); } S[myH[child]].clear(); } dep = (*S[hIdx].rbegin()) - depth[x]; ansS.insert(dep); } } void pop(int x) { int hIdx = find(myH[x]); int dep = (*S[hIdx].rbegin()) - depth[root[hIdx]]; ansS.erase(ansS.find(dep)); S[hIdx].erase(S[hIdx].find(depth[x])); if (S[hIdx].empty()) return; dep = (*S[hIdx].rbegin()) - depth[root[hIdx]]; ansS.insert(dep); } int main() { int n, k, i, j; scanf( %d%d , &n, &k); for (i = 1; i <= n; i++) scanf( %d , &a[i]); vector<xy> ST; ST.push_back({n + 1, n + 1}); for (i = n; i >= 1; i--) { while (ST.back().x <= a[i]) ST.pop_back(); par[i] = ST.back().y; C[par[i]].push_back(i); ST.push_back({a[i], i}); } dfs(n + 1, 0); for (i = 1; i <= n; i++) { push(i); if (k <= i) { printf( %d , *ansS.rbegin() + 1); if (i != n) pop(i - k + 1); } } return 0; }
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#include <bits/stdc++.h> using namespace std; #define ll long long #define deb(x) cout << #x << = << x << endl #define deb2(x, y) cout << #x << = << x << , << #y << = << y << endl #define nl n void solve() { int n; cin >> n; int arr[n][n]; int x = 1; for(int i=0;i<n;i++){ for(int j=0;j<n;j++){ if(i==j){ arr[i][j]=x; x++; } } } for (int k = 1; k <= 2 * n - 2; k++) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if(i!=j){ if (i + j == k) { arr[i][j] = x; x++; } } } } } if (n == 1) { cout << 1 << n ; return; } else if (n == 2) { cout << -1 << n ; } else { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cout << arr[i][j] << ; } cout << n ; } } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); srand(chrono::high_resolution_clock::now().time_since_epoch().count()); int t; cin >> t; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int N = 1e5 + 5; const long long int M = 1e3; const long long int mod = 1e7 + 7; const long long int m1 = 1e9 + 7; const long long int m2 = 1e9 + 9; const long long int p1 = 402653189; const long long int p2 = 1610612741; const int LN = 32; long long int powermodm(long long int x, long long int n, long long int M) { long long int result = 1; while (n > 0) { if (n % 2 == 1) result = (result * x) % M; x = (x * x) % M; n = n / 2; } return result; } long long int power(long long int _a, long long int _b) { long long int _r = 1; while (_b) { if (_b % 2 == 1) _r = (_r * _a); _b /= 2; _a = (_a * _a); } return _r; } long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } long long int lcm(long long int a, long long int b) { return (max(a, b) / gcd(a, b)) * min(a, b); } long long int dx[4] = {-1, 1, 0, 0}; long long int dy[4] = {0, 0, 1, -1}; long long int pw[LN], fact[N], invfact[N]; void pre() { fact[0] = 1; for (int i = 0; i < LN; i++) pw[i] = power(2, i); for (int i = 1; i < N; i++) fact[i] = (i * fact[i - 1]) % mod; for (int i = 0; i < N; i++) invfact[i] = powermodm(fact[i], mod - 2, mod); } long long int n, m, a[N], st[N], en[N], tme[N], curr, lazy[4 * N]; vector<long long int> adj[N]; bitset<M> B[4 * N], fin, bset; void dfs(long long int node, long long int par) { st[node] = ++curr; tme[curr] = node; for (auto it : adj[node]) { if (it == par) continue; dfs(it, node); } en[node] = curr; } void build(long long int pos, long long int left, long long int right) { if (left == right) { B[pos].set(a[tme[left]] % m); return; } long long int mid = (left + right) >> 1; build(2 * pos + 1, left, mid); build(2 * pos + 2, mid + 1, right); B[pos] = B[2 * pos + 1] | B[2 * pos + 2]; } void apply(bitset<M> &tmp, long long int shift) { tmp = (tmp << shift) | (tmp >> (m - shift)); } void update(long long int pos, long long int left, long long int right, long long int start, long long int end, long long int val) { if (lazy[pos] != 0) { apply(B[pos], lazy[pos]); if (left != right) { lazy[2 * pos + 1] = (lazy[2 * pos + 1] + lazy[pos]) % m; lazy[2 * pos + 2] = (lazy[2 * pos + 2] + lazy[pos]) % m; } lazy[pos] = 0; } if (left > end || right < start) return; else if (start <= left && right <= end) { apply(B[pos], val); if (left != right) { lazy[2 * pos + 1] = (lazy[2 * pos + 1] + val) % m; lazy[2 * pos + 2] = (lazy[2 * pos + 2] + val) % m; } return; } long long int mid = (left + right) >> 1; update(2 * pos + 1, left, mid, start, end, val); update(2 * pos + 2, mid + 1, right, start, end, val); B[pos] = B[2 * pos + 1] | B[2 * pos + 2]; } void query(long long int pos, long long int left, long long int right, long long int start, long long int end) { if (lazy[pos] != 0) { apply(B[pos], lazy[pos]); if (left != right) { lazy[2 * pos + 1] = (lazy[2 * pos + 1] + lazy[pos]) % m; lazy[2 * pos + 2] = (lazy[2 * pos + 2] + lazy[pos]) % m; } lazy[pos] = 0; } if (left > end || right < start) return; else if (start <= left && right <= end) { bset |= B[pos]; return; } long long int mid = (left + right) >> 1; query(2 * pos + 1, left, mid, start, end); query(2 * pos + 2, mid + 1, right, start, end); } bool pri[1005]; vector<long long int> prm; void fun() { for (long long int i = 2; i < m; i++) pri[i] = true; for (long long int i = 2; i < m; i++) { if (pri[i]) { prm.push_back(i); for (long long int j = 2 * i; j < m; j += i) pri[j] = false; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int i, j; fin.set(); cin >> n >> m; fun(); for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i < n; i++) { long long int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1, 0); build(0, 1, n); long long int q; cin >> q; while (q--) { long long int x; cin >> x; if (x == 1) { long long int node, val; cin >> node >> val; update(0, 1, n, st[node], en[node], val % m); } else { bset.reset(); long long int node; cin >> node; query(0, 1, n, st[node], en[node]); long long int ans = 0; for (i = 0; i < prm.size(); i++) { if (bset[prm[i]]) ans++; } printf( %lld n , ans); } } return 0; }
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`timescale 1ns/10ps
module RegBankP8Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] out_0;
wire [7:0] out_1;
wire [7:0] out_2;
wire [7:0] out_3;
wire [7:0] out_4;
wire [7:0] out_5;
wire [7:0] out_6;
wire [7:0] out_7;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`RegBankP8_LD0,8'hBA};
inst_en = 1;
#4 inst = {`RegBankP8_LD1,8'hFE};
inst_en = 1;
#4 inst = {`RegBankP8_LD2,8'h23};
inst_en = 1;
#4 inst = {`RegBankP8_LD3,8'h43};
inst_en = 1;
#4 inst = {`RegBankP8_LD4,8'h12};
inst_en = 1;
#4 inst = {`RegBankP8_LD5,8'hEA};
inst_en = 1;
#4 inst = {`RegBankP8_LD6,8'hFE};
inst_en = 1;
#4 inst = {`RegBankP8_LD7,8'hAB};
inst_en = 1;
#4 inst = {`RegBankP8_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`RegBankP8_LD1,8'h87};
inst_en = 0;
#4 inst = {`RegBankP8_LD0,8'hAE};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAB};
inst_en = 1;
#4 inst = {`RegBankP8_LD1,8'h27};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`RegBankP8_LD0,8'h1A};
inst_en = 1;
#4 inst = {`RegBankP8_NOP,8'bxxxxxxxx};
inst_en = 1;
end
RegBankP8
rbp8 (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.out_0(out_0),
.out_1(out_1),
.out_2(out_2),
.out_3(out_3),
.out_4(out_4),
.out_5(out_5),
.out_6(out_6),
.out_7(out_7));
endmodule // RegBankP8Sim
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#include <bits/stdc++.h> using namespace std; const int N = 100; double pr[10][N][N], p[N][N], dp[10][N][N]; int n; int main() { double ans = 0; cin >> n; for (int i = 0; i < (1 << n); i++) for (int j = 0; j < (1 << n); j++) cin >> p[i][j], p[i][j] /= 100; for (int i = 0; i < (1 << n); i++) pr[0][i][i] = 1; for (int i = 1; i <= n; i++) for (int j = 0; j < (1 << (n - i)); j++) { int d = (1 << i); for (int g = 0; g < d; g++) { int o = d * j + g; double t = pr[i - 1][j * 2 + (g >= d / 2)][o]; double k = 0; for (int h = 0; h < d / 2; h++) { int o2 = d * j + h; if (g < d / 2) o2 += d / 2; k += pr[i - 1][j * 2 + (g < d / 2)][o2] * p[o][o2]; } pr[i][j][o] = k * t; } } for (int i = 1; i <= n; i++) for (int j = 0; j < (1 << (n - i)); j++) { int d = (1 << i); int p3 = (1 << (i - 1)); for (int g = 0; g < d; g++) { int o = d * j + g; double t = dp[i - 1][j * 2 + (g >= d / 2)][o]; double p1 = pr[i - 1][j * 2 + (g >= d / 2)][o]; double m = 0; for (int h = 0; h < d / 2; h++) { int o2 = d * j + h; if (g < d / 2) o2 += d / 2; m = max(m, dp[i - 1][j * 2 + (g < d / 2)][o2]); } t += m; double k = 0; for (int h = 0; h < d / 2; h++) { int o2 = d * j + h; if (g < d / 2) o2 += d / 2; k += pr[i - 1][(j * 2 + (g < d / 2))][o2] * p[o][o2]; } t += p1 * p3 * k; dp[i][j][o] = t; if (i == n) ans = max(ans, t); } } cout << setprecision(9) << fixed << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 200010; map<int, int> mp; int n; struct pnt { int x, w; bool operator<(const pnt &p) const { return x < p.x; } } p[maxn]; int ask(int x) { int res = 0; for (int i = x; i > 0; i -= (i & -i)) if (mp.count(i)) res = max(res, mp[i]); return res; } void update(int x, int v) { for (int i = x; i < 0x3f3f3f3f; i += (i & -i)) mp[i] = max(mp[i], v); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d%d , &p[i].x, &p[i].w); sort(p, p + n); int ans = 0; for (int i = 0; i < n; i++) { int tmp = ask(p[i].x - p[i].w); ans = max(ans, tmp + 1); update(p[i].x + p[i].w, tmp + 1); } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int N, M, C; vector<pair<int, pair<int, int> > > V; int A[505][505], R[505]; int main() { int x, y, t; scanf( %d %d , &N, &M); memset(A, 40, sizeof A); for (int i = 1; i <= M; i++) { scanf( %d %d %d , &x, &y, &t); A[x][y] = A[y][x] = t; V.push_back(make_pair(t, make_pair(x, y))); } for (int i = 1; i <= N; i++) A[i][i] = 0; for (int k = 1; k <= N; k++) for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) A[i][j] = min(A[i][j], A[i][k] + A[k][j]); for (int i = 1; i <= N; i++) { memset(R, 0, sizeof R); for (typeof(V.begin()) it = V.begin(); it != V.end(); it++) { if (A[i][it->second.first] + it->first == A[i][it->second.second]) ++R[it->second.second]; if (A[i][it->second.second] + it->first == A[i][it->second.first]) ++R[it->second.first]; } for (int j = i + 1; j <= N; j++) { int ans = 0; for (int k = 1; k <= N; k++) if (A[i][k] + A[k][j] == A[i][j]) ans += R[k]; printf( %d , ans); } } cerr << nTime: << (double)clock() / CLOCKS_PER_SEC << seconds. << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 40; const int inf = 0x3fffffff; void read(int &x) { char ch; bool flag = 0; for (ch = getchar(); !isdigit(ch) && ((flag |= (ch == - )) || 1); ch = getchar()) ; for (x = 0; isdigit(ch); x = (x << 1) + (x << 3) + ch - 48, ch = getchar()) ; x *= 1 - 2 * flag; } char mp[4][105]; int n, m; bool ans = 1; bool check(int time, int x, int y) { y += 2 * time; if (y >= n || mp[x][y] == . ) return true; return false; } int vis[5][105]; void dfs(int x, int y) { if (vis[x][y]) return; vis[x][y] = 1; if (y == n - 1) { ans = 0; return; } if (!check(y, x, y + 1)) return; for (int i = x - 1; i <= x + 1; i++) { if (i < 0 || i >= 3) continue; if (check(y, i, y + 1) && check(y + 1, i, y + 1)) dfs(i, y + 1); } } int main() { int t; read(t); while (t--) { ans = 1; memset(vis, 0, sizeof(vis)); read(n), read(m); int st = -1; ans = 1; for (int i = 0; i < 3; i++) { cin >> mp[i]; for (int j = 0; j < m; j++) { if (mp[i][j] == s ) { st = i; } } } mp[st][0] = . ; dfs(st, 0); if (ans) puts( NO ); else puts( YES ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int a[501102]; int ans, cnt, sum, d; void solve() { ans = 0; cnt = 0; sum = 0; d = 0; int n; cin >> n; for (int i = 1; n >= i; i++) { cin >> a[i]; if (a[i] % 2 == 1) { ans++; if (a[i] * n % 2 == 1) d = 1; } else cnt++; sum += a[i]; } if (ans >= cnt && ans != n || sum % 2 == 1 || d != 0 || ans != 0 && cnt != 0) { cout << YES << endl; return; } cout << NO << endl; } int main() { int t; cin >> t; while (t--) { solve(); } return 0; }
|
//
// Designed by Qiang Wu
//
`timescale 1ns/1ps
`include "NF_2.1_defines.v"
`include "registers.v"
`include "reg_defines_reference_router.v"
module packet_buffer(
input clk,
input reset,
output [239:0] TRIG0,
input [63:0] in_data,
input [15:0] in_pkt_route,
input in_wr,
output reg in_empty,
input in_req,
output reg in_ack,
output reg [63:0] out_data,
output reg [15:0] out_pkt_route,
output reg out_wr,
output reg out_req,
input out_ack,
output reg [1:0] out_neighbor,
output reg out_bop,
output reg out_eop,
input out_rdy,
output reg out_bypass,
input [10:2] proc_addr,
input [31:0] proc_data_in,
output [31:0] proc_data_out,
input proc_we,
output reg proc_req,
input proc_done,
input proc_done_repeat,
input proc_wr_pkt_len,
input [7:0] proc_pkt_len
);
reg [32:0] repeat_count;
always @(posedge clk)
begin
if(reset) begin
repeat_count <= 0;
end else begin
if(repeat_count != 0) begin
repeat_count <= repeat_count + 1;
end else begin
if(proc_done_repeat) begin
repeat_count <= 1;
end
end
end
end
reg repeat_pkt;
always @(*)
begin
if (repeat_count != 0) begin
repeat_pkt = 1;
end else begin
repeat_pkt = 0;
end
end
wire wea;
wire web;
wire [8:0] addra;
wire [8:0] addrb;
wire [31:0] dia;
wire [31:0] dib;
wire [31:0] doa;
wire [31:0] dob;
wire [3:0] dipa;
wire [3:0] dipb;
RAM16_s36_s36_altera pm(
.q_a (doa),
.q_b (dob),
.address_a (addra),
.address_b (addrb),
.clock_a (clk),
.clock_b (clk),
.data_a (dia),
.data_b (dib),
.aclr_a (reset),
.aclr_b (reset),
.wren_a (wea),
.wren_b (web)
);
reg [7:0] pkt_len;
reg [7:0] send_len;
parameter BUFF_EMPTY = 3'b001,
BUFF_RECV_PKT = 3'b010,
BUFF_PROC_PKT = 3'b011,
BUFF_SEND_REQ = 3'b100,
BUFF_SEND_PKT = 3'b101,
BUFF_SEND_CANCEL = 3'b110;
wire [2:0] mux_ctrl;
assign mux_ctrl = {in_ack, proc_req, out_req};
assign dia = (mux_ctrl == 3'b100) ? in_data[63:32] :
(mux_ctrl == 3'b010) ? proc_data_in : 0;
assign dib = (mux_ctrl == 3'b100) ? in_data[31:0] : 0;
assign wea = (mux_ctrl == 3'b010) ? proc_we : in_wr;
assign web = in_wr;
assign addra = (mux_ctrl == 3'b100) ? {pkt_len, 1'b0} :
(mux_ctrl == 3'b010) ? proc_addr[10:2] :
(mux_ctrl == 3'b001) ? {send_len, 1'b0} : 0;
assign addrb = (mux_ctrl == 3'b100) ? {pkt_len, 1'b1} :
(mux_ctrl == 3'b001) ? {send_len, 1'b1} : 0;
assign proc_data_out = doa;
wire eop;
reg state_idle;
reg state_pkt_send;
reg need_process;
reg [2:0] buff_state;
reg [2:0] buff_state_next;
always @(*)
begin
buff_state_next = buff_state;
in_ack = 0;
proc_req = 0;
out_req = 0;
in_empty = 0;
out_wr = 0;
state_idle = 0;
state_pkt_send = 0;
case(buff_state)
BUFF_EMPTY: begin
state_idle = 1;
if(in_req) begin
in_ack = 1;
buff_state_next = BUFF_RECV_PKT;
end else begin
in_empty = 1;
end
end
BUFF_RECV_PKT: begin
in_ack = 1;
if(in_wr) begin
out_neighbor = in_pkt_route[1:0];
out_bypass = in_pkt_route[5];
out_pkt_route = {3'b000, in_pkt_route[15:3]};
end
if(!in_req) begin
buff_state_next = BUFF_PROC_PKT;
end
end
BUFF_PROC_PKT: begin
proc_req = 1;
if(proc_done) begin
proc_req = 0;
if(pkt_len != 0) begin
buff_state_next = BUFF_SEND_REQ;
end else begin
buff_state_next = BUFF_EMPTY;
end
end
if(repeat_pkt) begin
buff_state_next = BUFF_SEND_REQ;
end
end
BUFF_SEND_REQ: begin
out_req = 1;
if(out_ack) begin
buff_state_next = BUFF_SEND_PKT;
end
end
BUFF_SEND_PKT: begin
out_req = 1;
state_pkt_send = 1;
if(out_rdy) begin
if(send_len <= pkt_len+1) begin
out_data = {doa, dob};
out_wr = (send_len < 1) ? 0 : (send_len > pkt_len) ? 0 : 1;
out_bop = (send_len == 1) ? 1 : 0;
out_eop = (send_len == pkt_len) ? 1 : 0;
end
end
if(eop) begin
buff_state_next = BUFF_SEND_CANCEL;
end
end
BUFF_SEND_CANCEL: begin
out_req = 0;
if(!out_ack) begin
if(repeat_pkt) begin
buff_state_next = BUFF_SEND_REQ;
end else begin
buff_state_next = BUFF_EMPTY;
end
end
//if(repeat_pkt) begin
// proc_req = 1;
//end
end
default: begin
buff_state_next = BUFF_EMPTY;
end
endcase
end
always @(posedge clk)
begin
if(reset) begin
buff_state <= 0;
end else begin
buff_state <= buff_state_next;
end
if(state_idle) begin
pkt_len <= 0;
send_len <= 0;
end
if(in_wr) begin
pkt_len <= pkt_len + 1'b1;
end
//if(proc_wr_pkt_len) begin
// pkt_len <= proc_pkt_len;
//end
if(state_pkt_send && out_rdy) begin
send_len <= send_len + 1'b1;
end
end
assign eop = (send_len == pkt_len+1) ? 1 : 0;
assign TRIG0[63:0] = in_data;
assign TRIG0[79:64] = in_pkt_route;
assign TRIG0[80] = in_wr;
assign TRIG0[81] = in_empty;
assign TRIG0[82] = in_req;
assign TRIG0[83] = in_ack;
assign TRIG0[147:84] = out_data;
assign TRIG0[163:148] = out_pkt_route;
assign TRIG0[164] = out_wr;
assign TRIG0[165] = out_req;
assign TRIG0[166] = out_ack;
assign TRIG0[168:167] = out_neighbor;
assign TRIG0[169] = out_bop;
assign TRIG0[170] = out_eop;
assign TRIG0[171] = out_rdy;
assign TRIG0[175:172] = dia[7:4];
assign TRIG0[179:176] = doa[7:4];
assign TRIG0[188:180] = proc_addr;
assign TRIG0[189] = proc_we;
assign TRIG0[190] = proc_req;
assign TRIG0[191] = proc_done;
assign TRIG0[207:200] = pkt_len;
assign TRIG0[217:210] = send_len;
assign TRIG0[218] = eop;
assign TRIG0[219] = state_idle;
assign TRIG0[220] = state_pkt_send;
assign TRIG0[232:230] = buff_state;
endmodule
|
/* this file automatically generated by make_wp.py script
* for file rtl/ictlb.v
* for module ictlb
* with the instance name ictlb_dut
*/
`include "scmem.vh"
`define L1IT_PASSTHROUGH
module ictlb_wp(
/* verilator lint_off UNUSED */
input logic clk
,input logic reset
// core interface
,input logic coretoictlb_pc_valid
,output logic coretoictlb_pc_retry
// ,input I_coretoictlb_pc_type coretoictlb_pc
,input CORE_reqid_type coretoictlb_pc_coreid
,input SC_laddr_type coretoictlb_pc_laddr
,input SC_sptbr_type coretoictlb_pc_sptbr
// prefetch request (uses the fwd port opportunistically)
,input logic pfetol1tlb_req_valid
,output logic pfetol1tlb_req_retry
// ,input I_pfetol1tlb_req_type pfetol1tlb_req
,input logic pfetol1tlb_req_l2
,input SC_laddr_type pfetol1tlb_req_laddr
,input SC_sptbr_type pfetol1tlb_req_sptbr
// forward st core interface
,output logic l1tlbtol1_fwd_valid
,input logic l1tlbtol1_fwd_retry
// ,output I_l1tlbtol1_fwd_type l1tlbtol1_fwd
,output CORE_reqid_type l1tlbtol1_fwd_coreid
,output logic l1tlbtol1_fwd_prefetch
,output logic l1tlbtol1_fwd_l2_prefetch
,output SC_fault_type l1tlbtol1_fwd_fault
,output TLB_hpaddr_type l1tlbtol1_fwd_hpaddr
,output SC_ppaddr_type l1tlbtol1_fwd_ppaddr
// Notify the L1 that the index of the TLB is gone
,output logic l1tlbtol1_cmd_valid
,input logic l1tlbtol1_cmd_retry
// ,output I_l1tlbtol1_cmd_type l1tlbtol1_cmd
,output logic l1tlbtol1_cmd_flush
,output TLB_hpaddr_type l1tlbtol1_cmd_hpaddr
// Interface with the L2 TLB
,input logic l2tlbtol1tlb_snoop_valid
,output logic l2tlbtol1tlb_snoop_retry
// ,input I_l2tlbtol1tlb_snoop_type l2tlbtol1tlb_snoop
,input TLB_reqid_type l2tlbtol1tlb_snoop_rid
,input TLB_hpaddr_type l2tlbtol1tlb_snoop_hpaddr
,input logic l2tlbtol1tlb_ack_valid
,output logic l2tlbtol1tlb_ack_retry
// ,input I_l2tlbtol1tlb_ack_type l2tlbtol1tlb_ack
,input TLB_reqid_type l2tlbtol1tlb_ack_rid
,input TLB_hpaddr_type l2tlbtol1tlb_ack_hpaddr
,input SC_ppaddr_type l2tlbtol1tlb_ack_ppaddr
,input SC_dctlbe_type l2tlbtol1tlb_ack_dctlbe
,output logic l1tlbtol2tlb_req_valid
,input logic l1tlbtol2tlb_req_retry
// ,output I_l1tlbtol2tlb_req_type l1tlbtol2tlb_req
,output TLB_reqid_type l1tlbtol2tlb_req_rid
,output logic l1tlbtol2tlb_req_disp_req
,output logic l1tlbtol2tlb_req_disp_A
,output logic l1tlbtol2tlb_req_disp_D
,output TLB_hpaddr_type l1tlbtol2tlb_req_disp_hpaddr
,output SC_laddr_type l1tlbtol2tlb_req_laddr
,output SC_sptbr_type l1tlbtol2tlb_req_sptbr
,output logic l1tlbtol2tlb_sack_valid
,input logic l1tlbtol2tlb_sack_retry
// ,output I_l1tlbtol2tlb_sack_type l1tlbtol2tlb_sack
,output TLB_reqid_type l1tlbtol2tlb_sack_rid
/* verilator lint_on UNUSED */
);
I_coretoictlb_pc_type coretoictlb_pc;
assign coretoictlb_pc.coreid = coretoictlb_pc_coreid;
assign coretoictlb_pc.laddr = coretoictlb_pc_laddr;
assign coretoictlb_pc.sptbr = coretoictlb_pc_sptbr;
I_pfetol1tlb_req_type pfetol1tlb_req;
assign pfetol1tlb_req.l2 = pfetol1tlb_req_l2;
assign pfetol1tlb_req.laddr = pfetol1tlb_req_laddr;
assign pfetol1tlb_req.sptbr = pfetol1tlb_req_sptbr;
I_l1tlbtol1_fwd_type l1tlbtol1_fwd;
assign l1tlbtol1_fwd_coreid = l1tlbtol1_fwd.coreid;
assign l1tlbtol1_fwd_prefetch = l1tlbtol1_fwd.prefetch;
assign l1tlbtol1_fwd_l2_prefetch = l1tlbtol1_fwd.l2_prefetch;
assign l1tlbtol1_fwd_fault = l1tlbtol1_fwd.fault;
assign l1tlbtol1_fwd_hpaddr = l1tlbtol1_fwd.hpaddr;
assign l1tlbtol1_fwd_ppaddr = l1tlbtol1_fwd.ppaddr;
I_l1tlbtol1_cmd_type l1tlbtol1_cmd;
assign l1tlbtol1_cmd_flush = l1tlbtol1_cmd.flush;
assign l1tlbtol1_cmd_hpaddr = l1tlbtol1_cmd.hpaddr;
I_l2tlbtol1tlb_snoop_type l2tlbtol1tlb_snoop;
assign l2tlbtol1tlb_snoop.rid = l2tlbtol1tlb_snoop_rid;
assign l2tlbtol1tlb_snoop.hpaddr = l2tlbtol1tlb_snoop_hpaddr;
I_l2tlbtol1tlb_ack_type l2tlbtol1tlb_ack;
assign l2tlbtol1tlb_ack.rid = l2tlbtol1tlb_ack_rid;
assign l2tlbtol1tlb_ack.hpaddr = l2tlbtol1tlb_ack_hpaddr;
assign l2tlbtol1tlb_ack.ppaddr = l2tlbtol1tlb_ack_ppaddr;
assign l2tlbtol1tlb_ack.dctlbe = l2tlbtol1tlb_ack_dctlbe;
I_l1tlbtol2tlb_req_type l1tlbtol2tlb_req;
assign l1tlbtol2tlb_req_rid = l1tlbtol2tlb_req.rid;
assign l1tlbtol2tlb_req_disp_req = l1tlbtol2tlb_req.disp_req;
assign l1tlbtol2tlb_req_disp_A = l1tlbtol2tlb_req.disp_A;
assign l1tlbtol2tlb_req_disp_D = l1tlbtol2tlb_req.disp_D;
assign l1tlbtol2tlb_req_disp_hpaddr = l1tlbtol2tlb_req.disp_hpaddr;
assign l1tlbtol2tlb_req_laddr = l1tlbtol2tlb_req.laddr;
assign l1tlbtol2tlb_req_sptbr = l1tlbtol2tlb_req.sptbr;
I_l1tlbtol2tlb_sack_type l1tlbtol2tlb_sack;
assign l1tlbtol2tlb_sack_rid = l1tlbtol2tlb_sack.rid;
ictlb ictlb_dut(.*);
endmodule
|
module test;
reg fail = 1'b0;
reg [3:0] bus = 4'b0;
initial begin
// Check the initial value.
if (bus !== 4'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", bus);
fail = 1'b1;
end
// Check a bit assign and verify a normal bit assign does nothing.
#1 assign bus[0] = 1'b1;
bus[0] = 1'bz;
if (bus !== 4'b0001) begin
$display("FAILED: assign of bus[0], got %b, expected 0001.", bus);
fail = 1'b1;
end
// Check a part assign.
#1 assign bus[3:2] = 2'b11;
if (bus !== 4'b1101) begin
$display("FAILED: assign of bus[3:2], got %b, expected 1101.", bus);
fail = 1'b1;
end
// Check that we can change an unassigned bit.
#1 bus[1] = 1'bz;
if (bus !== 4'b11z1) begin
$display("FAILED: assignment of bus[1], got %b, expected 11z1.", bus);
fail = 1'b1;
end
// Check a bit deassign.
#1 deassign bus[0];
bus = 4'b000z;
if (bus !== 4'b110z) begin
$display("FAILED: deassign of bus[0], got %b, expected 110z.", bus);
fail = 1'b1;
end
// Check a part deassign (we keep the old value if not changed).
#1 deassign bus[3:2];
bus[3] = 1'b0;
if (bus !== 4'b010z) begin
$display("FAILED: deassign of bus[3:2], got %b, expected 010z.", bus);
fail = 1'b1;
end
// Check an assign from the upper thread bits >= 8.
#1 assign bus[2:1] = 2'bx1;
if (bus !== 4'b0x1z) begin
$display("FAILED: assign of bus[2:1], got %b, expected 0x1z.", bus);
fail = 1'b1;
end
if (!fail) $display("PASSED");
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fifo_w16_d2_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module fifo_w16_d2_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w16_d2_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w16_d2_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> frequency(vector<long long> v) { map<long long, long long> m; for (long long i = 0; i < v.size(); i++) { if (m.find(v[i]) != m.end()) m[v[i]]++; else { m.insert({v[i], 1}); } } return m; } void input(vector<long long>& v, long long n) { for (long long i = 0; i < (long long)(n); i++) { long long in; cin >> in; v.push_back(in); } } void output(vector<long long> v) { for (long long i = 0; i < (long long)(v.size()); i++) cout << v[i] << ; } void solve() { long long a, b, c, d; cin >> a >> b >> c >> d; long long m = max((3 * a) / 10, a - (a / 250) * c); long long v = max((3 * b) / 10, b - (b / 250) * d); if (m > v) { cout << Misha << endl; } else if (v > m) { cout << Vasya << endl; } else { cout << Tie << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long M = 1e9 + 7; const long long inf = 4e18; const long long N = 1e6; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n, m, k; cin >> n >> m >> k; char a[n][m]; bool pos[n][m]; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { cin >> a[i][j]; pos[i][j] = 0; } } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (a[i][j] == . ) continue; long long d = 0; for (long long h = 1; h <= min({i, j, m - 1 - j}); h++) { if (a[i - h][j - h] == * && a[i - h][j + h] == * ) d++; else break; } if (d < k) continue; pos[i][j] = 1; for (long long h = 1; h <= min({i, j, m - 1 - j}); h++) { if (a[i - h][j - h] == * && a[i - h][j + h] == * ) pos[i - h][j - h] = 1, pos[i - h][j + h] = 1; else break; } } } bool boob = 1; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (a[i][j] == * && !pos[i][j]) boob = 0; } } if (boob) cout << YES n ; else cout << NO n ; } }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const long long mod = 1e9 + 7; inline long long bigmod(long long B, long long P) { long long R = 1; while (P > 0) { if (P & 1) { R = (R * B) % mod; } P >>= 1; B = (B * B) % mod; } return R; } const long long mxn = 500; long long Mod(long long a) { if (a < 0) return (a + mod) % mod; else return a % mod; } long long Mul(long long a, long long b) { return Mod(Mod(a) * Mod(b)); } long long Add(long long a, long long b) { return Mod(Mod(a) + Mod(b)); } vector<long long> adj[mxn]; long long vis[mxn], pred[mxn], dist[mxn]; vector<long long> adj2[mxn]; long long vis2[mxn], pred2[mxn], dist2[mxn]; long long n; bool bfs(long long root) { queue<long long> q; q.push(root); vis[root] = 1; while (!q.empty()) { long long u = q.front(); q.pop(); for (long long v : adj[u]) { if (!vis[v]) { vis[v] = 1; dist[v] = dist[u] + 1; q.push(v); if (v == n) return true; } } } return false; } bool bfs2(long long root) { queue<long long> q; q.push(root); vis2[root] = 1; while (!q.empty()) { long long u = q.front(); q.pop(); for (long long v : adj2[u]) { if (!vis2[v]) { vis2[v] = 1; dist2[v] = dist2[u] + 1; q.push(v); if (v == n) return true; } } } return false; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long tt = 1; for (long long tc = 1; tc <= tt; tc++) { long long m, f = 0; cin >> n >> m; map<pair<long long, long long>, bool> trainase; for (long long i = 0; i < m; i++) { long long u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); trainase[{u, v}] = 1; trainase[{v, u}] = 1; if (u == n || v == n) f = 1; } if (!f) cout << -1 << n ; else { for (long long i = 1; i <= n; i++) { for (long long j = i + 1; j <= n; j++) { if (!trainase[{i, j}]) { adj2[i].push_back(j); adj2[j].push_back(i); } } } if (!bfs2(1) || !bfs(1)) { cout << -1 << n ; return 0; } bfs(1); bfs2(1); cout << max(dist2[n], dist[n]) << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; vector<long long> vec(n); for (long long i = 0; i < n; i++) { cin >> vec[i]; } vec.push_back(vec.back()); long long ans = 1; long long cnt = 1; for (long long i = 1; i < n; i++) { if (vec[i] > vec[i - 1] * 2) { ans = max(ans, cnt); cnt = 0; } cnt++; } ans = max(ans, cnt); cout << ans << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O41A_BEHAVIORAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire A4 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_BEHAVIORAL_V
|
module blocking_cond (in, out);
input in;
output reg out;
reg tmp;
always @* begin
tmp = 1;
out = 1'b0;
case (1'b1)
tmp: out = in;
endcase
tmp = 0;
end
endmodule
// -------------------------------------------------------------
module uut(clk, arst, a, b, c, d, e, f, out1);
input clk, arst, a, b, c, d, e, f;
output reg [3:0] out1;
always @(posedge clk, posedge arst) begin
if (arst)
out1 = 0;
else begin
if (a) begin
case ({b, c})
2'b00:
out1 = out1 + 9;
2'b01, 2'b10:
out1 = out1 + 13;
endcase
if (d) begin
out1 = out1 + 2;
out1 = out1 + 1;
end
case ({e, f})
2'b11:
out1 = out1 + 8;
2'b00:
;
default:
out1 = out1 + 10;
endcase
out1 = out1 ^ 7;
end
out1 = out1 + 14;
end
end
endmodule
// -------------------------------------------------------------
// extracted from ../asicworld/code_hdl_models_uart.v
// (triggered a bug in the proc_mux pass)
module uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);
input reset;
input txclk;
input ld_tx_data;
output reg tx_empty;
output reg [3:0] tx_cnt;
always @ (posedge txclk)
if (reset) begin
tx_empty <= 1;
tx_cnt <= 0;
end else begin
if (ld_tx_data) begin
tx_empty <= 0;
end
if (!tx_empty) begin
tx_cnt <= tx_cnt + 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2O_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A2BB2O_PP_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int M = 1000000007; const int MM = 998244353; const long double PI = acos(-1); const long long INF = 2e18; template <typename T, typename T1> void amax(T &a, T1 b) { if (b > a) a = b; } template <typename T, typename T1> void amin(T &a, T1 b) { if (b < a) a = b; } long long power(long long b, long long e) { if (e == 0) return 1; if (e & 1) return b * power(b * b, e / 2); return power(b * b, e / 2); } long long power(long long b, long long e, long long m) { if (e == 0) return 1; if (e & 1) return b * power(b * b % m, e / 2, m) % m; return power(b * b % m, e / 2, m); } long long modinv(long long a, long long m) { return power(a, m - 2, m); } int TLE_TERROR() { long long n, p, f = 0, zz = -1; cin >> n >> p; string s; cin >> s; if (p == 1) { cout << NO ; return 0; } if (p == 2) { if (n > 2) cout << NO ; else if (n == 1) { if (s[0] == a ) cout << b ; else cout << NO ; } else { if (s == ab ) cout << ba ; else cout << NO ; } return 0; } for (long long i = n - 1; i >= 0; i--) { char z = s[i]; while ((z - a + 1) < p) { z++; if (i > 0 && z == s[i - 1]) continue; if (i > 1 && z == s[i - 2]) continue; long long q = n - i; s[i] = z; f = 1; zz = i; break; } if (f == 1) break; } if (f == 0) cout << NO ; else { for (long long i = zz + 1; i < n; i++) { if (i > 1) { if (s[i - 1] != a && s[i - 2] != a ) s[i] = a ; else if (s[i - 1] != b && s[i - 2] != b ) s[i] = b ; else s[i] = c ; } else { if (s[i - 1] != a ) s[i] = a ; else if (s[i - 1] != b ) s[i] = b ; else s[i] = c ; } } cout << s; } return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int TESTS = 1; while (TESTS--) TLE_TERROR(); return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; string s; cin >> s; long long o = 0; long long z = 0; for (long long i = 0; i < n; i++) if (s[i] == n ) o++; else if (s[i] == z ) z++; while (o--) cout << 1 << ; while (z--) cout << 0 << ; } int main() { long long t; t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; bool Check(char x) { if (x <= 3 && x >= 1 ) return true; else return false; } int main() { char s[1000]; cin >> s; char x; for (int i = 0; i < strlen(s); ++i) { for (int j = i + 1; j < strlen(s); ++j) { if (s[j] < s[i] && Check(s[i]) && Check(s[j])) { x = s[i]; s[i] = s[j]; s[j] = x; } } } for (int i = 0; i < strlen(s); i++) { cout << s[i]; } return 0; }
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#include <bits/stdc++.h> using namespace std; void pb_200() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int32_t main() { long long int x; cin >> x; while (x--) { long long int n; cin >> n; long long int *arr = new long long int[n]; ; for (long long int i = 0; i < n; ++i) cin >> arr[i]; long long int i = n - 1; while (i > 0 and arr[i] <= arr[i - 1]) i--; if (i == 0) { cout << 0 << endl; continue; } while (i > 0 and arr[i] >= arr[i - 1]) i--; cout << i << endl; } }
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#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; int n; int a[N], sum[N], b[65][N], cnt[65]; long long ans; int t[2]; long long find(int l, int r, int lim) { int i, j; long long ret = 0; if (l > r) return 0; j = l - 1; t[0] = t[1] = 0; for (i = l; i <= r; ++i) { while (sum[i] - sum[j] >= lim) { ++t[sum[j] & 1]; ++j; } ret += (long long)t[sum[i] & 1]; } return ret; } void dfs(int l, int r, int mx) { if (r - l - 1 < 1) return; if (!mx) return; int i, tmx = 0; cnt[mx] = 1; b[mx][cnt[mx]] = l; for (i = l + 1; i <= r - 1; ++i) if (a[i] == mx) b[mx][++cnt[mx]] = i; b[mx][++cnt[mx]] = r; if (cnt[mx] > 2) { ans += find(l + 1, r - 1, mx + mx); for (i = 1; i <= cnt[mx] - 1; ++i) { ans -= find(b[mx][i] + 1, b[mx][i + 1] - 1, mx + mx); } } for (i = 1; i <= cnt[mx] - 1; ++i) dfs(b[mx][i], b[mx][i + 1], mx - 1); } int main() { int i, mx = 0; long long x; scanf( %d , &n); for (i = 1; i <= n; ++i) { scanf( %lld , &x); for (; x; x >>= 1) if (x & 1ll) ++a[i]; mx = max(mx, a[i]); sum[i] = sum[i - 1] + a[i]; } dfs(0, n + 1, mx); printf( %lld n , ans); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_1_V
`define SKY130_FD_SC_HVL__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_1_V
|
#include <bits/stdc++.h> using namespace std; const double error = 1e-15; const double pi = 2 * acos(0); const int maxn = (int)1e5 + 10; const int mod = (int)1e9; int dx[] = {0, -1, 0, +1, -1, -1, +1, +1}; int dy[] = {-1, 0, +1, 0, -1, +1, +1, -1}; long A[205][200], B[200]; vector<int> v; int main() { ios_base::sync_with_stdio(0); long i, j, n, m; cin >> n; for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) { cin >> A[i][j]; if (A[i][j] == 1) { B[i] = 1; } else if (A[i][j] == 2) { B[j] = 1; } else if (A[i][j] == 3) { B[i] = 1; B[j] = 1; } } m = 0; for (i = 1; i <= n; i++) if (B[i] == 0) { m++; v.push_back(i); } cout << m << endl; for (i = 0; i < m; i++) cout << v[i] << ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int cnt2[maxn]; int cnt[maxn]; struct trie { int nxt[maxn][26], fail[maxn], g[maxn]; int ed[maxn]; int rt, L; int newnode() { memset(nxt[L], -1, sizeof nxt[L]); ed[L++] = 0; return L - 1; } void init() { L = 0; rt = newnode(); } void insert(const string& buf) { int len = buf.size(); int now = rt; for (int i = 0; i < len; ++i) { if (nxt[now][buf[i] - a ] == -1) nxt[now][buf[i] - a ] = newnode(); now = nxt[now][buf[i] - a ]; } ed[now]++; } void build() { queue<int> q; fail[rt] = rt; g[rt] = rt; for (int i = 0; i < 26; ++i) { if (nxt[rt][i] == -1) nxt[rt][i] = rt; else { fail[nxt[rt][i]] = rt; g[nxt[rt][i]] = rt; q.push(nxt[rt][i]); } } while (!q.empty()) { int now = q.front(); q.pop(); for (int i = 0; i < 26; ++i) { if (nxt[now][i] == -1) nxt[now][i] = nxt[fail[now]][i]; else { fail[nxt[now][i]] = nxt[fail[now]][i]; if (ed[fail[nxt[now][i]]]) { g[nxt[now][i]] = fail[nxt[now][i]]; } else g[nxt[now][i]] = g[fail[nxt[now][i]]]; q.push(nxt[now][i]); } } } } void query(const string& buf) { int len = buf.size(); int now = rt; for (int i = 0; i < len; ++i) { now = nxt[now][buf[i] - a ]; int tmp = now; while (tmp != rt) { cnt[i] += ed[tmp]; tmp = g[tmp]; } } } } a, b; string t; string s[maxn]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; int n; cin >> n; a.init(); for (int i = 1; i <= n; ++i) { cin >> s[i]; a.insert(s[i]); } a.build(); a.query(t); memcpy(cnt2, cnt, sizeof cnt); memset(cnt, 0, sizeof cnt); b.init(); for (int i = 1; i <= n; ++i) { reverse(s[i].begin(), s[i].end()); b.insert(s[i]); } b.build(); reverse(t.begin(), t.end()); b.query(t); long long ans = 0; for (int i = 0; i < t.size() - 1; ++i) { ans += 1ll * cnt2[i] * cnt[t.size() - i - 2]; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n = 0, m = 0; char** values; bool** values1; void PrintArray() { cout << Values n ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << values[i][j] << ; } cout << endl; } cout << Values1 n ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << values1[i][j] << ; } cout << endl; } } void Check(int i, int j) { char valueToCheck = values[i][j]; if (i == n - 1) goto second; for (int i1 = i + 1; i1 < n; i1++) { if (valueToCheck == values[i1][j]) { values1[i][j] = true; values1[i1][j] = true; } } second: if (j == m - 1) return; for (int j1 = j + 1; j1 < m; j1++) { if (valueToCheck == values[i][j1]) { values1[i][j] = true; values1[i][j1] = true; } } } void ConstructString() { string result = ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (values1[i][j] != true) result += values[i][j]; } } cout << result; } int main() { string str, temp; cin >> n >> m; values = new char*[n + 1]; values1 = new bool*[n + 1]; for (int i = 0; i < n; i++) { values[i] = new char[m + 1]; values1[i] = new bool[m + 1]; memset(values1[i], 0, m + 1); cin >> values[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (values[i][j] == * ) continue; Check(i, j); } } ConstructString(); for (int i = 0; i < n; ++i) { delete[] values[i]; delete[] values1[i]; } delete[] values; return 0; }
|
// test_usb_ft232.v
`timescale 1 ns / 1 ps
module test_usb16;
reg clk = 0;
reg reset = 1;
// FT232 interface
reg usb_clk = 0;
wire wr_n;
wire rd_n;
wire oe_n;
wire [7:0]data;
reg txe_n = 1;
reg rxf_n = 1;
wire siwu_n;
// avs_ctrl
reg avs_ctrl_address = 1'bx;
reg avs_ctrl_write = 0;
reg [7:0]avs_ctrl_writedata = 8'hxx;
reg avs_ctrl_read = 0;
wire [7:0]avs_ctrl_readdata;
// asi_uplink
wire asi_uplink_ready;
reg asi_uplink_valid = 0;
reg [15:0]asi_uplink_data = 16'hxxxx;
reg asi_uplink_startofpacket = 0;
reg asi_uplink_endofpacket = 0;
reg asi_uplink_empty = 1'bx;
// --- clk
always #10 clk = !clk;
initial #15 reset = 0;
task waitclk(input integer n);
begin
repeat (n) @(posedge clk);
end
endtask
task waitusbclk(input integer n);
begin
repeat (n) @(posedge usb_clk);
end
endtask
// === ft232 ==============================================================
// --- transmitter
always #8.333 usb_clk = !usb_clk;
reg [3:0]ft_cnt = 0;
always @(posedge usb_clk)
begin
txe_n <= ft_cnt < 3;
ft_cnt <= ft_cnt + 1;
end
// -- receiver
reg [7:0]ft_data = 0;
reg [2:0]ft_wait = 0;
initial
begin
waitusbclk(5);
forever @(posedge usb_clk)
begin
rxf_n <= ft_wait < 2;
ft_wait <= ft_wait + 1;
end
end
always @(posedge usb_clk) if (!rxf_n && !rd_n) ft_data = ft_data + 1;
assign data = oe_n ? 8'hzz : (rd_n ? 8'hxx : ft_data);
// log write access to ft232, log read access from ft232
reg [7:0]ft232_write;
reg [7:0]ft232_read;
always @(negedge usb_clk)
begin
ft232_write <= wr_n ? 8'hzz : (txe_n ? 8'hxx : data);
ft232_read <= rd_n ? 8'hzz : (rxf_n ? 8'hxx : data);
end
// === avs_ctrl ===========================================================
task avsWrite(input [7:0]value, input address);
begin
waitclk(1);
avs_ctrl_write <= 1;
avs_ctrl_address <= 1;
avs_ctrl_writedata <= value;
waitclk(1);
avs_ctrl_write <= 0;
avs_ctrl_address <= 1'bx;
avs_ctrl_writedata <= 8'hxx;
end
endtask
task avsRead(output [7:0]value, input address);
begin
waitclk(1);
avs_ctrl_read <= 1;
avs_ctrl_address <= address;
@(negedge clk);
value <= avs_ctrl_readdata;
waitclk(1);
avs_ctrl_read <= 0;
avs_ctrl_address <= 1'bx;
end
endtask
reg [7:0]ret;
reg [7:0]rxdata;
initial
begin
waitclk(5);
avsRead(ret, 1);
avsRead(ret, 1);
avsWrite(8'hfe, 1);
forever
begin
avsRead(ret, 1);
if (ret) avsRead(rxdata,0);
end
end
// log read/write from/to avs ctrl
reg [7:0]avs_read_0;
reg [7:0]avs_read_1;
reg [7:0]avs_write_0;
reg [7:0]avs_write_1;
always @(negedge clk)
begin
avs_read_0 <= (avs_ctrl_read && !avs_ctrl_address) ? avs_ctrl_readdata : 8'hzz;
avs_read_1 <= (avs_ctrl_read && avs_ctrl_address) ? avs_ctrl_readdata : 8'hzz;
avs_write_0 <= (avs_ctrl_write && !avs_ctrl_address) ? avs_ctrl_writedata : 8'hzz;
avs_write_1 <= (avs_ctrl_write && avs_ctrl_address) ? avs_ctrl_writedata : 8'hzz;
end
// === asi_uplink =========================================================
task asi_burst_data(input [7:0]value, input integer size);
begin
case (size)
0:
begin
asi_uplink_data <= 16'hxxxx;
asi_uplink_empty <= 1'bx;
end
1:
begin
asi_uplink_data <= {value, 8'hxx};
asi_uplink_empty <= 1;
end
default
begin
asi_uplink_data <= {value, value+8'h1};
asi_uplink_empty <= 0;
end
endcase
end
endtask
task asi_burst(input [7:0]startvalue, input integer length);
begin
waitclk(1);
asi_uplink_startofpacket <= 1;
asi_uplink_valid <= 1;
while (length > 0)
begin
asi_burst_data(startvalue, length);
if (length <= 1) asi_uplink_endofpacket <= 1;
startvalue = startvalue + 2;
length = length - 2;
waitclk(1);
asi_uplink_startofpacket <= 0;
while (!asi_uplink_ready) waitclk(1);
end
asi_uplink_startofpacket <= 0;
asi_uplink_endofpacket <= 0;
asi_uplink_valid <= 0;
asi_uplink_data <= 16'hxxxx;
asi_uplink_empty <= 1'bx;
asi_uplink_valid <= 0;
end
endtask
initial
begin
waitclk(10);
// asi_burst(8'h00, 1120);
// waitclk(7);
// avsWrite(1, 1);
// waitclk(20);
forever @(posedge clk)
begin
asi_burst(8'h20, 1);
waitclk(5);
asi_burst(8'h30, 2);
waitclk(5);
asi_burst(8'h40, 3);
waitclk(5);
asi_burst(8'h50, 4);
waitclk(5);
asi_burst(8'h80, 10);
waitclk(5);
asi_burst(8'hc0, 19);
avsWrite(1, 1);
waitclk(2);
asi_burst(8'h00, 301);
avsWrite(1, 1);
waitclk(10);
repeat (6)
begin
asi_burst(8'h80, 7);
waitclk(4);
end
asi_burst(8'h40, 17);
waitclk(200);
end
end
// log write to uplink sink
reg [7:0]uplink_data1;
reg [7:0]uplink_data0;
always @(negedge clk)
begin
if (asi_uplink_valid && asi_uplink_ready)
begin
uplink_data1 <= asi_uplink_data[15:8];
uplink_data0 <= (!asi_uplink_endofpacket || !asi_uplink_empty) ?
asi_uplink_data[7:0] : 8'hzz;
end
else
begin
uplink_data1 <= 8'hzz;
uplink_data0 <= 8'hzz;
end
end
usb16 DUT
(
.clk(clk),
.reset(reset),
.avs_ctrl_address(avs_ctrl_address),
.avs_ctrl_write(avs_ctrl_write),
.avs_ctrl_writedata(avs_ctrl_writedata),
.avs_ctrl_read(avs_ctrl_read),
.avs_ctrl_readdata(avs_ctrl_readdata),
.asi_uplink_ready(asi_uplink_ready),
.asi_uplink_valid(asi_uplink_valid),
.asi_uplink_data(asi_uplink_data),
.asi_uplink_startofpacket(asi_uplink_startofpacket),
.asi_uplink_endofpacket(asi_uplink_endofpacket),
.asi_uplink_empty(asi_uplink_empty),
.usb_clk(usb_clk),
.wr_n(wr_n),
.rd_n(rd_n),
.oe_n(oe_n),
.data(data),
.txe_n(txe_n),
.rxf_n(rxf_n),
.siwu_n(siwu_n)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> parent; vector<int> Rank; int root(int v) { if (parent[v] == v) return v; return parent[v] = root(parent[v]); } void DSU(int a, int b) { a = root(a); b = root(b); if (a != b) { if (Rank[b] > Rank[a]) swap(a, b); Rank[a] += Rank[b]; parent[b] = a; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, q; cin >> n >> m >> q; parent.resize(n + m + 3); for (int i = 0; i < parent.size(); i++) { parent[i] = i; } Rank.resize(n + m + 3, 1); for (int i = 0; i < q; i++) { int a, b; cin >> a >> b; b += n; DSU(a, b); } set<int> roots; for (int i = 1; i <= n + m; i++) { roots.insert(root(i)); } cout << roots.size() - 1 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; vector<int> T; int l, size; void Stworz(int n) { int p = 1; while (p < n) p *= 2; l = p; size = 2 * p - 1; for (int i = 0; i <= size; ++i) T.push_back(INF); } void Ustaw(int a, int x) { a += l; T[a] = x; a /= 2; while (a != 0) { T[a] = min(T[2 * a], T[2 * a + 1]); a /= 2; } } int Mini(int a, int b) { a += l; b += l; int m = min(T[a], T[b]); while (a / 2 != b / 2) { if (a % 2 == 0) m = min(m, T[a + 1]); if (b % 2 == 1) m = min(m, T[b - 1]); a /= 2; b /= 2; } return m; } int main() { ios_base::sync_with_stdio(0); int n; cin >> n; vector<int> a(n); map<int, int> wyst, pier; for (int i = 0; i < n; ++i) { cin >> a[i]; wyst[a[i]] = 0; pier[a[i]] = INF; } Stworz(n); vector<int> odp; for (int L = 0; L < n;) { int P = L; while (P < n) { ++wyst[a[P]]; if (pier[a[P]] == INF) pier[a[P]] = P; Ustaw(P, pier[a[P]]); if (pier[a[P]] + 1 <= P - 1) { int ind = Mini(pier[a[P]] + 1, P - 1); if (ind < pier[a[P]]) { odp.push_back(a[ind]); odp.push_back(a[P]); odp.push_back(a[ind]); odp.push_back(a[P]); break; } } if (wyst[a[P]] >= 4) { for (int i = 0; i < 4; ++i) odp.push_back(a[P]); break; } ++P; } for (int i = L; i <= min(P, n); ++i) { --wyst[a[i]]; pier[a[i]] = INF; } L = P + 1; } cout << odp.size() << endl; for (int i = 0; i < odp.size(); ++i) cout << odp[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 25; int main(int argc, char *argv[]) { long long n; cin >> n; long long ret1 = (1LL << 60); long long ret2 = 0; for (long long x = 1; x * x <= n; ++x) { if (n % x) continue; long long m = n / x; for (long long y = 1; y * y <= m; ++y) { if ((n / x) % y) continue; long long z = m / y; long long a = x + 1; long long b = y + 2; long long c = z + 2; ret1 = min(a * b * c - n, ret1); ret2 = max(a * b * c - n, ret2); b = x + 2; c = z + 2; a = y + 1; ret1 = min(a * b * c - n, ret1); ret2 = max(a * b * c - n, ret2); a = z + 1; b = x + 2; c = y + 2; ret1 = min(a * b * c - n, ret1); ret2 = max(a * b * c - n, ret2); } } cout << ret1 << << ret2 << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_lp__udp_dff_p.v"
`celldefine
module sky130_fd_sc_lp__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fbkb
#(parameter
ID = 0,
NUM_STAGE = 9,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_7_full_dsp_32 convolve_kernel_ap_fadd_7_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// break function: when CPU M1 address equals to predefined, NMI is generated
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module zbreak
(
input wire fclk, // global FPGA clock
input wire rst_n, // system reset
input wire zpos,
input wire zneg,
input wire [15:0] a,
input wire mreq_n,
input wire m1_n,
input wire brk_ena,
input wire [15:0] brk_addr,
output reg imm_nmi
);
always @(posedge fclk, negedge rst_n)
if( !rst_n )
imm_nmi <= 1'b0;
else if( zneg && !mreq_n && !m1_n && a==brk_addr && brk_ena && !imm_nmi )
imm_nmi <= 1'b1;
else
imm_nmi <= 1'b0;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n",$time, cyc, crc, sum, crc[3:0], out1,out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
`define EXPECTED_SUM 64'h10204fa5567c8a4b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
case (in[3:0]) inside
default: {out1,out2} = {1'b0,5'h0F}; // Note not last item
4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01};
4'h4: {out1,out2} = {1'b1,5'h04};
[4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match
4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08};
[4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C};
endcase
end
endmodule
|
// AJ, Beck, and Ray
// ALUnit testbench
// 5/4/15
`include "Implementation/mux2_1.sv"
`include "adder_subtractor.v"
`include "flag.v"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "ALUnit.sv"
`include "addition.v"
`include "subtract.v"
`include "andGate.v"
`include "orGate.v"
`include "xorGate.v"
`include "setLT.v"
`include "shiftll.v"
module ALUnittest();
// localize variables
wire clk; // Clock
wire [2:0] control;
wire [31:0] busOut;
wire [31:0] busA, busB;
wire zero, overflow, carryout, negative;
// declare an instance of the module
ALUnit ALUnit (clk, control, busOut, busA, busB, zero, overflow, carryout, negative);
// Running the GUI part of simulation
ALUnittester tester (clk, control, busOut, busA, busB, zero, overflow, carryout, negative);
// file for gtkwave
initial
begin
$dumpfile("ALUnittest.vcd");
$dumpvars(1, ALUnit);
end
endmodule
module ALUnittester (clk, control, busOut, busA, busB, zero, overflow, carryout, negative);
output reg clk; // Clock
output reg [2:0] control;
input [31:0] busOut;
output reg [31:0] busA, busB;
input zero, overflow, carryout, negative;
parameter d = 20;
// generate a clock
always #(d/2) clk = ~clk;
initial // Response
begin
$display("busOut \t busA \t busB \t\t zero \t overflow \t carryout \t negative \t ");
#d;
end
initial
begin
$monitor("%b \t %b \t %b \t %b \t %b \t %b \t %b \t %b ", busOut, busA, busB, zero, overflow, carryout, negative, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101; control = 3'b000;
#(10*d);
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; control = 3'b001;// should overflow
#(10*d);
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; control = 3'b010;// 01010101 + -1
#(10*d);
busA = 32'h00000001; busB = 32'hF0000000; control = 3'b011;
#(10*d);
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101; control = 3'b100;
#(10*d);
busA = 32'hF0000000; busB = 32'h00000001; control = 3'b101;
#(10*d);
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; control = 3'b110;// -1 + -1
#(10*d);
busA = 32'h90000000; busB = 32'h80000000; control = 3'b111;// should overflow
#(10*d);
#(3*d);
$stop;
$finish;
end
endmodule
|
/*
* Copyright (c) 2013, The DDK Project
* Dmitry Nedospasov <dmitry at nedos dot net>
* Thorsten Schroeder <ths at modzero dot ch>
*
* All rights reserved.
*
* This file is part of Die Datenkrake (DDK).
*
* "THE BEER-WARE LICENSE" (Revision 42):
* <dmitry at nedos dot net> and <ths at modzero dot ch> wrote this file. As
* long as you retain this notice you can do whatever you want with this stuff.
* If we meet some day, and you think this stuff is worth it, you can buy us a
* beer in return. Die Datenkrake Project.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE DDK PROJECT BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Module: krake_port
* Description: Basic Krake I/O Port
*/
`include "reg_defs.v"
`include "uart_tx.v"
module krake_tx_port(
input wire clk_i,
input wire rst_i,
output reg ack_o,
input wire [7:0] dat_i,
input wire [3:0] adr_i,
output reg [7:0] dat_o,
input wire stb_i,
input wire we_i,
output wire dout);
reg [7:0] data;
reg tx_en;
wire tx_rdy;
reg tx_rst;
uart_tx txi(
.clk(clk_i),
.rst(rst_i),
.en(tx_en),
.data_out(data),
.rdy(tx_rdy),
.dout(dout));
always @ (posedge clk_i)
begin
if(rst_i)
begin
tx_rst <= 1'd1;
data <= 8'd0;
tx_en <= 1'd0;
end
else
begin
// Default Assignments
ack_o <= 1'b0;
dat_o <= 8'd0;
tx_en <= 1'b0;
data <= data;
if(stb_i)
begin
case(adr_i)
`UART_STATUS:
begin
if(we_i) // Write
begin
tx_en <= dat_i[0];
ack_o <= 1'b1;
end
else // Read
begin
dat_o[0] <= tx_rdy;
ack_o <= 1'b1;
end
end
`UART_DATAREG:
begin
if(we_i) // Write
begin
data <= dat_i;
ack_o <= 1'b1;
end
else // Read
begin
dat_o <= data;
ack_o <= 1'b1;
end
end
endcase
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct targ { long long x, r; int id, s; } tar[10004]; bool _x(targ a, targ b) { return a.x < b.x; } bool _id(targ a, targ b) { return a.id < b.id; } int fd(int l, int r, long long x) { if (l == r) return l; int m = l + r >> 1; if (tar[m].x < x) return fd(m + 1, r, x); else return fd(l, m, x); } int cnt = 0; void sl(int now, int p, long long x, long long y) { if ((x - tar[p].x) * (x - tar[p].x) + y * y <= tar[p].r * tar[p].r) tar[p].s = now, cnt++; } int main() { int n, m; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld%lld , &tar[i].x, &tar[i].r); tar[i].id = i; tar[i].s = -1; } sort(tar + 1, tar + n + 1, _x); scanf( %d , &m); long long x, y; for (int i = 1; i <= m; i++) { scanf( %lld%lld , &x, &y); int p = fd(1, n, x); if (tar[p].s == -1) sl(i, p, x, y); if (p - 1 && tar[p - 1].s == -1) sl(i, p - 1, x, y); } sort(tar + 1, tar + n + 1, _id); cout << cnt << endl; for (int i = 1; i <= n; i++) { printf( %d%c , tar[i].s, n [i == n]); } }
|
#include <bits/stdc++.h> using namespace std; const int nmax = 5e5 + 42; struct info { int u, v, cost; }; info inp[nmax]; pair<int, int> my[nmax]; int n, k, m; int parent[nmax]; int root(int node) { if (parent[node] == node) return node; parent[node] = root(parent[node]); return parent[node]; } long long outp; set<int> seen[nmax]; vector<int> adj[nmax]; set<pair<int, int> > my_edge; void solve(int node, int par) { int biggest = -1; for (auto k : adj[node]) if (k != par) { solve(k, node); if (biggest == -1) biggest = k; else if (seen[biggest].size() < seen[k].size()) biggest = k; } if (biggest != -1) { swap(seen[biggest], seen[node]); for (auto w : seen[biggest]) if (seen[node].count(w)) seen[node].erase(w); else seen[node].insert(w); } for (auto k : adj[node]) if (k != par && k != biggest) { for (auto w : seen[k]) if (seen[node].count(w)) seen[node].erase(w); else seen[node].insert(w); } if (my_edge.count({node, par}) || my_edge.count({par, node})) { if (seen[node].size() == 0) { printf( -1 n ); exit(0); } outp += inp[*seen[node].begin()].cost; } } int main() { scanf( %i%i%i , &n, &k, &m); for (int i = 1; i <= n; i++) parent[i] = i; for (int i = 1; i <= k; i++) { scanf( %i%i , &my[i].first, &my[i].second); adj[my[i].first].push_back(my[i].second); adj[my[i].second].push_back(my[i].first); parent[root(my[i].first)] = root(my[i].second); my_edge.insert({my[i].first, my[i].second}); } for (int i = 1; i <= m; i++) { scanf( %i%i%i , &inp[i].u, &inp[i].v, &inp[i].cost); if (root(inp[i].u) != root(inp[i].v)) { parent[root(inp[i].u)] = root(inp[i].v); adj[inp[i].u].push_back(inp[i].v); adj[inp[i].v].push_back(inp[i].u); } else { seen[inp[i].u].insert(i); seen[inp[i].v].insert(i); } } solve(1, 0); printf( %lld n , outp); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_BLACKBOX_V
/**
* udp_dff$P_pp$sN: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$sN (
Q ,
D ,
CLK ,
SLEEP_B ,
NOTIFIER
);
output Q ;
input D ;
input CLK ;
input SLEEP_B ;
input NOTIFIER;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_SN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; const int INF = 1000000009; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int a, b; cin >> a >> b; if ((a || b) && max(a, b) - min(a, b) < 2) { cout << YES ; } else { cout << NO ; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_wr_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_awready ,
input wire s_awvalid ,
output wire m_awvalid ,
input wire m_awready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
output wire b_push ,
input wire b_full ,
output wire a_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE_WAIT = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] next_state;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
end else begin
state <= next_state;
end
end
// Next state transitions.
always @( * )
begin
next_state = state;
case (state)
SM_IDLE:
if (s_awvalid) begin
next_state = SM_CMD_EN;
end else
next_state = state;
SM_CMD_EN:
if (m_awready & next_pending)
next_state = SM_CMD_ACCEPTED;
else if (m_awready & ~next_pending & b_full)
next_state = SM_DONE_WAIT;
else if (m_awready & ~next_pending & ~b_full)
next_state = SM_IDLE;
else
next_state = state;
SM_CMD_ACCEPTED:
next_state = SM_CMD_EN;
SM_DONE_WAIT:
if (!b_full)
next_state = SM_IDLE;
else
next_state = state;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_awvalid = (state == SM_CMD_EN);
assign next = ((state == SM_CMD_ACCEPTED)
| (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ;
assign a_push = (state == SM_IDLE);
assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
assign b_push = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> const double Pi = 3.14159265; const int N = 1e6 + 50; const int M = 1e5 + 15; const unsigned long long base = 163; const int INF = 0x3f3f3f3f; using namespace std; int a[N]; int main() { int n; scanf( %d , &n); int l = 0, r = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; } int pre = 1; int now = -1; int flag = 0; for (int i = 1; i <= n - 1; i++) { if (a[i] == a[i + 1]) { pre++; } else { flag = 1; if (now == -1) now = pre; else { if (pre != now) { cout << NO << endl; return 0; } } pre = 1; } } if (pre != now && flag) return cout << NO n , 0; cout << YES << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int sst(string g) { int f; stringstream ss; ss << g; ss >> f; return f; } int main() { string s, s1, s2, s3; cin >> s; int max = -1, h = 0; int t = s.size(), x, y, z; if (t < 3) { cout << -1 << endl; return 0; } for (int i = 0; i < t - 1; i++) { for (int j = i + 1; j < t - 1; j++) { s1 = s.substr(0, i + 1); s2 = s.substr(i + 1, j - i); s3 = s.substr(j + 1, t - j - 1); x = sst(s1); y = sst(s2); z = sst(s3); if (s1.size() == 0 || s2.size() == 0 || s3.size() == 0) continue; if (s1[0] == 0 && s1.size() > 1) continue; if (s2[0] == 0 && s2.size() > 1) continue; if (s3[0] == 0 && s3.size() > 1) continue; if (x <= 1000000 && y <= 1000000 && z <= 1000000 && x + y + z > max) { max = x + y + z; h = 1; } } } if (h = 1) cout << max; else cout << -1 ; return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_arb_mux
*/
module test_axis_arb_mux_4_64;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter LAST_ENABLE = 1;
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_arb_mux_4_64.lxt");
$dumpvars(0, test_axis_arb_mux_4_64);
end
axis_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 08/31/2016 03:34:58 PM
// Design Name:
// Module Name: KOA_c
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Recursive Karasuba Parameterized Algorithm
//
// Dependencies:
//
// Revision:
// Revision 0.03 - File Created
// Additional Comments: La primera version de este modulo se puede encontrar en la misma carpeta madre.
// The reason for a second version is the way the numbers with lenght lower than 8 are treated. Here, we change that
// by using an at the start before the case, so a multiplier below l = 7 is never instatiated.
//
// Revision 0.03
//
// 1. Width of KOA multipliers in the even case was fixed from the original version
// 2. Zero padding in the adders was fixed.
//////////////////////////////////////////////////////////////////////////////////
module KOA_c
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 54, parameter precision = 1)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-3)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
if (SW<=3 && precision == 0) begin
multiplier_C #(.W(SW)/*,.level(level1)*/) main(
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(sgf_result_o)
);
end if (SW<=7 && precision == 1) begin
multiplier_C #(.W(SW)/*,.level(level1)*/) main(
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(sgf_result_o)
);
end else begin
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_c #(.SW(SW/2), .precision(precision) /*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c #(.SW(SW/2), .precision(precision)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
KOA_c #(.SW(SW/2+1), .precision(precision)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_c #(.SW(SW/2), .precision(precision)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c #(.SW((SW/2)+1), .precision(precision)/*,.level(level2)*/) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
KOA_c #(.SW(SW/2+2), .precision(precision)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({leftside2,S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
//name : file_reader_a
//tag : c components
//output : output_z:16
//source_file : file_reader_a.c
///=============
///
///*Created by C2CHIP*
`timescale 1ns/1ps
module file_reader_a(output_z_ack,clk,rst,output_z,output_z_stb);
integer file_count;
integer input_file_0;
input clk;
input rst;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg [31:0] s_output_z;
reg s_output_z_stb;
reg [31:0] low;
reg [1:0] state;
initial
begin
input_file_0 = $fopenr("stim_a");
end
always @(posedge clk)
begin
case(state)
0:
begin
state <= 1;
end
1:
begin
file_count = $fscanf(input_file_0, "%d\n", low);
state <= 2;
end
2:
begin
s_output_z_stb <= 1;
s_output_z <= low;
if(s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= 0;
end
end
endcase
if (rst == 1'b1) begin
state <= 0;
s_output_z_stb <= 0;
end
end
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_green_leds (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename elemType> inline void Read(elemType &T) { elemType X = 0, w = 0; char ch = 0; while (!isdigit(ch)) { w |= ch == - ; ch = getchar(); } while (isdigit(ch)) X = (X << 3) + (X << 1) + (ch ^ 48), ch = getchar(); T = (w ? -X : X); } long long GCD(long long a, long long b) { return b == 0 ? a : GCD(b, a % b); } const int maxn = 100010; const long long MOD = 1000000007LL; struct Graph { struct edge { int Next, to; }; edge G[maxn << 1]; int head[maxn]; int cnt; Graph() : cnt(2) {} void clear(int node_num = 0) { cnt = 2; if (node_num == 0) memset(head, 0, sizeof(head)); else fill(head, head + node_num + 5, 0); } void add_edge(int u, int v) { G[cnt].to = v; G[cnt].Next = head[u]; head[u] = cnt++; } }; Graph G; long long Value[maxn]; map<long long, long long> Hash[maxn]; long long Ans = 0; int N; void DFS(int u, int fa) { ++Hash[u][Value[u]]; for (auto it : Hash[u]) Ans = (Ans + it.first * it.second % MOD) % MOD; for (int i = G.head[u]; i; i = G.G[i].Next) { int v = G.G[i].to; if (v == fa) continue; for (auto it : Hash[u]) { long long x = GCD(Value[v], it.first); Hash[v][x] += it.second; } DFS(v, u); } return; } int main() { Read(N); for (register int i = 1; i <= N; ++i) Read(Value[i]); for (register int i = 1; i <= N - 1; ++i) { int u, v; Read(u); Read(v); G.add_edge(u, v); G.add_edge(v, u); } DFS(1, 0); printf( %I64d n , Ans); return 0; }
|
#include <bits/stdc++.h> int main() { char s[5200] = {0}, next[5200] = {0}, p[5200] = {0}, t[5200] = {0}; while (scanf( %s , s + 1) != EOF) { s[0] = a ; double sum = 0; int f = 0; while (sscanf(s, %*[^0-9]%[0-9.]%[^ 0] , p, next) > 0) { double num1 = 0, num2 = 0; int len = strlen(p), flag = 0; if (len > 3 && p[len - 3] == . ) { sscanf(p + len - 3, %lf , &num1); flag = f = 1; } if (flag == 1) len = len - 3; for (int i = 0; i < len; i++) { if (p[i] == . ) continue; num2 = num2 * 10 + (p[i] - 0 ); } sum += num1 + num2; strcpy(s, next); memset(next, 0, sizeof(next)); } sprintf(t, %.2f , sum); int len = strlen(t), k = 0; char ans[5200]; if (f == 0) len -= 3; if (f == 1) { ans[k++] = t[--len]; ans[k++] = t[--len]; ans[k++] = t[--len]; if (ans[0] == 0 && ans[1] == 0 ) k = 0; } for (int i = len - 1, counts = 1; i >= 0; i--, counts++) { if (counts % 3 == 1 && counts != 1) ans[k++] = . ; ans[k++] = t[i]; } for (int i = k - 1; i >= 0; i--) printf( %c , ans[i]); printf( n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_BLACKBOX_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int S = 1003; bool a[S]; bool b[S]; string s; int k; int i, j; int main() { cin >> s; j = s.size() - 1; while (i < j) { if (s[i] == ( && s[j] == ) ) { b[i] = 1; b[j] = 1; k++; i++; j--; } else { if (s[i] == ) ) i++; if (s[j] == ( ) j--; } } if (k == 0) { cout << 0 ; return 0; }; cout << 1 << endl; cout << 2 * k << endl; for (int i = 0; i < s.size(); i++) if (b[i]) cout << i + 1 << ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1000000007; void solve() { string s; cin >> s; long long ans = INT_MAX; for (long long i = 0; i <= 9; i++) { long long count = 0; for (long long j = 0; j < (long long)s.size(); j++) { if (s[j] == (char)( 0 + i)) count++; } ans = min(ans, (long long)s.size() - count); } if (ans == 0) { cout << 0 << endl; return; } for (long long i = 0; i <= 9; i++) { for (long long j = 0; j <= 9; j++) { string temp; if (i == j) continue; temp += (char)( 0 + i); temp += (char)( 0 + j); long long count = 0; long long n = (long long)s.size(); long long curr = 0; for (long long k = 0; k < n; k++) { if (s[k] == temp[curr]) { if (curr == 1) { count++; } curr = (curr + 1) % 2; } } ans = min(ans, (long long)s.size() - 2 * count); } } cout << ans << endl; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; inline long long getint() { long long _x = 0, _tmp = 1; char _tc = getchar(); while ((_tc < 0 || _tc > 9 ) && _tc != - ) _tc = getchar(); if (_tc == - ) _tc = getchar(), _tmp = -1; while (_tc >= 0 && _tc <= 9 ) _x *= 10, _x += (_tc - 0 ), _tc = getchar(); return _x * _tmp; } inline long long add(long long _x, long long _y, long long _mod = 1000000007LL) { _x += _y; return _x >= _mod ? _x - _mod : _x; } inline long long sub(long long _x, long long _y, long long _mod = 1000000007LL) { _x -= _y; return _x < 0 ? _x + _mod : _x; } inline long long mul(long long _x, long long _y, long long _mod = 1000000007LL) { _x *= _y; return _x >= _mod ? _x % _mod : _x; } long long mypow(long long _a, long long _x, long long _mod) { if (_x == 0) return 1LL; long long _ret = mypow(mul(_a, _a, _mod), _x >> 1, _mod); if (_x & 1) _ret = mul(_ret, _a, _mod); return _ret; } long long mymul(long long _a, long long _x, long long _mod) { if (_x == 0) return 0LL; long long _ret = mymul(add(_a, _a, _mod), _x >> 1, _mod); if (_x & 1) _ret = add(_ret, _a, _mod); return _ret; } inline bool equal(double _x, double _y) { return _x > _y - 1e-9 && _x < _y + 1e-9; } int __ = 1, _cs; struct Nd { int sum, tl, tr; Nd() { sum = tl = tr = 0; } } nd[101010 * 30 * 4]; int nid; int new_node() { return ++nid; } inline int Sum(int x) { return x ? nd[x].sum : 0; } void modify(int now, int l, int r, int p) { if (l == r) { nd[now].sum++; return; } if (p <= ((l + r) >> 1)) { if (!nd[now].tl) nd[now].tl = new_node(); modify(nd[now].tl, l, ((l + r) >> 1), p); } else { if (!nd[now].tr) nd[now].tr = new_node(); modify(nd[now].tr, ((l + r) >> 1) + 1, r, p); } nd[now].sum = Sum(nd[now].tl) + Sum(nd[now].tr); } int query(int now, int l, int r, int ql, int qr) { if (!now || r < ql || l > qr) return 0; if (ql <= l && r <= qr) return nd[now].sum; return query(nd[now].tl, l, ((l + r) >> 1), ql, qr) + query(nd[now].tr, ((l + r) >> 1) + 1, r, ql, qr); } int rt[10101]; void build() {} int n, k, maxx, maxf; vector<pair<int, pair<int, int> > > v; void init() { n = getint(); k = getint(); for (int i = 0; i < n; i++) { int xi = getint(); int ri = getint(); int fi = getint(); maxx = max(maxx, xi); maxf = max(maxf, fi); v.push_back({ri, {xi, fi}}); } } void solve() { sort(v.begin(), v.end()); reverse(v.begin(), v.end()); long long ans = 0; for (auto i : v) { int nr = i.first; int nx = i.second.first; int nf = i.second.second; int lx = max(1, nx - nr), rx = min(maxx, nx + nr); int lf = max(1, nf - k), rf = min(maxf, nf + k); for (int j = lf; j <= rf; j++) ans += query(rt[j], 1, maxx, lx, rx); if (!rt[nf]) rt[nf] = new_node(); modify(rt[nf], 1, maxx, nx); } printf( %lld n , ans); } int main() { build(); while (__--) { init(); solve(); } }
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