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#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double pi = acos(-1.0); const int INF = 0x3f3f3f3f; const long long inf = (((long long)1) << 61) + 5; const int N = 100005; int f[N]; int g[N]; int a[N]; int bit[N]; int ans[N]; int sum1(int x) { int ans = 0; for (int i = x; i > 0; i -= i & -i) ans = max(bit[i], ans); return ans; } void add1(int x, int val) { for (int i = x; i <= N; i += i & -i) bit[i] = max(bit[i], val); } int sum2(int x) { int ans = 0; for (int i = x; i <= N; i += i & -i) ans = max(bit[i], ans); return ans; } void add2(int x, int val) { for (int i = x; i > 0; i -= i & -i) bit[i] = max(bit[i], val); } int main() { int n, res = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); int x = sum1(a[i] - 1); f[i] = x + 1; if (f[i] > res) res = f[i]; add1(a[i], f[i]); } memset(bit, 0, sizeof bit); for (int i = n; i >= 1; i--) { int x = sum2(a[i] + 1); g[i] = x + 1; add2(a[i], g[i]); } vector<int> q[N]; for (int i = 1; i <= n; i++) { if (f[i] + g[i] - 1 < res) ans[i] = 1; else q[f[i]].push_back(i); } for (int i = 1; i <= res; i++) { int sz = q[i].size(); for (int j = 0; j < sz; j++) { int v = q[i][j]; if (sz == 1) ans[v] = 3; else ans[v] = 2; } } for (int i = 1; i <= n; i++) printf( %d , ans[i]); puts( ); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int a[105], ma = 0, mi = 110, maxi, mini, tc; cin >> tc; for (int i = 0; i < tc; i++) { cin >> a[i]; if (a[i] > ma) { ma = a[i]; maxi = i; } if (a[i] <= mi) { mi = a[i]; mini = i; } } if (maxi > mini) { mini++; } cout << maxi + (tc - 1) - mini << endl; }
|
#include <bits/stdc++.h> int pprime[1010] = {0}; int prime[1010]; int total; void Getprime() { int i, j; for (i = 2; i * i <= 1010; i++) { if (!pprime[i]) { for (j = i; j * i <= 1010; j++) pprime[j * i] = 1; } } total = 0; for (i = 2; i <= 1010; i++) if (!pprime[i]) prime[total++] = i; } struct Edge { int next; int v; int gcd, lcm; } edge[10010]; int head[110]; int pos; void insert(int x, int y, int gcd, int lcm) { edge[pos].next = head[x]; edge[pos].v = y; edge[pos].gcd = gcd; edge[pos].lcm = lcm; head[x] = pos++; } int ans[110]; int mark[110]; bool dfs(int now, int pre) { int i; int l, r; for (i = head[now]; i; i = edge[i].next) { int v = edge[i].v; if (v == pre) continue; l = edge[i].gcd; r = edge[i].lcm; if (mark[now] != l && mark[now] != r) return false; if (mark[now] == l) { if (mark[v] == r) continue; else if (mark[v] == -1) { mark[v] = r; if (!dfs(v, now)) { mark[v] = -1; return false; } } else return false; } else { if (mark[v] == l) continue; else if (mark[v] == -1) { mark[v] = l; if (!dfs(v, now)) { mark[v] = -1; return false; } } else return false; } } return true; } struct fff { int x, y, gcd, lcm; } ooxx[10010]; int judge(int m) { for (int i = 0; i < m; i++) { if (ooxx[i].gcd != 1) return ooxx[i].gcd; if (ooxx[i].lcm != 1) return ooxx[i].lcm; } return 0; } int main() { Getprime(); int n, m; int x, y; int l, r; int now; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) ans[i] = 1; for (int i = 0; i < m; i++) scanf( %d %d %d %d , &ooxx[i].x, &ooxx[i].y, &ooxx[i].gcd, &ooxx[i].lcm); for (int i = 0; i < m; i++) if (ooxx[i].lcm % ooxx[i].gcd != 0) { printf( NO n ); return 0; } int flag; for (int k = 0; k < total; k++) { flag = judge(m); if (!flag) break; now = prime[k]; memset(head, 0, sizeof(head)); pos = 1; for (int i = 0; i < m; i++) { x = ooxx[i].x; y = ooxx[i].y; l = 0; r = 0; while (ooxx[i].gcd % now == 0) { l++; ooxx[i].gcd /= now; } while (ooxx[i].lcm % now == 0) { r++; ooxx[i].lcm /= now; } insert(x, y, l, r); insert(y, x, l, r); } memset(mark, -1, sizeof(mark)); for (int i = 1; i <= n; i++) if (mark[i] == -1) { if (!head[i]) { mark[i] = 0; continue; } int j = head[i]; l = edge[j].gcd; r = edge[j].lcm; mark[i] = l; if (dfs(i, -1)) continue; mark[i] = r; if (dfs(i, -1)) continue; printf( NO n ); return 0; } for (int i = 1; i <= n; i++) { int add = 1; int time = mark[i]; while (time--) add *= now; ans[i] *= add; } } while (1) { flag = judge(m); if (!flag) break; now = flag; memset(head, 0, sizeof(head)); pos = 1; for (int i = 0; i < m; i++) { x = ooxx[i].x; y = ooxx[i].y; l = 0; r = 0; while (ooxx[i].gcd % now == 0) { l++; ooxx[i].gcd /= now; } while (ooxx[i].lcm % now == 0) { r++; ooxx[i].lcm /= now; } insert(x, y, l, r); insert(y, x, l, r); } memset(mark, -1, sizeof(mark)); for (int i = 1; i <= n; i++) if (mark[i] == -1) { if (!head[i]) { mark[i] = 0; continue; } int j = head[i]; l = edge[j].gcd; r = edge[j].lcm; mark[i] = l; if (dfs(i, -1)) continue; mark[i] = r; if (dfs(i, -1)) continue; printf( NO n ); return 0; } for (int i = 1; i <= n; i++) { int add = 1; int time = mark[i]; while (time--) add *= now; ans[i] *= add; } } printf( YES n ); for (int i = 1; i <= n; i++) printf( %d , ans[i]); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long a, b; cin >> a >> b; long long ships = 0; while (a != 0 && b != 0) { if (b > a) { ships += b / a; b = b % a; } else { ships += a / b; a = a % b; } } cout << ships << endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_PP_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_PP_V
|
`timescale 1ns/1ps
`define prop_delay (0.1)
module AND2 (o, a, b);
output o;
input a, b;
and #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module AND3 (o, a, b, c);
output o;
input a, b, c;
and #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module NAND2 (o, a, b);
output o;
input a, b;
nand #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module NAND3 (o, a, b, c);
output o;
input a, b, c;
nand #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module OR2 (o, a, b);
output o;
input a, b;
or #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module OR3 (o, a, b, c);
output o;
input a, b, c;
or #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module NOR2 (o, a, b);
output o;
input a, b;
nor #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module NOR3 (o, a, b, c);
output o;
input a, b, c;
nor #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module AO22 (o, a1, a2, b1, b2);
output o;
input a1, a2, b1, b2;
wire a, b;
and (a, a1, a2);
and (b, b1, b2);
or #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module AO222 (o, a1, a2, b1, b2, c1, c2);
output o;
input a1, a2, b1, b2, c1, c2;
wire a, b, c;
and (a, a1, a2);
and (b, b1, b2);
and (c, c1, c2);
or #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module BUFF (o, i);
output o;
input i;
assign o = i;
endmodule
module INV (o, i);
output o;
input i;
not #(`prop_delay,`prop_delay) (o, i);
endmodule
module GND (o);
output o;
supply0 gnd;
assign o = gnd;
endmodule
module C2 (o, a, b);
output o;
input a, b;
UDP_C2 #(`prop_delay,`prop_delay) (o, a, b);
endmodule
module C2R (o, a, b, r);
output o;
input a, b, r;
UDP_C2R #(`prop_delay,`prop_delay) (o, a, b, r);
endmodule
module AC2 (o, a, u); // FIXME, change to C1U1
output o;
input a, u;
UDP_C1U1 #(`prop_delay,`prop_delay) (o, a, u);
endmodule
module C3 (o, a, b, c);
output o;
input a, b, c;
UDP_C3 #(`prop_delay,`prop_delay) (o, a, b, c);
endmodule
module MUTEX (ar, br, ag, bg);
input ar, br;
output ag, bg;
// FIXME
// assign ag = ar;
// assign bg = br;
UDP_mutex_top_half #(`prop_delay, `prop_delay) (ag, ar, br, bg);
UDP_mutex_bottom_half #(`prop_delay, `prop_delay) (bg, br, ar, ag);
endmodule
primitive UDP_C2 (o, a, b);
output o;
input a, b;
reg o;
table /*
a b : o : o' */
1 1 : ? : 1;
0 0 : ? : 0;
1 0 : ? : -;
0 1 : ? : -;
endtable
endprimitive
primitive UDP_C1U1 (o, a, u);
output o;
input a, u;
reg o;
table /*
a u : o : o' */
1 1 : ? : 1;
0 ? : ? : 0;
1 0 : ? : -;
endtable
endprimitive
primitive UDP_C2R (o, a, b, r);
output o;
input a, b, r;
reg o;
table /*
a b r : o : o' */
1 1 0 : ? : 1;
0 0 0 : ? : 0;
1 0 0 : ? : -;
0 1 0 : ? : -;
? ? 1 : ? : 0;
endtable
endprimitive
primitive UDP_C3 (o, a, b, c);
output o;
input a, b, c;
reg o;
table /*
a b c : o : o' */
1 1 1 : ? : 1;
0 0 0 : ? : 0;
1 0 0 : ? : -;
1 1 0 : ? : -;
0 1 0 : ? : -;
0 1 1 : ? : -;
0 0 1 : ? : -;
1 0 1 : ? : -;
endtable
endprimitive
/*
module top;
reg a, b;
wire o;
C2 I0 (o, a, b);
initial begin
$monitor ("%t a = %x b = %x o = %x", $time, a, b, o);
a = 0; b = 0;
#1 a = 1; b = 0;
#1 a = 1; b = 1;
#1 a = 1; b = 0;
#1 a = 0; b = 0;
end
endmodule
*/
primitive UDP_mutex_bottom_half (G, R1, R2, G2state);
output G;
input R1, R2, G2state;
reg G;
table
// ,--------- R1
// | ,-------- R2
// | | ,------- G2state
// | | | ,---- G
// | | | | ,- G'
// v v v : v : v
0 ? ? : ? : 0;
1 ? 1 : ? : 0;
1 0 0 : ? : 1;
1 x 0 : ? : 1;
1 ? x : ? : 1;
1 1 0 : 0 : 0;
1 1 0 : 1 : 1;
x x x : ? : x;
endtable
endprimitive
primitive UDP_mutex_top_half (G, R1, R2, G2state);
output G;
input R1, R2, G2state;
table
// ,-------- R1
// | ,------- R2
// | | ,------ G2state
// | | | ,--- G
// v v v : v
0 ? ? : 0;
1 ? 1 : 0;
1 ? 0 : 1;
1 ? x : 1;
x x x : x;
endtable
endprimitive
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#include <bits/stdc++.h> using namespace std; int n, a, b, ans; int main() { scanf( %d %d %d , &n, &a, &b); if (b < 0) { for (int i = b; i < 0; i++) { a--; if (a == 0) { a = n; } } ans = a; } else { for (int i = 0; i < b; i++) { a++; if (a > n) { a = 1; } } ans = a; } printf( %d n , ans); return 0; }
|
//-----------------------------------------------------------------------------
// Pretend to be an ISO 14443 tag. We will do this by alternately short-
// circuiting and open-circuiting the antenna coil, with the tri-state
// pins.
//
// We communicate over the SSP, as a bitstream (i.e., might as well be
// unframed, though we still generate the word sync signal). The output
// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
// -> ARM) is us using the A/D as a fancy comparator; this is with
// (software-added) hysteresis, to undo the high-pass filter.
//
// At this point only Type A is implemented. This means that we are using a
// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
//
// Jonathan Westhues, October 2006
//-----------------------------------------------------------------------------
module hi_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
// always be low.
assign pwr_hi = 1'b0;
assign pwr_lo = 1'b0;
// The comparator with hysteresis on the output from the peak detector.
reg after_hysteresis;
assign adc_clk = ck_1356meg;
always @(negedge adc_clk)
begin
if(& adc_d[7:5]) after_hysteresis = 1'b1;
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
end
// Divide 13.56 MHz by 32 to produce the SSP_CLK
// The register is bigger to allow higher division factors of up to /128
reg [6:0] ssp_clk_divider;
always @(posedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1);
assign ssp_clk = ssp_clk_divider[4];
// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
// this is arbitrary, because it's just a bitstream.
// One nasty issue, though: I can't make it work with both rx and tx at
// once. The phase wrt ssp_clk must be changed. TODO to find out why
// that is and make a better fix.
reg [2:0] ssp_frame_divider_to_arm;
always @(posedge ssp_clk)
ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
reg [2:0] ssp_frame_divider_from_arm;
always @(negedge ssp_clk)
ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
reg ssp_frame;
always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
if(mod_type == 3'b000) // not modulating, so listening, to ARM
ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
else
ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
// Synchronize up the after-hysteresis signal, to produce DIN.
reg ssp_din;
always @(posedge ssp_clk)
ssp_din = after_hysteresis;
// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that
reg modulating_carrier;
always @(mod_type or ssp_clk or ssp_dout)
if(mod_type == 3'b000)
modulating_carrier <= 1'b0; // no modulation
else if(mod_type == 3'b001)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if(mod_type == 3'b010)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else
modulating_carrier <= 1'b0; // yet unused
// This one is all LF, so doesn't matter
assign pwr_oe2 = modulating_carrier;
// Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
assign pwr_oe1 = modulating_carrier;
assign pwr_oe4 = modulating_carrier;
// This one is always on, so that we can watch the carrier.
assign pwr_oe3 = 1'b0;
assign dbg = after_hysteresis;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long f = 0, j, q = 1, i, n; while (q--) { long long y, k = 1, x, M, s; cin >> n >> M >> s >> f; unordered_map<int, pair<int, int> > m; for (i = 0; i < M; i++) { long long X, Y, Z; cin >> X >> Y >> Z; m.insert(make_pair(X, make_pair(Y, Z))); } if (s < f) { while (s != f) { if (m.count(k)) { if ((s >= m[k].first && s <= m[k].second) || (s + 1 >= m[k].first && s + 1 <= m[k].second)) cout << X ; else { cout << R ; s++; } } else { cout << R ; s++; } k++; } } else { while (s != f) { if (m.count(k)) { if ((s >= m[k].first && s <= m[k].second) || (s - 1 >= m[k].first && s - 1 <= m[k].second)) cout << X ; else { cout << L ; s--; } } else { cout << L ; s--; } k++; } } cout << endl; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
`define zednkw 200
module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr);
input zfghtn;
input [4:0] cjtmau;
input vipmpg;
input [7:0] knquim;
input [7:0] kqxkkr;
reg covfok;
reg [15:0] xwieqw;
reg [2:0] ofnjjt;
reg [37:0] hdsejo[1:0];
reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq;
reg vrqrih, ryyjxy;
reg fgzsox;
wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr;
wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10];
wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10];
wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr;
wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr;
wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1);
wire smxixw = vrqrih | (ryyjxy & ktsveg);
wire [7:0] grvsrs, kyxrft, uxhkka;
wire [7:0] eianuv = 8'h01 << ofnjjt;
wire [7:0] jvpnxn = {8{qnpfus}} & eianuv;
wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv;
wire [7:0] nahzat = {8{iytyol}} & eianuv;
genvar i;
generate
for (i=0;i<8;i=i+1)
begin : dnlpyw
DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i],
knquim[3:0], covfok, grvsrs[i]);
DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i],
knquim[7:4], covfok, kyxrft[i]);
DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i],
kqxkkr[3:0], covfok, uxhkka[i]);
end
endgenerate
endmodule
module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh);
input clk, fgzsox, fckiyr, covfok;
input [3:0] uezcjy;
output juvlsh;
task Xinit;
begin
`ifdef TEST_HARNESS
khgawe = 1'b0;
`endif
end
endtask
function X;
input vrdejo;
begin
`ifdef TEST_HARNESS
if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1;
`endif
X = vrdejo;
end
endfunction
task Xcheck;
input vzpwwy;
begin
end
endtask
reg [3:0] udbvtl;
assign juvlsh = |udbvtl;
wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1));
wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox;
always @(posedge clk)
begin
Xinit;
if (X(qqibou))
udbvtl <= #`zednkw mppedc;
Xcheck(fgzsox);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m; cin >> n >> m; long long int x[n][m], y[n][m], a[n][m], b[n], c[m], i, j, ans = 0, ans1 = 0, d[n], e[m]; for (i = 0; i < n; i++) { long long int min = 99999999999; for (j = 0; j < m; j++) { cin >> x[i][j]; a[i][j] = x[i][j]; y[i][j] = x[i][j]; } } for (i = 0; i < n; i++) { long long int min = 99999999999; for (j = 0; j < m; j++) { if (min > a[i][j]) min = a[i][j]; } b[i] = min; if (b[i] != 0) ans += b[i]; } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { a[i][j] -= b[i]; } } for (i = 0; i < m; i++) { long long int min = 99999999999; for (j = 0; j < n; j++) { if (min > a[j][i]) min = a[j][i]; } c[i] = min; if (c[i] != 0) ans += c[i]; } for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { a[j][i] -= c[i]; } } long long int count = 0; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (a[i][j] == 0) count++; } } for (i = 0; i < m; i++) { long long int min = 99999999999; for (j = 0; j < n; j++) { if (min > y[j][i]) min = y[j][i]; } e[i] = min; if (e[i] != 0) ans1 += e[i]; } for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { y[j][i] -= e[i]; } } for (i = 0; i < n; i++) { long long int min = 99999999999; for (j = 0; j < m; j++) { if (min > y[i][j]) min = y[i][j]; } d[i] = min; if (d[i] != 0) ans1 += d[i]; } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { y[i][j] -= d[i]; } } long long int count1 = 0; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (y[i][j] == 0) count1++; } } if (ans < ans1) { if (count == n * m) { cout << ans << endl; for (i = 0; i < n; i++) { if (b[i] != 0) { while (b[i]--) cout << row << i + 1 << endl; } } for (i = 0; i < m; i++) { if (c[i] != 0) { while (c[i]--) cout << col << i + 1 << endl; } } } else { cout << -1 << endl; } } else { if (count1 == n * m) { cout << ans1 << endl; for (i = 0; i < n; i++) { if (d[i] != 0) { while (d[i]--) cout << row << i + 1 << endl; } } for (i = 0; i < m; i++) { if (e[i] != 0) { while (e[i]--) cout << col << i + 1 << endl; } } } else { cout << -1 << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int Rint() { int x; scanf( %d , &x); return x; } const int MOD = 1e9 + 7; const int MAXN = 1e5 + 10; int alll(char* str_a, char* str_b, int n) { int ret = 1; for (int i = 0; i < n; ++i) { if (str_a[i] == ? ) ret = ret * 10ll % MOD; if (str_b[i] == ? ) ret = ret * 10ll % MOD; } return ret; } int upp(char* str_a, char* str_b, int n) { int ans = 1; for (int i = 0; i < n; ++i) { if (str_a[i] == str_b[i]) { if (str_a[i] != ? ) ; else ans = ans * 55ll % MOD; } else if (str_a[i] == ? ) { ans = ans * (long long)( 9 - str_b[i] + 1) % MOD; } else if (str_b[i] == ? ) { ans = ans * (long long)(str_a[i] - 0 + 1) % MOD; } else if (str_a[i] >= str_b[i]) { } else return 0; } return ans; } int equ(char* str_a, char* str_b, int n) { int ret = 1; for (int i = 0; i < n; ++i) if (str_a[i] == ? || str_b[i] == ? ) { if (str_a[i] == ? && str_b[i] == ? ) ret = ret * 10ll % MOD; } else if (str_a[i] != str_b[i]) return 0; return ret; } int n; char str_a[MAXN], str_b[MAXN]; int main() { while (cin >> n) { scanf( %s , str_a); scanf( %s , str_b); int all = alll(str_a, str_b, n); int mod1 = upp(str_a, str_b, n); int mod2 = upp(str_b, str_a, n); int mod3 = equ(str_a, str_b, n); int ans = ((mod1 + mod2 - mod3) % MOD + MOD) % MOD; ans = (all - ans + MOD) % MOD; printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t; cin >> t; while (t--) { long long n, k; cin >> n >> k; long long a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } if (k % 2 == 0) k = 2; else k = 1; while (k--) { long long m = -10000000000; for (int i = 0; i < n; i++) { m = max(m, a[i]); } for (int i = 0; i < n; i++) { a[i] = m - a[i]; } } for (int i = 0; i < n; i++) cout << a[i] << ; cout << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_SYMBOL_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_isobufsrc (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000007; const long long INF64 = 2000000000000000007; const int eps = 10e-6; long long solve(vector<int> one, vector<int> two, vector<int> three) { long long min_w = INF64; for (auto x : one) { long long b = x; auto a = lower_bound(two.begin(), two.end(), b); auto c = upper_bound(three.begin(), three.end(), b); if (a == two.end() || c == three.begin()) continue; long long aa = two[a - two.begin()]; long long cc = three[c - three.begin() - 1]; min_w = min(min_w, (aa - b) * (aa - b) + (b - cc) * (b - cc) + (cc - aa) * (cc - aa)); } return min_w; } int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int k, l, m; cin >> k >> l >> m; vector<int> red(k); vector<int> green(l); vector<int> blue(m); for (int i = 0; i < k; i++) cin >> red[i]; for (int i = 0; i < l; i++) cin >> green[i]; for (int i = 0; i < m; i++) cin >> blue[i]; sort(red.begin(), red.end()); sort(blue.begin(), blue.end()); sort(green.begin(), green.end()); long long ans = INF64; ans = min(ans, solve(red, green, blue)); ans = min(ans, solve(red, blue, green)); ans = min(ans, solve(green, red, blue)); ans = min(ans, solve(green, blue, red)); ans = min(ans, solve(blue, green, red)); ans = min(ans, solve(blue, red, green)); cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char buf[1 << 21], *p1 = buf, *p2 = buf; template <class T> void read(T &x) { x = 0; int c = getchar(); int flag = 0; while (c < 0 || c > 9 ) flag |= (c == - ), c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); if (flag) x = -x; } template <class T> T _max(T a, T b) { return b < a ? a : b; } template <class T> T _min(T a, T b) { return a < b ? a : b; } template <class T> bool checkmax(T &a, T b) { return a < b ? a = b, 1 : 0; } template <class T> bool checkmin(T &a, T b) { return b < a ? a = b, 1 : 0; } const int N = 82; int n; int l[N], r[N], foo[N]; int arr[N << 1], top = 0; int L, R; double f[N][N], g[N][N]; double ans[N][N]; void init() { read(n); for (int i = 1; i <= n; ++i) { read(l[i]); read(r[i]); arr[++top] = l[i]; arr[++top] = r[i]; foo[i] = r[i] - l[i]; } sort(arr + 1, arr + top + 1); top = unique(arr + 1, arr + top + 1) - arr - 1; } double calcl(int idx) { return 1.0 * _min(_max(0, L - l[idx]), foo[idx]) / foo[idx]; } double calcr(int idx) { return 1.0 * _min(_max(0, r[idx] - R), foo[idx]) / foo[idx]; } double calcmid(int idx) { return 1 - calcl(idx) - calcr(idx); } void run(int idx, int bar) { L = arr[bar], R = arr[bar + 1]; if (L < l[idx] || R > r[idx]) return; memset(f, 0, sizeof f); f[0][0] = 1; int tot = 0; for (int i = 1; i <= n; ++i) { if (i == idx) continue; ++tot; double cl = calcl(i), cr = calcr(i), cm = calcmid(i); for (int j = tot; j >= 0; --j) { for (int k = tot - j; k >= 0; --k) { if (j + k < tot) f[j][k] *= cm; else f[j][k] = 0; if (j) f[j][k] += f[j - 1][k] * cl; if (k) f[j][k] += f[j][k - 1] * cr; } } } double co = 1.0 * (R - L) / foo[idx]; for (int i = 0; i <= tot; ++i) { for (int j = 0; i + j <= tot; ++j) { int num = tot - i - j + 1; double res = f[i][j] / num * co; ans[idx][i + 1] += res; ans[idx][n - j + 1] -= res; } } } void solve() { for (int i = 1; i <= n; ++i) { for (int j = 1; j < top; ++j) { run(i, j); } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { ans[i][j] += ans[i][j - 1]; printf( %.8lf%c , ans[i][j], n [j == n]); } } } int main() { init(); solve(); return 0; }
|
`timescale 1ns/1ps
`default_nettype none
`ifndef VCDFILE
`define VCDFILE "testbench_error_output_logic_tb.vcd"
`endif
module test;
`include "../../../../library/tbassert.v"
localparam ADDR_WIDTH = 10;
localparam DATA_WIDTH = 1;
reg [0:0] rst = 1'b0;
reg [0:0] clk = 1'b0;
reg [0:0] loop_complete = 1'b0;
reg [0:0] error_detected = 1'b0;
reg [7:0] error_state = 8'b0;
reg [ADDR_WIDTH-1:0] error_address = {ADDR_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] expected_data = {DATA_WIDTH{1'b0}};
// Output to UART
reg [0:0] tx_data_accepted = 1'b0;
wire [0:0] tx_data_ready;
wire [7:0] tx_data;
// clock generation
always #1 clk=~clk;
wire [15:0] sw;
wire [15:0] led;
wire tx;
wire rx;
assign sw[0] = rst;
assign sw[1] = loop_complete;
assign sw[2] = error_detected;
assign sw[4:3] = error_state[1:0];
assign sw[14:5] = error_address;
assign sw[15] = expected_data;
assign rx = tx_data_accepted;
assign tx_data = led[7:0];
assign tx_data_ready = led[8];
top unt(
.clk(clk),
.rx(rx),
.tx(tx),
.sw(sw),
.led(led)
);
initial begin
$dumpfile(`VCDFILE);
$dumpvars;
#1.1 // 1
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 2
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
rst = 1;
#1 // 3
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 4
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
rst = 0;
#1 // 5
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 6 : Test simple output
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
loop_complete = 1;
#2 // 8
loop_complete = 0;
#3 // 11
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == "L", "Check data value!");
#1 // 12
tbassert(!clk, "Clock!");
loop_complete = 0;
tx_data_accepted = 1;
#1 // 13
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 14
tbassert(!clk, "Clock!");
#1 // 15
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b0, "Check data value!");
#4 // 19
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b0, "Check data value!");
#4 // 23
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b0, "Check data value!");
#4 // 27
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h0D, "Check data value!");
#4 // 31
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h0A, "Check data value!");
#3 // 34 : Check no extra data
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 35
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 36
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 37
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 38
tbassert(!clk, "Clock!");
error_detected = 1;
error_state = 8'b10;
error_address = 10'h3EF;
expected_data = 1;
#2 // 39
error_detected = 0;
#3 // 39
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == "E", "Check data value!");
#4 // 43
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b10, "Check error state!");
#4 // 47
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'hEF, "Check addr[0] state!");
#4 // 51
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h03, "Check addr[1] state!");
#4 // 55
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b1, "Check expected data[0] state!");
#4 // 59
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b0, "Check actual data[0] state!");
#4 // 63
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h0D, "Check data value!");
#4 // 67
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h0A, "Check data value!");
#3 // 70 : Check no extra data
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 71
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 72
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 73
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 $finish;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file pezhman_mem.v when simulating
// the core, pezhman_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module pezhman_mem(
clka,
addra,
douta
);
input clka;
input [14 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("pezhman_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; for (int i = 0; i < n; ++i) { for (int x = 0; x < n; ++x) if (i == x) cout << k << ; else cout << 0 << ; cout << endl; } }
|
/*
This file is part of avgai.
avgai is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
avgai is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with avgai. If not, see <http://www.gnu.org/licenses/>.
Copyright Dakota Fisher 2014
*/
module avgai(input clk, reset, input [9:0] SW,
output reg [9:0] LEDG,
output [3:0] VGA_R, VGA_G, VGA_B, output VGA_VS, VGA_HS,
inout [31:0] GPIO_1);
wire [5:0] inData = {GPIO_1[13],GPIO_1[11],GPIO_1[9],GPIO_1[7],GPIO_1[5],GPIO_1[3]};
wire inDataClk = GPIO_1[1];
wire ready;
wire wAck;
assign GPIO_1[0] = ready;
wire [15:0] SRAM_data;
wire [7:0] INT_X, INT_Y, SRAM_X, SRAM_Y;
wire [11:0] SRAM_out;
wire [11:0] VGA_Data;
wire [9:0] hNeed, vNeed;
vgaControl(clk, reset_, VGA_VS, VGA_HS, need, hNeed, vNeed);
wire [11:0] wDbg;
comm_int(clk, 0, inDataClk, inData, INT_X, INT_Y, SRAM_data, write);
wire SRAM_read = need;
wire SRAM_write = !SRAM_read & write;
assign ready = !write | wAck;
assign SRAM_X = SRAM_read ? hNeed >> 2 : INT_X;
assign SRAM_Y = SRAM_read ? vNeed >> 2 : INT_Y;
reg needBuf;
always @(posedge clk) needBuf <= need;
assign {VGA_R, VGA_G, VGA_B} = VGA_Data;
assign VGA_Data = needBuf ? SRAM_out : 0;
SRAM(clk, SRAM_read, SRAM_write, SRAM_X, SRAM_Y, SRAM_data >> 4, SRAM_out, wAck, wDbg);
clkDiv(clk, divClk);
// Debugging LEDs
always @* begin
LEDG[9] = inDataClk;
LEDG[8] = ready;
LEDG[7] = write;
LEDG[5:0] = inData;
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/********
* This module captures the relative frequency with which each bit in 'value'
* toggles. This can be useful for detecting address patterns for example.
*
* Eg. (in hex)
* Linear: 1ff ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Linear predicated: 1ff ff 80 40 00 00 00 20 10 8 4 2 1 0 0 0 ...
* Strided: 00 00 ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Random: ff ff ff ff ff ff ff ff ff ...
*
* The counters that track the toggle rates automatically get divided by 2 once
* any of their values comes close to overflowing. Hence the toggle rates are
* relative, and comparable only within a single module instance.
*
* The last counter (count[WIDTH]) is a saturating counter storing the number of
* times a scaledown was performed. If you assume the relative rates don't
* change between scaledowns, this can be used to approximate absolute toggle
* rates (which can be compared against rates from another instance).
*****************/
module acl_toggle_detect
#(
parameter WIDTH=13, // Width of input signal in bits
parameter COUNTERWIDTH=10 // in bits, MUST be greater than 3
)
(
input logic clk,
input logic resetn,
input logic valid,
input logic [WIDTH-1:0] value,
output logic [COUNTERWIDTH-1:0] count[WIDTH+1]
);
/******************
* LOCAL PARAMETERS
*******************/
/******************
* SIGNALS
*******************/
logic [WIDTH-1:0] last_value;
logic [WIDTH-1:0] bits_toggled;
logic scaledown;
/******************
* ARCHITECTURE
*******************/
always@(posedge clk or negedge resetn)
if (!resetn)
last_value<={WIDTH{1'b0}};
else if (valid)
last_value<=value;
// Compute which bits toggled via XOR
always@(posedge clk or negedge resetn)
if (!resetn)
bits_toggled<={WIDTH{1'b0}};
else if (valid)
bits_toggled<=value^last_value;
else
bits_toggled<={WIDTH{1'b0}};
// Create one counter for each bit in value. Increment the respective
// counter if that bit toggled.
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1)
begin:counters
always@(posedge clk or negedge resetn)
if (!resetn)
count[i] <= {COUNTERWIDTH{1'b0}};
else if (bits_toggled[i] && scaledown)
count[i] <= (count[i] + 2'b1) >> 1;
else if (bits_toggled[i])
count[i] <= count[i] + 2'b1;
else if (scaledown)
count[i] <= count[i] >> 1;
end
endgenerate
// Count total number of times scaled down - saturating counter
// This can be used to approximate absolute toggle rates
always@(posedge clk or negedge resetn)
if (!resetn)
count[WIDTH] <= 1'b0;
else if (scaledown && count[WIDTH]!={COUNTERWIDTH{1'b1}})
count[WIDTH] <= count[WIDTH] + 2'b1;
// If any counter value's top 3 bits are 1s, scale down all counter values
integer j;
always@(posedge clk or negedge resetn)
if (!resetn)
scaledown <= 1'b0;
else if (scaledown)
scaledown <= 1'b0;
else
for (j = 0; j < WIDTH; j = j + 1)
if (&count[j][COUNTERWIDTH-1:COUNTERWIDTH-3])
scaledown <= 1'b1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_1_V
`define SKY130_FD_SC_HD__TAPVGND2_1_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog wrapper for tapvgnd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tapvgnd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tapvgnd2 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_1_V
|
#include <bits/stdc++.h> using namespace std; double EPS = 1e-9; int INF = 1 << 30; long long INFL = 1LL << 60; int main() { int n; cin >> n; string w; cin >> w; int ile = 0; for (int i = 1; i < n; i += 2) { if (w[i] == a && w[i - 1] == a ) { w[i] = b ; ile++; } if (w[i] == b && w[i - 1] == b ) { w[i] = a ; ile++; } } cout << ile << n << w; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int f = 0, num; char ch; while (ch = getchar(), !isdigit(ch)) if (ch == - ) f = 1; num = ch - 0 ; while (ch = getchar(), isdigit(ch)) num = num * 10 + ch - 0 ; return f ? -num : num; } const int N = 103; char s[N], ans[N], tmp[103]; char ch; void is() { ch = getchar(); while (ch != n ) ch = getchar(); } int cnt, tot, T, f; int main() { T = read(); f = 0, cnt = 0; while (T--) { int f1 = 0; tot = 0; ch = getchar(); while (ch != n ) { if (ch == ) f1 = 1; if (f1) s[tot++] = ch; else if (ch != ) s[tot++] = ch; ch = getchar(); } s[tot++] = 0 ; if (f) { if (s[1] == r ) cnt++; if (s[0] == c ) { if (cnt) cnt--; else { tot = 0; int i = 6; while (s[i] != , ) { tmp[tot++] = s[i]; i++; } tmp[tot++] = 0 ; if (!strcmp(tmp, ans)) { int i = 7 + tot; while (s[i] != ) { cout << s[i]; i++; } cout << endl; f = 0; } } } } if (s[1] == h ) { f = 1; tot = 0; for (int i = 6; s[i] != ) ; i++) ans[tot++] = s[i]; ans[tot++] = 0 ; } } if (f) cout << Unhandled Exception << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, n, m; while (cin >> n >> k) { if (n * (n - 1) / 2 <= k) { puts( no solution ); } else { for (i = 0; i < n; i++) printf( 0 %d n , i); } } return 0; }
|
// BF2HW
// Copyright (C) 2017 Christian Fibich
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Toplevel module instantiating BAMBU generated hardware
//
module bf2hw_top(input clk12, input SERIAL_RX, output SERIAL_TX);
`define D_BAUD_FREQ 12'd4
`define D_BAUD_LIMIT 16'd621
wire TX_BUSY;
wire TX_WRITE;
wire RX_VALID;
wire [7:0] RX_DATA;
wire [7:0] TX_DATA;
wire TX_READY;
wire clock; // 24 MHz clock generated by the PLL
wire locked;
wire reset;
reg [2:0] reset_sync;
assign TX_READY = ~TX_BUSY;
pll the_pll (.clock_in(clk12), .clock_out(clock), .locked(locked));
assign reset = reset_sync[2];
initial begin
reset_sync <= 3'b11;
end
always @(posedge clock or negedge locked) begin
if (locked == 1'b0) begin
reset_sync <= 3'b11;
end else begin
reset_sync <= {reset_sync[1:0],1'b0};
end
end
uart_top uart (.clock(clock), .reset(reset),.ser_in(SERIAL_RX), .ser_out(SERIAL_TX),
.rx_data(RX_DATA), .new_rx_data(RX_VALID),
.tx_data(TX_DATA), .new_tx_data(TX_WRITE), .tx_busy(TX_BUSY),
.baud_freq(`D_BAUD_FREQ), .baud_limit(`D_BAUD_LIMIT),
.baud_clk()
);
main_minimal_interface main(.clock(clock), .reset(reset),
.start_port(1'b1), .RX_VALID(RX_VALID), .RX_DATA(RX_DATA),
.TX_READY(TX_READY), .done_port(), .return_port(),
.TX_ENABLE(TX_WRITE), .TX_DATA(TX_DATA));
endmodule
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#include <bits/stdc++.h> using namespace std; int ed; int l[360360 + 1], qd[8405400 + 1], qn[8405400 + 1]; int q[360360 + 1]; void bd(int first, int second) { qd[++ed] = second; qn[ed] = l[first]; l[first] = ed; } inline void bfs(int st, long long v[]) { for (int i = (0); i < (360360 + 1); ++i) v[i] = -1; v[st] = 0; q[0] = st; for (int i = 0, j = 0; i <= j; i++) { for (int k = (l[q[i]]); k; k = qn[k]) if (v[qd[k]] == -1) { v[qd[k]] = v[q[i]] + 1; q[++j] = qd[k]; } } } int main(int argc, char **argv) { long long A, B, K; cin >> A >> B >> K; for (int i = (0); i < (360360 + 1); ++i) { if (i) bd(i, i - 1); for (int j = (2); j < (K + 1); ++j) bd(i, i - (i % j)); } long long s[360360 + 1], t[360360 + 1]; bfs(A % 360360, s); bfs(360360, t); if (A / 360360 == B / 360360) cout << s[B % 360360]; else cout << (s[0] + t[0] * (A / 360360 - B / 360360 - 1) + t[B % 360360]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); int pal(string s) { int i = 0, j = s.length() - 1; while (i < j) { if (s[i] != s[j]) return 0; i++; j--; } return 1; } int main() { ios_base::sync_with_stdio(false); string str, tp, s; cin >> str; int l = str.length(); for (int i = 0; i <= l; i++) { s = str.substr(0, i); for (int j = 0; j < 26; j++) { char ch = a + j; tp = s + ch + str.substr(i); if (pal(tp)) { cout << tp << endl; return 0; } } } cout << NA << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; int c[maxn]; int p[64], q[64]; int l[maxn]; int ans[maxn]; vector<int> g[maxn]; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> c[i]; int Q; cin >> Q; for (int i = 1; i <= Q; i++) { int r; cin >> l[i] >> r; g[r].push_back(i); } for (int i = 1; i <= n; i++) { int r = i, x = c[i]; for (int j = 30; j >= 0; j--) { if (x >> j & 1) { if (!p[j]) { p[j] = x; q[j] = r; break; } if (q[j] < r) { swap(p[j], x); swap(q[j], r); } x ^= p[j]; } } for (int k = 0; k < g[i].size(); k++) { int now = g[i][k]; for (int j = 30; j >= 0; j--) { if (q[j] >= l[now]) ans[now] = max(ans[now], ans[now] ^ p[j]); } } } for (int i = 1; i <= Q; i++) cout << ans[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct pi { int x, y, t; double p; } pp[1005]; double dp[1005]; int cmp(pi a, pi b) { return a.t < b.t; } double get(int a, int b) { return sqrt(pow(pp[a].x - pp[b].x, 2.0) + pow(pp[a].y - pp[b].y, 2.0)); } int main() { int i, j, n; cin >> n; for (i = 1; i <= n; i++) { scanf( %d%d%d%lf , &pp[i].x, &pp[i].y, &pp[i].t, &pp[i].p); } sort(pp + 1, pp + 1 + n, cmp); dp[1] = pp[1].p; for (i = 2; i <= n; i++) { dp[i] = pp[i].p; for (j = 1; j < i; j++) { if (get(j, i) <= pp[i].t - pp[j].t) { dp[i] = max(dp[i], dp[j] + pp[i].p); } } } double s = 0; for (i = 1; i <= n; i++) s = max(s, dp[i]); printf( %.9lf n , s); }
|
#include <bits/stdc++.h> using namespace std; const int t = 1111; bitset<t> a[t], q[t]; int x[t], y[t]; char s[t]; void cl(int l, int r, int u, int d) { int i; for (i = l; i <= r; i++) q[i][u] = q[i][d] = 1; for (i = u; i <= d; i++) q[l][i] = q[r][i] = 1; } int main() { int n, m, i, j, cx, cy, l1, r1, u1, d1, l2, r2, u2, d2, cnt; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) { a[i] = 0; scanf( %s , s); for (j = 0; j < m; j++) a[i][j + 1] = s[j] == # ? 1 : 0; } for (cx = 0, i = 1; i <= n; i++) { for (cnt = 0, j = 1; j <= m && cnt < 3; j++) cnt = a[i][j] ? cnt + 1 : 0; if (cnt == 3) x[cx++] = i; } if (cx > 4) { x[2] = x[cx - 2]; x[3] = x[cx - 1]; cx = 4; } for (cy = 0, i = 1; i <= m; i++) { for (cnt = 0, j = 1; j <= n && cnt < 3; j++) cnt = a[j][i] ? cnt + 1 : 0; if (cnt == 3) y[cy++] = i; } if (cy > 4) { y[2] = y[cy - 2]; y[3] = y[cy - 1]; cy = 4; } for (l1 = 0; l1 < cx; l1++) for (r1 = l1 + 1; r1 < cx; r1++) if (x[r1] - x[l1] > 1) for (u1 = 0; u1 < cy; u1++) for (d1 = u1 + 1; d1 < cy; d1++) if (y[d1] - y[u1] > 1) for (l2 = l1; l2 < cx; l2++) for (r2 = l2 + 1; r2 < cx; r2++) if (x[r2] - x[l2] > 1) for (u2 = 0; u2 < cy; u2++) for (d2 = u2 + 1; d2 < cy; d2++) if (y[d2] - y[u2] > 1) { for (i = 1; i <= n; i++) q[i] = 0; cl(x[l1], x[r1], y[u1], y[d1]); cl(x[l2], x[r2], y[u2], y[d2]); for (i = 1; i <= n && q[i] == a[i]; i++) ; if (i == n + 1) { puts( YES ); printf( %d %d %d %d n%d %d %d %d n , x[l1], y[u1], x[r1], y[d1], x[l2], y[u2], x[r2], y[d2]); return 0; } } puts( NO ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; void solve() { int n, k; cin >> n >> k; vector<int> a(n * k); for (auto &it : a) cin >> it; reverse(a.begin(), a.end()); long long ans = 0; int mid = n / 2, cnt = 0; for (int i = mid; i < (int)a.size() && cnt++ != k; i += mid + 1) { ans += a[i]; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T &x) { x = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) x = x * 10 + (c & 15), c = getchar(); } const int P = 998244353; int n, m; char c[500001]; struct matrix { int n, m, a[3][3]; inline matrix(int n = 0, int m = 0) : n(n), m(m) { memset(a, 0, sizeof(a)); } } s[500001 << 2]; inline matrix operator*(const matrix &a, const matrix &b) { matrix c(a.n, b.m); for (int i = 1; i <= c.n; i++) for (int k = 1; k <= a.m; k++) for (int j = 1; j <= c.m; j++) c.a[i][j] = (c.a[i][j] + (long long)a.a[i][k] * b.a[k][j]) % P; return c; } inline void build(int p, int l, int r) { if (l == r) { s[p] = matrix(2, 2), s[p].a[1][2] = (c[l - 1] == 1 ? 9 - c[l] : 0), s[p].a[2][1] = 1, s[p].a[2][2] = c[l] + 1; return; } int mid = (l + r) >> 1; build(p << 1, l, mid), build(p << 1 | 1, mid + 1, r); s[p] = s[p << 1] * s[p << 1 | 1]; } inline void add(int p, int l, int r, int x) { if (x > r || x < l) return; if (l == r) { s[p].a[1][2] = (c[l - 1] == 1 ? 9 - c[l] : 0), s[p].a[2][1] = 1, s[p].a[2][2] = c[l] + 1; return; } int mid = (l + r) >> 1; if (mid >= x) add(p << 1, l, mid, x); else add(p << 1 | 1, mid + 1, r, x); s[p] = s[p << 1] * s[p << 1 | 1]; } signed main() { read(n), read(m), scanf( %s , c + 1); for (int i = 1; i <= n; i++) c[i] -= 0 ; build(1, 1, n); while (m--) { int x, y; read(x), read(y), c[x] = y, add(1, 1, n, x), add(1, 1, n, x + 1); matrix ans(1, 2); ans.a[1][1] = ans.a[1][2] = 1; ans = ans * s[1]; printf( %d n , ans.a[1][2]); } return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Encoder_To_Position_And_Velocity.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Encoder_To_Position_And_Velocity
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Encoder_To_Position_And_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
encoder_valid,
encoder_counter,
param_zero_offset,
position_valid,
rotor_position,
electrical_position,
rotor_velocity
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input encoder_valid;
input [15:0] encoder_counter; // uint16
input signed [17:0] param_zero_offset; // sfix18_En14
output position_valid;
output signed [17:0] rotor_position; // sfix18_En14
output signed [17:0] electrical_position; // sfix18_En14
output signed [17:0] rotor_velocity; // sfix18_En8
wire signed [17:0] Rotor_To_Electrical_Position_out1; // sfix18_En14
wire signed [17:0] Calculate_Rotor_Velocity_out1; // sfix18_En8
// Quadrature Encoder To Position And Velocity
assign position_valid = encoder_valid;
// <S2>/Encoder_To_Rotor_Position
controllerHdl_Encoder_To_Rotor_Position u_Encoder_To_Rotor_Position (.counter(encoder_counter), // uint16
.param_zero_offset(param_zero_offset), // sfix18_En14
.position(rotor_position) // sfix18_En14
);
// <S2>/Rotor_To_Electrical_Position
controllerHdl_Rotor_To_Electrical_Position u_Rotor_To_Electrical_Position (.R(rotor_position), // sfix18_En14
.E(Rotor_To_Electrical_Position_out1) // sfix18_En14
);
assign electrical_position = Rotor_To_Electrical_Position_out1;
// <S2>/Calculate_Rotor_Velocity
controllerHdl_Calculate_Rotor_Velocity u_Calculate_Rotor_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.valid(encoder_valid),
.position(rotor_position), // sfix18_En14
.rotor_velocity(Calculate_Rotor_Velocity_out1) // sfix18_En8
);
assign rotor_velocity = Calculate_Rotor_Velocity_out1;
endmodule // controllerHdl_Encoder_To_Position_And_Velocity
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5; int p[N + 10], a[N + 10], pos[N + 10]; struct seg { int l, r, min; } t[N * 4 + 10]; int nxt[N + 10][20]; int get(int x, int n) { int ans = x, cnt = 0; while (n) { if (n & 1) ans = nxt[ans][cnt]; if (ans >= 0x7f7f7f7f) break; n >>= 1; cnt++; } return ans; } int n; void build(int p, int l, int r) { t[p].l = l; t[p].r = r; if (l == r) { t[p].min = get(l, n - 1); return; } int mid = (l + r) / 2; build(p * 2, l, mid); build(p * 2 + 1, mid + 1, r); t[p].min = min(t[p * 2].min, t[p * 2 + 1].min); } int query(int p, int l, int r) { if (l <= t[p].l && t[p].r <= r) return t[p].min; int mid = (t[p].l + t[p].r) / 2, ans = 0x7f7f7f7f; if (l <= mid) ans = min(ans, query(p * 2, l, r)); if (r > mid) ans = min(ans, query(p * 2 + 1, l, r)); return ans; } int ans[N + 10]; int main() { int m, q; scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= n; i++) { scanf( %d , &p[i]); pos[p[i]] = i; } for (int i = 1; i <= m; i++) { scanf( %d , &a[i]); a[i] = pos[a[i]]; } memset(pos, 0x7f, sizeof(pos)); for (int i = m; i; i--) { nxt[i][0] = pos[a[i] == n ? 1 : a[i] + 1]; pos[a[i]] = i; } int logn = (int)(log(n) / log(2)) + 1; for (int s = 1; s <= logn; s++) { for (int i = 1; i <= m; i++) { if (i + (1 << s) - 1 > m) { nxt[i][s] = 0x7f7f7f7f; continue; } if (nxt[i][s - 1] > m) { nxt[i][s] = 0x7f7f7f7f; continue; } nxt[i][s] = nxt[nxt[i][s - 1]][s - 1]; } } build(1, 1, m); for (int i = 1; i <= q; i++) { int l, r; scanf( %d%d , &l, &r); int tmp = query(1, l, r); ans[i] = (tmp <= r); } for (int i = 1; i <= q; i++) putchar(48 ^ ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100010; bool operator<(pair<int, int> lhs, pair<int, int> rhs) { return (lhs.first != rhs.first) ? (lhs.first < rhs.first) : (lhs.second < rhs.second); } set<pair<int, int> > inqUp, inqDown, pendUp, pendDown; int N, M, prsis, rci; long long T, Ans[MAXN]; struct User { int id, ar, f, t; }; bool cmp_Useraraz(User lhs, User rhs) { return lhs.ar < rhs.ar; } User u[MAXN], ru[MAXN]; int Where; void Unload() { while ((inqUp.size()) && (inqUp.begin()->first == Where)) { Ans[inqUp.begin()->second] = T; inqUp.erase(inqUp.begin()); rci++; } while (((inqDown.size()) && (--inqDown.end())->first == Where)) { Ans[(--inqDown.end())->second] = T; inqDown.erase(--inqDown.end()); rci++; } } void Request() { while ((prsis != N) && (u[prsis + 1].ar == T)) { prsis++; if (u[prsis].f >= Where) pendUp.insert(make_pair(u[prsis].f, u[prsis].id)); else pendDown.insert(make_pair(u[prsis].f, u[prsis].id)); } } void Load(int id) { if (ru[id].t >= Where) inqUp.insert(make_pair(ru[id].t, id)); else inqDown.insert(make_pair(ru[id].t, id)); } void Load() { while ((pendUp.size()) && (pendUp.begin()->first == Where)) { Load(pendUp.begin()->second); pendUp.erase(pendUp.begin()); } while ((pendDown.size()) && ((--pendDown.end())->first == Where)) { Load((--pendDown.end())->second); pendDown.erase(--pendDown.end()); } } int main() { scanf( %d%d , &N, &M); int i; for (i = 1; i <= N; i++) { scanf( %d%d%d , &u[i].ar, &u[i].f, &u[i].t); u[i].id = i; ru[i] = u[i]; } sort(u + 1, u + N + 1, cmp_Useraraz); inqUp.clear(); inqDown.clear(); pendUp.clear(); pendDown.clear(); Where = 1; T = 0; prsis = rci = 0; while (rci < N) { Unload(); Request(); Load(); int pUp = inqUp.size() + pendUp.size(); int pDown = inqDown.size() + pendDown.size(); int Action = (pUp + pDown) ? ((pUp >= pDown) ? 1 : -1) : 0; int timePass = (prsis == N) ? M : (u[prsis + 1].ar - T); if (Action == 1) { if (pendUp.size()) timePass = min(timePass, pendUp.begin()->first - Where); if (inqUp.size()) timePass = min(timePass, inqUp.begin()->first - Where); } if (Action == -1) { if (pendDown.size()) timePass = min(timePass, Where - (--pendDown.end())->first); if (inqDown.size()) timePass = min(timePass, Where - (--inqDown.end())->first); } T += timePass; Where += timePass * Action; } for (i = 1; i <= N; i++) printf( %I64d n , Ans[i]); }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int INF = (int)1e9 + 7; const long long LINF = (long long)9e18 + 7; const long long P1 = 353251; const long long P2 = 239017; const long long MOD = 1e9 + 7; const long long MOD1 = 1e9 + 7; const long long MOD2 = 1e9 + 9; int n, m; long long ans = 0; pair<long long, long long> a[107]; long long t[107]; const bool is_testing = 0; int main() { srand( D + E + N + I + S + S + O + N + time(NULL)); if (is_testing) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } else { } cin >> n; for (int i = 0; i < n; i++) cin >> a[i].second >> a[i].first; cin >> m; for (int i = 0; i < m; i++) cin >> t[i]; long long sum = t[0]; for (int i = 1; i < m; i++) { t[i] -= sum; sum += t[i]; } t[m] = LINF; sort(a, a + n); int uk = 0; for (int i = 0; i < n; i++) { long long now = a[i].second; while (now) { if (now < t[uk]) { ans += now * a[i].first * (uk + 1); t[uk] -= now; now = 0; } else { now -= t[uk]; ans += t[uk] * a[i].first * (uk + 1); uk++; } } } cout << ans; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_SYMBOL_V
`define SKY130_FD_SC_LP__LSBUFISO0P_SYMBOL_V
/**
* lsbufiso0p: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbufiso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_SYMBOL_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
input enable_in, output reg enable_out );
always @(posedge clock)
if(enable_in)
product <= #1 x*y;
else
product <= #1 31'd0;
always @(posedge clock)
enable_out <= #1 enable_in;
endmodule // mult
|
#include <bits/stdc++.h> using namespace std; int n, c, d; const int maxn = 3456789; const long double PI = acos((long double)(-1.0)); const long double eps = 1e-18; long double ang[maxn]; int main() { while (cin >> n >> c >> d) { for (int i = 0; i < (n); i++) { int r, w; scanf( %d%d , &r, &w); long double x = r - c; long double y = w - d; ang[i] = atan2(y, x); } sort(ang, ang + n); for (int i = 0; i < (n + 3); i++) ang[i + n] = ang[i] + 2 * PI; long long ans = 1LL * n * (n - 1) * (n - 2) / 6; int j = 0, lo = 0, hi = 0; for (int i = 0; i < (n); i++) { while (ang[j + 1] - ang[i] < PI + eps) ++j; while (ang[lo] - ang[i] < PI - eps) ++lo; while (ang[hi + 1] - ang[i] < PI + eps) ++hi; ans -= 1LL * (j - i) * (j - i - 1) / 2; ans += 1LL * (hi - lo) * (hi - lo + 1) / 2; } cout << ans << endl; } return 0; }
|
`begin_keywords "1364-2005"
`timescale 1ns / 1ns
module gentest;
reg [7:0] a=0, b=0;
wire co;
wire [7:0] result;
adder work(a, b, 1'b0, result, co);
integer cc;
initial begin
for (cc=0; cc<10; cc=cc+1) begin
a=a+1;
#10;
$display("%d %d %d", a, b, result);
b=result;
end
if (b==55) $display("PASSED");
else $display("FAIL");
end
endmodule
module adder(a, b, ci, out, co);
parameter SIZE=8;
input [SIZE-1:0] a;
input [SIZE-1:0] b;
input ci;
output [SIZE-1:0] out;
output co;
wire [SIZE:0] c;
assign c[0] = ci;
assign co = c[SIZE];
`ifdef NOGENERATE
add1 bit0(a[0], b[0], c[0], out[0], c[0+1]);
add1 bit1(a[1], b[1], c[1], out[1], c[1+1]);
add1 bit2(a[2], b[2], c[2], out[2], c[2+1]);
add1 bit3(a[3], b[3], c[3], out[3], c[3+1]);
add1 bit4(a[4], b[4], c[4], out[4], c[4+1]);
add1 bit5(a[5], b[5], c[5], out[5], c[5+1]);
add1 bit6(a[6], b[6], c[6], out[6], c[6+1]);
add1 bit7(a[7], b[7], c[7], out[7], c[7+1]);
`else
genvar i;
generate for(i=0; i<SIZE; i=i+1) begin:addbit
add1 bit(a[i], b[i], c[i], out[i], c[i+1]);
end endgenerate
`endif
endmodule
module add1(a, b, ci, sum, co);
input a, b, ci;
output sum, co;
assign {co,sum} = a + b + ci;
endmodule
`end_keywords
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 50, inf = 1e9; int n, m, be[N], f[N], cnt, sub[N], SUB[N], vfa[N], q[N * 2], l, r; bool vis[N], tp[N]; vector<int> e[N], v[N], vv; void cmax(int &x, int y) { y > x ? x = y : 0; } void dfs1(int x) { vis[x] = 1; if (f[x]) e[x].erase(find(e[x].begin(), e[x].end(), f[x])); for (int i = 0, y; i < e[x].size(); i++) { if (!vis[y = e[x][i]]) f[y] = x, dfs1(y); else if (!be[y]) { be[y] = ++cnt; tp[y] = 1; v[cnt].push_back(y); for (int z = x; z != y; z = f[z]) be[z] = cnt, v[cnt].push_back(z); } } if (!be[x]) be[x] = ++cnt, tp[x] = 1, v[cnt].push_back(x); } void calc1(int x) { int id = be[x], sz = v[id].size(); for (int i = 0; i < sz; i++) { int mx0 = 0, mx1 = -inf; int z = v[id][i]; for (int j = 0, y; j < e[z].size(); j++) if (be[y = e[z][j]] != id) { int val = SUB[y] + 1; if (val > mx0) mx1 = mx0, mx0 = val; else if (val > mx1) mx1 = val; } sub[z] = mx0; cmax(SUB[x], mx0 + min(i, sz - i)); for (int j = 0, y; j < e[z].size(); j++) if (be[y = e[z][j]] != id) cmax(vfa[y], SUB[y] + 1 != mx0 ? mx0 + 1 : mx1 + 1); } } void dfs2(int x) { vis[x] = 1; for (int i = 0, y; i < e[x].size(); i++) if (!vis[y = e[x][i]]) dfs2(y); if (tp[x]) calc1(x); } void calc2(int x) { cmax(sub[x], vfa[x]); vv.clear(); int id = be[x], sz = v[id].size(); for (int i = 0; i < 2; i++) for (int j = 0; j < v[id].size(); j++) vv.push_back(v[id][j]); l = 1; r = 0; for (int i = 0; i < vv.size(); i++) { if (i - q[l] > sz / 2) l++; if (l <= r) cmax(vfa[vv[i]], i - q[l] + sub[vv[q[l]]]); while (l <= r && sub[vv[q[r]]] - q[r] < sub[vv[i]] - i) r--; q[++r] = i; } l = 1; r = 0; for (int i = vv.size() - 1; ~i; i--) { if (q[l] - i > sz / 2) l++; if (l <= r) cmax(vfa[vv[i]], q[l] - i + sub[vv[q[l]]]); while (l <= r && sub[vv[q[r]]] + q[r] < sub[vv[i]] + i) r--; q[++r] = i; } for (int i = 0; i < v[id].size(); i++) for (int z = v[id][i], j = 0, y; j < e[z].size(); j++) if (be[y = e[z][j]] != id) cmax(vfa[y], vfa[z] + 1); } void dfs3(int x) { vis[x] = 1; if (tp[x]) calc2(x); for (int i = 0, y; i < e[x].size(); i++) if (!vis[y = e[x][i]]) dfs3(y); } int main() { scanf( %d%d , &n, &m); for (int i = 1, x, y; i <= m; i++) scanf( %d%d , &x, &y), e[x].push_back(y), e[y].push_back(x); dfs1(1); memset(vis, 0, sizeof(vis)); dfs2(1); memset(vis, 0, sizeof(vis)); dfs3(1); for (int i = 1; i <= n; i++) printf( %d , max(sub[i], vfa[i])); return 0; }
|
// file: SystemClockUnit_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module SystemClockUnit_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
SystemClockUnit_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
module step_ex_st(clk, rst_, ena_, rdy_,
mem_we_, abus, dbus,
r0_dout, r1_dout);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_we_;
output[7:0] abus;
output[7:0] dbus;
input[7:0] r0_dout, r1_dout;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg mem_we_en;
assign mem_we_ = mem_we_en ? 1'b0 : 1'bZ;
reg bus_en;
assign abus = bus_en ? r1_dout : 8'bZ;
assign dbus = bus_en ? r0_dout : 8'bZ;
reg[1:0] state;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
bus_en <= 0;
state <= 0;
end else begin
/*
State 0: ena_=0 state=00
rdy_en=0 bus_en=1 state=01
State 1: ena_=1 state=01
rdy_en=0 bus_en=1 state=10
State 2: ena_=1 state=10
rdy_en=1 bus_en=0 state=00
State 3: ena_=1 state=00
rdy_en=0 bus_en=0 state=00
*/
rdy_en <= state[1];
bus_en <= state[0] | ~ena_;
state <= {state[0], ~ena_};
end
always @(negedge rst_ or negedge clk)
if(!rst_)
mem_we_en <= 0;
else
/*
State 0.5: state=01
mem_we_en=1
State 1.5: state=10
mem_we_en=0
State 2.5: state=00
mem_we_en=0
*/
mem_we_en <= state[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long n, i; long long a[102]; long long dp[102][102][2]; signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { cin >> n; string s[2]; cin >> s[0] >> s[1]; long long r, c; r = 0; for (i = 0; i < n; ++i) { if (s[r % 2][i] >= 3 ) { if (s[(r + 1) % 2][i] < 3 ) { break; } else { r = (r + 1) % 2; } } } if (i == n && r == 1) { puts( yes n ); } else puts( no n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T fetch() { T ret; cin >> ret; return ret; } template <typename T> inline vector<T> fetch_vec(long long sz) { vector<T> ret(sz); for (auto& it : ret) cin >> it; return ret; } template <typename T> inline void makeUnique(vector<T>& v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); } template <typename T> inline T max_(T a, T b) { if (a > b) return a; return b; } template <typename T> inline T min_(T a, T b) { if (a < b) return a; return b; } void file() {} void Match() {} const long long N = 2e5 + 5; long long son[N * 32][2], pos = 0, cnt[N * 32]; long long dfs(long long p, long long digit) { long long p0 = son[p][0]; long long p1 = son[p][1]; if (digit == 0) return max(cnt[p0], cnt[p1]) + (cnt[p0] & cnt[p1]); long long num0 = 0, num1 = 0; if (p0) num0 = dfs(p0, digit - 1); if (p1) num1 = dfs(p1, digit - 1); return max(num0, num1) + (num0 && num1); } signed main() { ios::sync_with_stdio(false); cin.tie(0); ; file(); long long n; cin >> n; for (long long i = 0; i < n; i++) { long long num, p = 0; cin >> num; for (long long i = 30; i >= 0; i--) { long long& t = son[p][num >> i & 1]; if (!t) t = ++pos; cnt[t]++; p = t; } } cout << n - dfs(0, 30) << n ; Match(); return 0; }
|
module cross_bar_tb;
reg rst, clk;
reg [0:7] wr_en;
reg [63:0] d;
wire [0:7] full;
wire [0:7] valid;
wire [63:0] q;
reg [0:7] stall;
wire [0:7] almost_full;
cross_bar #(8, 8)dut(rst, clk, wr_en, d, full, valid, q, stall, almost_full);
wire [7:0] internal_q [0:7];
initial begin
clk = 0;
forever #5 clk = ~clk;
end
integer i, j, tmp;
integer i2;
initial begin
rst = 1;
wr_en = 0;
d = 0;
stall = 0;
#31 rst = 0;
#10 for(i = 0; i < 1; i = i + 1) begin
wr_en = 0;
d = d + 1;
for(j = 0; j < 1; j = j + 1) begin
if(!full[j])
wr_en[j] = 1;
end
#10 ;
end
wr_en = 0;
d = 0;
stall = 0;
#200 $finish;
end
always @(posedge clk) begin
for(i2 = 0; i2 < 8; i2 = i2 + 1) begin
if(valid[i2])
$display("valid: port:%d, time:%d, data:%b", i2, $time, q);
end
end
endmodule
|
// Computer_System_VGA_Subsystem_VGA_PLL.v
// This file was auto-generated from altera_up_avalon_video_pll_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_VGA_Subsystem_VGA_PLL (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire vga_clk_clk, // vga_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire video_pll_locked_export; // video_pll:locked -> reset_from_locked:locked
Computer_System_VGA_Subsystem_VGA_PLL_video_pll video_pll (
.refclk (ref_clk_clk), // refclk.clk
.rst (ref_reset_reset), // reset.reset
.outclk_0 (), // outclk0.clk
.outclk_1 (vga_clk_clk), // outclk1.clk
.outclk_2 (), // outclk2.clk
.locked (video_pll_locked_export) // locked.export
);
altera_up_avalon_reset_from_locked_signal reset_from_locked (
.reset (reset_source_reset), // reset_source.reset
.locked (video_pll_locked_export) // locked.export
);
endmodule
|
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
11/08/2011
fixed the wb_ack to be 0 when nothing is selected
*/
/*
Thanks Rudolf Usselmann yours was a better implementation than mine
Copyright (C) 2000-2002
Rudolf Usselmann
www.asics.ws
*/
`timescale 1ns/1ps
module wishbone_interconnect (
clk,
rst,
i_m_we,
i_m_cyc,
i_m_sel,
i_m_stb,
o_m_ack,
i_m_dat,
o_m_dat,
i_m_adr,
o_m_int,
//virtual slave master 0
o_s0_we,
o_s0_cyc,
o_s0_sel,
o_s0_stb,
i_s0_ack,
o_s0_dat,
i_s0_dat,
o_s0_adr,
i_s0_int,
//virtual slave master 0
o_s1_we,
o_s1_cyc,
o_s1_sel,
o_s1_stb,
i_s1_ack,
o_s1_dat,
i_s1_dat,
o_s1_adr,
i_s1_int
);
parameter ADDR_0 = 8'h00;
parameter ADDR_1 = 8'h01;
parameter ADDR_FF = 8'hFF;
//state
//control signals
input clk;
input rst;
//wishbone slave signals
input i_m_we;
input i_m_stb;
input i_m_cyc;
input [3:0] i_m_sel;
input [31:0] i_m_adr;
input [31:0] i_m_dat;
output reg [31:0] o_m_dat = 32'h0;
output reg o_m_ack = 1'h0;
output o_m_int;
output o_s0_we;
output o_s0_stb;
output o_s0_cyc;
output [3:0] o_s0_sel;
output [31:0] o_s0_adr;
output [31:0] o_s0_dat;
input [31:0] i_s0_dat;
input i_s0_ack;
input i_s0_int;
output o_s1_we;
output o_s1_stb;
output o_s1_cyc;
output [3:0] o_s1_sel;
output [31:0] o_s1_adr;
output [31:0] o_s1_dat;
input [31:0] i_s1_dat;
input i_s1_ack;
input i_s1_int;
//this should be parameterized
wire [7:0]slave_select;
assign slave_select = i_m_adr[31:24];
wire [31:0] interrupts;
/*
initial begin
$monitor("%t, int: %h, i_s0_int: %h, s1_int: %h", $time, interrupts, s0_int, s1_int);
$monitor ("%t adr: %h, stb: %h, ack: %h", $time, i_m_adr, i_m_stb, o_m_ack);
end
*/
//data
always @ (slave_select or i_s0_dat or i_s1_dat or interrupts) begin
case (slave_select)
ADDR_0: begin
o_m_dat <= i_s0_dat;
end
ADDR_1: begin
o_m_dat <= i_s1_dat;
end
default: begin
//$display("WBI: interrupt address selected");
o_m_dat <= interrupts;
end
endcase
end
//ack
always @ (slave_select or i_s0_ack or i_s1_ack) begin
case (slave_select)
ADDR_0: begin
o_m_ack <= i_s0_ack;
end
ADDR_1: begin
o_m_ack <= i_s1_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int
//set up the interrupts flags
assign interrupts[0] = i_s0_int;
assign interrupts[1] = i_s1_int;
//set all other interrupts to zero
assign interrupts[31:2] = 0;
assign o_m_int = (interrupts != 0);
assign o_s0_we = (slave_select == ADDR_0) ? i_m_we: 0;
assign o_s0_stb = (slave_select == ADDR_0) ? i_m_stb: 0;
assign o_s0_sel = (slave_select == ADDR_0) ? i_m_sel: 0;
assign o_s0_cyc = (slave_select == ADDR_0) ? i_m_cyc: 0;
assign o_s0_adr = (slave_select == ADDR_0) ? {8'h0 , i_m_adr[23:0]}: 0;
assign o_s0_dat = (slave_select == ADDR_0) ? i_m_dat: 0;
assign o_s1_we = (slave_select == ADDR_1) ? i_m_we: 0;
assign o_s1_stb = (slave_select == ADDR_1) ? i_m_stb: 0;
assign o_s1_sel = (slave_select == ADDR_1) ? i_m_sel: 0;
assign o_s1_cyc = (slave_select == ADDR_1) ? i_m_cyc: 0;
assign o_s1_adr = (slave_select == ADDR_1) ? {8'h0 , i_m_adr[23:0]}: 0;
assign o_s1_dat = (slave_select == ADDR_1) ? i_m_dat: 0;
endmodule
|
module InBuff #(parameter WIDTH = 16)(
input clk,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out,
input read,
input clkdiv,
output reg outclk,
output toread);
reg [WIDTH-1:0] inbuf [20:0];
reg [6:0] i;
reg [15:0] counter = 0;
reg oldread = 0;
reg [6:0] bufpointer = 0;
assign toread = (bufpointer > 0);
always @(posedge clk) begin
if (counter > clkdiv) begin//@TODO: external clk
outclk <= !outclk;
counter <= 0;
if (in != 0) begin
for(i=1;i<21;i=i+1) begin//probably very slow //WHAT THE FUCK-@TODO: implement cyclic buffer
inbuf[i] <= inbuf[i-1];
end
inbuf[0] <= in;
bufpointer <= bufpointer + 1;
end
end
if (!oldread) begin
if (read) begin
if(bufpointer > 0) begin
out <= inbuf[bufpointer - 1];
bufpointer <= bufpointer - 1;
oldread <= 1;
end
end
end
if (!read) begin
oldread <= 0;
end
end
endmodule
module OutBuff #(parameter WIDTH = 13)(
input clk,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out,
input writedone,
input clkdiv,
output reg outclk,
output towrite);
reg [6:0] i;
reg [WIDTH-1:0] outbuf [20:0];
reg [15:0] counter = 0;
reg oldwrite = 0;
reg [6:0] bufpointer = 0;
assign towrite = (bufpointer < 8'd19);
always @(posedge clk) begin
if (counter > clkdiv) begin
outclk <= !outclk;
counter <= 0;
if (bufpointer > 0) begin
out <= outbuf[bufpointer - 1];
bufpointer <= bufpointer - 1;
end
end
if (!oldwrite) begin
if (writedone) begin
if(bufpointer > 0) begin
for(i=1;i<21;i=i+1) begin//probably very slow
outbuf[i] <= outbuf[i-1];
end
outbuf[0] <= in;
bufpointer <= bufpointer + 1;
oldwrite <= 1;
end
end
end
if (!writedone) begin
oldwrite <= 0;
end
end
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// Depth 1 FIFO
// Allows simultaneous ENQ and DEQ (at the expense of potentially
// causing combinational loops).
module FIFOL10(CLK, RST, ENQ, FULL_N, DEQ, EMPTY_N, CLR);
input CLK;
input RST;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
reg empty_reg;
assign FULL_N = !empty_reg || DEQ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFOL10: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && ! DEQ)
begin
enqerror = 1 ;
$display( "Warning: FIFOL10: %m -- Enqueuing to a full fifo" ) ;
end
end
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 777; vector<int> G[maxn]; map<int, int> savesiz[maxn]; int siz[maxn]; vector<int> ans; int n; void dfs(int s, int fa) { siz[s] = 1; int cnt = 0; for (int d : G[s]) { if (d == fa) continue; dfs(d, s); savesiz[s][siz[d]]++; cnt++; siz[s] += siz[d]; } if (n - siz[s] > 0) { savesiz[s][n - siz[s]]++; cnt++; } if (savesiz[s].size() == 1 && cnt >= 2) ans.push_back(s); } vector<int> aans; map<int, int> have[maxn]; void func(int s) { int nowsiz = 1; int nowid = G[s][0]; int fa = s; while (G[nowid].size() == 2) { nowsiz++; if (G[nowid][0] == fa) { fa = nowid; nowid = G[nowid][1]; } else { fa = nowid; nowid = G[nowid][0]; } } if (have[nowid].count(nowsiz)) return; if (have[nowid].size() >= 2) return; have[nowid][nowsiz] = 1; if ((savesiz[nowid][nowsiz] == 1 && savesiz[nowid].size() == 2) || savesiz[nowid].size() == 1) { aans.push_back(s); } } set<int> se[maxn]; int vis[maxn]; bool ck(int s) { for (int i = 0; i <= n; i++) { se[i].clear(); vis[i] = 0; } queue<pair<int, int> > q; vis[s] = 1; q.push(make_pair(s, 0)); while (!q.empty()) { int nowid = q.front().first; int nowdis = q.front().second; q.pop(); se[nowdis].insert(G[nowid].size()); if (se[nowdis].size() >= 2) return false; for (int d : G[nowid]) { if (vis[d]) continue; vis[d] = 1; q.push(make_pair(d, nowdis + 1)); } } return true; } void solve() { scanf( %d , &n); if (n == 1) { cout << 1 << endl; return; } for (int i = 1; i < n; i++) { int a, b; scanf( %d %d , &a, &b); G[a].push_back(b); G[b].push_back(a); } dfs(1, 1); for (int iid : ans) { if (ck(iid)) { cout << iid << endl; return; } } for (int i = 1; i <= n; i++) { if (G[i].size() == 1) { func(i); } } for (int iid : aans) { if (ck(iid)) { cout << iid << endl; return; } } cout << -1 << endl; } signed main() { solve(); }
|
#include <bits/stdc++.h> using namespace std; inline long long max2(long long a, long long int b) { return (a) > (b) ? (a) : (b); } inline long long max3(long long a, long long b, long long c) { return (a) > (b) ? ((a) > (c) ? (a) : (c)) : ((b) > (c) ? (b) : (c)); } inline long long min2(long long a, long long b) { return (a) < (b) ? (a) : (b); } inline long long min3(long long a, long long b, long long c) { return (a) < (b) ? ((a) < (c) ? (a) : (c)) : ((b) < (c) ? (b) : (c)); } using namespace std; const long long modu = 998244353; long long dr8[] = {0, 0, 1, -1, 1, 1, -1, -1}; long long dc8[] = {1, -1, 0, 0, -1, 1, -1, 1}; long long dr4[] = {0, 1, -1, 0}; long long dc4[] = {1, 0, 0, -1}; inline void deb_vi(vector<long long> a) { for (long long i = 0; i < a.size(); i++) cout << a[i] << ; } inline void deb_vll(vector<long long> a) { for (long long i = 0; i < a.size(); i++) cout << a[i] << ; } inline bool is_palindrome(const string& s) { return std::equal(s.begin(), s.end(), s.rbegin()); } using namespace std::chrono; long long power(long long a, long long b) { long long result = 1; while (b) { if (b & 1) result = result * a % modu; a = (a * a) % modu; b /= 2; result %= modu; } return result; } long long fun1(string s) { long long ans = 0; long long l = s.length() - 1; long long exp = 0; for (long long i = l; i >= 0; i--) { ans = (s[i] - 0 ) % modu * power(10, exp) + ans; ans %= modu; exp += 2; } return ans % modu; } long long fun2(string s) { long long ans = 0; long long l = s.length() - 1; long long exp = 1; for (long long i = l; i >= 0; i--) { ans = (s[i] - 0 ) % modu * power(10, exp) + ans; ans %= modu; exp += 2; } return ans % modu; } int32_t main() { auto start = high_resolution_clock::now(); { long long n; cin >> n; string a[n]; long long ans = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; long long t1 = fun1(a[i]) * n; t1 %= modu; long long t2 = fun2(a[i]) * n; t2 %= modu; ans += (t1 + t2); ans %= modu; } cout << (ans + modu) % modu; } auto stop = high_resolution_clock::now(); auto duration = duration_cast<microseconds>(stop - start); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int T, cas = 0; scanf( %d , &T); while (cas++ < T) { int sum = 0, s[251], maxi = 0; for (int i = 1; i <= 250; i++) { scanf( %d , s + i); sum += s[i]; maxi = max(s[i], maxi); } double aver = sum / 250.0, fang = 0; for (int i = 1; i <= 250; i++) { fang += (s[i] - aver) * (s[i] - aver); } fang /= 250; if (fang / aver > 2) { printf( %.0f n , maxi * 1.04 / 2); } else printf( %.0f n , aver); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, piles[100000], q; cin >> n; cin >> q; piles[0] = q; for (int i = int(1); i < int(n); i++) { cin >> q; piles[i] = piles[i - 1] + q; } cin >> m; for (int i = int(0); i < int(m); i++) { cin >> q; int ans = upper_bound(piles, piles + n, q) - piles; if (ans > 0 && piles[ans - 1] == q) ans--; ans++; cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; if (n % k == 0) cout << n + k << endl; else cout << n + (k - n % k); return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { long long n; cin >> n; long long p[n + 1]; p[1] = -1; for (long long i = 2; i <= n; i++) cin >> p[i]; vector<long long> ans; long long x = n; while (p[x] != -1) { ans.push_back(p[x]); x = p[x]; } reverse(ans.begin(), ans.end()); for (long long i : ans) cout << i << ; cout << n << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2ai (
VPWR,
VGND,
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire nand1_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__EDFXBP_PP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NAND4BB_FUNCTIONAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O21BA_PP_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, i, j, k, l, t; cin >> t; while (t--) { cin >> n; vector<int> a(n); for (i = 0; i < n; i++) { cin >> a[i]; } k = 1; long long total = 0; for (i = 0; i < n; i++) { if (k % 2 != 0) { total += a[i]; if (a[i + 1] == 0) { while (i + 1 < n && a[i + 1] == 0) { i++; } } } else { if (a[i + 1] == 1) i++; } k++; } cout << total << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, l[3], k[3], z = 0, j; cin >> n >> m; char a[n][m]; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == * ) { k[z] = i + 1; l[z] = j + 1; z++; } } } if (k[0] == k[1]) { cout << k[2] << ; } else if (k[1] == k[2]) { cout << k[0] << ; } if (k[0] == k[2]) cout << k[1] << ; if (l[0] == l[1]) { cout << l[2] << ; } if (l[1] == l[2]) { cout << l[0] << ; } if (l[0] == l[2]) cout << l[1]; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, h, a, ans = 0; cin >> n >> h; for (int i = 0; i < n; i++) { cin >> a; int add = 1; if (a > h) add++; ans += add; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; long long mul(long long a, long long b) { return (a * b) % MOD; } long long bin_pow(long long a, long long p) { if (p == 0) return 1; long long ans = bin_pow(mul(a, a), p / 2); if (p % 2) ans = mul(ans, a); return ans; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m, a; cin >> n >> m >> a; vector<long long> b(m + 1); b[0] = 0; for (long long i = 0; i < m; i++) cin >> b[i + 1]; long long ans = 1; for (long long i = 0; i < (long long)(b).size() - 1; i++) { long long seg = b[i + 1] - b[i]; long long p = bin_pow(a, seg); long long p1 = (p * (p - 1) / 2) % MOD; long long delta = (p1 + p) % MOD; ans = mul(ans, delta); } long long ost = n - b.back() * 2; ans = mul(ans, bin_pow(a, ost)); cout << ans; return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file msu_databuf.v when simulating
// the core, msu_databuf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module msu_databuf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [7 : 0] dina;
input clkb;
input [13 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
/**
* lpflow_inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire or0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__OR2B_BEHAVIORAL_PP_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2B_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long double mm = 0; int xs[4]; int ys[4]; int mxs[4]; int mys[4]; int used[1001][1001]; long double di(int x1, int y1, int x2, int y2) { return sqrt(abs((long double)x1 - (long double)x2) * abs((long double)x1 - (long double)x2) + abs((long double)y1 - (long double)y2) * abs((long double)y1 - (long double)y2)); } int n, m; void dfs(int x, int y, int d, long double ma) { if (x < 0 || y < 0) return; if (x > n || y > m) return; if (used[x][y]) return; used[x][y] = 1; xs[d] = x; ys[d] = y; if (d == 3) { if (ma > mm) { mm = ma; for (int i = 0; i < 4; i++) { mxs[i] = xs[i]; mys[i] = ys[i]; } } used[x][y] = 0; return; } for (int i = 0; i < 4; i++) { for (int ii = 0; ii < 4; ii++) { dfs(i, ii, d + 1, ma + di(x, y, i, ii)); } } for (int i = 0; i < 4; i++) { for (int ii = 0; ii < 4; ii++) { dfs(n - i, m - ii, d + 1, ma + di(x, y, n - i, m - ii)); } } used[x][y] = 0; } int main() { cin >> n >> m; for (int i = 0; i < 4; i++) { for (int ii = 0; ii < 4; ii++) { dfs(i, ii, 0, 0); } } for (int i = 0; i < 4; i++) { cout << mxs[i] << << mys[i] << endl; } }
|
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; using ll = long long; using ld = long double; constexpr int nax = 1000 * 1000 + 105; constexpr int infty = 1000 * 1000 * 1000 + 5; constexpr int mod = 1000 * 1000 * 1000 + 7; int main() { int n; scanf( %d , &n); set<int> s; for (int i = 0; i < n; i++) { int a; scanf( %d , &a); s.insert(a); } printf( %d n , n + 1 - (int)s.size()); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mxn = 1e6 + 3; struct node { int v, i, j, id; } a[mxn]; int n, m, r[mxn], c[mxn], f[mxn], v[mxn], o[mxn]; int cmp(node a, node b) { return a.v < b.v; } int fffa(int x) { return f[x] == x ? x : f[x] = fffa(f[x]); } int main() { scanf( %d%d , &n, &m); for (int(i) = (int)(1); (i) <= (int)(n); ++(i)) for (int(j) = (int)(1); (j) <= (int)(m); ++(j)) { int id = (i - 1) * m + j; scanf( %d , &o[id]); a[id].v = o[id]; a[id].i = i; a[id].j = j; a[id].id = f[id] = id; } sort(a + 1, a + 1 + n * m, cmp); for (int(i) = (int)(1); (i) <= (int)(n * m); ++(i)) { int fi = fffa(r[a[i].i]); int fj = fffa(c[a[i].j]); v[a[i].id] = max(v[fi] + (a[i].v > o[fi]), v[fj] + (a[i].v > o[fj])); int p = fffa(a[i].id); if (a[i].v == o[fi]) f[fi] = p; if (a[i].v == o[fj]) f[fj] = p; r[a[i].i] = c[a[i].j] = p; } for (int(i) = (int)(1); (i) <= (int)(n); ++(i)) for (int(j) = (int)(1); (j) <= (int)(m); ++(j)) printf( %d%c , v[fffa((i - 1) * m + j)], n [j == m]); return 0; }
|
//======================================================================
//
// fpga_entropy.v
// --------------
// Top level wrapper for the fpga entropy generator core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fpga_entropy(
input wire clk,
input wire reset_n,
// API interface.
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
// Debug output.
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// API addresses.
parameter ADDR_CORE_NAME0 = 8'h00;
parameter ADDR_CORE_NAME1 = 8'h01;
parameter ADDR_CORE_VERSION = 8'h02;
parameter ADDR_UPDATE = 8'h10;
parameter ADDR_OPA = 8'h11;
parameter ADDR_RND_READ = 8'h20;
// Core ID constants.
parameter CORE_NAME0 = 32'h66706761; // "fpga"
parameter CORE_NAME1 = 32'h5f656e74; // "_ent"
parameter CORE_VERSION = 32'h302e3031; // "0.01"
// Default value assigned to operand A.
// Operand B will be the inverse value of operand A.
parameter DEFAULT_OPA = 32'haaaaaaaa;
// Delay in cycles between updating the debug port with
// a new random value sampled from the rng core port.
// Corresponds to about 1/20s with a clock @ 50 MHz.
parameter DELAY_MAX = 32'h002625a0;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] opa_reg;
reg [31 : 0] opb_reg;
reg [31 : 0] opa_new;
reg opa_we;
reg update_reg;
reg update_new;
reg update_we;
reg [31 : 0] delay_ctr_reg;
reg [31 : 0] delay_ctr_new;
reg [7 : 0] debug_reg;
reg debug_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg tmp_error;
reg [31 : 0] tmp_read_data;
wire [31 : 0] core_rnd;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
assign debug = debug_reg;
//----------------------------------------------------------------
// core
//
// Instantiation of the uart core.
//----------------------------------------------------------------
fpga_entropy_core core(
.clk(clk),
.reset_n(reset_n),
.opa(opa_reg),
.opb(opb_reg),
.update(update_reg),
.rnd(core_rnd)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
opa_reg <= DEFAULT_OPA;
opb_reg <= ~DEFAULT_OPA;
update_reg <= 1;
debug_reg <= 8'h00;
end
else
begin
delay_ctr_reg <= delay_ctr_new;
if (opa_we)
begin
opa_reg <= opa_new;
opb_reg <= ~opa_new;
end
if (update_we)
begin
update_reg <= update_new;
end
if (debug_we)
begin
debug_reg <= core_rnd[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// delay_ctr
//
// Simple counter that counts to DELAY_MAC. Used to slow down
// the debug port updates to human speeds.
//----------------------------------------------------------------
always @*
begin : delay_ctr
debug_we = 0;
if (delay_ctr_reg == DELAY_MAX)
begin
delay_ctr_new = 32'h00000000;
debug_we = 1;
end
else
begin
delay_ctr_new = delay_ctr_reg + 1'b1;
end
end // delay_ctr
//----------------------------------------------------------------
// api
//
// The core API that allows an internal host to control the
// core functionality.
//----------------------------------------------------------------
always @*
begin: api
// Default assignments.
opa_new = 32'h00000000;
opa_we = 0;
update_new = 0;
update_we = 0;
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
// Write operations.
case (address)
ADDR_UPDATE:
begin
update_new = write_data[0];
update_we = 1;
end
ADDR_OPA:
begin
opa_new = write_data;
opa_we = 1;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
else
begin
// Read operations.
case (address)
ADDR_CORE_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_CORE_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_CORE_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
ADDR_UPDATE:
begin
tmp_read_data = update_reg;
end
ADDR_OPA:
begin
tmp_read_data = opa_reg;
end
ADDR_RND_READ:
begin
tmp_read_data = core_rnd;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end
endmodule // fpga_entropy
//======================================================================
// EOF fpga_entropy.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; const int N = 3 * 1e5 + 5; int main() { int t; cin >> t; double a[1005], b[1005]; for (int i = 1; i <= t; ++i) { int d; cin >> d; if (d < 4 && d > 0) { a[i] = -1; b[i] = -1; continue; } double discr = sqrt((d * d - 4 * d) * 1.0); a[i] = (d + discr) / 2; b[i] = (d - discr) / 2; } for (int i = 1; i <= t; ++i) { if (a[i] == -1) cout << N n ; else { cout << Y ; printf( %.9f %.9f n , a[i], b[i]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int n, i, j, k, c, v, l = 1, r = 1, maxm = 0, minm; cin >> n; int A[n]; string s; cin >> s; for (i = 0; i < n; i++) A[i] = 0; for (i = 0; i < n; i++) { for (j = i; j < n; j++) { swap(s[i], s[j]); v = 0; c = 0; for (k = 0; k < n; k++) { if (s[k] == ( ) v++; else v--; A[k] = v; } if (v == 0) { minm = 0; for (k = 0; k < n; k++) { if (A[k] < minm) { minm = A[k]; c = 1; } else if (A[k] == minm) c++; } if (c > maxm) { maxm = c; l = i + 1; r = j + 1; } } swap(s[i], s[j]); } } cout << maxm << endl; cout << l << << r << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; int sum = accumulate(a.begin(), a.end(), 0); vector<vector<int>> dp(n + 1, vector<int>(2, -1)); function<int(int, int)> solve = [&](int idx, int cur) { if (idx == n) return 0; if (dp[idx][cur] != -1) return dp[idx][cur]; int res = 0; if (cur == 0) res = max(a[idx] + solve(idx + 1, !cur), solve(idx + 1, cur)); else res = min(solve(idx + 1, !cur), a[idx] + solve(idx + 1, cur)); return dp[idx][cur] = res; }; int ans = solve(0, 0); cout << sum - ans << << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 4e5 + 47, mod = 1e9 + 7, inf = 1e9 + 7; long long n, m; vector<long long> val; void read() { cin >> n; val.resize(n); for (long long i = 0; i < n; ++i) cin >> val[i]; } vector<long long> fenw(MAXN, 0); void update(long long pos) { for (; pos < MAXN; pos = (pos | (pos + 1))) fenw[pos]++; } long long get_sum(long long l) { long long res = 0; for (; l >= 0; l = (l & (l + 1)) - 1) res += fenw[l]; return res; } bool comp(pair<long long, long long> &a, pair<long long, long long> &b) { if (a.first < b.first) return false; if (a.first > b.first) return true; return a.second <= b.second; } void solve() { cin >> m; vector<vector<pair<long long, long long> > > quer(n + 1); for (long long i = 0; i < m; ++i) { long long x, y; cin >> x >> y; quer[x - 1].push_back({y, i}); } vector<pair<long long, long long> > suck(n); for (long long i = 0; i < n; ++i) suck[i] = {val[i], i}; sort(suck.begin(), suck.end(), comp); vector<long long> ans(m, 0); for (long long len = 0; len < n; ++len) { update(suck[len].second); for (pair<long long, long long> p : quer[len]) { long long k = p.first; long long l = 0, r = n; while (l < r) { long long mid = l + (r - l) / 2; if (get_sum(mid) < k) l = mid + 1; else r = mid; } ans[p.second] = val[l]; } } for (long long i = 0; i < m; ++i) cout << ans[i] << ; cout << endl; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long t = 1; while (t--) { read(); solve(); } }
|
// An asynchronous generic memory wrapper around a synchronous memory
module async_mem (/*AUTOARG*/
// Outputs
ack, dout,
// Inputs
req, addr, din, we
);
parameter ACCESS_TIME = 10;
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter filename = "code.hex";
localparam COL_WIDTH = 8;
localparam NB_COL = 4;
localparam CLOCK_PULSE_WIDTH = 5;
input req;
output ack;
input [ADDR_WIDTH-1:0] addr; // To U_SSRAM of bytewrite_ram_32bits.v
input [NB_COL*COL_WIDTH-1:0] din; // To U_SSRAM of bytewrite_ram_32bits.v
input [NB_COL-1:0] we; // To U_SSRAM of bytewrite_ram_32bits.v
output [NB_COL*COL_WIDTH-1:0] dout; // From U_SSRAM of bytewrite_ram_32bits.v
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
// local clock
wire ack_clk;
wire ack;
assign #1 clk = req ^ ack ;
delay #(.DELAY(CLOCK_PULSE_WIDTH)) U_DELAY_CLOCK_PULSE(.i(req), .d(ack_clk));
delay #(.DELAY(ACCESS_TIME)) U_DELAY_ACCESS_TIME(.i(req), .d(ack));
/* bytewrite_ram_32bits AUTO_TEMPLATE(
); */
bytewrite_ram_32bits #(
.SIZE(SIZE),
.ADDR_WIDTH(ADDR_WIDTH),
.filename(filename)
) U_SSRAM (
.clk (clk),
/*AUTOINST*/
// Outputs
.dout (dout[NB_COL*COL_WIDTH-1:0]),
// Inputs
.we (we[NB_COL-1:0]),
.addr (addr[ADDR_WIDTH-1:0]),
.din (din[NB_COL*COL_WIDTH-1:0]));
endmodule // async_mem
/*
Local Variables:
verilog-library-directories:(
"."
"../../misc_lib"
)
End:
*/
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int mx = (1 << 30) - 1; int n, m; struct node { vector<pair<int, int> > p; void cal(int a, int b) { int res = a ^ b; for (int i = 0; i < 30; i++) { int t = res ^ (1 << i) ^ (res & ((1 << i) - 1)); if ((t ^ a) > b) p.emplace_back(t, t + (1 << i) - 1); } } void get(int first, int l, int r) { cal(first, r); cal(mx ^ first, mx ^ l); } }; void solve() { node temp; scanf( %d%d , &n, &m); temp.get(n, 0, m); sort(temp.p.begin(), temp.p.end()); printf( %d n , temp.p[0].first); } int main() { int t; scanf( %d , &t); while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; vector<int> lefts[2000000], rights[2000000]; vector<pair<pair<int, int>, bool>> lws; int maxleft[2000000]; int maxright[2000000]; int minright[2000000]; vector<int> ans; bool fail = false; int n; int dfs(int v, int needed) { int cur = v; if (maxleft[v] > v) cur = dfs(cur + 1, maxleft[v]); ans.push_back(v); if (cur >= minright[v]) { fail = true; return n; } if (needed <= cur && maxright[v] <= cur) return cur; return dfs(cur + 1, max(needed, maxright[v])); } int main() { ios_base::sync_with_stdio(false); int c; cin >> n >> c; for (int i = 1; i <= n; i++) { maxleft[i] = maxright[i] = i; minright[i] = 1e9; } for (int i = 0; i < c; i++) { int a, b; string s; cin >> a >> b >> s; lws.push_back(make_pair(make_pair(a, b), s != LEFT )); if (s == LEFT ) { lefts[a].push_back(b); if (b <= a) fail = true; maxleft[a] = max(maxleft[a], b); } if (s == RIGHT ) { rights[a].push_back(b); if (b <= a) fail = true; maxright[a] = max(maxright[a], b); minright[a] = min(minright[a], b); } } for (int i = 1; i <= n; i++) { if (minright[i] <= maxleft[i]) fail = true; } dfs(1, n); if (fail) cout << IMPOSSIBLE ; else { for (int i = 0; i < n; i++) { cout << ans[i] << ; } } }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int SIZE = 1e6 + 10; using namespace std; struct E { int k, c; E() {} E(int _k, int _c) : k(_k), c(_c) {} } es[4200010]; struct Flow { int n, m, dis[500010]; int qq[500010], qr, ql; vector<int> e[500010]; void init(int _n) { n = _n; m = 0; for (int i = 0; i < n; i++) e[i] = vector<int>(); } void add_edge(int a, int b, int c) { e[a].push_back(m); es[m] = E(b, c); m++; e[b].push_back(m); es[m] = E(a, 0); m++; } bool BFS() { memset(dis, -1, n * sizeof(int)); ql = qr = 0; qq[qr++] = 0; dis[0] = 0; while (ql != qr && dis[n - 1] == -1) { int p = qq[ql++]; for (__typeof((e[p]).begin()) it = (e[p]).begin(); it != (e[p]).end(); it++) { E ee = es[*it]; if (ee.c == 0 || dis[ee.k] != -1) continue; dis[ee.k] = dis[p] + 1; qq[qr++] = ee.k; } } return dis[n - 1] != -1; } long long go(int p, long long c) { if (p == n - 1) return c; long long ret = 0, tmp; for (__typeof((e[p]).begin()) it = (e[p]).begin(); it != (e[p]).end(); it++) { E &ee = es[*it]; if (ee.c == 0 || dis[p] + 1 != dis[ee.k]) continue; tmp = go(ee.k, min(c - ret, (long long)ee.c)); ret += tmp; ee.c -= tmp; es[(*it) ^ 1].c += tmp; if (ret == c) break; } if (ret == 0) dis[p] = -1; return ret; } long long maxflow() { long long ret = 0; while (BFS()) ret += go(0, 1LL << 60); return ret; } } flow; vector<int> cc[301][301], cn[301]; int need_id, an[301], xx[301], yy[301]; pair<int, int> need[1000001]; int to[301]; bool used[301]; bool match(pair<int, int> X, pair<int, int> Y) { if (X.first != Y.first && Y.first != -1) return 0; if (X.second != Y.second && Y.second != -1) return 0; return 1; } void go(int ma_id, int ma_hi, int n) { if (ma_id != 1 && ((int)(cc[ma_id][0]).size()) == 0) return; vector<pair<int, int> > qq; int oo = need_id; for (int i = ma_hi; i >= 0; i--) { if (((int)(cc[ma_id][i]).size()) == 0) { need[++need_id] = make_pair(ma_id, i); cc[ma_id][i].push_back(-need_id); qq.push_back(make_pair(ma_id, i)); } } if (need_id > n) { for (int i = 0; i < (((int)(qq).size())); ++i) cc[qq[i].first][qq[i].second].pop_back(); need_id = oo; return; } flow.init(need_id + n + 2); for (int i = (1); i < (n + 1); ++i) flow.add_edge(need_id + i, need_id + n + 1, 1); for (int i = (1); i < (need_id + 1); ++i) { flow.add_edge(0, i, 1); for (int j = (1); j < (n + 1); ++j) { if (used[j]) continue; if (match(need[i], make_pair(yy[j], xx[j]))) flow.add_edge(i, need_id + j, 1); } } if (flow.maxflow() != need_id) { need_id = oo; return; } for (int i = 0; i < flow.m; i += 2) { if (es[i].k > need_id && es[i + 1].k <= need_id && es[i].c == 0) { used[es[i].k - need_id] = 1; to[es[i + 1].k] = es[i].k - need_id; } } for (int i = (1); i < (n + 1); ++i) { for (int j = 0; j < (n); ++j) { for (int k = 0; k < (((int)(cc[i][j]).size())); ++k) { if (cc[i][j][k] < 0) cc[i][j][k] = to[-cc[i][j][k]]; } } } for (int i = (1); i < (n + 1); ++i) { if (!used[i]) { used[i] = 1; if (xx[i] == -1 && yy[i] == -1) cc[1][0].push_back(i); else if (yy[i] != -1) cc[yy[i]][1].push_back(i); else if (xx[i] != -1) { if (xx[i] == 0) cc[1][0].push_back(i); else cc[ma_id][xx[i]].push_back(i); } } } for (int i = (1); i < (n + 1); ++i) { for (int j = 0; j < (((int)(cc[i][0]).size())); ++j) { if (j % i == 0) an[cc[i][0][j]] = cc[i][0][j + i - 1]; else an[cc[i][0][j]] = cc[i][0][j - 1]; } for (int j = (1); j < (n); ++j) { for (int k = 0; k < (((int)(cc[i][j]).size())); ++k) an[cc[i][j][k]] = cc[i][j - 1][0]; } } for (int i = (1); i < (n + 1); ++i) printf( %d%c , an[i], n [i == n]); exit(0); } int main() { int(n); scanf( %d , &n); int ma_hi = -1; for (int i = (1); i < (n + 1); ++i) { char s1[20], s2[20]; scanf( %s , (s1)); scanf( %s , (s2)); int x = -1, y = -1; if (s1[0] != ? ) x = atoi(s1); if (s2[0] != ? ) y = atoi(s2); if (x != -1 && y != -1) { cc[y][x].push_back(i); used[i] = 1; } else if (y != -1) cn[y].push_back(i); xx[i] = x; yy[i] = y; ma_hi = max(ma_hi, x); } int mi = 10000, ma_id = 1; for (int i = (1); i < (n + 1); ++i) { int hi = n - 1; while (hi >= 0 && ((int)(cc[i][hi]).size()) == 0) hi--; while (hi >= 0) { if (!((int)(cc[i][hi]).size())) { need[++need_id] = make_pair(i, hi); cc[i][hi].push_back(-need_id); } hi--; } if (((int)(cn[i]).size()) && ((int)(cc[i][0]).size()) == 0) { need[++need_id] = make_pair(i, 0); cc[i][0].push_back(-need_id); } while (((int)(cc[i][0]).size()) % i) { need[++need_id] = make_pair(i, 0); cc[i][0].push_back(-need_id); } } for (int ker = 1; ker <= n; ker++) { go(ker, ma_hi, n); } return 0 * puts( -1 ); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Driss Hafdi.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
initial begin
if (getUnpacked($c("0")) != "0") $stop;
if (getUnpacked($c("1")) != "1") $stop;
if (getUnpacked($c("2")) != "2") $stop;
if (getUnpacked($c("3")) != "3") $stop;
if (getUnpacked($c("4")) != "4") $stop;
if (getUnpacked($c("5")) != "5") $stop;
if (getUnpacked($c("6")) != "6") $stop;
if (getUnpacked($c("7")) != "7") $stop;
if (getUnpacked($c("8")) != "8") $stop;
if (getUnpacked($c("9")) != "9") $stop;
if (getPacked($c("0")) != "0") $stop;
if (getPacked($c("1")) != "1") $stop;
if (getPacked($c("2")) != "2") $stop;
if (getPacked($c("3")) != "3") $stop;
if (getPacked($c("4")) != "4") $stop;
if (getPacked($c("5")) != "5") $stop;
if (getPacked($c("6")) != "6") $stop;
if (getPacked($c("7")) != "7") $stop;
if (getPacked($c("8")) != "8") $stop;
if (getPacked($c("9")) != "9") $stop;
if (getString($c("0")) != "0") $stop;
if (getString($c("1")) != "1") $stop;
if (getString($c("2")) != "2") $stop;
if (getString($c("3")) != "3") $stop;
if (getString($c("4")) != "4") $stop;
if (getString($c("5")) != "5") $stop;
if (getString($c("6")) != "6") $stop;
if (getString($c("7")) != "7") $stop;
if (getString($c("8")) != "8") $stop;
if (getString($c("9")) != "9") $stop;
if (getStruct($c("0")) != "0") $stop;
if (getStruct($c("1")) != "1") $stop;
if (getStruct($c("2")) != "2") $stop;
if (getStruct($c("3")) != "3") $stop;
if (getStruct($c("4")) != "4") $stop;
if (getStruct($c("5")) != "5") $stop;
if (getStruct($c("6")) != "6") $stop;
if (getStruct($c("7")) != "7") $stop;
if (getStruct($c("8")) != "8") $stop;
if (getStruct($c("9")) != "9") $stop;
if (getType($c("0")) != "0") $stop;
if (getType($c("1")) != "1") $stop;
if (getType($c("2")) != "2") $stop;
if (getType($c("3")) != "3") $stop;
if (getType($c("4")) != "4") $stop;
if (getType($c("5")) != "5") $stop;
if (getType($c("6")) != "6") $stop;
if (getType($c("7")) != "7") $stop;
if (getType($c("8")) != "8") $stop;
if (getType($c("9")) != "9") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
function automatic logic [7:0] getUnpacked(logic[3:0] d);
`ifdef NO_INLINE
/* verilator no_inline_task */
`endif
localparam logic [7:0] digits [10] =
'{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"};
return digits[d];
endfunction
function automatic logic [7:0] getPacked(logic[3:0] d);
`ifdef NO_INLINE
/* verilator no_inline_task */
`endif
localparam logic [9:0][7:0] digits =
{"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"};
return digits[d];
endfunction
function automatic string getString(logic[3:0] d);
`ifdef NO_INLINE
/* verilator no_inline_task */
`endif
localparam string digits [10] =
'{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"};
return digits[d];
endfunction
function automatic logic [7:0] getStruct(logic[3:0] d);
`ifdef NO_INLINE
/* verilator no_inline_task */
`endif
// Silly indirect lookup table because we want to use a struct
typedef struct packed {
logic [7:0] result;
longint index;
} lut_t;
localparam lut_t digits [10] =
'{
'{result: "1", index: 9},
'{result: "2", index: 0},
'{result: "3", index: 1},
'{result: "4", index: 2},
'{result: "5", index: 3},
'{result: "6", index: 4},
'{result: "7", index: 5},
'{result: "8", index: 6},
'{result: "9", index: 7},
'{result: "0", index: 8}
};
return digits[4'(digits[d].index)].result;
endfunction
function automatic logic [7:0] getType(logic[3:0] d);
`ifdef NO_INLINE
/* verilator no_inline_task */
`endif
localparam type octet_t = logic [7:0];
localparam octet_t [9:0] digits =
{"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"};
return digits[d];
endfunction
|
module top (
);
// Both RAMB18 in the same tile
(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y25" *)
RAMB18E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36)
) RAMB18E1_BOTH_X1 (
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b1),
.RSTRAMB(1'b1),
.RSTREGARSTREG(1'b1),
.RSTREGB(1'b1),
.WEA({1'b0}),
.WEBWE({1'b0})
);
(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y24" *)
RAMB18E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36)
) RAMB18E1_BOTH_X0 (
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b1),
.RSTRAMB(1'b1),
.RSTREGARSTREG(1'b1),
.RSTREGB(1'b1),
.WEA({1'b0}),
.WEBWE({1'b0})
);
// ---------------------------------------
// One RAMB18 in Y0
(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y22" *)
RAMB18E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36)
) RAMB18E1_X0 (
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b1),
.RSTRAMB(1'b1),
.RSTREGARSTREG(1'b1),
.RSTREGB(1'b1),
.WEA({1'b0}),
.WEBWE({1'b0})
);
// ---------------------------------------
// One RAMB18 in Y1
(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y21" *)
RAMB18E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36)
) RAMB18E1_X1 (
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b1),
.RSTRAMB(1'b1),
.RSTREGARSTREG(1'b1),
.RSTREGB(1'b1),
.WEA({1'b0}),
.WEBWE({1'b0})
);
// ---------------------------------------
// One RAMB36
(* KEEP, DONT_TOUCH, LOC="RAMB36_X0Y9" *)
RAMB36E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(72),
.READ_WIDTH_B(0),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(72)
) RAMB36E1_X0 (
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b1),
.RSTRAMB(1'b1),
.RSTREGARSTREG(1'b1),
.RSTREGB(1'b1),
.WEA({1'b0}),
.WEBWE({1'b0})
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21A_PP_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_PP_BLACKBOX_V
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: Sora_RCB_top
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Non-Posted Packet Generator wrapper file.
// Connects the NonPosted Packet Slicer and Non-Posted Packet Builder modules
// together
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// modified by Jiansong Zhang:
// add logic for TX descriptor request ----------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "Sora_config.v"
module non_posted_pkt_gen(
input clk,
input rst,
/// Jiansong: control signal for transfer recovering
`ifdef TF_RECOVERY
input transferstart,
`endif
//inputs from dma_ctrl_wrapper
input [63:0] dmaras,
input [31:0] dmarad,
input [31:0] dmarxs,
input rd_dma_start,
/// Jiansong: added for TX descriptor request
input rd_TX_des_start,
input [63:0] TX_des_addr,
//inputs from pcie block plus
input [2:0] read_req_size,
input [15:0] req_id,
//outputs to non posted header fifo
output non_posted_fifo_wren,
output [63:0] non_posted_fifo_data,
//in and outs to tag_generator
output tag_inc,
input tag_gnt,
input [7:0] tag_value,
//outputs to read_request_wrapper
output [4:0] tx_waddr,
output [31:0] tx_wdata,
output tx_we
);
//internal wrapper connections
wire [31:0] dmarad_reg;
wire [63:0] dmaras_reg;
wire [9:0] length;
wire ack,go; //handshake signals
wire isDes;
wire rd_dma_start_one;
wire rd_TX_des_start_one;
/// Jiansong: moved here from tx engine
rising_edge_detect rd_dma_start_one_inst(
.clk(clk),
.rst(rst_reg),
.in(rd_dma_start),
.one_shot_out(rd_dma_start_one)
);
/// Jiansong: added for TX des request trigger
rising_edge_detect rd_TX_des_start_one_inst(
.clk(clk),
.rst(rst_reg),
.in(rd_TX_des_start),
.one_shot_out(rd_TX_des_start_one)
);
non_posted_pkt_slicer non_posted_pkt_slicer_inst(
.clk(clk),
.rst(rst),
/// Jiansong: control signal for transfer recovering
`ifdef TF_RECOVERY
.transferstart(transferstart),
`endif
//interface to dma_ctrl_wrapper
.rd_TX_des_start_one(rd_TX_des_start_one),/// Jiansong:
.TX_des_addr(TX_des_addr), /// added for TX des request
.isDes(isDes), ///
.rd_dma_start(rd_dma_start_one),
.dmarad(dmarad),
.dmarxs(dmarxs),
.dmaras(dmaras),
.read_req_size(read_req_size), //from pcie block
//interface to non_posted_pkt_builder
.ack(ack),
.go(go),
.dmarad_reg(dmarad_reg[31:0]),
.dmaras_reg(dmaras_reg[63:0]),
.length(length[9:0])
);
non_posted_pkt_builder non_posted_pkt_builder_inst(
.clk(clk),
.rst(rst),
.req_id(req_id[15:0]), //from pcie block
//interface to/from non_posted_pkt_slicer
.go(go),
.ack(ack),
.dmaras(dmaras_reg[63:0]),
.dmarad(dmarad_reg[31:0]),
.length(length[9:0]),
.isDes(isDes), /// Jiansong:
//interface to/from tag_generator
.tag_value(tag_value[7:0]),
.tag_gnt(tag_gnt),
.tag_inc(tag_inc),
//interface to/from a64_64_distram_np(non-posted header fifo)
.header_data_out(non_posted_fifo_data[63:0]),
.header_data_wren(non_posted_fifo_wren),
//interface to read_request_wrapper
.tx_waddr(tx_waddr[4:0]),
.tx_wdata(tx_wdata[31:0]),
.tx_we(tx_we)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; getline(cin, s); for (int i = 0; i < n; i++) { getline(cin, s); if (s.length() >= 5) { if ((s.substr(0, 5) == miao. ) && (s.substr(s.length() - 5, 5) != lala. )) cout << Rainbow s << endl; else if ((s.substr(0, 5) != miao. ) && (s.substr(s.length() - 5, 5) == lala. )) cout << Freda s << endl; else cout << OMG>.< I don t know! << endl; } else cout << OMG>.< I don t know! << endl; } return 0; }
|
module opc5system ( input clk, input[7:0] sw, output[7:0] led, input rxd, output txd,
output [6:0] seg, output [3:0] an, input select);
// CLKSPEED is the main clock speed
parameter CLKSPEED = 32000000;
// BAUD is the desired serial baud rate
parameter BAUD = 115200;
// RAMSIZE is the size of the RAM address bus
parameter RAMSIZE = 11;
// Duty Cycle controls the brightness of the seven segment display (0..15)
parameter SEVEN_SEG_DUTY_CYCLE = 0;
wire [15:0] cpu_din;
wire [15:0] cpu_dout;
wire [15:0] ram_dout;
wire [15:0] uart_dout;
wire [15:0] address;
wire rnw;
reg reset_b;
wire uart_cs_b = !({address[15:1], 1'b0} == 16'hfe08);
wire ram_cs_b = !(address[15:RAMSIZE] == 0);
// Synchronize reset
always @(posedge clk)
reset_b <= select;
// The OPC5 CPU
opc5cpu CPU ( cpu_din, cpu_dout, address, rnw, clk, reset_b);
// A block RAM - clocked off negative edge to mask output register
ram RAM (cpu_dout, ram_dout, address[RAMSIZE-1:0], rnw, !clk, ram_cs_b);
// A simple 115200 baud UART
uart #(CLKSPEED, BAUD) UART (cpu_dout, uart_dout, address[0], rnw, clk, reset_b, uart_cs_b, rxd, txd);
// Use the 4-digit hex display for the address
sevenseg #(SEVEN_SEG_DUTY_CYCLE) DISPLAY (sw[0] ? cpu_din : address, clk, an, seg);
// Data Multiplexor
assign cpu_din = ram_cs_b ? (uart_cs_b ? 16'hffff : uart_dout) : ram_dout;
// LEDs could be used for debugging in the future
assign led = sw;
endmodule
|
#include <bits/stdc++.h> using namespace std; char W[1000 + 10]; int N[1000 + 10]; int main() { int n, m; scanf( %d%d%s , &n, &m, W); for (int i = 0; i < n; ++i) (N[i] = W[i] - a ); bool fixed = false; for (int i = n - 1; i >= 0; --i) { while (true) { N[i]++; if (N[i] == m) break; if (i - 1 >= 0 && N[i] == N[i - 1]) continue; if (i - 2 >= 0 && N[i] == N[i - 2]) continue; fixed = true; for (int j = i + 1; j < n; ++j) { N[j] = -1; while (true) { N[j]++; if (j - 1 >= 0 && N[j] == N[j - 1]) continue; if (j - 2 >= 0 && N[j] == N[j - 2]) continue; break; } } break; } if (fixed) break; } if (!fixed) printf( NO n ); else { for (int i = 0; i < n; ++i) printf( %c , a + N[i]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1001; int a[N][N], LR[N][N], RR[N][N], LC[N][N], RC[N][N]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; ++i) { vector<int> v; for (int j = 1; j <= m; ++j) { cin >> a[i][j]; v.push_back(a[i][j]); } sort(v.begin(), v.end()); auto last = unique(v.begin(), v.end()); v.erase(last, v.end()); for (int j = 1; j <= m; ++j) { int l = 0, r = (int)v.size() - 1; while (l <= r) { int m = (l + r) / 2; if (v[m] >= a[i][j]) { if (v[m] == a[i][j]) { LR[i][j] = m; RR[i][j] = (int)v.size() - 1 - m; } r = m - 1; } else { l = m + 1; } } } } for (int i = 1; i <= m; ++i) { set<int> s; vector<int> v; for (int j = 1; j <= n; ++j) { v.push_back(a[j][i]); } sort(v.begin(), v.end()); auto last = unique(v.begin(), v.end()); v.erase(last, v.end()); for (int j = 1; j <= n; ++j) { int l = 0, r = (int)v.size() - 1; while (l <= r) { int m = (l + r) / 2; if (v[m] >= a[j][i]) { if (v[m] == a[j][i]) { LC[j][i] = m; RC[j][i] = (int)v.size() - 1 - m; } r = m - 1; } else { l = m + 1; } } } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cout << max(LC[i][j], LR[i][j]) + 1 + max(RC[i][j], RR[i][j]) << ; } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; inline void speed() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int compare(pair<long long int, long long int> a, pair<long long int, long long int> b) { return a.first > b.first; } int main() { speed(); long long int n; cin >> n; vector<pair<long long int, long long int> > a; for (long long int i = 0; i < n; i++) { long long int temp; cin >> temp; a.push_back({temp, i}); } sort(a.begin(), a.end(), compare); long long int k = 0; long long int tk = 0; for (long long int i = 0; i < n; i++) { k = (a[i].first) * i + 1; tk += k; } cout << tk << n ; for (long long int i = 0; i < n; i++) { cout << a[i].second + 1 << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.1415926535897932384626433; const long long mod = 1000000007; const int INF = 0x3f3f3f3f; const double eps = 1e-8; template <class T> T gcd(T a, T b) { if (!b) return a; return gcd(b, a % b); } const int maxn = 1e5 + 10; vector<int> edg[maxn], vi, ans; int now[maxn], nxt[maxn], len1, len2, n, m, vis[maxn], st[maxn], flg; void dfs(int u) { if (st[u] < 0) flg = 0; if (flg == 0) return; vis[u] = 1; ans.push_back(u); for (int i = 0; i < edg[u].size(); i++) { int nxt = edg[u][i]; if (st[nxt] < 0) flg = 0; if (!vis[nxt]) dfs(nxt); } } int deal(int *a1, int *a2) { int len = min(len1, len2); for (int i = 0; i < len; i++) { if (a1[i] < a2[i]) { edg[a2[i]].push_back(a1[i]); return 1; } else if (a1[i] > a2[i]) { vi.push_back(a1[i]); if (st[a1[i]] == -1 || st[a2[i]] == 1) return 0; st[a1[i]] = 1; st[a2[i]] = -1; return 1; } } return len1 <= len2; } int solve() { memset(st, 0, sizeof(st)); int *a1 = now, *a2 = nxt; scanf( %d , &len1); for (int i = 0; i < len1; i++) scanf( %d , &a1[i]); flg = 1; for (int t = 1; t < n; t++) { scanf( %d , &len2); for (int i = 0; i < len2; i++) scanf( %d , &a2[i]); if (deal(a1, a2) == 0) flg = 0; swap(a1, a2); len1 = len2; } memset(vis, 0, sizeof(vis)); for (int i = 0; i < vi.size(); i++) if (!vis[vi[i]]) dfs(vi[i]); return flg; } int main() { scanf( %d , &n); scanf( %d , &m); if (solve()) { printf( Yes n%d n , ans.size()); for (int i = 0; i < ans.size(); i++) printf( %d , ans[i]); puts( ); } else { printf( No n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[1010]; int main() { int n, i; cin >> n; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int ans = 0; int x; for (int i = 0; i < n; i++) { x = 1; if (a[i] >= 0) { ans++; for (int j = i + 1; j < n; j++) { if (a[j] >= x) { x++; a[j] = -1; } } } } cout << ans << endl; return 0; }
|
`default_nettype none
module gci_std_display_request_controller #(
parameter P_AREA_H = 640,
parameter P_AREA_V = 480,
parameter P_AREAA_HV_N = 19,
parameter P_MEM_ADDR_N = 23
)(
input wire iCLOCK,
input wire inRESET,
//BUS
input wire iRQ_VALID,
output wire oRQ_BUSY,
input wire [P_MEM_ADDR_N-1:0] iRQ_ADDR,
input wire [23:0] iRQ_DATA,
//VRAM
output wire oRQ_VALID,
input wire iRQ_BUSY,
output wire [23:0] oRQ_DATA,
//New
output wire oIF_REQ,
input wire iIF_ACK,
output wire oIF_FINISH,
input wire iIF_BREAK,
input wire iIF_BUSY,
output wire oIF_ENA,
output wire oIF_RW,
output wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
output wire [7:0] oIF_R,
output wire [7:0] oIF_G,
output wire [7:0] oIF_B,
input wire iIF_VALID,
output wire oIF_BUSY,
input wire [31:0] iIF_DATA
);
assign oBUSMOD_WAIT = reqfifo_wr_full;
wire request_break_condition = iIF_BREAK || ;
wire reqfifo_read_condition =
gci_std_sync_fifo #(24, 16, 4) VRAM_REQ_FIFO(
.inRESET(inRESET),
.iREMOVE(1'b0),
.iCLOCK(iCLOCK),
.iWR_EN(iRQ_VALID && !read_fifo_wr_full),
.iWR_DATA(iIF_DATA[23:0]),
.oWR_FULL(read_fifo_wr_full),
.oWR_ALMOST_FULL(),
.iRD_EN(!read_fifo_rd_empty && !iRQ_BUSY),
.oRD_DATA(read_fifo_rd_data),
.oRD_EMPTY(read_fifo_rd_empty)
);
localparam P_L_MAIN_STT_IDLE = 3'h0;
localparam P_L_MAIN_STT_IF_REQ = 3'h1;
localparam P_L_MAIN_STT_IF_WORK = 3'h2;
localparam P_L_MAIN_STT_IF_READ_WAIT = 3'h3;
localparam P_L_MAIN_STT_IF_END = 3'h4;
reg [2:0] b_main_state;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
else begin
case(b_main_state)
P_L_MAIN_STT_IDLE:
begin
if(iRQ_VALID)begin
b_main_state <= P_L_MAIN_STT_IF_REQ;
end
end
P_L_MAIN_STT_IF_REQ:
begin
if(iIF_ACK)begin
b_main_state <= P_L_MAIN_STT_IF_WORK;
end
end
P_L_MAIN_STT_IF_WORK:
begin
if(request_break_condition)begin
b_main_state <= P_L_MAIN_STT_IF_END;
end
else if()begin
b_main_state <= P_L_MAIN_STT_IF_READ_WAIT;
end
end
P_L_MAIN_STT_IF_READ_WAIT:
begin
if(iIF_VALID && !read_fifo_wr_full)begin
b_main_state <= P_L_MAIN_STT_IF_END;
end
end
P_L_MAIN_STT_IF_END:
begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
default:
begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
endcase
end
end //main(vram-interface) state always
wire read_fifo_wr_full;
wire read_fifo_rd_empty;
wire [23:0] read_fifo_rd_data;
gci_std_sync_fifo #(24, 4, 2) VRAM_RESULT_FIFO(
.inRESET(inRESET),
.iREMOVE(1'b0),
.iCLOCK(iCLOCK),
.iWR_EN(iIF_VALID && !read_fifo_wr_full),
.iWR_DATA(iIF_DATA[23:0]),
.oWR_FULL(read_fifo_wr_full),
.oWR_ALMOST_FULL(),
.iRD_EN(!read_fifo_rd_empty && !iRQ_BUSY),
.oRD_DATA(read_fifo_rd_data),
.oRD_EMPTY(read_fifo_rd_empty)
);
assign oRQ_VALID = !read_fifo_rd_empty && !iRQ_BUSY;
assign oRQ_DATA = read_fifo_rd_data;
assign oIF_BUSY = read_fifo_wr_full;
/***************************************************
Assertion
***************************************************/
/*
`ifdef GCI_STD_DISP_SVA_ASSERTION
proterty PRO_FIFO_NEVER_NOT_FULL;
@(posedge iCLOCK) disable iff (!inRESET) (!read_fifo_wr_full);
endproperty
assert property(PRO_FIFO_NEVER_NOT_FULL);
`endif
*/
endmodule
`default_nettype wire
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_enable,
src_dac_data,
src_dac_valid,
dst_dac_enable,
dst_dac_data,
dst_dac_valid
);
localparam RP_ID = 8'hA1;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_enable;
input [15:0] src_dac_data;
output src_dac_valid;
input dst_dac_enable;
output [15:0] dst_dac_data;
input dst_dac_valid;
reg [15:0] dst_dac_data = 0;
reg src_dac_valid = 0;
reg src_dac_enable = 0;
reg [15:0] dac_prbs = 32'hA2F19C;
reg [31:0] status = 0;
reg [ 2:0] counter = 0;
reg pattern = 0;
reg [15:0] sin_tone = 0;
reg [15:0] cos_tone = 0;
reg [ 3:0] mode;
wire [15:0] dac_pattern_s;
// prbs function
function [15:0] pn;
input [15:0] din;
reg [15:0] dout;
begin
dout[15] = din[14] ^ din[15];
dout[14] = din[13] ^ din[14];
dout[13] = din[12] ^ din[13];
dout[12] = din[11] ^ din[12];
dout[11] = din[10] ^ din[11];
dout[10] = din[ 9] ^ din[10];
dout[ 9] = din[ 8] ^ din[ 9];
dout[ 8] = din[ 7] ^ din[ 8];
dout[ 7] = din[ 6] ^ din[ 7];
dout[ 6] = din[ 5] ^ din[ 6];
dout[ 5] = din[ 4] ^ din[ 5];
dout[ 4] = din[ 3] ^ din[ 4];
dout[ 3] = din[ 2] ^ din[ 3];
dout[ 2] = din[ 1] ^ din[ 2];
dout[ 1] = din[ 0] ^ din[ 1];
dout[ 0] = din[14] ^ din[15] ^ din[ 0];
pn = dout;
end
endfunction
always @(posedge clk) begin
status <= {24'h0, RP_ID};
mode <= control[7:4];
end
// sine tone generation
always @(posedge clk) begin
if ((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
counter <= counter + 1;
end
end
always @(counter) begin
case(counter)
3'd0 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h7FFF;
end
3'd1 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'h5A82;
end
3'd2 : begin
sin_tone <= 16'h7FFF;
cos_tone <= 16'h0000;
end
3'd3 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'hA57E;
end
3'd4 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h8001;
end
3'd5 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'hA57E;
end
3'd6 : begin
sin_tone <= 16'h8001;
cos_tone <= 16'h0000;
end
3'd7 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'h5A82;
end
endcase
end
// prbs generation
always @(posedge clk) begin
if((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
dac_prbs <= pn(dac_prbs);
end
end
// constant pattern generator
always @(posedge clk) begin
if((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
pattern <= ~pattern;
end
end
assign dac_pattern_s = (pattern == 1'h1) ? 16'h5555 : 16'hAAAA;
// output mux for tx side
always @(posedge clk) begin
src_dac_enable <= dst_dac_enable;
src_dac_valid <= (mode == 0) ? dst_dac_valid : 1'b0;
end
always @(posedge clk) begin
case(mode)
4'h0 : begin
dst_dac_data <= src_dac_data;
end
4'h1 : begin
dst_dac_data <= {cos_tone, sin_tone};
end
4'h2 : begin
dst_dac_data <= dac_prbs;
end
4'h3 : begin
dst_dac_data <= dac_pattern_s;
end
default : begin
dst_dac_data <= src_dac_data;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[1005]; long long t, ans = 0; int x, l; int main() { scanf( %s , s); int len = strlen(s); for (int i = 0; i < len; i++) { if (isalpha(s[i])) { if (t) { if (l == 2) ans += t; else ans += t * 100; } t = 0; x = 0; l = 0; } else { if (isdigit(s[i])) { t = t * 10 + s[i] - 0 ; if (x) { l++; } } else { x = 1; l = 0; } } } if (t) { if (l == 2) { ans += t; } else ans += t * 100; } long long temp = ans / 100; long long temp1 = ans % 100; len = 0; string A = ; if (temp == 0) A = A + 0 ; while (temp) { if (len && len % 3 == 0) { A = A + . ; } char c = 0 + temp % 10; A = A + c; temp /= 10; len++; } reverse(A.begin(), A.end()); cout << A; if (temp1) { printf( .%.2I64d , temp1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; set<string> a, b, c; void solve() { cin >> n >> m; for (int i = 1; i <= n; i++) { string s; cin >> s; a.insert(s); } for (int i = 1; i <= m; i++) { string s; cin >> s; if (a.count(s)) c.insert(s); b.insert(s); } while (1) { if (a.empty()) { cout << NO n ; return; } if (!c.empty()) { a.erase(*c.begin()); b.erase(*c.begin()); c.erase(c.begin()); } else { if (b.count(*a.begin())) b.erase(*a.begin()); a.erase(a.begin()); } if (b.empty()) { cout << YES n ; return; } if (!c.empty()) { a.erase(*c.begin()); b.erase(*c.begin()); c.erase(c.begin()); } else { if (a.count(*b.begin())) a.erase(*b.begin()); b.erase(b.begin()); } } } int main() { int t = 1; while (t--) { solve(); } return 0; }
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module write_axi(
input clock_recovery,
input clock_50,
input reset_n,
input [13:0] data_rec,
output reg [13:0] data_stand
);
always@(posedge clock_50 or negedge reset_n )
begin
if(!reset_n)
begin
data_stand <= 14'd0;
end
else
begin
if(clock_recovery)
data_stand <= data_rec;
else
data_stand <= data_stand;
end
end
endmodule
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Load, store unit for espresso pipeline
All combinatorial outputs to pipeline
Dbus interface request signal out synchronous
32-bit specific due to sign extension of results
Copyright (C) 2012 Authors
Author(s): Julius Baxter <>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_lsu_espresso
(/*AUTOARG*/
// Outputs
lsu_result_o, lsu_valid_o, lsu_except_dbus_o, lsu_except_align_o,
dbus_adr_o, dbus_req_o, dbus_dat_o, dbus_bsel_o, dbus_we_o,
dbus_burst_o,
// Inputs
clk, rst, padv_fetch_i, lsu_adr_i, rfb_i, op_lsu_load_i,
op_lsu_store_i, lsu_length_i, lsu_zext_i, exception_taken_i,
du_restart_i, stepping_i, next_fetch_done_i, dbus_err_i,
dbus_ack_i, dbus_dat_i
);
parameter OPTION_OPERAND_WIDTH = 32;
parameter OPTION_REGISTERED_IO = "NO";
input clk, rst;
input padv_fetch_i;
// calculated address from ALU
input [OPTION_OPERAND_WIDTH-1:0] lsu_adr_i;
// register file B in (store operand)
input [OPTION_OPERAND_WIDTH-1:0] rfb_i;
// from decode stage regs, indicate if load or store
input op_lsu_load_i;
input op_lsu_store_i;
input [1:0] lsu_length_i;
input lsu_zext_i;
input exception_taken_i;
input du_restart_i;
input stepping_i;
input next_fetch_done_i;
output [OPTION_OPERAND_WIDTH-1:0] lsu_result_o;
output lsu_valid_o;
// exception output
output lsu_except_dbus_o;
output lsu_except_align_o;
// interface to data bus
output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o;
output dbus_req_o;
output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o;
output [3:0] dbus_bsel_o;
output dbus_we_o;
output dbus_burst_o;
input dbus_err_i;
input dbus_ack_i;
input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i;
reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_aligned; // comb.
reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_extended; // comb.
reg [OPTION_OPERAND_WIDTH-1:0] dbus_adr_r;
reg [3:0] dbus_bsel;
reg dbus_err_r;
reg access_done;
reg [OPTION_OPERAND_WIDTH-1:0] lsu_result_r;
reg op_lsu;
wire align_err_word;
wire align_err_short;
wire align_err;
wire except_align;
reg except_align_r;
reg except_dbus;
reg execute_go;
assign dbus_dat_o = (lsu_length_i == 2'b00) ? // byte access
{rfb_i[7:0],rfb_i[7:0],rfb_i[7:0],rfb_i[7:0]} :
(lsu_length_i == 2'b01) ? // halfword access
{rfb_i[15:0],rfb_i[15:0]} :
rfb_i; // word access
assign align_err_word = |dbus_adr_o[1:0];
assign align_err_short = dbus_adr_o[0];
assign lsu_valid_o = dbus_ack_i | dbus_err_r| access_done;
assign lsu_except_dbus_o = dbus_err_r | except_dbus;
assign align_err = (lsu_length_i == 2'b10) & align_err_word |
(lsu_length_i == 2'b01) & align_err_short;
assign lsu_except_align_o = except_align_r;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
execute_go <= 0;
else
execute_go <= padv_fetch_i | (stepping_i & next_fetch_done_i);
always @(posedge clk `OR_ASYNC_RST)
if (rst)
access_done <= 0;
else if (padv_fetch_i | du_restart_i)
access_done <= 0;
else if (dbus_ack_i | dbus_err_r | lsu_except_align_o)
access_done <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
except_align_r <= 0;
else if (exception_taken_i)
except_align_r <= 0;
else
except_align_r <= except_align;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
except_dbus <= 0;
else if (exception_taken_i)
except_dbus <= 0;
else if (dbus_err_r)
except_dbus <= 1;
// Need to register address due to behavior of RF when source register is
// same as destination register - value changes after one cycle to the
// forwarding register's value, which is incorrect.
// So we save it on first cycle.
// TODO - perhaps detect in RF when this is case, and make it keep the
// output steady to avoid an extra address registering stage here.
always @(posedge clk `OR_ASYNC_RST)
if (rst)
dbus_adr_r <= 0;
else if (execute_go & (op_lsu_load_i | op_lsu_store_i))
dbus_adr_r <= lsu_adr_i;
// Big endian bus mapping
always @(*)
case (lsu_length_i)
2'b00: // byte access
case(dbus_adr_o[1:0])
2'b00:
dbus_bsel = 4'b1000;
2'b01:
dbus_bsel = 4'b0100;
2'b10:
dbus_bsel = 4'b0010;
2'b11:
dbus_bsel = 4'b0001;
endcase
2'b01: // halfword access
case(dbus_adr_o[1])
1'b0:
dbus_bsel = 4'b1100;
1'b1:
dbus_bsel = 4'b0011;
endcase
2'b10,
2'b11:
dbus_bsel = 4'b1111;
endcase
assign dbus_bsel_o = dbus_bsel;
assign dbus_we_o = op_lsu_store_i;
// Select part of read word
// Can use registered address here, as it'll take at least one cycle for
// the data to come back, and by that time dbus_adr_r has the address
always @*
case(dbus_adr_r[1:0])
2'b00:
dbus_dat_aligned = dbus_dat_i;
2'b01:
dbus_dat_aligned = {dbus_dat_i[23:0],8'd0};
2'b10:
dbus_dat_aligned = {dbus_dat_i[15:0],16'd0};
2'b11:
dbus_dat_aligned = {dbus_dat_i[7:0],24'd0};
endcase // case (dbus_adr_r[1:0])
// Do appropriate extension
always @(*)
case({lsu_zext_i, lsu_length_i})
3'b100: // lbz
dbus_dat_extended = {24'd0,dbus_dat_aligned[31:24]};
3'b101: // lhz
dbus_dat_extended = {16'd0,dbus_dat_aligned[31:16]};
3'b000: // lbs
dbus_dat_extended = {{24{dbus_dat_aligned[31]}},
dbus_dat_aligned[31:24]};
3'b001: // lhs
dbus_dat_extended = {{16{dbus_dat_aligned[31]}},
dbus_dat_aligned[31:16]};
default:
dbus_dat_extended = dbus_dat_aligned;
endcase
// Register result incase writeback doesn't occur for a few cycles
// TODO - remove this - we should write straight into the RF!
always @(posedge clk)
if (dbus_ack_i & op_lsu_load_i)
lsu_result_r <= dbus_dat_extended;
assign dbus_burst_o = 0;
// Break up paths of signals which are usually pretty long
generate
if (OPTION_REGISTERED_IO!="NO")
begin : registered_io
assign dbus_adr_o = dbus_adr_r;
always @(posedge clk)
begin
dbus_err_r <= dbus_err_i;
op_lsu <= op_lsu_load_i | op_lsu_store_i;
end
// Make sure padv_i isn't high because we'll be registering the
// fact that this cycle is an LSU op while it is
assign dbus_req_o = !execute_go & op_lsu &
!(except_align | except_align_r) &
!access_done;
assign except_align = op_lsu & (op_lsu_load_i | op_lsu_store_i) &
align_err & !execute_go;
end
else
begin : nonregistered_io
assign dbus_adr_o = execute_go ? lsu_adr_i : dbus_adr_r;
always @*
begin
dbus_err_r = dbus_err_i;
op_lsu = op_lsu_load_i | op_lsu_store_i;
end
assign dbus_req_o = op_lsu & !except_align & !access_done;
assign except_align = op_lsu & align_err;
end
endgenerate
assign lsu_result_o = access_done ? lsu_result_r : dbus_dat_extended;
endmodule // mor1kx_lsu
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_drp
*/
module test_wb_drp;
// Parameters
parameter ADDR_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wb_adr_i = 0;
reg [15:0] wb_dat_i = 0;
reg wb_we_i = 0;
reg wb_stb_i = 0;
reg wb_cyc_i = 0;
reg [15:0] drp_di = 0;
reg drp_rdy = 0;
// Outputs
wire [15:0] wb_dat_o;
wire wb_ack_o;
wire [ADDR_WIDTH-1:0] drp_addr;
wire [15:0] drp_do;
wire drp_en;
wire drp_we;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wb_adr_i,
wb_dat_i,
wb_we_i,
wb_stb_i,
wb_cyc_i,
drp_di,
drp_rdy
);
$to_myhdl(
wb_dat_o,
wb_ack_o,
drp_addr,
drp_do,
drp_en,
drp_we
);
// dump file
$dumpfile("test_wb_drp.lxt");
$dumpvars(0, test_wb_drp);
end
wb_drp #(
.ADDR_WIDTH(ADDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i),
.wb_stb_i(wb_stb_i),
.wb_ack_o(wb_ack_o),
.wb_cyc_i(wb_cyc_i),
.drp_addr(drp_addr),
.drp_do(drp_do),
.drp_di(drp_di),
.drp_en(drp_en),
.drp_we(drp_we),
.drp_rdy(drp_rdy)
);
endmodule
|
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