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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_BLACKBOX_V
/**
* udp_dff$PR_pp$sN: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$sN (
Q ,
D ,
CLK ,
RESET ,
SLEEP_B ,
NOTIFIER
);
output Q ;
input D ;
input CLK ;
input RESET ;
input SLEEP_B ;
input NOTIFIER;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_SN_BLACKBOX_V
|
/*************************************************************************
* This file is part of Stierlitz: *
* https://github.com/asciilifeform/Stierlitz *
*************************************************************************/
/**************************************************************************
* (c) Copyright 2012 Stanislav Datskovskiy *
* http://www.loper-os.org *
**************************************************************************
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
* *
*************************************************************************/
/**************************************************************************/
module stierlitz
(clk,
reset,
enable,
/* Control wiring */
bus_ready,
bus_address,
bus_data,
bus_rw,
bus_start_op,
/* CY7C67300 wiring */
cy_hpi_address,
cy_hpi_data,
cy_hpi_oen,
cy_hpi_wen,
cy_hpi_csn,
cy_hpi_irq,
cy_hpi_resetn
);
/**************************************************************************/
localparam [1:0] /* The four HPI addresses: */
HPI_REG_DMA_DATA = 2'b00, /* Put or get DMA data. (R/W) */
HPI_REG_MAILBOX = 2'b01, /* Send or receive data using Mailbox. (R/W) */
HPI_REG_DMA_ADDRESS = 2'b10, /* Latch address for start of DMA transaction. (W) */
HPI_REG_STATUS = 2'b11; /* Read chip status register, for free. (R) */
localparam [2:0]
STATE_IDLE = 0,
STATE_MBX_READ_1 = 1,
STATE_MBX_READ_2 = 2,
STATE_MBX_WRITE_1 = 3,
STATE_MBX_WRITE_2 = 4,
STATE_CMD = 5,
STATE_BUS_READ = 6,
STATE_BUS_WRITE = 7;
/**************************************************************************/
/**************************************************************************/
/* System */
input wire clk; /* ? MHz (? x max HPI freq.) */
input wire reset; /* Active-high */
input wire enable; /* Active-high. */
/* Bus interface */
output wire [40:0] bus_address; /* LBA of active block and block offset. */
inout wire [7:0] bus_data; /* Data in/out on bus. */
output wire bus_rw; /* Bus Op type: 1=Read 0=Write*/
output wire bus_start_op; /* Start of operation (active-high.) */
input wire bus_ready; /* Bus is ready (high) if no op is in progress. */
/* Connections to CY7C67300 */
output wire [1:0] cy_hpi_address; /* Select HPI register. */
inout wire [15:0] cy_hpi_data; /* Bidirectional HPI data. */
output wire cy_hpi_oen; /* HPI Read Enable (active-low) */
output wire cy_hpi_wen; /* HPI Write Enable (active-low) */
output wire cy_hpi_csn; /* HPI Chip Select (active-low) */
input wire cy_hpi_irq; /* HPI IRQ line (active-high) */
output wire cy_hpi_resetn; /* HPI Chip Reset (active-low) */
/**************************************************************************/
/**************************************************************************/
/* Bus (user) side */
reg [7:0] LBA [3:0]; /* Current LBA address */
reg [8:0] byte_offset; /* Offset of current byte in block. */
assign bus_address[8:0] = byte_offset;
assign bus_address[16:9] = LBA[0];
assign bus_address[24:17] = LBA[1];
assign bus_address[32:25] = LBA[2];
assign bus_address[40:33] = LBA[3];
reg [7:0] bus_byte_out;
reg bus_rw_control; /* Bus Op type: 1=Read 0=Write*/
assign bus_rw = bus_rw_control;
assign bus_data = bus_rw_control ? 8'bz : bus_byte_out;
reg bus_op;
assign bus_start_op = bus_op;
/**************************************************************************/
/**************************************************************************/
/* HPI side */
assign cy_hpi_csn = ~enable;
assign cy_hpi_resetn = ~reset; /* TODO: proper reset logic? */
assign cy_hpi_address[1:0] = HPI_REG_MAILBOX; /* For now, no DMA support. */
reg read_enable;
reg write_enable;
assign cy_hpi_oen = ~read_enable;
assign cy_hpi_wen = ~write_enable; /* CY latches data on the rising edge of WEN */
wire output_enable;
assign output_enable = write_enable & ~(read_enable) & enable;
reg [15:0] hpi_data_out_reg;
assign cy_hpi_data = output_enable ? hpi_data_out_reg : 16'bz;
reg [15:0] hpi_data_in_reg;
/**************************************************************************/
reg [2:0] hpi_state; /* Current FSM state */
always @(posedge clk, posedge reset)
if (reset)
begin
read_enable <= 0;
write_enable <= 0;
bus_rw_control <= 1;
hpi_data_in_reg <= 0;
hpi_data_out_reg <= 0;
LBA[0] <= 0;
LBA[1] <= 0;
LBA[2] <= 0;
LBA[3] <= 0;
bus_op <= 0;
bus_byte_out <= 0;
byte_offset <= 0;
hpi_state = STATE_IDLE;
end
else
begin
case (hpi_state)
STATE_IDLE:
begin
read_enable <= 0;
write_enable <= 0;
bus_rw_control <= 1;
/* Idle forever until IRQ is received. */
hpi_state = cy_hpi_irq ? STATE_MBX_READ_1 : STATE_IDLE;
end
STATE_MBX_READ_1:
begin
read_enable <= 1;
write_enable <= 0;
hpi_state = STATE_MBX_READ_2;
end
STATE_MBX_READ_2:
begin
read_enable <= 1;
write_enable <= 0;
hpi_data_in_reg <= cy_hpi_data;
hpi_state = STATE_CMD;
end
STATE_MBX_WRITE_1:
begin
read_enable <= 0;
write_enable <= 1;
bus_op <= 0;
hpi_state = STATE_MBX_WRITE_2;
end
STATE_MBX_WRITE_2:
begin
read_enable <= 0;
write_enable <= 0;
/* Increment block offset only if op is done. */
byte_offset <= bus_ready ? (byte_offset + 1) : byte_offset;
hpi_state = STATE_IDLE;
end
STATE_CMD:
begin
read_enable <= 0;
write_enable <= 0;
case (hpi_data_in_reg[15:14])
2'b00:
begin
/* Set nth byte of LBA address (0...3) */
LBA[(hpi_data_in_reg[9:8])] <= hpi_data_in_reg[7:0];
byte_offset <= 0; /* Reset block offset when setting LBA */
hpi_state = STATE_IDLE;
end
2'b10:
begin
/* HPI byte will be written on bus. */
bus_byte_out <= hpi_data_in_reg[7:0];
bus_rw_control <= 0; /* WRITE */
hpi_state = STATE_BUS_WRITE;
end
2'b01:
begin
/* Byte will be read from bus and sent back on HPI. */
bus_rw_control <= 1; /* READ */
bus_op <= 1;
hpi_state = STATE_BUS_READ;
end
default:
begin
/* Malformed command? Do nothing. */
hpi_state = STATE_IDLE;
end
endcase // case (hpi_data_in_reg[15:14])
end
STATE_BUS_READ:
begin
read_enable <= 0;
write_enable <= 0;
hpi_data_out_reg[7:0] <= bus_data; /* Read a byte off the bus. */
/* Spin until the bus is READY again. Then send back the byte read. */
hpi_state = bus_ready ? STATE_MBX_WRITE_1 : STATE_BUS_READ;
end
STATE_BUS_WRITE:
begin
read_enable <= 0;
write_enable <= 0;
bus_op <= 1;
/* Spin until the bus is READY again. Then write back byte written. */
hpi_state = bus_ready ? STATE_MBX_WRITE_1 : STATE_BUS_WRITE;
end
default:
begin
read_enable <= 0;
write_enable <= 0;
hpi_state = STATE_IDLE;
end
endcase // case (state)
end // else: !if(reset)
/**************************************************************************/
endmodule
/**************************************************************************/
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns / 1ps
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [31:0] sum;
wire [8:0] Output;
wire [8:0] Input = crc[8:0];
assigns assigns (/*AUTOINST*/
// Outputs
.Output (Output[8:0]),
// Inputs
.Input (Input[8:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module assigns(Input, Output);
input [8:0] Input;
output [8:0] Output;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : ap
assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200000 + 5, inf = 2e9; const long double EPS = 1e-9L; vector<pair<int, int> > pairs[26]; vector<int> mn[26]; int leftSub[N], rightSub[N]; void computeSub(string& a, string& b, int ans[]) { for (int i = 0; i < (int)(a).size(); ++i) { int prv = 0; if (i != 0) prv = ans[i - 1]; if (prv == (int)(b).size() || a[i] != b[prv]) ans[i] = ans[i - 1]; else ans[i] = 1 + ans[i - 1]; } } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s, t; cin >> s >> t; for (int i = 0; i < (int)(t).size(); ++i) { int l = i, r = (int)(t).size() - 1 - i; pairs[t[i] - a ].push_back({l, r}); } for (int c = 0; c < 26; ++c) { sort(pairs[c].begin(), pairs[c].end()); for (int i = 0; i < (int)(pairs[c]).size(); ++i) { if (i == 0) mn[c].push_back(pairs[c][i].second); else mn[c].push_back(min(pairs[c][i].second, mn[c][i - 1])); } } computeSub(s, t, leftSub); reverse(s.begin(), s.end()), reverse(t.begin(), t.end()); computeSub(s, t, rightSub); reverse(s.begin(), s.end()), reverse(rightSub, rightSub + (int)(s).size()); for (int i = 0; i < (int)(s).size(); ++i) { int a = 0, b = 0; if (i != 0) a = leftSub[i - 1]; if (i != (int)(s).size() - 1) b = rightSub[i + 1]; pair<int, int> p = {a, inf}; if (pairs[s[i] - a ].empty() || pairs[s[i] - a ][0] > p) { cout << No n ; return 0; } int ind = upper_bound(pairs[s[i] - a ].begin(), pairs[s[i] - a ].end(), p) - begin(pairs[s[i] - a ]); if (mn[s[i] - a ][ind - 1] > b) { cout << No n ; return 0; } } cout << Yes n ; }
|
#include <bits/stdc++.h> using namespace std; int n; long long a[200100]; long long t[800800]; long long d[800800]; void build(int v, int tl, int tr) { if (tl == tr) { t[v] = a[tl]; } else { int tm = (tl + tr) / 2; build(2 * v, tl, tm); build(2 * v + 1, tm + 1, tr); t[v] = t[2 * v] + t[2 * v + 1]; } } int ind(int v, int tl, int tr, int pos) { if (tl == tr) { return v; } else { int tm = (tl + tr) / 2; if (pos <= tm) { return ind(2 * v, tl, tm, pos); } else { return ind(2 * v + 1, tm + 1, tr, pos); } } } void push(int v, int tl, int tr) { if (d[v] != 0 && 2 * v + 1 < 800800) { d[2 * v] += d[v]; d[2 * v + 1] += d[v]; int tm = (tl + tr) / 2; t[2 * v] += (tm - tl + 1) * d[v]; t[2 * v + 1] += (tr - tm) * d[v]; d[v] = 0; } } long long sum(int v, int tl, int tr, int l, int r) { if (l <= tl && tr <= r) { return t[v]; } if (l > tr || tl > r) { return 0; } int tm = (tl + tr) / 2; push(v, tl, tr); return sum(2 * v, tl, tm, l, r) + sum(2 * v + 1, tm + 1, tr, l, r); } void update(int v, int tl, int tr, int l, int r, int x) { if (l <= tl && tr <= r) { d[v] += x; t[v] += (tr - tl + 1) * x; return; } if (l > tr || tl > r) { return; } int tm = (tl + tr) / 2; push(v, tl, tr); update(2 * v, tl, tm, l, r, x); update(2 * v + 1, tm + 1, tr, l, r, x); t[v] = t[2 * v] + t[2 * v + 1]; } void update_new_val(int v, int tl, int tr, int pos, int new_val) { if (tl == tr) { t[v] = new_val; } else { int tm = (tl + tr) / 2; push(v, tl, tr); if (pos <= tm) { update_new_val(2 * v, tl, tm, pos, new_val); } else { update_new_val(2 * v + 1, tm + 1, tr, pos, new_val); } t[v] = t[2 * v] + t[2 * v + 1]; } } int main() { for (int i = 0; i < 200100; i++) { a[i] = 0; } scanf( %d , &n); long long l = 1; for (int i = 0; i < 800800; i++) { d[i] = 0; } build(1, 0, 200099); for (int i = 0; i < n; i++) { int z; scanf( %d , &z); if (z == 1) { int k; long long x; cin >> k >> x; if (x != 0) { update(1, 0, 200099, 0, k - 1, x); } } if (z == 2) { long long new_val; cin >> new_val; update_new_val(1, 0, 200099, l, new_val); l++; } if (z == 3) { update_new_val(1, 0, 200099, l - 1, 0); l--; } long long s = sum(1, 0, 200099, 0, 200099); double q = l * 1.0; double sr = (1.0 * s) / q; printf( %.10f n , sr); } return 0; }
|
module fetch(IR_load_mux,new_IR_multi,equ,pr2_IR ,pr3_IR ,pr4_IR, pr5_IR,fromPipe2_PCim, fromPipe2_970, fromPipe3RFOut, fromPipe3PCInc, fromPipe4_Aluout, fromPipe5Mem, PCWrite, PCOut, IROut, incPCOut, clk, reset);
output [15:0] PCOut, IROut, incPCOut;
input [15:0]new_IR_multi;
wire [15:0] next_IR;//read from instruction memory
input IR_load_mux;
input [15:0] fromPipe2_PCim, fromPipe2_970, fromPipe3RFOut, fromPipe3PCInc, fromPipe4_Aluout, fromPipe5Mem;
input [15:0] pr2_IR ,pr3_IR ,pr4_IR, pr5_IR;
wire [ 2:0] fromForwarding;
input PCWrite, clk, reset;
input equ;
wire [15:0] PCWriteWire;
pc_forwarding f_u(.clk(clk),.equ(equ),.pr2_IR(pr2_IR),.pr3_IR(pr3_IR),.pr4_IR(pr4_IR),.pr5_IR(pr5_IR),.pc_mux_select(fromForwarding)) ;
mux16x8 PCWriteSelect(.data0(incPCOut), .data1(fromPipe3RFOut), .data2(fromPipe5Mem), .data3(fromPipe2_PCim), .data4(fromPipe3PCInc), .data5(fromPipe2_970), .data6(fromPipe4_Aluout), .data7(16'b0), .selectInput(fromForwarding), .out(PCWriteWire));
register16 PCReg(.clk(clk), .out(PCOut), .in(PCWriteWire), .write(PCWrite), .reset(reset));
plus_one PlusOne(.in(PCOut), .out(incPCOut));
instr_mem InstructionMemory(.readAdd(PCOut), .out(next_IR));
mux16x2 IR_write_select(.data0(next_IR), .data1(new_IR_multi), .selectInput(IR_load_mux), out(IROut));
endmodule
module pc_forwarding(clk,equ,pr2_IR,pr3_IR,pr4_IR,pr5_IR,pc_mux_select);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
parameter rb=3'd1;
parameter c=3'd2;
parameter m= 3'd3;
parameter one = 3'd4;
parameter h = 3'd5;
parameter a = 3'd6;
output reg [2:0] pc_mux_select;
input [15:0] pr2_IR,pr3_IR,pr4_IR,pr5_IR;
input equ,clk;
wire [5:0] op2,op3,op4,op5;
wire[2:0] pr2RA,pr2RB,pr4RC,pr5RA;
assign op2={pr2_IR[15:12],pr2_IR[1:0]};
assign op3={pr3_IR[15:12],pr3_IR[1:0]};
assign op4={pr4_IR[15:12],pr4_IR[1:0]};
assign op5={pr5_IR[15:12],pr5_IR[1:0]};
assign pr2RA = pr2_IR[11:9];
assign pr2RB = pr2_IR[8:6];
assign pr4RC = pr2_IR[5:3];
assign pr5RA = pr5_IR[11:9];
always @(negedge clk)
begin
if((op5[5:2]==LW||op5[5:2]==LM)&&pr5RA==3'b111)
pc_mux_select=c;//from mem
else if(op2[5:2]==LHI&&pr2RA==3'b111)
pc_mux_select=h;//970 from pr2
else if((op4==ADD||op4==NDU||op4==ADC||op4==ADZ||op4==NDC||op4==NDC||op4==NDZ)&&(pr4RC==3'b111))
pc_mux_select=a;//ALU_out in pr4
else if(op4[5:2]==ADI&&pr2RB==3'b111)
pc_mux_select=a;//ALU_out in pr4
else if(equ==1&&op3[5:2]==BEQ)
pc_mux_select=one;//pc+Im6, in pr3
else if(op3[5:2]==JLR)
pc_mux_select=rb;//from RFout2 of pr3
else if(op2[5:2]==JAL)
pc_mux_select=m;//PC+Im6 , in pr2
else
pc_mux_select=0;
end//always
endmodule
|
`include "bsg_defines.v"
`include "config_defs.v"
module config_snooper_bind
(input clk, // this reflects the destiniation domain clock
input [data_max_bits_lp - 1 : 0] id_o,
input [data_max_bits_lp - 1 : 0] data_o);
logic [data_max_bits_lp - 1 : 0] id_o_r, id_o_n;
logic [data_max_bits_lp - 1 : 0] data_o_r, data_o_n;
logic [id_width_lp - 1 : 0] id_o_ref;
logic [data_max_bits_lp - 1 : 0] data_o_ref;
integer test_file;
integer rt, ch;
integer has_reset = 0;
integer node_id = -1;
integer test_sets = -1;
integer node_id_found = 0;
integer restart_pos; // start position of valid references
integer errors = 0;
initial
begin: initial_open_file
if ($test$plusargs("config-snooper-bind")) begin
test_file = $fopen("config_test.in", "r"); // open config_probe.in file to read
end else begin
test_file = 0;
end
if (!test_file) begin
disable initial_open_file;
end
id_o_ref = '0;
data_o_ref = '0; // need initialization to get rid of Lint warning about never assigning variables
ch = $fgetc(test_file);
while(ch != -1) begin // end of file
if ( (ch == "#") || (ch == " ") ) begin // comments, and white spaces are skipped
rt = $ungetc(ch, test_file);
while ( (ch != "\n") && (ch != -1) ) begin // dump chars until the end of this line
ch = $fgetc(test_file);
end
end else if (ch == "\n") begin // empty newlines are also skipped
ch = $fgetc(test_file);
continue;
end else begin
rt = $ungetc(ch, test_file);
restart_pos = $ftell(test_file); // bookmark the test_file position
rt = $fscanf(test_file, "%d\t\t%b\n", id_o_ref, data_o_ref);
break; // to be continued from here
end
ch = $fgetc(test_file);
end
end
assign id_o_n = id_o;
assign data_o_n = data_o;
always @ (posedge clk) begin
id_o_r <= id_o_n;
data_o_r <= data_o_n;
end
// Since the design is synchronized to posedge of clk, using negedge clk
// here is to allow all flip-flops become stable in the register connected
// to data_o. This might guarantee simulation correct even at gate level,
// when all flip-flops don't necessarily change at the same time.
always @ (negedge clk)
begin: always_check_change
if (test_file) begin
if (has_reset == 0) begin // reset value check
if (data_o === '0) begin
$display("\n @time %0d: \t snooper node data_o reset to %b", $time, data_o);
has_reset = 1;
end
end else begin
if ( (id_o !== id_o_r) || (data_o !== data_o_r) ) begin
$display("\n @time %0d: \t snooped id, tag, and data changed to %d, %b, %b", $time, id_o[0 +: id_width_lp], id_o[id_width_lp +: id_tag_bits_lp], data_o);
if (data_o !== data_o_ref) begin
$display("\n @time %0d: \t ERROR snooped data_o = %b <-> expected = %b", $time, data_o, data_o_ref);
errors += 1;
end
if (id_o[0 +: id_width_lp] !== id_o_ref) begin
$display("\n @time %0d: \t ERROR snooped id_o = %d <-> expected = %d", $time, id_o[0 +: id_width_lp], id_o_ref);
errors += 1;
end
ch = $fgetc(test_file);
if (ch == -1) begin // end of file
if ($test$plusargs("cyclic-test")) begin
rt = $fseek(test_file, restart_pos, 0); // circulate
rt = $fscanf(test_file, "%d\t\t%b\n", id_o_ref, data_o_ref);
has_reset = 0;
end
end else begin
rt = $ungetc(ch, test_file);
rt = $fscanf(test_file, "%d\t\t%b\n", id_o_ref, data_o_ref);
end
end
end
end else begin
disable always_check_change;
end
end
final
begin: final_statistics
if (test_file) begin
if (has_reset == 0) begin
$display("### FAILED: Snooper node has not reset properly!\n");
end else begin
if (errors != 0) begin
$display("### FAILED: Snooper node has detected at least %0d wrong packet(s)!\n", errors);
end else begin
$display("### PASSED: Snooper node is probably working properly.\n");
end
end
$fclose(test_file);
end else begin
disable final_statistics;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 14; const int INF = 0x3f3f3f3f; int N, M; vector<int> G[Maxn + 5]; void addedge(int u, int v) { G[u].push_back(v), G[v].push_back(u); } int f[(1 << Maxn) + 5]; pair<int, int> last[(1 << Maxn) + 5]; int lasts[(1 << Maxn) + 5]; bool go[Maxn + 3][Maxn + 3][(1 << Maxn) + 3]; int lastnode[Maxn + 3][Maxn + 3][(1 << Maxn) + 3]; inline int lowbit(int x) { return x & (-x); } inline int bitcount(int x) { int ret = 0; while (x) ret++, x -= lowbit(x); return ret; } int main() { scanf( %d %d , &N, &M); for (int i = 1; i <= M; i++) { int u, v; scanf( %d %d , &u, &v); addedge(u, v); } memset(f, 0x3f, sizeof f); for (int u = 1; u <= N; u++) for (auto v : G[u]) go[u][v][0] = true, lastnode[u][v][0] = u; for (int s = 0; s < (1 << N); s++) for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) { if ((s & (1 << (i - 1))) || (s & (1 << (j - 1))) || i == j || !go[i][j][s]) continue; for (auto k : G[j]) { if (s & (1 << (k - 1)) || k == i && s == 0) continue; int t = s ^ (1 << (j - 1)); if (!go[i][k][t]) go[i][k][t] = true, lastnode[i][k][t] = j; } } f[1] = 0; for (int s = 0; s < (1 << N); s++) for (int t = s; t; t = (t - 1) & s) { int lst = s ^ t; int cnt = bitcount(t) + 1; if (f[lst] + cnt >= f[s]) continue; for (int u = 1; u <= N; u++) { if (!(lst & (1 << (u - 1)))) continue; for (int v = 1; v <= N; v++) { if (!(lst & (1 << (v - 1)))) continue; if (go[u][v][t]) { f[s] = f[lst] + cnt; last[s] = make_pair(u, v); lasts[s] = t; } } } } if (f[(1 << N) - 1] == INF) { puts( -1 ); return 0; } printf( %d n , f[(1 << N) - 1]); int t = (1 << N) - 1; while (t != 1) { int lst = lasts[t]; int x = last[t].first, y = last[t].second; t ^= lst; while (lst) { int z = lastnode[x][y][lst]; printf( %d %d n , y, z); lst ^= (1 << (z - 1)); y = z; } printf( %d %d n , x, y); } return 0; }
|
`include "timescale.v"
module fb_slave_mac (MRxClk, MRxDV, MRxD, Reset, TxData,
SlaveDataStartCnt, SlaveDataEndCnt, LastSlave, TotalFrmNibbleCnt,
MTxD, MTxEn, RxData, RxValid, RxRamAddr, TxRamAddr
CrcError,
StateIdle, StatePreamble, StateFFS, StateData, StateSlaveData, StateSlaveCrc, StateFrmCrc
);
input MRxClk;
input MRxDV; // from PHY
input [3:0] MRxD; // from PHY
input Reset;
input [7:0] TxData; // from memory
input SlaveDataStartCnt; // from register
input SlaveDataEndCnt; // from register
input LastSlave; // from register
input TotalFrmNibbleCnt; // from register(from Preamble to CRCn, no frame CRC)
output [3:0] MTxD; // to PHY
output MTxEn; // to PHY
output [7:0] RxData; // to rx memory
output RxValid;
output CrcError;
output [7:0] TxRamAddr; // tx memory address
output [7:0] RxRamAddr; // rx memory address
output StateIdle;
output StatePreamble;
output StateFFS;
output StateData;
output StateSlaveData;
output StateSlaveCrc;
output StateFrmCrc;
reg [7:0] RxData; // to rx memory
reg RxValid;
reg [3:0] MRxD_q1; // delayed data, at least 4 nibbles are needed for SoC check
reg [3:0] MRxD_q2;
reg [3:0] MRxD_q3;
reg [3:0] MRxD_q4;
wire MRxDEqDataSoC;
wire MRxDEq5;
wire SlaveDataStart;
wire SlaveDataEnd;
wire SlaveCrcEnd;
wire LastSlave;
wire DataFrameEnd;
wire FrmCrcStateEnd;
wire [7:0] TxRamAddr;
wire [7:0] RxRamAddr;
wire SlaveByteCntEq0;
wire StartIdle;
wire [7:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire [15:0] TotalNibCnt;
wire GenerateRxValid;
wire IncrementTotalNibCnt;
assign MRxDEq5 = MRxD == 4'h5;
assign MRxDEqDataSoC = MRxD == 4'h7;
assign SlaveDataStart = TotalNibCnt == SlaveDataStartCnt;
assign SlaveDataEnd = TotalNibCnt == SlaveDataEndCnt;
assign DataFrameEnd = TotalNibCnt == TotalFrmNibbleCnt;
// latch the received data and delay them
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
MRxD_q1 <= 1'b0;
MRxD_q2 <= 1'b0;
MRxD_q3 <= 1'b0;
MRxD_q4 <= 1'b0;
end
else
begin
MRxD_q1 <= MRxD;
MRxD_q2 <= MRxD_q1;
MRxD_q3 <= MRxD_q2;
MRxD_q4 <= MRxD_q3;
end
end
///////////////////////// Rx State Machine module /////////////////
fb_slave_statem fb_slave_statem_ins
(
.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.MRxDEqDataSoC(MRxDEqDataSoC),
.MRxDEq5(MRxDEq5),
.SlaveDataStart(SlaveDataStart)
.SlaveDataEndSlaveDataEnd
.SlaveCrcEnd(SlaveCrcEnd),
.LastSlave(LastSlave),
.DataFrameEnd(DataFrameEnd),
.FrmCrcStateEnd(FrmCrcStateEnd),
.StateIdle(StateIdle),
.StateFFS(StateFFS),
.StatePreamble(StatePreamble),
.StateData(StateData),
.StateSlaveData(StateSlaveData),
.StateSlaveCrc(StateSlaveCrc),
.StateFrmCrc(StateFrmCrc),
.StartIdle(StartIdle)
);
/////////////////////// Rx counter module ///////////////////////
fb_slave_counters fb_slave_counters_ins
(
.MRxClk(MRxClk),
.Reset(Reset),
.MRxDEqDataSoC(MRxDEqDataSoC),
.StateIdle(StateIdle),
.StatePreamble(StatePreamble),
.StateData(StateData),
.StateSlaveData(StateSlaveData),
.StateSlaveCrc(StateSlaveCrc),
.StateFrmCrc(StateFrmCrc),
.TotalNibCnt(TotalNibCnt),
//.NibCnt(),
.SlaveCrcEnd(SlaveCrcEnd),
.FrmCrcStateEnd(FrmCrcStateEnd),
.TxRamAddr(TxRamAddr),
.RxRamAddr(RxRamAddr),
.SlaveByteCntEq0(SlaveByteCntEq0)
.IncrementTotalNibCnt(IncrementTotalNibCnt)
);
/////////////////////////////// transmitting part //////////////////
always @ (StateData or StateSlaveData or StateSlaveCrc or StateFrmCrc or MRxD_q4 or TxData or Crc or FrmCrc)
begin
if(StateData)
MTxD_d[3:0] = MRxD_q4; // Lower nibbles
else
if(StateSlaveData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibbles
else
if(StateSlaveData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateSlaveCrc)
MTxD_d[3:0] = {~Crc[4], ~Crc[5], ~Crc[6], ~Crc[7]}; // Crc
else
if (StateFrmCrc)
MTxD_d[3:0] = {~FrmCrc[4], ~FrmCrc[5], ~FrmCrc[6], ~FrmCrc[7]};
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= 1'b0;
else
MTxEn <= StateData | (|StateSlaveData) | StateSlaveCrc | StateFrmCrc ;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= 4'h0;
else
MTxD[3:0] <= MTxD_d[3:0];
end
/////////////////////////////// end of transmitting part //////////////////
//
/*
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
DlyCrcCnt[3:0] < 4'h9;
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
// Connecting module Crc
eth_crc crcrx
(.Clk(MRxClk),
.Reset(Reset),
.Data(Data_Crc),
.Enable(Enable_Crc),
.Initialize(Initialize_Crc),
.Crc(Crc),
.CrcError(CrcError)
);
*/
// Output byte stream
assign GenerateRxValid = StateSlaveData[0] & ~SlaveByteCntEq0;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
LatchedByte[7:0] <= 8'h0;
RxData[7:0] <= 8'h0;
end
else
begin
// Latched byte
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
if(GenerateRxValid)
// Data goes through only in data state
RxData[7:0] <= LatchedByte[7:0] & {8{|StateData}};
else
// Delaying data to be valid for two cycles.
// Zero when not active.
RxData[7:0] <= 8'h0; // Output data byte
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid <= 1'b0;
end
else
begin
RxValid <= GenerateRxValid ;
end
end
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateSlaveCrc;
assign Data_Crc = MTxD_d;
assign Initialize_Crc = StateIdle | StateData | EndCrcState;
// Connecting module Crc
fb_crc slavecrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
wire Enable_FrmCrc;
wire [3:0] Data_FrmCrc;
wire Initialize_FrmCrc;
assign Enable_FrmCrc = ~StateFrmCrc;
assign Data_FrmCrc = MTxD_d;
assign Initialize_FrmCrc = StateIdle;
// Connecting module Crc
fb_crc framecrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_FrmCrc), .Enable(Enable_FrmCrc), .Initialize(Initialize_FrmCrc),
.Crc(FrmCrc), .CrcError(FrmCrcError)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> edge[80005]; int cnt[80005]; unsigned long long ret; int n; void dfs(int v, int u) { cnt[v] = 1; unsigned long long val = 1ull * n * (n - 1) / 2ull; for (int i = 0; i < edge[v].size(); i++) { int to = edge[v][i]; if (to == u) continue; dfs(to, v); val -= 1ull * cnt[to] * (cnt[to] - 1) / 2ull; cnt[v] += cnt[to]; } val -= 1ull * (n - cnt[v]) * (n - cnt[v] - 1) / 2ull; ret -= (val * val - (1ull * (n - cnt[v]) * cnt[v]) * (1ull * (n - cnt[v]) * cnt[v])); } int main() { cin >> n; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; edge[u].push_back(v); edge[v].push_back(u); } ret = 1ull * n * (n - 1) / 2ull; ret *= ret; dfs(rand() % n + 1, -1); cout << ret << endl; }
|
#include <bits/stdc++.h> using namespace std; int a, b, c; unsigned long ans = 0; unordered_map<int, int> um; void eval(int x) { int t = 0; for (int i = 1; i <= sqrt(x); ++i) { if (i * i == x) t += 1; else if (x % i == 0) t += 2; } ans += t; um[x] = t; } int main() { cin >> a >> b >> c; for (int i = 1; i <= a; ++i) { for (int j = 1; j <= b; ++j) { for (int k = 1; k <= c; ++k) { if (um.find(i * j * k) != um.end()) ans = (ans + um[i * j * k]) % 1073741824LL; else eval(i * j * k); } } } cout << ans << endl; }
|
module fmrv32im_reg
(
input RST_N,
input CLK,
input [4:0] WADDR,
input WE,
input [31:0] WDATA,
input [4:0] RS1ADDR,
output reg [31:0] RS1,
input [4:0] RS2ADDR,
output reg [31:0] RS2,
// for custom instruction
output [31:0] x10,
output [31:0] x11,
output [31:0] x12,
output [31:0] x13,
output [31:0] x14,
output [31:0] x15,
input PC_WE,
input [31:0] PC_WDATA,
output reg [31:0] PC
);
reg [31:0] reg01, reg02, reg03, reg04, reg05, reg06, reg07,
reg08, reg09, reg0A, reg0B, reg0C, reg0D, reg0E, reg0F,
reg10, reg11, reg12, reg13, reg14, reg15, reg16, reg17,
reg18, reg19, reg1A, reg1B, reg1C, reg1D, reg1E, reg1F;
always @(posedge CLK) begin
if(!RST_N) begin
//reg00 <= 0;
reg01 <= 0;
reg02 <= 0;
reg03 <= 0;
reg04 <= 0;
reg05 <= 0;
reg06 <= 0;
reg07 <= 0;
reg08 <= 0;
reg09 <= 0;
reg0A <= 0;
reg0B <= 0;
reg0C <= 0;
reg0D <= 0;
reg0E <= 0;
reg0F <= 0;
reg10 <= 0;
reg11 <= 0;
reg12 <= 0;
reg13 <= 0;
reg14 <= 0;
reg15 <= 0;
reg16 <= 0;
reg17 <= 0;
reg18 <= 0;
reg19 <= 0;
reg1A <= 0;
reg1B <= 0;
reg1C <= 0;
reg1D <= 0;
reg1E <= 0;
reg1F <= 0;
end else begin
//if(WE && (WADDR == 5'h00)) reg00 <= WDATA;
if(WE && (WADDR == 5'h01)) reg01 <= WDATA;
if(WE && (WADDR == 5'h02)) reg02 <= WDATA;
if(WE && (WADDR == 5'h03)) reg03 <= WDATA;
if(WE && (WADDR == 5'h04)) reg04 <= WDATA;
if(WE && (WADDR == 5'h05)) reg05 <= WDATA;
if(WE && (WADDR == 5'h06)) reg06 <= WDATA;
if(WE && (WADDR == 5'h07)) reg07 <= WDATA;
if(WE && (WADDR == 5'h08)) reg08 <= WDATA;
if(WE && (WADDR == 5'h09)) reg09 <= WDATA;
if(WE && (WADDR == 5'h0A)) reg0A <= WDATA;
if(WE && (WADDR == 5'h0B)) reg0B <= WDATA;
if(WE && (WADDR == 5'h0C)) reg0C <= WDATA;
if(WE && (WADDR == 5'h0D)) reg0D <= WDATA;
if(WE && (WADDR == 5'h0E)) reg0E <= WDATA;
if(WE && (WADDR == 5'h0F)) reg0F <= WDATA;
if(WE && (WADDR == 5'h10)) reg10 <= WDATA;
if(WE && (WADDR == 5'h11)) reg11 <= WDATA;
if(WE && (WADDR == 5'h12)) reg12 <= WDATA;
if(WE && (WADDR == 5'h13)) reg13 <= WDATA;
if(WE && (WADDR == 5'h14)) reg14 <= WDATA;
if(WE && (WADDR == 5'h15)) reg15 <= WDATA;
if(WE && (WADDR == 5'h16)) reg16 <= WDATA;
if(WE && (WADDR == 5'h17)) reg17 <= WDATA;
if(WE && (WADDR == 5'h18)) reg18 <= WDATA;
if(WE && (WADDR == 5'h19)) reg19 <= WDATA;
if(WE && (WADDR == 5'h1A)) reg1A <= WDATA;
if(WE && (WADDR == 5'h1B)) reg1B <= WDATA;
if(WE && (WADDR == 5'h1C)) reg1C <= WDATA;
if(WE && (WADDR == 5'h1D)) reg1D <= WDATA;
if(WE && (WADDR == 5'h1E)) reg1E <= WDATA;
if(WE && (WADDR == 5'h1F)) reg1F <= WDATA;
end
end // always @ (posedge CLK)
always @(posedge CLK) begin
if(!RST_N) begin
RS1 <= 0;
end else begin
case(RS1ADDR)
//5'h00: RS1 <= reg00;
5'h01: RS1 <= reg01;
5'h02: RS1 <= reg02;
5'h03: RS1 <= reg03;
5'h04: RS1 <= reg04;
5'h05: RS1 <= reg05;
5'h06: RS1 <= reg06;
5'h07: RS1 <= reg07;
5'h08: RS1 <= reg08;
5'h09: RS1 <= reg09;
5'h0A: RS1 <= reg0A;
5'h0B: RS1 <= reg0B;
5'h0C: RS1 <= reg0C;
5'h0D: RS1 <= reg0D;
5'h0E: RS1 <= reg0E;
5'h0F: RS1 <= reg0F;
5'h10: RS1 <= reg10;
5'h11: RS1 <= reg11;
5'h12: RS1 <= reg12;
5'h13: RS1 <= reg13;
5'h14: RS1 <= reg14;
5'h15: RS1 <= reg15;
5'h16: RS1 <= reg16;
5'h17: RS1 <= reg17;
5'h18: RS1 <= reg18;
5'h19: RS1 <= reg19;
5'h1A: RS1 <= reg1A;
5'h1B: RS1 <= reg1B;
5'h1C: RS1 <= reg1C;
5'h1D: RS1 <= reg1D;
5'h1E: RS1 <= reg1E;
5'h1F: RS1 <= reg1F;
default: RS1 <= 32'd0;
endcase // case (RS1ADDR)
end
end
always @(posedge CLK) begin
if(!RST_N) begin
RS2 <= 0;
end else begin
case(RS2ADDR)
//5'h00: RS2 <= reg00;
5'h01: RS2 <= reg01;
5'h02: RS2 <= reg02;
5'h03: RS2 <= reg03;
5'h04: RS2 <= reg04;
5'h05: RS2 <= reg05;
5'h06: RS2 <= reg06;
5'h07: RS2 <= reg07;
5'h08: RS2 <= reg08;
5'h09: RS2 <= reg09;
5'h0A: RS2 <= reg0A;
5'h0B: RS2 <= reg0B;
5'h0C: RS2 <= reg0C;
5'h0D: RS2 <= reg0D;
5'h0E: RS2 <= reg0E;
5'h0F: RS2 <= reg0F;
5'h10: RS2 <= reg10;
5'h11: RS2 <= reg11;
5'h12: RS2 <= reg12;
5'h13: RS2 <= reg13;
5'h14: RS2 <= reg14;
5'h15: RS2 <= reg15;
5'h16: RS2 <= reg16;
5'h17: RS2 <= reg17;
5'h18: RS2 <= reg18;
5'h19: RS2 <= reg19;
5'h1A: RS2 <= reg1A;
5'h1B: RS2 <= reg1B;
5'h1C: RS2 <= reg1C;
5'h1D: RS2 <= reg1D;
5'h1E: RS2 <= reg1E;
5'h1F: RS2 <= reg1F;
default: RS2 <= 32'd0;
endcase
end // else: !if(!RST_N)
end
always @(posedge CLK) begin
if(!RST_N) begin
PC <= 0;
end else begin
if(PC_WE) PC <= PC_WDATA;
end
end
assign x10 = reg0A;
assign x11 = reg0B;
assign x12 = reg0C;
assign x13 = reg0D;
assign x14 = reg0E;
assign x15 = reg0F;
endmodule // fmrv32im_reg
|
#include <bits/stdc++.h> int a[3005]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); int cnt = 0; for (int i = 1; i < n; ++i) for (int j = 0; j < i; ++j) if (a[i] < a[j]) ++cnt; if (cnt & 1) printf( %d , cnt * 2 - 1); else printf( %d , 2 * cnt); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 5; const long long MOD = 998244353; int n, k; vector<int> a, b; long long ans[MAXN][3][5]; bool found[MAXN][3][5]; long long mul(long long a, long long b) { return (a * b) % MOD; } long long dp(int pos, int last, int var) { if (pos == 1) return (last == 1) ? 1LL : 0LL; if (found[pos][last][var]) return ans[pos][last][var]; found[pos][last][var] = true; ans[pos][last][var] = 0LL; for (int i = 0; i < var; ++i) if (last == 0 || i != last) { long long koef = 1; if (i == 0) koef = k - var + 1; if (last == 0 && i == 0) koef--; koef = max(koef, 0LL); ans[pos][last][var] = (ans[pos][last][var] + mul(dp(pos - 1, i, var), koef)) % MOD; } return ans[pos][last][var]; } long long calc(const vector<int> &A) { vector<pair<int, int> > fixed; fixed.push_back(pair<int, int>(0, -1)); for (int i = 0; i < A.size(); ++i) { if (A[i] != -1) { fixed.push_back(pair<int, int>(A[i], i)); } } fixed.push_back(pair<int, int>(0, A.size())); long long tmpAns = 1LL; for (int i = 0; i < fixed.size() - 1; ++i) { int l = fixed[i].second, r = fixed[i + 1].second; if (fixed[i].first == 0 && fixed[i + 1].first == 0) { tmpAns = mul(tmpAns, k); for (int j = l + 2; j < r; ++j) tmpAns = mul(tmpAns, k - 1); } else if (fixed[i].first == 0 || fixed[i + 1].first == 0) { for (int j = l + 1; j < r; ++j) tmpAns = mul(tmpAns, k - 1); } else { if (A[l] == A[r]) { tmpAns = mul(tmpAns, dp(r - l + 1, 1, 2)); } else { tmpAns = mul(tmpAns, dp(r - l + 1, 2, 3)); } } } return tmpAns; } int main() { scanf( %d %d , &n, &k); for (int i = 0; i < n; ++i) { int tmp; scanf( %d , &tmp); if (i % 2) a.push_back(tmp); else b.push_back(tmp); } printf( %lld n , mul(calc(a), calc(b))); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A2111OI_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[300005]; vector<int> v[300005]; int cnt; int main(int argc, char** argv) { int T; cin >> T; while (T--) { int n; cin >> n; a[0] = {-1, 0}; for (int i = 1; i <= n; i++) scanf( %d , &a[i].first), a[i].second = i; sort(a + 1, a + n + 1); for (int i = 1; i <= cnt + 1; i++) v[i].clear(); cnt = 0; for (int i = 1; i <= n; i++) { if (a[i].first != a[i - 1].first) ++cnt; v[cnt].push_back(a[i].second); } int lst = 1, now = 0, ans = 0; v[cnt + 1].push_back(-1); for (int i = 1; i <= cnt + 1; i++) { if (!v[i - 1].size() || v[i][0] > v[i - 1][v[i - 1].size() - 1]) now += v[i].size(); else { for (auto x : v[i]) if (x > v[i - 1][v[i - 1].size() - 1]) ++now; for (auto x : v[lst - 1]) if (x < v[lst][0]) ++now; ans = max(ans, now); lst = i, now = v[i].size(); } int nw = 0; for (int j = 0; j < v[i].size(); j++) { while (nw < v[i + 1].size() && v[i + 1][nw] <= v[i][j]) ++nw; ans = max(ans, j + (int)v[i + 1].size() - nw + 1); } } cout << n - ans << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_8_V
`define SKY130_FD_SC_HDLL__EBUFN_8_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__ebufn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__ebufn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_8_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; long long a[maxn], b[maxn], dp[maxn]; int q[maxn]; int head = 0, tail = 0; double A(int i, int j) { return dp[i] - dp[j]; } double B(int i, int j) { return b[i] - b[j]; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i]; dp[1] = 0; int head = 1, tail = 1; q[tail] = 1; for (int i = 2; i <= n; i++) { while (head < tail && A(q[head + 1], q[head]) / B(q[head + 1], q[head]) >= -a[i]) head++; dp[i] = dp[q[head]] + b[q[head]] * a[i]; while (head < tail && A(i, q[tail]) / B(i, q[tail]) >= A(q[tail], q[tail - 1]) / B(q[tail], q[tail - 1])) tail--; q[++tail] = i; } cout << dp[n] << n ; return 0; }
|
module decoder (cx,d);
output [7:0] d;
input [12:0] cx;
reg [7:0] d;
reg [4:0] s;
reg [12:0] cx1;
parameter s0 = 5'b11001;
parameter s1 = 5'b11000;
parameter s2 = 5'b10010;
parameter s3 = 5'b00010;
parameter s4 = 5'b10110;
parameter s5 = 5'b10000;
parameter s6 = 5'b11100;
parameter s7 = 5'b00000;
parameter s8 = 5'b10000;
parameter s9 = 5'b01000;
parameter s10 = 5'b00100;
parameter s11 = 5'b00010;
parameter s12 = 5'b00001;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
cx1[9] = cx[9];
cx1[10] = cx[10];
cx1[11] = cx[11];
cx1[12] = cx[12];
s[0]= cx[0]+ cx[1]+ cx[2]+ cx[4]+ cx[5]+ cx[6]+ cx[8];
s[1]= cx[0]+ cx[1]+ cx[6]+ cx[9];
s[2]= cx[4]+ cx[6]+ cx[10];
s[3]= cx[2]+ cx[3]+ cx[4]+ cx[11];
s[4]= cx[0]+ cx[12];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
s9:
begin
if(cx[9]==1'b0)
begin
cx1[9]=1'b1;
end
else
begin
cx1[9]=1'b0;
end
end
s10:
begin
if(cx[10]==1'b0)
begin
cx1[10]=1'b1;
end
else
begin
cx1[10]=1'b0;
end
end
s11:
begin
if(cx[11]==1'b0)
begin
cx1[11]=1'b1;
end
else
begin
cx1[11]=1'b0;
end
end
s12:
begin
if(cx[12]==1'b0)
begin
cx1[12]=1'b1;
end
else
begin
cx1[12]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
cx1[9]=cx[9];
cx1[10]=cx[10];
cx1[11]=cx[11];
cx1[12]=cx[12];
end
endcase
d[0] = cx1[0];
d[1] = cx1[1];
d[2] = cx1[2];
d[3] = cx1[3];
d[4] = cx1[4];
d[5] = cx1[5];
d[6] = cx1[6];
d[7] = cx1[7];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; char a[15][15]; vector<long long int> dp[1 << 14][14]; int main() { cin.tie(nullptr); ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> a[i][j]; } } for (int i = 0; i < n; i++) { dp[1 << i][i].push_back(1LL); } for (int i = 1; i < (1 << n); i++) { int p = __builtin_popcount(i); for (int j = 0; j < n; j++) { if (((i >> j) & 1) == 0) continue; for (int k = 0; k < n; k++) { if ((i >> k) & 1) continue; if (dp[i + (1 << k)][k].size() == 0) { dp[i + (1 << k)][k].resize((1 << p)); } int t = 0; if (a[j][k] == 1 ) t = 1; for (int l = 0; l < dp[i][j].size(); l++) { dp[i + (1 << k)][k][t * (1 << (p - 1)) + l] += dp[i][j][l]; } } } } for (int i = 0; i < (1 << (n - 1)); i++) { long long int res = 0; for (int j = 0; j < n; j++) { res += dp[(1 << n) - 1][j][i]; } printf( %lld , res); } printf( n ); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, i, s, f, h, co = 0, sum, savesum, res, re, savere; cin >> n; long long a[n + 1]; for (i = 1; i <= n; i++) { cin >> a[i]; } cin >> s >> f; h = f - s; queue<long long> qu; i = 1; sum = 0; savesum = 0; res = 1; for (i = 1; i <= h; i++) { qu.push(a[i]); sum += a[i]; savesum = sum; } re = s; savere = s; for (i = h + 1; i <= n; i++) { sum += a[i] - qu.front(); qu.pop(); qu.push(a[i]); if (sum > savesum) { res = i - h + 1; savesum = sum; re = s - res + 1; if (re < 1) re += n; savere = re; } else if (sum == savesum) { res = i - h + 1; savesum = sum; re = s - res + 1; if (re < 1) re += n; if (savere > re) savere = re; } } for (i = 1; i <= h; i++) { sum += a[i] - qu.front(); qu.pop(); qu.push(a[i]); if (sum > savesum) { savesum = sum; res = n - h + 1 + i; re = s - res + 1; if (re < 1) re += n; savere = re; } else if (sum == savesum) { res = n - h + 1 + i; re = s - res + 1; if (re < 1) re += n; if (savere > re) savere = re; } } cout << savere; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[300005], b[300005], f[300005], ori[300005]; queue<int> q; int main() { int n, i, j, k, u, v, up = n; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (i = 1; i <= n; i++) { scanf( %d , &b[i]); } q.push(n); f[n] = n; while (!q.empty()) { u = q.front(); q.pop(); for (i = u - a[u]; i <= min(u, up); i++) { v = i + b[i]; if (f[v] != 0) continue; f[v] = u; ori[v] = i; q.push(v); } up = min(u - a[u], up); } if (f[0] == 0) { printf( -1 ); return 0; } vector<int> ans; for (i = 0; i < n; i = f[i]) ans.push_back(i); printf( %d n , ans.size()); for (i = ans.size() - 1; i >= 0; i--) printf( %d , ori[ans[i]]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 5100; int n, T; int pr[MAXN], t[MAXN]; double rest[MAXN]; double dp[MAXN][MAXN]; double pw[MAXN]; int main() { ios_base::sync_with_stdio(false); cin >> n >> T; for (int i = 1; i <= n; ++i) { cin >> pr[i] >> t[i]; double mult = (100. - pr[i]) / 100.; rest[i] = 1.; for (int k = 1; k < t[i]; ++k) { rest[i] *= mult; if (rest[i] < 1e-15) { rest[i] = 0.; } } } dp[0][0] = 1.; for (int i = 1; i <= n; ++i) { if (t[i] == 1) { for (int j = 1; j <= T; ++j) { dp[i][j] = dp[i - 1][j - 1]; } } else { double p = pr[i] / 100., q = 1 - p; double cur_val = 0.; double last_prob = p; { double tmp = q; int pw = t[i] - 2; while (pw) { if (pw & 1) { last_prob *= tmp; } pw /= 2; tmp *= tmp; } if (last_prob < 1e-15) { last_prob = 0.; } } for (int j = 1, r = 0; j <= T; ++j) { if (j > r + (t[i] - 1)) { cur_val -= dp[i - 1][r] * last_prob; ++r; } cur_val *= q; cur_val += p * dp[i - 1][j - 1]; dp[i][j] = cur_val; if (j >= t[i]) { dp[i][j] += rest[i] * dp[i - 1][j - t[i]]; } if (dp[i][j] < 1e-15) { dp[i][j] = 0.; } } } } double res = 0.; for (int i = 1; i < n; ++i) { pw[1] = 1; double q = (100. - pr[i + 1]) / 100.; for (int j = 2; j <= t[i + 1]; ++j) { pw[j] = pw[j - 1] * q; if (pw[j] < 1e-15) { pw[j] = 0.; } } for (int j = t[i + 1] + 1; j <= T; ++j) { pw[j] = 0.; } for (int j = 1; j <= T; ++j) { res += i * dp[i][j] * pw[T + 1 - j]; } } for (int j = 1; j <= T; ++j) { res += n * dp[n][j]; } cout << fixed << setprecision(10); cout << res << n ; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:15:34 03/28/2014
// Design Name: next_pc
// Module Name: D:/XilinxProject/CPU/pc_test.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: next_pc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module pc_test;
// Inputs
reg [31:0] inst;
reg [1:0] pc_source;
reg clk;
// Outputs
reg [31:0] pc;
wire [31:0] npc;
// Instantiate the Unit Under Test (UUT)
next_pc uut (
.inst(inst),
.pc_source(pc_source),
.clk(clk),
.pc(pc),
.npc(npc)
);
always #100
begin clk = ~clk;
inst = inst + 1;
end
initial begin
// Initialize Inputs
inst = 0;
pc_source = 0;
clk = 0;
pc = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:15:34 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module sync_master(
input wire clk, // clock input
input wire clk_2x, // clock 90 input
input wire datain, // data inputs
input wire rst, // reset input
output wire useaout, // useA output for cascade
output wire usebout, // useB output for cascade
output wire usecout, // useC output for cascade
output wire usedout, // useD output for cascade
output wire [1:0] ctrlout, // ctrl outputs for cascade
output reg sdataout // data out
);
wire aa0 ;
wire bb0 ;
wire cc0 ;
wire dd0 ;
reg usea ;
reg useb ;
reg usec ;
reg used ;
reg useaint ;
reg usebint ;
reg usecint ;
reg usedint ;
reg [1:0] ctrlint;
wire sdataa ;
wire sdatab ;
wire sdatac ;
wire sdatad ;
wire [1:0] az ;
wire [1:0] bz ;
wire [1:0] cz ;
wire [1:0] dz ;
reg aap, bbp, ccp, ddp, az2, bz2, cz2, dz2 ;
reg aan, bbn, ccn, ddn ;
reg pipe_ce0 ;
assign useaout = useaint ;
assign usebout = usebint ;
assign usecout = usecint ;
assign usedout = usedint ;
assign ctrlout = ctrlint ;
assign sdataa = {(aa0 && useaint)} ;
assign sdatab = {(bb0 && usebint)} ;
assign sdatac = {(cc0 && usecint)} ;
assign sdatad = {(dd0 && usedint)} ;
//SRL16 saa0(.D(az2), .CLK(clk), .A0(ctrlint[0]), .A1(ctrlint[1]), .A2(1'b0), .A3(1'b0), .Q(aa0));
//SRL16 sbb0(.D(bz2), .CLK(clk), .A0(ctrlint[0]), .A1(ctrlint[1]), .A2(1'b0), .A3(1'b0), .Q(bb0));
//SRL16 scc0(.D(cz2), .CLK(clk), .A0(ctrlint[0]), .A1(ctrlint[1]), .A2(1'b0), .A3(1'b0), .Q(cc0));
//SRL16 sdd0(.D(dz2), .CLK(clk), .A0(ctrlint[0]), .A1(ctrlint[1]), .A2(1'b0), .A3(1'b0), .Q(dd0));
reg [3:0] data_az2;
always@(posedge clk)
data_az2[3:0] <= {data_az2[2:0], az2};
assign aa0 = data_az2[ctrlint];
reg [3:0] data_bz2;
always@(posedge clk)
data_bz2[3:0] <= {data_bz2[2:0], bz2};
assign bb0 = data_bz2[ctrlint];
reg [3:0] data_cz2;
always@(posedge clk)
data_cz2[3:0] <= {data_cz2[2:0], cz2};
assign cc0 = data_cz2[ctrlint];
reg [3:0] data_dz2;
always@(posedge clk)
data_dz2[3:0] <= {data_dz2[2:0], dz2};
assign dd0 = data_dz2[ctrlint];
always @ (posedge clk or posedge rst) begin
if (rst) begin
ctrlint <= 2'b10 ;
useaint <= 1'b0 ; usebint <= 1'b0 ; usecint <= 1'b0 ; usedint <= 1'b0 ;
usea <= 1'b0 ; useb <= 1'b0 ; usec <= 1'b0 ; used <= 1'b0 ;
pipe_ce0 <= 1'b0 ; sdataout <= 1'b1 ;
aap <= 1'b0 ; bbp <= 1'b0 ; ccp <= 1'b0 ; ddp <= 1'b0 ;
aan <= 1'b0 ; bbn <= 1'b0 ; ccn <= 1'b0 ; ddn <= 1'b0 ;
az2 <= 1'b0 ; bz2 <= 1'b0 ; cz2 <= 1'b0 ; dz2 <= 1'b0 ;
end
else begin
az2 <= az[1] ; bz2 <= bz[1] ; cz2 <= cz[1] ; dz2 <= dz[1] ;
aap <= (az ^ az[1]) & ~az[1] ; // find positive edges
bbp <= (bz ^ bz[1]) & ~bz[1] ;
ccp <= (cz ^ cz[1]) & ~cz[1] ;
ddp <= (dz ^ dz[1]) & ~dz[1] ;
aan <= (az ^ az[1]) & az[1] ; // find negative edges
bbn <= (bz ^ bz[1]) & bz[1] ;
ccn <= (cz ^ cz[1]) & cz[1] ;
ddn <= (dz ^ dz[1]) & dz[1] ;
// aap <= (az[1] ^ az2) & ~az2; // find positive edges
// bbp <= (bz[1] ^ bz2) & ~bz2;
// ccp <= (cz[1] ^ cz2) & ~cz2;
// ddp <= (dz[1] ^ dz2) & ~dz2;
// aan <= (az[1] ^ az2) & az2; // find negative edges
// bbn <= (bz[1] ^ bz2) & bz2;
// ccn <= (cz[1] ^ cz2) & cz2;
// ddn <= (dz[1] ^ dz2) & dz2;
usea <= (bbp & ~ccp & ~ddp & aap) | (bbn & ~ccn & ~ddn & aan) ;
useb <= (ccp & ~ddp & aap & bbp) | (ccn & ~ddn & aan & bbn) ;
usec <= (ddp & aap & bbp & ccp) | (ddn & aan & bbn & ccn) ;
used <= (aap & ~bbp & ~ccp & ~ddp) | (aan & ~bbn & ~ccn & ~ddn) ;
if (usea | useb | usec | used) begin
pipe_ce0 <= 1'b1 ;
useaint <= usea ;
usebint <= useb ;
usecint <= usec ;
usedint <= used ;
end
if (pipe_ce0)
sdataout <= sdataa | sdatab | sdatac | sdatad ;
if (usedint & usea) // 'd' going to 'a'
ctrlint <= ctrlint - 1 ;
else if (useaint & used) // 'a' going to 'd'
ctrlint <= ctrlint + 1 ;
end
end
// 320MHz clock domain
// *** do not touch code below ***
wire [1:0] DDRQ;
IDDR IDDR_inst (
.Q1(DDRQ[1]), // 1-bit output for positive edge of clock
.Q2(DDRQ[0]), // 1-bit output for negative edge of clock
.C(clk_2x), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(datain), // 1-bit DDR data input
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
reg [1:0] DDRQ_DLY;
always@(posedge clk_2x)
DDRQ_DLY[1:0] <= DDRQ[1:0];
reg [3:0] DDRQ_DATA;
always@(posedge clk_2x)
DDRQ_DATA[3:0] <= {DDRQ_DLY[1:0], DDRQ[1:0]};
// *** do not touch code above ***
// 160MHz clock domain
reg [3:0] DATA_IN;
always@(posedge clk)
DATA_IN[3:0] <= {DDRQ_DATA[3:0]};
reg [3:0] DATA_IN_DLY;
always@(posedge clk)
DATA_IN_DLY[3:0] <= {DATA_IN[3:0]};
assign az[0] = DATA_IN[3];
assign bz[0] = DATA_IN[2];
assign cz[0] = DATA_IN[1];
assign dz[0] = DATA_IN[0];
assign az[1] = DATA_IN_DLY[3];
assign bz[1] = DATA_IN_DLY[2];
assign cz[1] = DATA_IN_DLY[1];
assign dz[1] = DATA_IN_DLY[0];
//FDC ff_az0(.D(datain), .C(clk), .CLR(rst), .Q(az[0]))/*synthesis rloc = "x0y0" */;
//FDC ff_az1(.D(az[0]), .C(clk), .CLR(rst), .Q(az[1]))/*synthesis rloc = "x2y0" */;
//FDC ff_bz0(.D(datain), .C(clk90), .CLR(rst), .Q(bz[0]))/*synthesis rloc = "x1y0" */;
//FDC ff_bz1(.D(bz[0]), .C(clk), .CLR(rst), .Q(bz[1]))/*synthesis rloc = "x4y0" */;
//FDC ff_cz0(.D(datain), .C(notclk), .CLR(rst), .Q(cz[0]))/*synthesis rloc = "x1y1" */;
//FDC ff_cz1(.D(cz[0]), .C(clk), .CLR(rst), .Q(cz[1]))/*synthesis rloc = "x2y0" */;
//FDC ff_dz0(.D(datain), .C(notclk90), .CLR(rst), .Q(dz[0]))/*synthesis rloc = "x0y1" */;
//FDC ff_dz1(.D(dz[0]), .C(clk90), .CLR(rst), .Q(dz[1]))/*synthesis rloc = "x3y0" */;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_1_V
`define SKY130_FD_SC_LP__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_1_V
|
module Not(input in, output out);
nand g(out, in, in);
}
CHIP Or {
IN a, b;
OUT out;
PARTS:
Not(in=a, out=nota);
Not(in=b, out=notb);
Nand(a=nota, b=notb, out=out);
}
CHIP Xor {
IN a, b;
OUT out;
PARTS:
Nand (a=a, b=b, out= AnandB);
Or (a=a, b=b, out= AorB);
And (a=AnandB, b=AorB, out=out);
}
CHIP And {
IN a, b;
OUT out;
PARTS:
Nand(a=a, b=b, out=AnandB);
Nand(a=AnandB, b=AnandB, out=out);
}
module fulladder (input a, b, c_in, output sum, c_out);
wire s1, c1, c2;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
or g5(c_out, c2, c1) ;
endmodule
CHIP Add16 {
IN a[16], b[16];
OUT out[16];
PARTS:
FullAdder(a=a[0], b=b[0], c=false, sum=out[0], carry=c0);
FullAdder(a=a[1], b=b[1], c=c0, sum=out[1], carry=c1);
FullAdder(a=a[2], b=b[2], c=c1, sum=out[2], carry=c2);
FullAdder(a=a[3], b=b[3], c=c2, sum=out[3], carry=c3);
FullAdder(a=a[4], b=b[4], c=c3, sum=out[4], carry=c4);
FullAdder(a=a[5], b=b[5], c=c4, sum=out[5], carry=c5);
FullAdder(a=a[6], b=b[6], c=c5, sum=out[6], carry=c6);
FullAdder(a=a[7], b=b[7], c=c6, sum=out[7], carry=c7);
FullAdder(a=a[8], b=b[8], c=c7, sum=out[8], carry=c8);
FullAdder(a=a[9], b=b[9], c=c8, sum=out[9], carry=c9);
FullAdder(a=a[10], b=b[10], c=c9, sum=out[10], carry=c10);
FullAdder(a=a[11], b=b[11], c=c10, sum=out[11], carry=c11);
FullAdder(a=a[12], b=b[12], c=c11, sum=out[12], carry=c12);
FullAdder(a=a[13], b=b[13], c=c12, sum=out[13], carry=c13);
FullAdder(a=a[14], b=b[14], c=c13, sum=out[14], carry=c14);
FullAdder(a=a[15], b=b[15], c=c14, sum=out[15], carry=c15);
}
CHIP ALU {
IN
x[16], y[16], // 16-bit inputs
zx, // zero the x input?
nx, // negate the x input?
zy, // zero the y input?
ny, // negate the y input?
f, // compute out = x + y (if 1) or x & y (if 0)
no; // negate the out output?
OUT
out[16], zr, ng;
PARTS:
Mux16(a=x, b=false, sel=zx, out=x1); // if (zx == 1) set x = 0
Not16(in=x1,out=notx1);
Mux16(a=x1, b=notx1, sel=nx, out=x2); // if (nx == 1) set x = !x
Mux16(a=y, b=false, sel=zy, out=y1); // if (zy == 1) set y = 0
Not16(in=y1,out=noty1);
Mux16(a=y1, b=noty1, sel=ny, out=y2); // if (ny == 1) set y = !y
Add16(a=x2, b=y2, out=addxy); // addxy = x + y
And16(a=x2, b=y2, out=andxy); // andxy = x & y
Mux16(a=andxy, b=addxy, sel=f, out=o1); // if (f == 1) set out = x + y else set out = x & y
Not16(in=o1, out=noto1);
Mux16(a=o1, b=noto1, sel=no, out=o2); // if (no == 1) set out = !out
// o2 就是 out, 但必須中間節點才能再次當作輸入，所以先用 o2。
And16(a=o2, b=o2, out[0..7]=outLow, out[8..15]=outHigh);
Or8Way(in=outLow, out=orLow); // orLow = Or(out[0..7]);
Or8Way(in=outHigh, out=orHigh); // orHigh = Or(out[8..15]);
Or(a=orLow, b=orHigh, out=notzr); // nzr = Or(out[0..15]);
Not(in=notzr, out=zr); // zr = !nzr
And16(a=o2, b=o2, out[15]=ng); // ng = out[15]
And16(a=o2, b=o2, out=out);
}
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a[200010], m = INT_MAX; string s; cin >> n >> s; for (int i = 0; i < n; i++) cin >> a[i]; long long int j = -1; for (long long int i = 0; i < s.length(); i++) { if (s[i] == R ) j = i; else { if (j != -1) { long long int temp = abs(a[i] - a[j]) / 2; if (temp < m) m = temp; } } } if (m == INT_MAX) cout << -1; else cout << m; }
|
module pipeline5(
clk_in,
RST,
ctrl_in,
data,
addr,
data_out,
addr_out,
en_out
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// input / output
input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input signed [DATA_WIDTH-1:0] data;
input [REG_ADDR_WIDTH-1:0] addr;
output reg signed [DATA_WIDTH-1:0] data_out;
output reg [REG_ADDR_WIDTH-1:0] addr_out;
output reg en_out;
// repasse dos enderecos data e addr
always @(posedge clk_in) begin
data_out <= data;
addr_out <= addr;
end
// execucao da gravacao nos registradores
always @(posedge clk_in) begin
if (!RST) begin
// rotina de reset
en_out <= 0;
end else begin
// Case para controle de habilitação de escrita no registrador de acordo com o opcode de entrada.
case (ctrl_in)
// ------------ Data Trasnfer -----------------
LW: en_out <= 1;
LW_IMM: en_out <= 1;
// ------------ Arithmetic -----------------
ADD: en_out <= 1;
SUB: en_out <= 1;
MUL: en_out <= 1;
DIV: en_out <= 1;
// ------------ Lógic -----------------
AND: en_out <= 1;
OR : en_out <= 1;
NOT: en_out <= 1;
// ------------ Control Transfer -----------------
// All default
default: en_out <= 0;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int inline read() { int num = 0, neg = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) neg = -1; c = getchar(); } while (isdigit(c)) { num = (num << 3) + (num << 1) + c - 0 ; c = getchar(); } return num * neg; } const int maxn = 500010; int n, T, k, head[maxn], cnt, deg[maxn], used[maxn]; long long f[maxn][2]; struct Edge { int nxt, to, dis; } edge[maxn << 1]; void add_edge(int x, int y, int z) { edge[++cnt].nxt = head[x]; edge[cnt].to = y; edge[cnt].dis = z; head[x] = cnt; } struct Node { int val, id; } A[maxn]; bool cmp(Node x, Node y) { return x.val > y.val; } void dfs(int x, int fa) { int flag = 1; for (int i = head[x]; i; i = edge[i].nxt) { int v = edge[i].to; if (v == fa) continue; flag = 0; dfs(v, x); } int tot = 0; if (flag) return; for (int i = head[x]; i; i = edge[i].nxt) { int v = edge[i].to; if (v == fa) continue; A[++tot].id = v; A[tot].val = f[v][1] + edge[i].dis - f[v][0]; } sort(A + 1, A + tot + 1, cmp); for (int i = 1; i <= min(k, tot); i++) { if (A[i].val <= 0) break; f[x][0] += A[i].val + f[A[i].id][0]; used[A[i].id] = 1; if (i != k) f[x][1] += A[i].val + f[A[i].id][0]; } if (k <= tot && used[A[k].id]) f[x][1] += f[A[k].id][0]; for (int i = head[x]; i; i = edge[i].nxt) { int v = edge[i].to; if (v == fa) continue; if (used[v]) continue; f[x][1] += f[v][0]; f[x][0] += f[v][0]; } } int main() { T = read(); while (T--) { n = read(); k = read(); cnt = 0; long long ans = 0; for (int i = 1; i < n; i++) { int u = read(), v = read(), w = read(); add_edge(u, v, w); add_edge(v, u, w); deg[u]++; deg[v]++; } dfs(1, 0); for (int i = 1; i <= n; i++) ans = max(ans, max(f[i][0], f[i][1])); cout << ans << endl; for (int i = 1; i <= n; i++) head[i] = deg[i] = f[i][0] = f[i][1] = used[i] = 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; int x = min(a, b / 2); int y = min(x, c / 4); cout << y * 7; return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring signed by unsigned divider ////
//// Uses the non-restoring unsigned by unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_su.v,v 1.3 2002-10-31 12:52:54 rherveille Exp $
//
// $Date: 2002-10-31 12:52:54 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/23 09:07:03 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module div_su(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width-1:0] z; // divident
input [d_width-1:0] d; // divisor
output [d_width :0] q; // quotient
output [d_width-1:0] s; // remainder
output div0;
output ovf;
reg [d_width :0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// variables
//
reg [z_width -1:0] iz;
reg [d_width -1:0] id;
reg [d_width +1:0] spipe;
wire [d_width -1:0] iq, is;
wire idiv0, iovf;
//
// module body
//
// delay d
always @(posedge clk)
if (ena)
id <= #1 d;
// check z, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= #1 ~z +1'h1;
else
iz <= #1 z;
// generate spipe (sign bit pipe)
integer n;
always @(posedge clk)
if(ena)
begin
spipe[0] <= #1 z[z_width-1];
for(n=1; n <= d_width+1; n=n+1)
spipe[n] <= #1 spipe[n-1];
end
// hookup non-restoring divider
div_uu #(z_width, d_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(is),
.div0(idiv0),
.ovf(iovf)
);
// correct divider results if 'd' was negative
always @(posedge clk)
if(ena)
if(spipe[d_width+1])
begin
q <= #1 (~iq) + 1'h1;
s <= #1 (~is) + 1'h1;
end
else
begin
q <= #1 {1'b0, iq};
s <= #1 {1'b0, is};
end
// delay flags same as results
always @(posedge clk)
if(ena)
begin
div0 <= #1 idiv0;
ovf <= #1 iovf;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mn = 100010; long long x[mn], y[mn]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld %lld , &x[i], &y[i]); if (n <= 4) { printf( YES n ); return 0; } bool flag = 0; for (int i = 1; i <= 2; i++) { for (int j = i + 1; j <= 3; j++) { long long a = y[j] - y[i]; long long b = x[i] - x[j]; long long c = y[i] * x[j] - y[j] * x[i]; long long xa, ya, xb, yb; int t = 0; int k = 1; for (k = 1; k <= n; k++) { if (a * x[k] + b * y[k] + c == 0) continue; else { t++; if (t == 1) xa = x[k], ya = y[k]; else if (t == 2) xb = x[k], yb = y[k]; else break; } } if (t <= 2) { flag = 1; break; } long long ta = yb - ya; long long tb = xa - xb; long long tc = ya * xb - yb * xa; bool q = 0; for (int p = k; p <= n; p++) { if ((a * x[p] + b * y[p] + c == 0) || ta * x[p] + tb * y[p] + tc == 0) continue; else q = 1; if (q) break; } if (!q) { flag = 1; break; } } if (flag) break; } if (!flag) printf( NO n ); else printf( YES n ); return 0; }
|
#include <bits/stdc++.h> int main(void) { unsigned short int m, n, c; scanf( %hu%hu , &m, &n); c = m * n; int i = 1; while (i) { if (c >= 2 * i) i++; else break; } printf( %d n , (i - 1)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int N; scanf( %d , &N); if (N <= 2) printf( %d , -1); else { for (int i = N; i >= 1; i--) { printf( %d , i); printf( ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__XNOR3_PP_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[200001]; int dis[200001]; int par[200001]; void addEdge(int u, int v) { adj[u].push_back(v); adj[v].push_back(u); } void dfs(int src, int parent, int dist) { dis[src] = dist; par[src] = parent; for (int child : adj[src]) { if (child != parent) { dfs(child, src, dist + 1); } } } int solve() { int n; cin >> n; int u, v; for (int i = 0; i < n - 1; i++) { cin >> u >> v; addEdge(u, v); } dfs(1, 0, 0); set<pair<int, int> > st; for (int i = 1; i <= n; i++) { if (dis[i] > 2) { st.insert({-dis[i], i}); } } int ans = 0; while (!st.empty()) { int rmv = (*st.begin()).second; st.erase(st.begin()); rmv = par[rmv]; auto itr = st.find({-dis[rmv], rmv}); if (itr != st.end()) st.erase(itr); for (int c : adj[rmv]) { if (dis[c] > 2) { itr = st.find({-dis[c], c}); if (itr != st.end()) st.erase(itr); } } ans++; } return ans; } int main() { cout << solve() << n ; }
|
/*
* Integer conversion module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_conv (
input [15:0] x,
input [ 2:0] func,
output [31:0] out,
input [ 1:0] iflags, // afi, cfi
output [ 2:0] oflags // afo, ofo, cfo
);
// Net declarations
wire afi, cfi;
wire ofo, afo, cfo;
wire [15:0] aaa, aas;
wire [ 7:0] daa, tmpdaa, das, tmpdas;
wire [15:0] cbw, cwd;
wire acond, dcond;
wire tmpcf;
// Module instances
zet_mux8_16 mux8_16 (func, cbw, aaa, aas, 16'd0,
cwd, {x[15:8], daa}, {x[15:8], das}, 16'd0, out[15:0]);
// Assignments
assign aaa = (acond ? (x + 16'h0106) : x) & 16'hff0f;
assign aas = (acond ? (x - 16'h0106) : x) & 16'hff0f;
assign tmpdaa = acond ? (x[7:0] + 8'h06) : x[7:0];
assign daa = dcond ? (tmpdaa + 8'h60) : tmpdaa;
assign tmpdas = acond ? (x[7:0] - 8'h06) : x[7:0];
assign das = dcond ? (tmpdas - 8'h60) : tmpdas;
assign cbw = { { 8{x[ 7]}}, x[7:0] };
assign { out[31:16], cwd } = { {16{x[15]}}, x };
assign acond = ((x[7:0] & 8'h0f) > 8'h09) | afi;
assign dcond = (x[7:0] > 8'h99) | cfi;
assign afi = iflags[1];
assign cfi = iflags[0];
assign afo = acond;
assign ofo = 1'b0;
assign tmpcf = (x[7:0] < 8'h06) | cfi;
assign cfo = func[2] ? (dcond ? 1'b1 : (acond & tmpcf))
: acond;
assign oflags = { afo, ofo, cfo };
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_SYMBOL_V
`define SKY130_FD_SC_HVL__MUX4_SYMBOL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__mux4 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X ,
//# {{control|Control Signals}}
input S0,
input S1
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_SYMBOL_V
|
#include <bits/stdc++.h> long long n, k, l, m, ans; struct mat { long long a[3][3]; } A, B; inline mat operator*(mat x, mat y) { mat c; memset(c.a, 0, sizeof c.a); for (int k = (0), __ = (2); k < __; ++k) for (int i = (0), __ = (2); i < __; ++i) for (int j = (0), __ = (2); j < __; ++j) (c.a[i][j] += (x.a[i][k] * y.a[k][j]) % m) %= m; return c; } inline mat operator^(mat a, long long y) { mat c; for (int i = (0), __ = (2); i < __; ++i) for (int j = (0), __ = (2); j < __; ++j) c.a[i][j] = (i == j); while (y) { if (y & 1) c = c * a; a = a * a; y >>= 1; } return c; } long long Pow(long long x) { long long s = 1, c = 2; while (x) { if (x & 1) s = (s * c) % m; c = c * c % m; x >>= 1; } return s; } int main() { mat p, x; p.a[0][0] = 0; p.a[0][1] = 1; p.a[1][0] = 1; p.a[1][1] = 1; x.a[0][0] = 1; x.a[0][1] = 2; x.a[1][0] = 0; x.a[1][1] = 0; std::cin >> n >> k >> l >> m; ans = 0; if (l == 64 || (1ull << l) > k) { ++ans; p = p ^ n; x = x * p; long long t1 = x.a[0][0]; long long t2 = (m + Pow(n) - t1) % m; for (int i = (0), __ = (l); i < __; ++i) { if (k & (1ull << i)) ans = ans * t2 % m; else ans = ans * t1 % m; } } std::cout << ans % m << std::endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s; cin >> s; int sz = s.size(); s = X + s; int k; cin >> k; int ans = 0; for (int i = 1; i <= sz; i++) { for (int len = 1; len <= 400; len++) { if (i + 2 * len - 1 > sz + k) break; bool can = true; for (int l = i; l <= i + len - 1; l++) { if (l > sz) break; if (l + len <= sz) { if (s[l] != s[l + len]) { can = false; break; } } } if (can) ans = max(ans, 2 * len); } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double eps = 1e-6; const int maxn = 3e5 + 10; const int maxm = 1e6 + 10; const long long mod = 998244353; int a[maxn], b[maxn]; bool judge(int mid, int h) { int temph = h; for (int i = 0; i < mid; i++) b[i] = a[i]; sort(b, b + mid); int ans = 0; for (int i = 0; i < mid; i += 2) { if (b[i] <= h) ans++; if (i + 1 < mid && b[i + 1] <= h) ans++; if (i == mid - 1) h -= b[i]; else h -= b[i + 1]; if (h <= 0) break; } if (ans >= mid) return true; ans = 0, h = temph; for (int i = mid - 1; i >= 0; i -= 2) { if (b[i] <= h) ans++; if (i - 1 >= 0 && b[i - 1] <= h) ans++; h -= b[i]; if (h <= 0) break; } return ans >= mid; } int main() { int n, h; cin >> n >> h; for (int i = 0; i < n; i++) cin >> a[i]; int ans = 1; int l = 1, r = n; while (l <= r) { int mid = (l + r) >> 1; if (judge(mid, h)) l = mid + 1, ans = mid; else r = mid - 1; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; int sz[maxn], N, M; int main() { scanf( %d%d , &N, &M); memset(sz, 0, sizeof(sz)); vector<int> cnt; cnt.resize(N); int a, b; for (int i = 1; i <= M; i++) { scanf( %d%d , &a, &b); a--, b--; cnt[a]++, cnt[b]++; } sort(cnt.begin(), cnt.end()); for (int i = 0; i < N; i++) sz[cnt[i]]++; if (sz[2] == N) printf( ring topology n ); else if (sz[1] == 2 && sz[2] == N - 2) printf( bus topology n ); else if (sz[1] == N - 1 && sz[N - 1] == 1) printf( star topology n ); else printf( unknown topology n ); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Roman Popov.
// SPDX-License-Identifier: CC0-1.0
module dut
#(
parameter DEPTH = 16,
parameter WIDTH = 32,
parameter RAM_SPLIT_WIDTH = 16
)
(
output logic [WIDTH-1:0] ram_dataout
);
localparam RAM_ADDR_WIDTH = $clog2(DEPTH); // = 4
localparam NUM_RAM_BLOCKS = (WIDTH/RAM_SPLIT_WIDTH) + {31'h0, ((WIDTH % RAM_SPLIT_WIDTH) > 0)}; // = 2
typedef logic [NUM_RAM_BLOCKS:0][31:0] block_index_t; // width 96
function automatic block_index_t index_calc(input int WIDTH, NUM_RAM_BLOCKS);
index_calc[0] = '0;
for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = WIDTH/NUM_RAM_BLOCKS + {31'h0, (i < (WIDTH%NUM_RAM_BLOCKS))};
for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = index_calc[i+1] + index_calc[i];
// bug1467 was this return
return index_calc;
endfunction
localparam block_index_t RAM_BLOCK_INDEX = index_calc(WIDTH, NUM_RAM_BLOCKS);
generate
begin : ram_dataout_gen
for (genvar i = 0; i < NUM_RAM_BLOCKS; i++) begin
always_comb ram_dataout[RAM_BLOCK_INDEX[i+1]-1:RAM_BLOCK_INDEX[i]] = 0;
end
end
endgenerate
initial begin
if (RAM_BLOCK_INDEX != {32'd32, 32'd16, 32'd0}) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module t
(
input clk,
output logic [31:0] ram_dataout
);
dut dut0(.*);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2, typename T3> struct pair3 { T1 first; T2 second; T3 third; }; template <typename T1, typename T2, typename T3, typename T4> struct pair4 { T1 first; T2 second; T3 third; T4 fourth; }; const long long MOD = 1000000007; const long double PI = acos(-1.0); int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, m; cin >> n; vector<long long> ar(n); for (long long i = 0; i < n; ++i) { cin >> ar[i]; } vector<vector<long long>> ans(n + 1); for (long long len = 1; len <= n; ++len) { vector<long long> temp; long long mx = -1, mn = INT_MAX; multiset<long long> st; auto del = [&](long long val) { auto it = temp.end(); --it; while (1) { if (*it == val) { temp.erase(it); break; } it -= 1; } }; for (long long start = 0; start < n; ++start) { if (temp.size() < len) { temp.push_back(ar[start]); st.insert(ar[start]); } else { if (ar[start] > *st.begin()) { del(*st.begin()); st.erase(st.begin()); st.insert(ar[start]); temp.push_back(ar[start]); } } ans[len] = temp; } } cin >> m; long long l, idx; while (m--) { cin >> l >> idx; cout << ans[l][idx - 1] << endl; } return 0; }
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from rst button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard leds
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
output [23:0] io_led, // LEDs on IO Shield
output [7:0] io_seg, // 7-segment LEDs on IO Shield
output [3:0] io_sel, // Digit select on IO Shield
input [3:0] pb,
input en,
output pm
);
wire rst = ~rst_n; // make rst active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[7:0] = {8{slow_clk}};
reg [25:0] slow_clk_d, slow_clk_q;
reg slow_clk;
always @(slow_clk_q) begin
if (pb[0] && ~(slow_clk_q % 8'hFA)) begin
slow_clk_d = slow_clk_q + 8'hFA;
end else if (pb[1] && ~(slow_clk_q % 11'h4E2)) begin
slow_clk_d = slow_clk_q + 11'h4E2;
end else if (pb[2] && ~(slow_clk_q % 13'h186A)) begin
slow_clk_d = slow_clk_q + 13'h186A;
end else begin
slow_clk_d = slow_clk_q + 1'b1;
end
end
always @(posedge clk, posedge rst) begin
if (rst == 1) begin
slow_clk_q <= 25'b0;
slow_clk <= 1'b0;
end else if (slow_clk_q == 25'h17D7840) begin
slow_clk_q <= 25'b0;
slow_clk <= ~slow_clk;
end else begin
slow_clk_q <= slow_clk_d;
end
end
clock real_deal (
.clk(slow_clk),
.fast_clk(slow_clk_q[16]),
.rst(rst),
.en(~en),
.sec(io_led[7:0]),
.pm(io_led[23:8]),
.io_seg(io_seg),
.io_sel(io_sel)
);
endmodule
|
/* Simple external interrupt controller for MIPSfpga+ system
* managed using AHB-Lite bus
* Copyright(c) 2017 Stanislav Zhelnio
* https://github.com/zhelnio/ahb_lite_eic
*/
module priority_encoder255
(
input [ 255 : 0 ] in,
output reg detect,
output reg [ 7 : 0 ] out
);
wire [3:0] detectL;
wire [5:0] preoutL [3:0];
wire [1:0] preoutM;
//1st order entries
priority_encoder64 e10( in[ 63:0 ], detectL[0], preoutL[0] );
priority_encoder64 e11( in[ 127:64 ], detectL[1], preoutL[1] );
priority_encoder64 e12( in[ 191:128 ], detectL[2], preoutL[2] );
priority_encoder64 e13( in[ 255:192 ], detectL[3], preoutL[3] );
always @ (*)
casez(detectL)
default : {detect, out} = 9'b0;
4'b0001 : {detect, out} = { 3'b100, preoutL[0] };
4'b001? : {detect, out} = { 3'b101, preoutL[1] };
4'b01?? : {detect, out} = { 3'b110, preoutL[2] };
4'b1??? : {detect, out} = { 3'b111, preoutL[3] };
endcase
endmodule
module priority_encoder64
(
input [ 63 : 0 ] in,
output detect,
output [ 5 : 0 ] out
);
wire [7:0] detectL;
wire [2:0] preoutL [7:0];
wire [2:0] preoutM;
//3rd order entries
priority_encoder8 e30( in[ 7:0 ], detectL[0], preoutL[0] );
priority_encoder8 e31( in[ 15:8 ], detectL[1], preoutL[1] );
priority_encoder8 e32( in[ 23:16 ], detectL[2], preoutL[2] );
priority_encoder8 e33( in[ 31:24 ], detectL[3], preoutL[3] );
priority_encoder8 e34( in[ 39:32 ], detectL[4], preoutL[4] );
priority_encoder8 e35( in[ 47:40 ], detectL[5], preoutL[5] );
priority_encoder8 e36( in[ 55:48 ], detectL[6], preoutL[6] );
priority_encoder8 e37( in[ 63:56 ], detectL[7], preoutL[7] );
//2nd order entry
priority_encoder8 e20(detectL, detect, preoutM);
assign out = detect ? { preoutM, preoutL[preoutM] } : 6'b0;
endmodule
module priority_encoder8
(
input [ 7 : 0 ] in,
output reg detect,
output reg [ 2 : 0 ] out
);
always @ (*)
casez(in)
default : {detect, out} = 4'b0000;
8'b00000001 : {detect, out} = 4'b1000;
8'b0000001? : {detect, out} = 4'b1001;
8'b000001?? : {detect, out} = 4'b1010;
8'b00001??? : {detect, out} = 4'b1011;
8'b0001???? : {detect, out} = 4'b1100;
8'b001????? : {detect, out} = 4'b1101;
8'b01?????? : {detect, out} = 4'b1110;
8'b1??????? : {detect, out} = 4'b1111;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, i, m = 1000000007, a, b; int main() { cin >> n; a = 1, b = 1; for (i = 0; i < 3 * n; i++) a = (a * 3) % m; for (i = 0; i < n; i++) b = (b * 7) % m; cout << (a - b + m) % m; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { int n; cin >> n; long long int a[n + 1]; int o = 0, idx, z = 0; long long int maxo = -1000000007; vector<int> v, v0; for (long long int i = 1; i < n + 1; i++) { cin >> a[i]; if (a[i] < 0) { o++; if (maxo < a[i]) { maxo = a[i]; idx = i; } } if (a[i] != 0) v.push_back(i); else v0.push_back(i); } if (o % 2 == 1) { v.erase(find(v.begin(), v.end(), idx)); v0.push_back(idx); sort(v0.begin(), v0.end()); } bool ch = 0; if (v.size() > 0) { for (long long int i = 0; i < v.size() - 1; i++) { ch = 1; cout << 1 << v[i] << << v[i + 1] << n ; } if (v0.size() > 0) { for (long long int i = 0; i < v0.size() - 1; i++) { cout << 1 << v0[i] << << v0[i + 1] << n ; } cout << 2 << v0[v0.size() - 1] << n ; } } else { if (idx == n) { cout << 2 << idx << n ; for (long long int i = 1; i < v0.size() - 1; i++) cout << 1 << v0[i] << << v0[i + 1] << n ; } else { for (long long int i = 0; i < v0.size() - 1; i++) cout << 1 << v0[i] << << v0[i + 1] << n ; } } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41O_BLACKBOX_V
`define SKY130_FD_SC_MS__A41O_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; void io() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } const int N = 1e5 + 5; vector<int> g[N]; int sz[N], parent[N], done[N]; int lvl[N]; void dfs(int u, int p) { sz[u] = 1; for (int v : g[u]) { if (done[v] || v == p) continue; dfs(v, u); sz[u] += sz[v]; } } int find_centroid(int u, int p, int total) { for (int v : g[u]) { if (done[v] || v == p) continue; if (sz[v] + sz[v] > total) return find_centroid(v, u, total); } return u; } int centroid(int u, int p) { dfs(u, 0); int cnt = sz[u]; int center = find_centroid(u, 0, cnt); done[center] = 1; lvl[center] = lvl[p] + 1; for (int v : g[center]) { if (done[v]) continue; parent[centroid(v, center)] = center; } return center; } int main() { io(); int n; cin >> n; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } centroid(1, 0); for (int i = 1; i <= n; i++) { char c = lvl[i] + A - 1; cout << c << ; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: MossbauerLab
// Engineer: EvilLord666 (Ushakov MV)
//
// Create Date: 11:24:46 09/19/2017
// Design Name:
// Module Name: messbauer_test_environment
// Project Name:
// Target Devices: Spartan 6
// Tool versions: Xilinx ISE 14.7
// Description:
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module messbauer_test_environment
(
input wire global_clock, // 50 MHz GCLK, T8
input wire global_reset, // L3 as Button
// Left Side of AX309 Board
output wire v1_channel, // F16
output wire v1_start, // E16
output wire [11:0] v1_velocity_reference,
output wire v1_lower_threshold, // C10
output wire v1_upper_threshold, // D16
// Right Side of AX309 Board
output wire v2_channel, // L16
output wire v2_start, // M15
output wire [11:0] v2_velocity_reference,
output wire v2_lower_threshold, // R16
output wire v2_upper_threshold // T14
);
reg internal_reset;
reg [5:0] counter;
// Left Side (v1) interface
// Start, Channel generation
messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(1)) v1_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v1_start), .channel(v1_channel));
// Saw tooth generation (velocity refence signal)
messbauer_saw_tooth_generator #(.DIRECT_SLOPE_DURATION(512)) v1_velocity_reference_generator(.clk(global_clock), .areset_n(global_reset & internal_reset), .out_value(v1_velocity_reference));
// Signals 4 testing Differntial discriminator test
messbauer_diff_discriminator_signals v1_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v1_channel), .lower_threshold(v1_lower_threshold), .upper_threshold(v1_upper_threshold));
// Right Side (v1) interface
// Start, Channel generation
messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(2)) v2_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v2_start), .channel(v2_channel));
// Saw tooth generation (velocity refence signal)
messbauer_saw_tooth_generator #(.DIRECT_SLOPE_DURATION(512)) v2_velocity_reference_generator(.clk(global_clock), .areset_n(global_reset & internal_reset), .out_value(v2_velocity_reference));
// Signals 4 testing Differntial discriminator test
messbauer_diff_discriminator_signals v2_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v2_channel), .lower_threshold(v2_lower_threshold), .upper_threshold(v2_upper_threshold));
// Reset generation
always @(posedge global_clock)
begin
if(~global_reset)
begin
internal_reset <= 1;
counter <= 0;
end
if(counter < 16)
counter <= counter + 1'b1;
if(counter >= 16 && counter < 32)
begin
counter <= counter + 1'b1;
internal_reset <= 0;
end
if(counter == 32)
internal_reset <= 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_P_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_P_BLACKBOX_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_P_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct two { long long int f, s; }; signed main() { long long int n; cin >> n; map<string, set<string> > mp; while (n--) { string str; cin >> str; for (long long int i = 0; i < str.size(); i++) { string tmp = ; for (long long int j = i; j < str.size(); j++) { tmp += str[j]; mp[tmp].insert(str); } } } long long int q; cin >> q; while (q--) { string str; cin >> str; if (mp.find(str) != mp.end()) cout << mp[str].size() << << *mp[str].begin() << endl; else cout << 0 << << - << endl; } }
|
/*
* Maze rom file #1.
* Format: each byte indicates maps row.
* Opened cell is marked as True (1)
* Closed cell is marked as False (0)
*
* Start / end point format
*
* +---------+---------+------+------+------+------+------+------+
* |Preserved|Preserved|row(2)|row(1)|row(0)|col(2)|col(1)|col(0)|
* +---------+---------+------+------+------+------+------+------+
*
* Start point address : 0b1000
* End point address : 0b1001
*
*/
module maprom1(clk, en, addr, data);
input clk;
input en;
input [3:0] addr;
output reg [7:0] data;
always @(posedge clk)
begin
if(en)
begin
case(addr)
4'b0000: data <= 8'b11111111;
4'b0001: data <= 8'b10000001;
4'b0010: data <= 8'b11101111;
4'b0011: data <= 8'b01100100;
4'b0100: data <= 8'b11110111;
4'b0101: data <= 8'b00010001;
4'b0110: data <= 8'b11110111;
4'b0111: data <= 8'b10001100;
4'b1000: data <= 8'b00001000;
4'b1001: data <= 8'b00111100;
default: data <= 8'b00000000;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> #define dumb ios_base::sync_with_stdio(false);cin.tie(NULL); typedef long long ll; using namespace std; #define modulo 1000000007; bool isprime(long long n) { for(long long int i=2;i*i<=n;i++) { if(n%i==0) return 0; } return 1; } long long gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } // Function to return LCM of two numbers long long lcm(int a, int b) { return (a / gcd(a, b)) * b; } ll ncr(ll n,ll k) { ll res = 1; if (k > n - k) k = n - k; for (ll i = 0; i < k; ++i) { res *= (n - i); res /= (i + 1); } return res; } map<int,int> m; void solve() { int n; cin>>n; auto it=m.lower_bound(n); if(it->first==n) { cout<<it->second<<endl; return; } else { int diff=it->first-n; if(diff==1) cout<<it->second+1<<endl; else cout<<it->second<<endl; return; } return; } int main() { dumb; int t=1; cin>>t; int i=1; m[0]=0; int sum=0; while(1) { m[sum+i]=i; if(sum+i>1000000) break; sum+=i; i++; } while(t--) { //cout<< in ; solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; struct ask { int l, r, cur; } tmp; long long pre[maxn], suf[maxn], s[maxn], d[maxn], h[maxn], ans[maxn]; vector<ask> V, W; int n, m, a, b; long long solve(int l, int r, vector<ask> &V) { if (l == r) return 0; int mid = (l + r) >> 1; long long best; vector<ask> Vl, Vr, Vt; pre[mid] = 0; for (int i = (mid + 1); i <= int(r); i++) pre[i] = max(pre[i - 1], s[i] - s[mid] + 2 * h[i]); suf[mid + 1] = 0; for (int i = (mid); i >= (l); i--) suf[i] = max(suf[i + 1], s[mid] - s[i] + 2 * h[i]); for (auto x : V) if (x.r <= mid) Vl.push_back(x); else if (mid + 1 <= x.l) Vr.push_back(x); else if (l != x.l || r != x.r) { ans[x.cur] = max(ans[x.cur], suf[x.l] + pre[x.r]); Vl.push_back((ask){x.l, mid, x.cur}); Vr.push_back((ask){mid + 1, x.r, x.cur}); } best = pre[r] + suf[l]; best = max(best, solve(l, mid, Vl)); best = max(best, solve(mid + 1, r, Vr)); for (auto x : V) if (l == x.l && r == x.r) ans[x.cur] = max(ans[x.cur], best); return best; } void solve2() { pre[0] = 0; for (int i = (1); i <= int(n); i++) pre[i] = max(pre[i - 1], s[i] - s[1] + 2 * h[i]); suf[n + 1] = 0; for (int i = (n); i >= (1); i--) suf[i] = max(suf[i + 1], s[n + 1] - s[i] + 2 * h[i]); for (auto x : W) ans[x.cur] = max(ans[x.cur], pre[x.l] + suf[x.r]); } int main() { scanf( %d%d , &n, &m); for (int i = (1); i <= int(n); i++) scanf( %I64d , &d[i]), s[i + 1] = s[i] + d[i]; for (int i = (1); i <= int(n); i++) scanf( %I64d , &h[i]); for (int i = (1); i <= int(m); i++) { scanf( %d%d , &a, &b); if (a <= b) { if (3 <= a) V.push_back((ask){1, a - 1, i}); if (b <= n - 2) V.push_back((ask){b + 1, n, i}); if (2 <= a && b <= n - 1) W.push_back((ask){a - 1, b + 1, i}); } else V.push_back((ask){b + 1, a - 1, i}); } solve(1, n, V); solve2(); for (int i = (1); i <= int(m); i++) printf( %I64d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T ABS(T a) { return a > 0 ? a : -a; } template <typename T> inline T MIN(T a, T b) { return a < b ? a : b; } template <typename T> inline T MAX(T a, T b) { return a > b ? a : b; } template <typename T> inline T CHKMIN(T &a, T b) { if (a > b) a = b; return a; } template <typename T> inline T CHKMAX(T &a, T b) { if (a < b) a = b; return a; } template <typename T> inline void SWAP(T &a, T &b) { static T c; c = a; a = b; b = c; } template <typename T, typename... T0> T MAX(T a, T b, T0... c) { return a > b ? MAX(a, c...) : MAX(b, c...); } template <typename T, typename... T0> T MIN(T a, T b, T0... c) { return a < b ? MIN(a, c...) : MIN(b, c...); } template <typename T, int n> void myin(T a[]) { for (int i = (0); i < (int)(n); ++i) cin >> a[i]; } template <typename T> void myin(T &a) { cin >> a; } template <typename T> void print(T a) { cout << a << ; } template <typename T, typename... T0> void print(T a, T0... b) { print(a); print(b...); } template <typename T> void println(T a) { cout << a << endl; } template <typename T, typename... T0> void println(T a, T0... b) { print(a); println(b...); } int n, in[120000]; long long dp[120000]; int main() { long long sum = 0; while (cin >> n) { for (int i = (0); i < (int)(n); ++i) { scanf( %d , in + i); sum += in[i]; } if (sum % 3 != 0) { puts( 0 ); continue; } long long tmp = sum / 3, now = 0, ans = 0; for (int i = (0); i < (int)(n); ++i) { now += in[i]; if (i == 0) dp[i] = 0; else dp[i] = dp[i - 1]; if (now == tmp) ++dp[i]; } tmp += tmp, now = in[0]; for (int i = (1); i < (int)(n - 1); ++i) { now += in[i]; if (now == tmp) ans += dp[i - 1]; } println(ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1 << 17; pair<int, int> v[MAXN]; set<pair<int, int> > ans; queue<int> Q; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> v[i].first >> v[i].second; if (v[i].first == 1) Q.push(i); } while (!Q.empty()) { int k = Q.front(); Q.pop(); if (v[k].first == 0) continue; int id = v[k].second; v[id].first--, v[id].second ^= k; ans.insert(make_pair(k, id)); if (v[id].first == 1) Q.push(id); } cout << ans.size() << endl; for (auto it = ans.begin(); it != ans.end(); it++) { pair<int, int> a = *it; cout << a.first << << a.second << endl; } return 0; }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program combines two events with an event or. The tricky part
* for the vvp target is that there is a mix of posedge and negedge
* events.
*/
module ndFF ( nset, reset, Q );
input nset; // clk negedge set Q=1
input reset; // reset posedge set Q=0
output Q ; // Q output
reg Q ;
always @(negedge nset or posedge reset)
begin
if (nset ==1'b0) Q = 1'b1;
else if (reset==1'b1) Q = 1'b0;
end
endmodule
module main;
reg nset, reset;
wire Q;
ndFF dut(nset, reset, Q);
initial begin
#0 nset = 1;
reset = 1;
#1 nset = 0;
#1 if (Q !== 1'b1) begin
$display("FAILED (a) nset=%b, reset=%b, Q=%b", nset, reset, Q);
$finish;
end
nset = 1;
#1 if (Q !== 1'b1) begin
$display("FAILED (b) nset=%b, reset=%b, Q=%b", nset, reset, Q);
$finish;
end
reset = 0;
#1 if (Q !== 1'b1) begin
$display("FAILED (c) nset=%b, reset=%b, Q=%b", nset, reset, Q);
$finish;
end
reset = 1;
#1 if (Q !== 1'b0) begin
$display("FAILED (d) nset=%b, reset=%b, Q=%b", nset, reset, Q);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: thomasdaede.com:user:daala_idct4_stream:1.0
// IP Revision: 15
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module daala_zynq_daala_idct4_stream_0_1 (
axis_aclk,
axis_aresetn,
s00_axis_tready,
s00_axis_tdata,
s00_axis_tlast,
s00_axis_tvalid,
m00_axis_tvalid,
m00_axis_tdata,
m00_axis_tlast,
m00_axis_tready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 axis_signal_clock CLK" *)
input axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
input axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TREADY" *)
output s00_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TDATA" *)
input [63 : 0] s00_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TLAST" *)
input s00_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TVALID" *)
input s00_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TVALID" *)
output m00_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TDATA" *)
output [63 : 0] m00_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TLAST" *)
output m00_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TREADY" *)
input m00_axis_tready;
daala_idct4_stream_v1_0 #(
.C_M00_AXIS_TDATA_WIDTH(64),
.C_M00_AXIS_START_COUNT(32),
.C_S00_AXIS_TDATA_WIDTH(64)
) inst (
.axis_aclk(axis_aclk),
.axis_aresetn(axis_aresetn),
.s00_axis_tready(s00_axis_tready),
.s00_axis_tdata(s00_axis_tdata),
.s00_axis_tlast(s00_axis_tlast),
.s00_axis_tvalid(s00_axis_tvalid),
.m00_axis_tvalid(m00_axis_tvalid),
.m00_axis_tdata(m00_axis_tdata),
.m00_axis_tlast(m00_axis_tlast),
.m00_axis_tready(m00_axis_tready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4_SYMBOL_V
`define SKY130_FD_SC_HS__OR4_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4_SYMBOL_V
|
module mod1(input logic [1:0] reg1[4],
input logic reg2[5][6],
input logic [1:0] [3:0] [2:0] reg4);
endmodule
module mod2(output logic [1:0] reg1[4],
output logic [1:0] [3:0] [2:0] reg4);
endmodule
module dut (
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic reg2 [5][6] // To foo_i of mod1.v
// End of automatics
/*AUTOOUTPUT*/
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [1:0] reg1 [4]; // From drv_i of mod2.v
logic [1:0][3:0] [2:0] reg4; // From drv_i of mod2.v
// End of automatics
mod1 foo_i(/*AUTOINST*/
// Inputs
.reg1 (reg1/*[1:0].[4]*/),
.reg2 (reg2/*.[5][6]*/),
.reg4 (reg4/*[1:0][3:0][2:0]*/));
/* drv_i AUTO_TEMPLATE (.reg1(reg1[]), );*/
mod2 drv_i(/*AUTOINST*/
// Outputs
.reg1 (reg1/*[1:0].[4]*/),
.reg4 (reg4/*[1:0][3:0][2:0]*/));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int n, i, j, k, sum = 0, ev = 0, ze = 0; string s; cin >> s; n = s.length(); for (i = 0; i < n; i++) { sum = sum + s[i] - 0 ; if ((s[i] - 0 ) % 2 == 0) ev++; if (s[i] - 0 == 0) ze++; } if (ze == 0) cout << cyan << endl; else { if (ev < 2) cout << cyan << endl; else { if (sum % 3 == 0) cout << red << endl; else cout << cyan << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { double v, d, l, g, r; cin >> l >> d >> v >> g >> r; double t; t = d / v; double k = 0; while (k <= t) { k += g; if (t < k) { t += (l - d) / v; cout << setprecision(8) << t; exit(0); } k += r; if (t < k) { t += (k - t); t += (l - d) / v; cout << setprecision(8) << t; exit(0); } } }
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "system1_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 15: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 51200,
the_altsyncram.numwords_a = 51200,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__EBUFN_PP_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ebufn (
A ,
TE_B,
Z ,
VPWR,
VGND
);
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_PP_BLACKBOX_V
|
/*
* Copyright (C) 2009 Onno Kortmann <>
* 2015 Klaus Rudolph <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
module ATmega32(clk, PA, PB, PC, PD);
parameter progfile="UNSPECIFIED";
input clk;
inout [7:0] PA;
inout [7:0] PB;
inout [7:0] PC;
inout [7:0] PD;
defparam core.progfile=progfile;
defparam core.name="atmega32";
AVRCORE core(clk);
avr_pin #("A0") pa0(PA[0]);
avr_pin #("A1") pa1(PA[1]);
avr_pin #("A2") pa2(PA[2]);
avr_pin #("A3") pa3(PA[3]);
avr_pin #("A4") pa4(PA[4]);
avr_pin #("A5") pa5(PA[5]);
avr_pin #("A6") pa6(PA[6]);
avr_pin #("A7") pa7(PA[7]);
avr_pin #("B0") pb0(PB[0]);
avr_pin #("B1") pb1(PB[1]);
avr_pin #("B2") pb2(PB[2]);
avr_pin #("B3") pb3(PB[3]);
avr_pin #("B4") pb4(PB[4]);
avr_pin #("B5") pb5(PB[5]);
avr_pin #("B6") pb6(PB[6]);
avr_pin #("B7") pb7(PB[7]);
avr_pin #("C0") pc0(PC[0]);
avr_pin #("C1") pc1(PC[1]);
avr_pin #("C2") pc2(PC[2]);
avr_pin #("C3") pc3(PC[3]);
avr_pin #("C4") pc4(PC[4]);
avr_pin #("C5") pc5(PC[5]);
avr_pin #("C6") pc6(PC[6]);
avr_pin #("D0") pd0(PD[0]);
avr_pin #("D1") pd1(PD[1]);
avr_pin #("D2") pd2(PD[2]);
avr_pin #("D3") pd3(PD[3]);
avr_pin #("D4") pd4(PD[4]);
avr_pin #("D5") pd5(PD[5]);
avr_pin #("D6") pd6(PD[6]);
avr_pin #("D7") pd7(PD[7]);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 100; int arr[maxn]; int main() { int T; cin >> T; while (T--) { int n; cin >> n; for (int i = 0; i < n; ++i) cin >> arr[i]; for (int i = 0; i < n; ++i) { if (i % 2) { if (arr[i] > 0) arr[i] = -arr[i]; } else { if (arr[i] < 0) arr[i] = -arr[i]; } } for (int i = 0; i < n; ++i) cout << arr[i] << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void cline() { cout << n ; } template <typename T, typename... V> void cline(T t, V... v) { cout << t; if (sizeof...(v)) cout << ; cline(v...); } void cspc() { cout << ; } template <typename T, typename... V> void cspc(T t, V... v) { cout << t; if (sizeof...(v)) cout << ; cspc(v...); } const long long N = 2e5 + 4; long long state[2 * N][2]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); memset(state, 0, sizeof(state)); long long n, m; cin >> n >> m; long long ind = -1; long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; if (m == a[i]) ind = i; } long long oki = 0, cnt = 0; for (long long i = 0; i < n; i++) { if (a[i] < m) oki--; else if (a[i] > m) oki++; if (i >= ind) state[N + oki][i & 1]++; } oki = 0; for (long long i = 0; i <= ind; ++i) { if (i % 2 == 1) { cnt += state[N + oki + 1][0]; cnt += state[N + oki][1]; } else { cnt += state[N + oki][0]; cnt += state[N + oki + 1][1]; } if (a[i] < m) oki--; else oki++; } cspc(cnt); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; map<char, int> mp; for (int i = 0; i < s.length(); i++) { mp[s[i]]++; } int mn; set<int> st; set<int>::iterator it; st.insert(mp[ B ]); st.insert(mp[ u ] / 2); st.insert(mp[ l ]); st.insert(mp[ b ]); st.insert(mp[ a ] / 2); st.insert(mp[ s ]); st.insert(mp[ r ]); it = st.begin(); cout << *it; }
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#include <bits/stdc++.h> using namespace std; int main() { long long int l, r, x, y, k; cin >> l >> r >> x >> y >> k; for (long long int i = x; i <= y; ++i) { if (k * i >= l && k * i <= r) { cout << YES << endl; exit(0); } } cout << NO << endl; }
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module cache_test();
reg clk;
reg re, we, we2, we3;
reg [31:0] address, writedata;
wire [31:0] readdatacache;
wire hit, miss, dirty;
// test
memory_system DUT(clk, re, we, we2, we3, address, writedata, readdatacache, hit, miss, dirty);
// generate clock to sequence tests
always begin
clk <= 1;
#5;
clk <= 0;
# 5;
end
// check results
initial begin
re <= 1'b0;
we <= 1'b0;
we2 <=1'b0;
we3 <= 1'b0;
address <= 32'h0;
writedata <= 32'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'h7;
#10;
we <= 1'b0;
#10;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h54;
writedata <= 32'h7;
#10;
we <= 1'b0;
#200;
/*
// Write Miss: Miss generated, gets main memory, write this data to this cache value
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00001006;
writedata <= 32'h12345678;
#10;
we <= 1'b0;
#200;
we2 <= 1'b1;
#5;
we2 <= 1'b0;
#5;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00001006;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Read Miss: !Hit generated, gets main memory, read out of cache is initialized mainmemory value after writing new cache value
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00002006;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#200;
we3 <= 1'b1;
#10;
we3 <= 1'b0;
#20;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00002005;
writedata <= 32'h87654321;
#10;
we <= 1'b0;
#200;
*/
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int mod = 1000000000 + 7; int main() { string s; long long n; cin >> n; long long a[n]; for (int i = 0; i < n; ++i) cin >> a[i]; long long x = 0, y = n - 1, z = 0; while (x <= y) { if (max(a[x], a[y]) < z) break; else { if (a[x] < a[y] && a[x] > z) { z = a[x]; s += L ; x++; } else if (a[y] > z) { z = a[y]; s += R ; y--; } else { z = a[x]; s += L ; x++; } } } cout << s.size() << endl; cout << s; return 0; }
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#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int cases; scanf( %d , &cases); while (cases--) { int n, p; scanf( %d%d , &n, &p); for (int i = 2; i <= n; i++) { printf( %d %d n , 1, i); } for (int i = 2; i < n; i++) { printf( %d %d n , i, i + 1); } printf( %d %d n , n, 2); int count = 0, extra = 2 * n + p - 2 * (n - 1); for (int i = 2; i <= n; i++) { for (int j = i + 2; j <= n; j++) { if (i == 2 && j == n) break; printf( %d %d n , i, j); count++; if (count == extra) goto here; } } here: continue; } return 0; }
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#include <bits/stdc++.h> using namespace std; struct node { long long a, sum; } t, tt; vector<node> vec[300005]; long long cost[300005], in[300005], dp[300005][2], vis[300005]; queue<node> que; int main(void) { long long i, j, n, m, a, b, c; long long ans; scanf( %lld , &n); ans = 0; for (i = 1; i <= n; i++) { scanf( %lld , &cost[i]); ans = max(ans, cost[i]); } for (i = 1; i < n; i++) { scanf( %lld %lld %lld , &a, &b, &c); in[a]++; in[b]++; t.sum = c; t.a = b; vec[a].push_back(t); t.a = a; vec[b].push_back(t); } for (i = 1; i <= n; i++) { if (in[i] == 1) { t.a = i; t.sum = cost[i]; que.push(t); in[i]--; } } while (que.size()) { t = que.front(); ans = max(ans, t.sum); vis[t.a] = 1; que.pop(); for (auto x : vec[t.a]) { if (vis[x.a] == 1) { continue; } else { if (dp[x.a][0] < t.sum - x.sum) { dp[x.a][1] = dp[x.a][0]; dp[x.a][0] = t.sum - x.sum; } else if (dp[x.a][1] < t.sum - x.sum) { dp[x.a][1] = t.sum - x.sum; } ans = max(ans, dp[x.a][0] + dp[x.a][1] + cost[x.a]); in[x.a]--; if (in[x.a] == 1) { tt.a = x.a; tt.sum = dp[x.a][0] + cost[x.a]; que.push(tt); } } } } printf( %lld n , ans); }
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#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); printf( %d n , (n & 1) ? (n - 1) + (n - 1) * ((n - 3) / 2) / 2 : (n - 2) * (n - 2) / 4 + (n - 2)); if (n & 1) { for (int i = 2; i <= n; i += 2) { printf( %d %d %d %d n , 3, 1, i, i + 1); printf( %d %d %d %d n , 3, 1, i, i + 1); for (int j = 2; j < i; j += 2) { printf( %d %d %d %d %d n , 4, i, j, i + 1, j + 1); printf( %d %d %d %d %d n , 4, i, j, i + 1, j + 1); } } } else { puts( 4 1 2 3 4 ), puts( 4 1 3 4 2 ), puts( 4 1 4 2 3 ); for (int i = 5; i <= n; i += 2) { printf( %d %d %d %d n , 3, 1, i, i + 1); printf( %d %d %d %d n , 3, 2, i, i + 1); printf( %d %d %d %d %d n , 4, 1, i, 2, i + 1); for (int j = 3; j < i; j += 2) { printf( %d %d %d %d %d n , 4, i, j, i + 1, j + 1); printf( %d %d %d %d %d n , 4, i, j, i + 1, j + 1); } } } return 0; }
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#include <bits/stdc++.h> using std::make_pair; using std::pair; const int N = 3e5 + 1e3; int n, k; int tot, rt; struct Pair { int l, r, pos, v1; bool operator<(const Pair m) const { return v1 > m.v1; } } p1[N], p2[N]; int sum[N << 4], ls[N << 4], rs[N << 4], mn[N << 4]; int r[N], a[N], mx[N], ans[N]; int ask(int cur, int l, int r, int L, int R) { if (!cur) return 0; if (L <= l && r <= R) { return sum[cur]; } int mid = l + r >> 1; int ans = 0; if (L <= mid) ans += ask(ls[cur], l, mid, L, R); if (R > mid) ans += ask(rs[cur], mid + 1, r, L, R); return ans; } int get(int cur, int l, int r, int L, int R) { if (!cur) return 0; if (L <= l && r <= R) { return mn[cur]; } int mid = l + r >> 1; int ans = 0; if (L <= mid) ans = std::max(ans, get(ls[cur], l, mid, L, R)); if (R > mid) ans = std::max(ans, get(rs[cur], mid + 1, r, L, R)); return ans; } void add(int &cur, int l, int r, int x, int v) { if (!cur) cur = ++tot; if (l == r) { sum[cur] += v; mn[cur] = std::max(mn[cur], v); return; } int mid = l + r >> 1; if (x <= mid) add(ls[cur], l, mid, x, v); else add(rs[cur], mid + 1, r, x, v); sum[cur] = sum[ls[cur]] + sum[rs[cur]]; mn[cur] = std::max(mn[ls[cur]], mn[rs[cur]]); } int main() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; ++i) scanf( %d , &r[i]); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= n; ++i) { p1[i].v1 = r[i], p1[i].l = a[i], p1[i].pos = i; } std::sort(p1 + 1, p1 + 1 + n); std::reverse(p1 + 1, p1 + 1 + n); for (int i = 1; i <= n; ++i) { add(rt, 1, 1e9 + 2, p1[i].l, 1); mx[p1[i].pos] = ask(rt, 1, 1e9 + 2, std::max(1, p1[i].l - k), std::min(p1[i].l + k, (int(1e9)) + 2)); } int q; scanf( %d , &q); memset(ls, 0, sizeof(ls)); memset(rs, 0, sizeof(rs)); memset(sum, 0, sizeof(sum)); rt = tot = 0; memset(mn, 0, sizeof(mn)); for (int i = 1; i <= q; ++i) { int l, r; scanf( %d %d , &l, &r); p2[i].l = l, p2[i].r = r, p2[i].pos = i, p2[i].v1 = std::max(::r[l], ::r[r]); } std::sort(p2 + 1, p2 + 1 + q); std::sort(p1 + 1, p1 + 1 + n); int now = 1; for (int i = 1; i <= q; ++i) { while (p2[i].v1 <= p1[now].v1 && now <= n) { add(rt, 1, 1e9 + 1, a[p1[now].pos], mx[p1[now].pos]); now++; } if (abs(a[p2[i].l] - a[p2[i].r]) > 2 * k) { ans[p2[i].pos] = 0; continue; } ans[p2[i].pos] = get( rt, 1, 1e9 + 1, std::max(1, std::max(a[p2[i].l] - k, a[p2[i].r] - k)), std::min((int(1e9)), std::min(a[p2[i].l] + k, a[p2[i].r] + k))); } for (int i = 1; i <= q; ++i) printf( %d , ans[i] <= 0 ? -1 : ans[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; int getint() { unsigned int c; int x = 0; while (((c = getchar()) - 0 ) >= 10) { if (c == - ) return -getint(); if (!~c) exit(0); } do { x = (x << 3) + (x << 1) + (c - 0 ); } while (((c = getchar()) - 0 ) < 10); return x; } const int L = 222; const int G = 222; int nTour, needWin, initCap; double winProb[200]; int award[200]; double cache[L][L + G + 1][L]; double solve(int pos, int cap, int won) { double& res = cache[pos][cap][won]; if (res > -1) return res; if (pos == nTour) { if (won >= needWin) { if (cap >= G) { return res = 1; } else { return res = 0; } } else { return res = 0; } } if (award[pos] == -1) { res = winProb[pos] * solve(pos + 1, cap - 1, won + 1); } else { res = winProb[pos] * solve(pos + 1, min(L + G, cap + award[pos]), won + 1); } res += (1 - winProb[pos]) * solve(pos + 1, cap, won); return res; } int main() { int i, j, k, tcc, tc = 1 << 28; for (tcc = 0; tcc < tc; tcc++) { nTour = getint(); needWin = getint(); initCap = getint(); for (i = 0; i < nTour; i++) { winProb[i] = getint() / 100.0; } for (i = 0; i < nTour; i++) { award[i] = getint(); } for (i = 0; i < L; i++) for (j = 0; j < L + G + 1; j++) for (k = 0; k < L; k++) cache[i][j][k] = -1e40; double res = solve(0, initCap + G, 0); printf( %.10lf n , res); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_TB_V
`define SKY130_FD_SC_LS__EDFXTP_TB_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__edfxtp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__edfxtp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_TB_V
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* if "ack" is 1, then current input has been used. */
module f_permutation(clk, reset, in, in_ready, ack, out, out_ready);
input clk, reset;
input [575:0] in;
input in_ready;
output ack;
output reg [1599:0] out;
output reg out_ready;
reg [22:0] i; /* select round constant */
wire [1599:0] round_in, round_out;
wire [63:0] rc; /* round constant */
wire update;
wire accept;
reg calc; /* == 1: calculating rounds */
assign accept = in_ready & (~ calc); // in_ready & (i == 0)
always @ (posedge clk)
if (reset) i <= 0;
else i <= {i[21:0], accept};
always @ (posedge clk)
if (reset) calc <= 0;
else calc <= (calc & (~ i[22])) | accept;
assign update = calc | accept;
assign ack = accept;
always @ (posedge clk)
if (reset)
out_ready <= 0;
else if (accept)
out_ready <= 0;
else if (i[22]) // only change at the last round
out_ready <= 1;
assign round_in = accept ? {in ^ out[1599:1599-575], out[1599-576:0]} : out;
rconst
rconst_ ({i, accept}, rc);
round
round_ (round_in, rc, round_out);
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= round_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; using LLI = long long; long long NWD(long long blep, long long b) { return (b == 0) ? blep : NWD(b, blep % b); } long long NWW(long long blep, long long b) { return blep / NWD(blep, b) * b; } const int MX = 3e5 + 400; int n, T[MX]; long long ans[MX]; void out() { cout << YES << endl; for (int i = 1; i <= n; i++) cout << ans[i] << ; cout << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> T[i]; T[n + 1] = T[1]; T[0] = T[n]; for (int i = 1; i <= n; i++) { if (T[i] > T[i - 1]) { ans[i] = T[i]; if (i == 1) ans[n + 1] = ans[1]; else if (i == n) ans[0] = ans[n]; for (int j = i - 1; j > i - n; j--) { int blep = (j + n) % n; if (blep == 0) blep = n; ans[blep] = ans[blep + 1] + T[blep]; while (ans[blep] <= (long long)T[blep - 1]) ans[blep] += ans[blep + 1]; if (j == 1) ans[n + 1] = ans[1]; else if (j == n) ans[0] = ans[n]; } return out(), 0; } } for (int i = 1; i <= n; i++) ans[i] = 1; if (T[1] == 0) out(); else cout << NO << endl; getchar(); getchar(); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ccnu
// Engineer: Poyi Xiong
//
// Create Date: 01/12/2017 12:00:21 PM
// Design Name:
// Module Name: Clock_SR_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Clock_SR_tb #(parameter WIDTH=170, CNT_WIDTH=8)();
reg clk;
reg rst;
reg start;
reg [CNT_WIDTH-1:0] count;
wire clk_sr;
Clock_SR #(.WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH))
DUT1(
.clk(clk),
.rst(rst),
.start(start),
.count(count),
.clk_sr(clk_sr)
);
initial begin
$dumpfile("Clock_SR.dump");
$dumpvars(0, Clock_SR);
end
initial begin
clk=0;
forever #50 clk=~clk;
end
initial begin
rst=1'b1;
#200 rst=1'b0;
end
initial begin
count=8'b0;
#50 count=8'b0;
forever #100 count=count+1'b1;
end
initial begin
start=1'b0;
#250 start=1'b1;
#100 start=1'b0;
#17600 start=1'b1;
#100 start=1'b0;
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
module mbus_ext_int(
input CLKIN,
input RESETn,
input REQ_INT,
input BUS_BUSYn,
input BC_PWR_ON,
input LC_PWR_ON,
output reg EXTERNAL_INT_TO_WIRE,
output reg EXTERNAL_INT_TO_BUS,
input CLR_EXT_INT
);
wire RESETn_local = (RESETn & CLKIN);
wire RESETn_local2 = (RESETn & (~CLR_EXT_INT));
wire INT_BUSY = (REQ_INT & BUS_BUSYn);
always @ (posedge INT_BUSY or negedge RESETn_local)
begin
if (~RESETn_local)
EXTERNAL_INT_TO_WIRE <= 0;
else
begin
case ({BC_PWR_ON, LC_PWR_ON})
// Both in sleep
{`IO_HOLD, `IO_HOLD}: begin EXTERNAL_INT_TO_WIRE <= 1; end
// Both in sleep, BC is on, LC is off,
// only interrupt when the bus is not busy
{`IO_RELEASE, `IO_HOLD}: begin if (BUS_BUSYn) EXTERNAL_INT_TO_WIRE <= 1; end
// If both is on, doing nothing,
// BC is off, LC is on is a non-exist state
default: begin end
endcase
end
end
always @ (posedge INT_BUSY or negedge RESETn_local2)
begin
if (~RESETn_local2)
EXTERNAL_INT_TO_BUS <= 0;
else
begin
case ({BC_PWR_ON, LC_PWR_ON})
// Both in sleep
{`IO_HOLD, `IO_HOLD}: begin EXTERNAL_INT_TO_BUS <= 1; end
// Both in sleep, BC is on, LC is off,
// only interrupt when the bus is not busy
{`IO_RELEASE, `IO_HOLD}: begin if (BUS_BUSYn) EXTERNAL_INT_TO_BUS <= 1; end
// If both is on, doing nothing,
// BC is off, LC is on is a non-exist state
default: begin end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MIN = 1e3 + 2; const int MXN = 1e6 + 3; const int INF = 1e9 + 7; const long long LINF = 1e18 + 15; const double EPS = 1e-9; int s, x1, x2; int t1, t2; int p, d; int main() { cin >> s >> x1 >> x2; cin >> t1 >> t2; cin >> p >> d; if (x1 <= x2) { if (p <= x1) { if (d == 1) { cout << min((x2 - x1) * t2, (x2 - p) * t1); cerr << << 1; return 0; } cout << min((x2 - x1) * t2, (x2 + p) * t1); cerr << << 2; return 0; } if (d == 1) { cout << min((x2 - x1) * t2, (s - p + s + x2) * t1); cerr << << 3; return 0; } cout << min((x2 - x1) * t2, (x2 + p) * t1); cerr << << 4; return 0; } if (p >= x1) { if (d == 1) { cout << min((x1 - x2) * t2, (s - x2 + s - p) * t1); cerr << << 5; return 0; } cout << min((x1 - x2) * t2, (p - x2) * t1); cerr << << 6; return 0; } if (d == 1) { cout << min((x1 - x2) * t2, (s - x2 + s - p) * t1); cerr << << 7; return 0; } cout << min((x1 - x2) * t2, (s + p + s - x2) * t1); cerr << << 8; return 0; }
|
#include <bits/stdc++.h> using namespace std; int mod = 1000000007; inline int toInt(string s) { int v; istringstream sin(s); sin >> v; return v; } inline long long toll(string s) { long long v; istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } long long memo[5010]; int isStart[5010]; int isEnd[5010]; int vis[5010]; int visss[5010][5010]; vector<int> v; int n; long long solve(int i) { if (i == n) { return 0; } if (memo[i] != -1) { return memo[i]; } int viss[5010]; for (int j = 0; j < 5010; j++) { viss[j] = 0; } long long take = 0; int curEnd = 0; long long res = solve(i + 1); if (isStart[i]) { return memo[i] = res; } else { for (int j = i; j < n; j++) { curEnd = max(isEnd[j], curEnd); if (!viss[v[j]]) { take = take ^ v[j]; } if (visss[i][v[j]] == 1) { res = max(res, solve(j + 1)); break; } viss[v[j]] = 1; if (j >= curEnd) { res = max(res, take + solve(j + 1)); } } return memo[i] = res; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { int t; cin >> t; v.push_back(t); } for (int i = 0; i < n; i++) { for (int j = 0; j < i; j++) { visss[i][v[j]] = 1; } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (v[j] == v[i]) { isEnd[i] = j; } } } for (int i = 0; i < n; i++) { if (vis[v[i]]) { isStart[i] = 1; } vis[v[i]] = 1; } memset(memo, -1, sizeof(memo)); for (int i = 0; i < 5010; i++) { memo[i] = -1; vis[i] = 0; } cout << solve(0) << endl; ; return 0; }
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_broadcaster:1.1
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_axis_broadcaster_0_0 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [7 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input wire [0 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TVALID [0:0] [0:0], xilinx.com:interface:axis:1.0 M01_AXIS TVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TREADY [0:0] [0:0], xilinx.com:interface:axis:1.0 M01_AXIS TREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TDATA [7:0] [7:0], xilinx.com:interface:axis:1.0 M01_AXIS TDATA [7:0] [15:8]" *)
output wire [15 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TKEEP [0:0] [0:0], xilinx.com:interface:axis:1.0 M01_AXIS TKEEP [0:0] [1:1]" *)
output wire [1 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TLAST [0:0] [0:0], xilinx.com:interface:axis:1.0 M01_AXIS TLAST [0:0] [1:1]" *)
output wire [1 : 0] m_axis_tlast;
top_design_1_axis_broadcaster_0_0 #(
.C_FAMILY("zynq"),
.C_NUM_MI_SLOTS(2),
.C_S_AXIS_TDATA_WIDTH(8),
.C_M_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_S_AXIS_TUSER_WIDTH(1),
.C_M_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000000011011)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(1'H1),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
|
// verilog mode bug1346 testcase
module design(/*AUTOARG*/);
parameter w1 = 2;
parameter w2 = 4;
parameter w3 = 256;
input [w1:0] i0;
input [w2:0] i1;
output [w2*w1 :0] y10; // 8:0
output [w2/w1 :0] y11; // 2:0
output [w2+w1 :0] y12; // 6:0
output [w2-w1 :0] y13; // 2:0
output [w2>>w1 :0] y14; // 1:0
output [w2>>>w1:0] y15; // 1:0
output [w2<<w1 :0] y16; //16:0
output [w2<<<w1:0] y17; //16:0
output [w2<>>w1:0] y18; //4<>>2:0
output [w2>><w1:0] y19; //4>><2:0
output [w1*w2/w1+w1 :0] y20; // 6:0
output [w2*w1/w1+w1 :0] y21; // 6:0
output [w1*w2/(w2-w1)+w1 :0] y22; // 6:0
output [w2*w1/(w2-w1)+w2-w1 :0] y23; // 6:0
output [w2*w1/(w2-w1)+w1<<1>>1 :0] y24; // 6:0
output [w2*w1/(w2-w1)+w1<<w1-w1:0] y25; // 6:0
output [(8*4)-1 :0] y26; // 31:0
output [((w3>>3)-1) :0] y27; // 31:0
output [w2*w1/w1 +w2+w1 <<w2 >>w1 :0] y30; // 40:0
output [w2*w1/w1 +w1+w2 <<w1+w1 >>w2-w1:0] y31; // 40:0
output [w2*w1/w1 +w1+w2 <<w1+w1 >>w2/w1:0] y32; // 40:0
output [w1*w2/w1 +w1+w2 <<w2 >>w1 :0] y33; // 40:0
output [w1*w2/(w2-w1) +w1+w2 <<w2 >>w1 :0] y34; // 40:0
output [w1*w2/(w2/w1) +w1+w2 <<w2 >>w2-w1:0] y35; // 40:0
output [w1*w2/(w1+0) +w1+w2 <<w2 >>w1 :0] y36; // 40:0
output [w2*w1/w1 +w2*1+w1 <<w2/1 *1 >>w1 *1:0] y40; // 40:0
output [w2*w1/w1 +w1*1+w2 <<w1/1+w1*1 >>w2-w1*1:0] y41; // 40:0
output [w2*w1/w1 +w1*1+w2 <<w1/1+w1*1 >>w2/w1*1:0] y42; // 40:0
output [w1*w2/w1 +w1*1+w2 <<w2/1 *1 >>w1 *1:0] y43; // 40:0
output [w1*w2/(w2-w1) +w1*1+w2 <<w2/1 *1 >>w1 *1:0] y44; // 40:0
output [w1*w2/(w2/w1) +w1*1+w2 <<w2/1 *1 >>w2-w1*1:0] y45; // 40:0
endmodule // design
module test(/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
design #(.w1(2),.w2(4),.w3(256)) i0_design(/*AUTOINST*/);
endmodule // test
// Local Variables:
// verilog-auto-inst-param-value: t
// End:
|
#include <bits/stdc++.h> int n, sum, ans[6050]; bool isprime(int x) { if (x < 2 || (x & 1) == 0) { return 0; } for (int i = 2; i * i <= x; ++i) { if (x % i == 0) { return 0; } } return 1; } int main() { scanf( %d , &n); sum = n * (n + 1) / 2; if (isprime(sum)) { for (int i = 1; i <= n; ++i) { ans[i] = 1; } } else if ((sum & 1) == 0) { for (int i = 3; i <= n; ++i) { if (isprime(i) && isprime(sum - i)) { ans[i] = 2; break; } } for (int i = 1; i <= n; ++i) { if (!ans[i]) { ans[i] = 1; } } } else { if (isprime(sum - 2)) { for (int i = 1; i <= n; ++i) { ans[i] = 1; } ans[2] = 2; } else { sum -= 3; ans[3] = 3; for (int i = 5; i <= n; ++i) { if (isprime(i) && isprime(sum - i)) { ans[i] = 2; break; } } for (int i = 1; i <= n; ++i) { if (!ans[i]) { ans[i] = 1; } } } } for (int i = 1; i <= n; ++i) { printf( %d , ans[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> void show(T *a, int n) { for (int i = 0; i < n; i++) cout << a[i] << ; puts( ); } template <class T> void queue_clear(T *a, int n) { for (int i = 0; i < n; i++) { while (!a->empty()) a->pop(); } } template <class T> void Bit_add(T *a, int x, int p, int MAX) { while (p < MAX) { a[p] += x; p += p & (-p); } } template <class T> T Bit_sum(T *a, int p) { T ret = 0; while (p) { ret += a[p]; p -= p & (-p); } return ret; } const int MAXN = 1007; int d[MAXN], s[MAXN]; int main() { int m, k; while (~scanf( %d%d , &m, &k)) { int i; for (i = 1; i <= m; i++) scanf( %d , d + i); for (i = 1; i <= m; i++) scanf( %d , s + i); int tank = s[1], mx = s[1]; int p = 1, ans = 0; while (p <= m) { if (tank < d[p]) { int t = ((d[p] - tank) + mx - 1) / mx; ans += t * k; tank += t * mx; } tank -= d[p]; ans += d[p]; p++; mx = max(mx, s[p]); tank += s[p]; } printf( %d n , ans); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module hilbert(CLK,RST,ED,START,DReal,DImag,RDY,DOReal,DOImag);
parameter total_bits = 32;
input CLK;
input RST;
input ED;
input START;
input [total_bits-1:0] DReal;
input [total_bits-1:0] DImag;
output reg RDY;
output reg signed [total_bits-1:0] DOReal;
output reg signed [total_bits-1:0] DOImag;
wire rdy1;
wire signed [total_bits-1:0] dr1,di1;
wire start1;
reg startReg;
wire [total_bits-1:0] inr1,ini1;
reg signed [total_bits-1:0] RE,IM;
assign inr1 = (state==0)?DReal:RE;
assign ini1 = (state==0)?DImag:IM;
assign start1 = (state==0)?START:startReg;
reg signed [total_bits-1:0] dataREstage1[0:31];
reg signed [total_bits-1:0] dataIMstage1[0:31];
fft32 #(total_bits) FF(.CLK(CLK),.RST(RST),.ED(ED),.START(start1),.DReal(inr1),.DImag(ini1),.RDY(rdy1),.DOReal(dr1),.DOImag(di1),.ifft(1'b0));
reg [5:0] count;
reg [2:0] state;
reg flag;
initial begin
state<=0;
count<=0;
flag<=0;
startReg<=0;
dataREstage1[0]<=0;
dataIMstage1[0]<=0;
dataREstage1[16]<=0;
dataIMstage1[16]<=0;
end
always@(posedge CLK) begin
if(RST) begin
count<=32;
state<=0;
end
else if(START) begin
count<=0;
state<=0;
end
else if(ED)begin
RDY<=0;startReg<=0;
if(rdy1)begin
if(state==0)begin
state<=1;
count<=1;
end
if(state==2)begin
state<=3;
count<=1;
end
end
if(state==1)begin
if(count>=1&&count<=15)begin
dataREstage1[count]<=di1;
dataIMstage1[count]<=-1*dr1;
end
else if(count>=17&&count<=31)begin
dataREstage1[count]<=-1*di1;
dataIMstage1[count]<=dr1;
end
if(count<32)
count<=count+1;
//if(count<32)
//$display("count:%d %d+i%d",count-1,dataREstage1[count-1],dataIMstage1[count-1]);
if(count==31)
flag<=1;
if(count==32&&flag==1)begin
startReg<=1;state=2;flag<=0;count<=0;end
end
if(state==2)begin
RE<=dataREstage1[count];
IM<=dataIMstage1[count];
if(count<32)
count<=count+1;
end
if(state==3)begin
dataREstage1[32-count]<=(dr1>>>5);
dataIMstage1[32-count]<=(di1>>>5);
if(count<32)
count<=count+1;
if(count==31) begin
state<=4; count<=0;RDY<=1;end
//if(count<32)
//$display("count:%d %d+i%d",count-1,dataREstage1[count-1],dataIMstage1[count-1]);
end
else if(state==2&&rdy1) begin
dataREstage1[0]<=(dr1>>>5);
dataIMstage1[0]<=(di1>>>5);
end
if(state==4) begin
//$display("count:%d ")
DOReal<=dataREstage1[count];
DOImag<=dataIMstage1[count];
if(count<32)
count<=count+1;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_0_0/affine_block_ieee754_fp_multiplier_0_0_stub.v
// Design : affine_block_ieee754_fp_multiplier_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ieee754_fp_multiplier,Vivado 2016.4" *)
module affine_block_ieee754_fp_multiplier_0_0(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z[31:0]" */;
input [31:0]x;
input [31:0]y;
output [31:0]z;
endmodule
|
#include <bits/stdc++.h> long long stk[300001][3], top = 1, n, m, best = 1, nownum, K, B; long long eval(long long x) { return (K + stk[x][0]) * stk[x][2] + B + stk[x][1]; } double intersect(long long x, long long y) { return (double)(stk[x][0] - stk[y][0]) / (stk[y][1] - stk[x][1]); } bool comp(long long x) { return eval(top) * (stk[top][2] - stk[top - 1][2]) >= (eval(top - 1) - eval(top)) * (x - stk[top][2]); } signed main() { scanf( %I64d%I64d , &nownum, &m); --nownum; for (long long i = 1, opt, k, b, s; i <= m; i++) { scanf( %I64d , &opt); if (opt == 1) { scanf( %I64d , &k); top = 1; K = B = 0; stk[top][0] = 0; stk[top][1] = 0; stk[top][2] = 0; nownum += k; } else if (opt == 2) { scanf( %I64d , &k); if (eval(top) == 0) { nownum += k; goto loop; } while (top > 1 && comp(nownum + 1)) --top; ++top; stk[top][0] = -K; stk[top][1] = -B; stk[top][2] = nownum + 1; nownum += k; } else { scanf( %I64d%I64d , &b, &s); K += s; B += b; while (top > 1 && eval(top - 1) <= eval(top)) --top; } loop: printf( %I64d %I64d n , stk[top][2] + 1, eval(top)); } }
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// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im:1.0
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_0 (
RST_N,
CLK,
I_MEM_WAIT,
I_MEM_ENA,
I_MEM_ADDR,
I_MEM_RDATA,
I_MEM_BADMEM_EXCPT,
D_MEM_WAIT,
D_MEM_ENA,
D_MEM_WSTB,
D_MEM_ADDR,
D_MEM_WDATA,
D_MEM_RDATA,
D_MEM_BADMEM_EXCPT,
EXT_INTERRUPT,
TIMER_EXPIRED
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_WAIT" *)
input wire I_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ENA" *)
output wire I_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] I_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] I_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire I_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WAIT" *)
input wire D_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ENA" *)
output wire D_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WSTB" *)
output wire [3 : 0] D_MEM_WSTB;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] D_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WDATA" *)
output wire [31 : 0] D_MEM_WDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] D_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire D_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 EXT_INTERRUPT INTERRUPT" *)
input wire EXT_INTERRUPT;
input wire TIMER_EXPIRED;
fmrv32im #(
.MADD33_ADDON(0)
) inst (
.RST_N(RST_N),
.CLK(CLK),
.I_MEM_WAIT(I_MEM_WAIT),
.I_MEM_ENA(I_MEM_ENA),
.I_MEM_ADDR(I_MEM_ADDR),
.I_MEM_RDATA(I_MEM_RDATA),
.I_MEM_BADMEM_EXCPT(I_MEM_BADMEM_EXCPT),
.D_MEM_WAIT(D_MEM_WAIT),
.D_MEM_ENA(D_MEM_ENA),
.D_MEM_WSTB(D_MEM_WSTB),
.D_MEM_ADDR(D_MEM_ADDR),
.D_MEM_WDATA(D_MEM_WDATA),
.D_MEM_RDATA(D_MEM_RDATA),
.D_MEM_BADMEM_EXCPT(D_MEM_BADMEM_EXCPT),
.EXT_INTERRUPT(EXT_INTERRUPT),
.TIMER_EXPIRED(TIMER_EXPIRED)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; for (int i = 0; i <= t / (1234567); i++) { for (int j = 0; j <= t / 123456; j++) { if (t - (i * 1234567) - (j * 123456) >= 0 && ((t - (i * 1234567) - (j * 123456)) % 1234 == 0)) { cout << YES ; return 0; } } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; int n, m, p; const double PI = acos(-1); vector<int> a, b; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> n >> m >> p; for (int i = (int)1; i <= (int)n; i++) { int x; cin >> x; a.push_back(x); } for (int i = (int)1; i <= (int)m; i++) { int x; cin >> x; b.push_back(x); } int i = 0, j = 0; while (i < n) { if (a[i] % p != 0) break; i++; } while (j < m) { if (b[j] % p != 0) break; j++; } cout << i + j << endl; }
|
//Listing 9.3
module kb_code
// #(parameter W_SIZE = 2) // 2^W_SIZE words in FIFO
(
input wire clk, reset,scan_done_tick,
input wire [7:0] scan_out,
output reg got_code_tick
);
// constant declaration
localparam BRK = 8'hf0; // break code
// symbolic state declaration
localparam
wait_brk = 1'b0,
get_code = 1'b1;
// signal declaration
reg state_reg, state_next;
//=======================================================
// FSM to get the scan code after F0 received
//=======================================================
// state registers
always @(posedge clk, posedge reset)
if (reset)
state_reg <= wait_brk;
else
state_reg <= state_next;
// next-state logic
always @*
begin
got_code_tick = 1'b0;
state_next = state_reg;
case (state_reg)
wait_brk: // wait for F0 of break code
if (scan_done_tick==1'b1 && scan_out==BRK)
state_next = get_code;
get_code: // get the following scan code
if (scan_done_tick)
begin
got_code_tick =1'b1;
state_next = wait_brk;
end
endcase
end
endmodule
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