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#include <bits/stdc++.h> using namespace std; int a[200001]; int b[200000]; int c[200001]; int main() { int n, i, j; cin >> n; map<int, int> m; for (i = 0; i < n; i++) { cin >> b[i]; m[b[i]]++; a[b[i]] = 1; } vector<int> v; for (i = 1; i <= n; i++) { if (a[i] == 0) { v.push_back(i); } } sort(v.begin(), v.end()); cout << v.size() << endl; int p = 0; for (i = 0; i < n; i++) { if (c[b[i]] == 1) { cout << v[p] << ; p++; c[b[i]] = 1; m[b[i]]--; } else { if (m[b[i]] == 1) { cout << b[i] << ; } else if (m[b[i]] > 1) { if (v[p] < b[i]) { cout << v[p] << ; m[b[i]]--; p++; } else { cout << b[i] << ; c[b[i]] = 1; m[b[i]]--; } } } } return 0; }
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/*****************************************************************************
* File : processing_system7_bfm_v2_0_regc.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int win(long long s, long long e) { if (e % 2 == 1) { if (s % 2 == 1) return 0; else return 1; } else { if (2 * s > e) { if (s % 2 == 1) return 1; else return 0; } else if (2 * s <= e && 4 * s > e) { return 1; } else return win(s, e / 4); } } int lose(long long s, long long e) { if (2 * s > e) return 1; else return win(s, e / 2); } int Win[N], Lose[N]; int get_lose(int x); int get_win(int x); int get_win(int x) { if (x == 1) return Win[1]; return Win[x] ? get_lose(x - 1) : get_win(x - 1); } int get_lose(int x) { if (x == 1) return Lose[1]; return Lose[x] ? get_lose(x - 1) : get_win(x - 1); } void io() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); } int main(int argc, char const *argv[]) { io(); int t; cin >> t; long long s, e; for (int i = 1; i <= t; i++) { cin >> s >> e; Win[i] = win(s, e); Lose[i] = lose(s, e); } cout << get_win(t) << << get_lose(t) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; unsigned N, M; vector<unsigned> V; double dens(const unsigned idxV1, const unsigned idxV2, const unsigned eW) { if (eW == 0) { return 0; } return (double)(V[idxV1] + V[idxV2]) / (double)eW; } int main() { unsigned v1, v2, w, n, m; double densidad; double max = 0; cout << setprecision(20); cin >> N; cin >> M; V = vector<unsigned>(N); for (n = 0; n < N; n++) { cin >> w; V[n] = w; } for (m = 0; m < M; m++) { cin >> v1; cin >> v2; cin >> w; v1--; v2--; densidad = dens(v1, v2, w); if (densidad > max) { max = densidad; } } cout << max << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.length(); bool sign = false; for (int i = 0; i < n; i++) { if (s[i] == a && !sign) continue; if (s[i] == a && sign) break; s[i]--; sign = true; } if (!sign) s[n - 1] = z ; cout << s << n ; }
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#include <bits/stdc++.h> using namespace std; const int pi = 3.14159265; const int INF = 1 << 30; const int maxn = 1e5; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, k; string s; cin >> n >> k; cin >> s; int t = s.find( T ); int g = s.find( G ); if (g > t) swap(t, g); for (int i = g; i < n && i <= t; i += k) { if (s[i] == # ) { cout << NO << endl; return 0; } if (i == t) { cout << YES << endl; return 0; } } cout << NO << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; scanf( %d %d %d %d , &a, &b, &c, &d); int M, M1, M2, V, V1, V2; M1 = (3 * a) / 10; M2 = (a - (a / 250) * c); if (M1 > M2) { M = M1; } else { M = M2; } V1 = (3 * b) / 10; V2 = (b - (b / 250) * d); if (V1 > V2) { V = V1; } else { V = V2; } if (M > V) { printf( Misha n ); } else { if (V > M) { printf( Vasya ); } else { printf( Tie ); } } return 0; }
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#include <bits/stdc++.h> using namespace std; int a[100002]; int gcd(int a, int b) { int c; while (a != 0) { c = a; a = b % a; b = c; } return b; } int main() { int n; int mina = 2000000009; cin >> n; cin >> a[1]; int ucln; ucln = a[1]; for (long long int i = 2; i <= n; i++) { scanf( %d , a + i); ucln = gcd(ucln, a[i]); } int res0 = 1; for (long long int i = 1; i <= n; i++) { if (a[i] % ucln != 0) { res0 = 0; } } if (ucln == 1) { res0 = 0; } if (res0 == 1) { cout << YES n ; cout << 0; } else { a[n + 1] = 2; int res = 0; for (int i = 1; i <= n;) { if (a[i] % 2 == 0) { i++; } else { if (a[i + 1] % 2 == 1) { res += 1; i += 2; } else { res += 2; i += 2; } } } cout << YES n ; cout << res; } }
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/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
module RegFileLoadSyn
(CLK, RST_N,
ADDR_IN, D_IN, WE,
ADDR_1, D_OUT_1
);
parameter file = "";
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
parameter binary = 0;
input CLK;
input RST_N;
input [addr_width - 1 : 0] ADDR_IN;
input [data_width - 1 : 0] D_IN;
input WE;
input [addr_width - 1 : 0] ADDR_1;
output [data_width - 1 : 0] D_OUT_1;
reg [data_width - 1 : 0] arr[lo:hi];
initial
begin : init_block
$readmemh(file, arr, lo, hi);
end
always@(posedge CLK)
begin
if (WE && RST_N)
arr[ADDR_IN] <= D_IN;
end // always@ (posedge CLK)
assign D_OUT_1 = arr[ADDR_1];
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n, k; scanf( %d%d , &n, &k); long long ans1 = 1, ans2 = 1; for (int i = 1; i <= k - 1; i++) ans1 = ans1 * k % 1000000007; for (int i = 1; i <= n - k; i++) ans2 = ans2 * (n - k) % 1000000007; printf( %I64d n , ans1 * ans2 % 1000000007); return 0; }
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#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double eps = 0.0000000001; const int N = 100000 + 100; int head[N]; int tot; struct node { int to, next; } edge[N << 1]; int color[N]; int vis[N]; int a[N]; int b[N]; int num[N]; void init() { memset(head, -1, sizeof(head)); tot = 0; } void add(int u, int v) { edge[tot].to = v; edge[tot].next = head[u]; head[u] = tot++; } int DFS(int u, int t) { if (vis[u] == 0) { if (color[u] == 0) a[t]++; if (color[u] == 1) b[t]++; num[t]++; } vis[u] = 1; for (int i = head[u]; i != -1; i = edge[i].next) { int v = edge[i].to; if (color[v] == 0) { color[v] = color[u] ^ 1; if (DFS(v, t) == 0) return 0; } else if (color[u] == color[v]) { return 0; } } return 1; } int main() { int n, m; scanf( %d%d , &n, &m); init(); int u, v; for (int i = 1; i <= m; i++) { scanf( %d%d , &u, &v); add(u, v); add(v, u); } if (m == 0) { cout << 3 << << (long long)n * (n - 1) * (n - 2) / 6 << endl; return 0; } memset(color, 0, sizeof(color)); memset(vis, 0, sizeof(vis)); int flag = 0; int t = 0; for (int i = 1; i <= n; i++) { if (color[i] == 0 && vis[i] == 0) { if (DFS(i, ++t) == 0) { color[i] = 0; flag = 1; break; } } } if (flag == 1) { cout << 0 << << 1 << endl; return 0; } long long ans = 0; flag = 0; for (int i = 1; i <= t; i++) { if (num[i] <= 2) { flag++; continue; } ans = ans + (long long)a[i] * (a[i] - 1) / 2 + (long long)b[i] * (b[i] - 1) / 2; } if (flag != t) cout << 1 << << ans << endl; else { cout << 2 << << (long long)m * (n - 2) << endl; } }
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#include <bits/stdc++.h> using namespace std; int n; int a[100007], ans[100007], vis[100007]; int count(int x) { int cnt = 0, now = 0; memset(vis, 255, sizeof(vis)); for (int i = 1; i <= n; i++) { if (vis[a[i]] == now) continue; vis[a[i]] = now; if (++cnt > x) { cnt = 1; vis[a[i]] = ++now; } } return now + 1; } void work(int l, int r) { if (l > r) return; int cnt1 = count(l), cnt2 = count(r); if (cnt1 == cnt2) { for (int i = l; i <= r; i++) ans[i] = cnt1; return; } ans[l] = cnt1; ans[r] = cnt2; int mid = (l + r) >> 1; work(l + 1, mid); work(mid + 1, r - 1); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); work(1, n); for (int i = 1; i <= n; i++) printf( %d , ans[i]); return 0; }
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// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: string_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module string_rom
#( parameter A_WIDTH = 13,
parameter D_WIDTH = 16,
parameter INIT_FILE = "2.mif"
)
(
clock,
address,
q);
input [A_WIDTH-1:0] address;
input clock;
output [D_WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [D_WIDTH-1:0] sub_wire0;
wire [D_WIDTH-1:0] q = sub_wire0[D_WIDTH-1:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({D_WIDTH{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = INIT_FILE,
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2**A_WIDTH,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = A_WIDTH,
altsyncram_component.width_a = D_WIDTH,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../font/2"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../font/2"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL string_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL string_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL string_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL string_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL string_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL string_rom_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n; cin >> n; vector<int> a(101); for (int i = 0; i < n; i++) { int x; cin >> x; ++a[x]; } cout << *max_element(a.begin(), a.end()) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); template <typename T, typename U> inline void amin(T &x, U y) { if (y < x) x = y; } template <typename T, typename U> inline void amax(T &x, U y) { if (x < y) x = y; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) n ; } template <class T> ostream &operator<<(ostream &os, set<T> V) { os << [ ; for (auto vv : V) os << vv << , ; return os << b b] n ; } template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto vv : V) os << vv << , ; return os << b b] n ; } template <class K, class X> ostream &operator<<(ostream &os, map<K, X> V) { os << [ ; for (auto vv : V) os << vv << , ; return os << b b] n ; } long int ceildiv(long int n, long int f) { if (n % f) { return n / f + 1; } else return n / f; } string checkTicket(vector<long> first, vector<long> second) { int n = first.size(); if (first[0] < second[0]) { for (int i = 0; i < n; i += 1) { if (first[i] >= second[i]) { return NO n ; } } } else if (first[0] > second[0]) { for (int i = 0; i < n; i += 1) { if (first[i] <= second[i]) { return NO n ; } } } else { return NO n ; } return YES n ; } int main() { long int n; cin >> n; string s; cin >> s; vector<long> first, second; for (int i = 0; i < n; i++) { first.push_back(s[i] - 0 ); } for (int i = n; i < 2 * n; i++) { second.push_back(s[i] - 0 ); } sort(first.begin(), first.end()); sort(second.begin(), second.end()); cerr << first << second; cout << checkTicket(first, second); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long maxn = 400010, inf = 1e18; long long q, lastans, cnt = 1, w[maxn]; long long fa[maxn][21], sum[maxn][21]; void add(long long x, long long v) { w[++cnt] = v; if (w[cnt] <= w[x]) fa[cnt][0] = x; else { int y = x; for (int i = 20; i >= 0; i--) { if (w[fa[y][i]] < w[cnt]) y = fa[y][i]; } fa[cnt][0] = fa[y][0]; } if (fa[cnt][0] == 0) sum[cnt][0] = inf; else sum[cnt][0] = w[fa[cnt][0]]; for (int i = 1; i <= 20; i++) { fa[cnt][i] = fa[fa[cnt][i - 1]][i - 1]; if (fa[cnt][i] == 0) sum[cnt][i] = inf; else sum[cnt][i] = sum[cnt][i - 1] + sum[fa[cnt][i - 1]][i - 1]; } } long long query(long long x, long long v) { if (w[x] > v) return 0; v -= w[x]; long long res = 1; for (int i = 20; i >= 0; i--) { if (v >= sum[x][i]) { v -= sum[x][i]; res += (1 << i); x = fa[x][i]; } } return res; } int main() { w[0] = inf; for (int i = 0; i <= 20; i++) sum[1][i] = inf; scanf( %lld , &q); while (q--) { int id; long long a, b; scanf( %d , &id); scanf( %lld%lld , &a, &b); a ^= lastans; b ^= lastans; if (id == 1) add(a, b); else printf( %lld n , lastans = query(a, b)); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200000 + 10; const int hashnum = 3; long long base[] = {233, 23, 97}; long long mod[] = {122420729, 1000000007, 1000000009}; int sum[maxn]; char s[maxn]; long long power[hashnum][maxn]; int n; struct node { long long hv[hashnum]; int pref, suf, len; }; node zer; inline void init() { zer.pref = zer.suf = zer.len = 0; for (int i = (0); i < (hashnum); ++i) zer.hv[i] = 0; for (int i = (0); i < (hashnum); ++i) { power[i][0] = 1; for (int j = (1); j < (maxn); ++j) power[i][j] = power[i][j - 1] * base[i] % mod[i]; } } node merge(node& a, node& b) { node c = zer; if (a.len == 0 && b.len == 0) c.suf = c.pref = a.pref + b.pref; else if (a.len == 0) c = b, c.pref += a.pref; else if (b.len == 0) c = a, c.suf += b.pref; else { c.len = a.len + b.len + (a.suf + b.pref) % 2; c.pref = a.pref; c.suf = b.suf; for (int i = (0); i < (hashnum); ++i) { if ((a.suf + b.pref) % 2 == 1) { c.hv[i] = a.hv[i] * power[i][b.len + 1] % mod[i]; (c.hv[i] += 2 * power[i][b.len] % mod[i]) %= mod[i]; (c.hv[i] += b.hv[i]) %= mod[i]; } else { c.hv[i] = a.hv[i] * power[i][b.len] % mod[i]; (c.hv[i] += b.hv[i]) %= mod[i]; } } } return c; } struct segtree { node t[maxn << 2]; int n, ql, qr; node ans; void init(int n) { this->n = n; } void maintain(int o) { t[o] = merge(t[o << 1], t[o << 1 | 1]); } void build(int l, int r, int o) { t[o] = zer; if (l == r) { if (s[l] == 0 ) { t[o].len++; for (int i = (0); i < (hashnum); ++i) t[o].hv[i] = 1; } else t[o].suf = t[o].pref = 1; return; } int mid = l + r >> 1; build(l, mid, o << 1), build(mid + 1, r, o << 1 | 1); maintain(o); } void query(int l, int r, int o) { if (ql <= l && qr >= r) ans = merge(ans, t[o]); else { int mid = l + r >> 1; if (ql <= mid) query(l, mid, o << 1); if (qr > mid) query(mid + 1, r, o << 1 | 1); } } node Query(int l, int r) { ans = zer; ql = l, qr = r; query(1, n, 1); return ans; } }; segtree tree; bool judge(node& a, node& b) { if (a.suf % 2 != b.suf % 2 || a.pref % 2 != b.pref % 2 || a.len != b.len) return false; for (int i = (0); i < (hashnum); ++i) if (a.hv[i] != b.hv[i]) return false; return true; } int main(void) { scanf( %d%s , &n, s + 1); init(); tree.init(n); tree.build(1, n, 1); for (int i = (1); i <= (n); ++i) { sum[i] = sum[i - 1]; if (s[i] == 1 ) sum[i]++; } int q; scanf( %d , &(q)); for (; q--;) { int l1, l2, r1, r2, len; scanf( %d%d%d , &l1, &l2, &len); r1 = l1 + len - 1; r2 = l2 + len - 1; if (sum[r2] - sum[l2 - 1] != sum[r1] - sum[l1 - 1]) { puts( No ); continue; } node x = tree.Query(l1, r1); node y = tree.Query(l2, r2); if (judge(x, y)) puts( Yes ); else puts( No ); } return 0; }
|
module count_minutes(
manual_inc,
automatic_inc,
ones_digit,
tens_digit,
count_out
);
// port declarations
input manual_inc;
input automatic_inc;
output [3:0] ones_digit;
output [3:0] tens_digit;
output reg count_out;
// wire declarations
wire carry;
reg module_reset;
reg pre_count;
reg increment;
// teh logikz
initial module_reset <= 0;
bcd_counter u1(module_reset, increment, ones_digit, carry);
bcd_counter u2(module_reset, carry, tens_digit, );
always begin
if (manual_inc) begin
// we handle manual increments by setting count_out to zero by default
// - as to not worry about incrementing the other set of digits when
// - incrementing this one.
count_out <= 0;
increment <= 1;
end else begin
// In the general case, we simply route pre_count (or module_reset)
// - into count out to let the proceeding module know that we have reset
increment <= automatic_inc;
count_out <= module_reset;
end
// here's a bunch of module reset logic
module_reset <= (tens_digit == 4'h6);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int i, j, k, l, s[1000005], n, m, tot, last[1000005], Next[1000005], to[1000005], dfn[1000005], low[1000005]; int vis[1000005], q[1000005], Q[1000005], q1[1000005], r, r1, G[1000005], T; vector<int> gt; int ans[1000005], A[1000005], B[1000005], a[1000005], b[1000005], x, y; inline void add(int x, int y) { Next[++tot] = last[x]; last[x] = tot; to[tot] = y; } inline void tarjan(int x) { dfn[x] = low[x] = ++tot; q[++r] = x; vis[x] = 1; for (int i = last[x]; i; i = Next[i]) { if (!dfn[to[i]]) tarjan(to[i]), low[x] = min(low[x], low[to[i]]); else if (vis[to[i]]) low[x] = min(low[x], low[to[i]]); } if (low[x] == dfn[x]) { ++T; while (q[r] != x) { G[q[r]] = T; vis[q[r]] = 0; r--; s[T]++; } G[q[r]] = T; vis[q[r]] = 0; r--; s[T]++; } } inline void bfs(int x) { int l = 0, r = 1; Q[1] = x; while (l < r) { int k = Q[++l]; for (int i = last[k]; i; i = Next[i]) { if (!vis[to[i]]) vis[Q[++r] = to[i]] = 1; } } } inline bool check(int x, int y) { int s = 0; int p = x; while (x) { s += x & 1; x >>= 1; } x = y; while (x) { s -= x & 1; x >>= 1; } if (s > 0) return true; if (s < 0) return false; if (s == 0 && p != (1 << r1) - 1) return true; return false; } int main() { scanf( %d%d , &n, &m); if (n == 1) return puts( YES ), 0; for (i = 1; i <= m; i++) scanf( %d%d , &x, &y), add(x, y); tot = 0; for (i = 1; i <= n; i++) if (!dfn[i]) tarjan(i); for (i = 1; i <= n; i++) for (j = last[i]; j; j = Next[j]) { B[G[to[j]]]++, A[G[i]]++; if (G[to[j]] != G[i]) a[G[i]] = b[G[to[j]]] = 1; } for (i = 1; i <= T; i++) if (!A[i] && !B[i]) return puts( NO ), 0; for (i = 1; i <= n; i++) { if (!A[G[i]]) gt.push_back(i); else if (!B[G[i]]) q1[++r1] = i; } for (i = 1; i <= T; i++) { if (A[i] && B[i] && r1 && (!a[i] || !b[i])) return puts( NO ), 0; } if (!r1 && T > 1) return puts( NO ), 0; for (i = 1; i <= r1; i++) { for (j = 1; j <= n; j++) vis[j] = 0; bfs(q1[i]); for (j = 0; j < gt.size(); j++) if (vis[gt[j]]) ans[i] += (1 << (j)); } for (i = 1; i < (1 << r1); i++) { int x = i; int s = 0, t = 1; while (x) { if (x & 1) s |= ans[t]; t++; x >>= 1; } if (check(i, s)) return puts( NO ), 0; } puts( YES ); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int c, r; cin >> c >> r; bool flag = true; for (int i = 1; i <= c; i++) { if (i & 1) { for (int j = 1; j <= r; j++) { cout << # ; } cout << endl; } else { if (flag) { for (int j = 1; j <= r - 1; j++) { cout << . ; } cout << # << endl; flag = false; } else { cout << # ; for (int j = 1; j <= r - 1; j++) { cout << . ; } cout << endl; flag = true; } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_DIODE_PP_SYMBOL_V
`define SKY130_FD_SC_HS__FILL_DIODE_PP_SYMBOL_V
/**
* fill_diode: Fill diode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fill_diode (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_DIODE_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, a[100010]; long long t; int main() { cin >> n >> m; a[0] = 1; for (int i = 1; i <= m; i++) { cin >> a[i]; if (a[i] > a[i - 1]) t += (a[i] - a[i - 1]); if (a[i] < a[i - 1]) t += (n - a[i - 1] + a[i]); } cout << t; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n1, n2, k1, k2; cin >> n1 >> n2 >> k1 >> k2; if (n1 > n2) { cout << First ; } else { cout << Second ; } return 0; }
|
// cog_ctr
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ctr
(
input clk_cog,
input clk_pll,
input ena,
input setctr,
input setfrq,
input setphs,
input [31:0] data,
input [31:0] pin_in,
output reg [32:0] phs,
output [31:0] pin_out,
output pll
);
// control
reg [31:0] ctr;
reg [31:0] frq;
always @(posedge clk_cog or negedge ena)
if (!ena)
ctr <= 32'b0;
else if (setctr)
ctr <= data;
always @(posedge clk_cog)
if (setfrq)
frq <= data;
always @(posedge clk_cog)
if (setphs || trig)
phs <= setphs ? {1'b0, data} : {1'b0, phs[31:0]} + {1'b0, frq};
// input pins
reg [1:0] dly;
always @(posedge clk_cog)
if (|ctr[30:29])
dly <= {ctr[30] ? pin_in[ctr[13:9]] : dly[0], pin_in[ctr[4:0]]};
// trigger, outputs
// trigger outb outa
wire [15:0][2:0] tp = { dly == 2'b10, !dly[0], 1'b0, // neg edge w/feedback
dly == 2'b10, 1'b0, 1'b0, // neg edge
!dly[0], !dly[0], 1'b0, // neg w/feedback
!dly[0], 1'b0, 1'b0, // neg
dly == 2'b01, !dly[0], 1'b0, // pos edge w/feedback
dly == 2'b01, 1'b0, 1'b0, // pos edge
dly[0], !dly[0], 1'b0, // pos w/feedback
dly[0], 1'b0, 1'b0, // pos
1'b1, !phs[32], phs[32], // duty differential
1'b1, 1'b0, phs[32], // duty single
1'b1, !phs[31], phs[31], // nco differential
1'b1, 1'b0, phs[31], // nco single
1'b1, !pll, pll, // pll differential
1'b1, 1'b0, pll, // pll single
1'b1, 1'b0, 1'b0, // pll internal
1'b0, 1'b0, 1'b0 }; // off
wire [3:0] pick = ctr[29:26];
wire [2:0] tba = tp[pick];
wire trig = ctr[30] ? pick[dly] : tba[2]; // trigger
wire outb = ctr[30] ? 1'b0 : tba[1]; // outb
wire outa = ctr[30] ? 1'b0 : tba[0]; // outa
// output pins
assign pin_out = outb << ctr[13:9] | outa << ctr[4:0];
// pll simulator
reg [35:0] pll_fake;
always @(posedge clk_pll)
if (~&ctr[30:28] && |ctr[27:26])
pll_fake <= pll_fake + {4'b0, frq};
wire [7:0] pll_taps = pll_fake[35:28];
assign pll = pll_taps[~ctr[25:23]];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:35 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: channel_init_sm.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// CHANNEL_INIT_SM
//
//
// Description: the CHANNEL_INIT_SM module is a state machine for managing channel
// bonding and verification.
//
// The channel init state machine is reset until the lane up signals
// of all the lanes that constitute the channel are asserted. It then
// requests channel bonding until the lanes have been bonded and
// checks to make sure the bonding was successful. Channel bonding is
// skipped if there is only one lane in the channel. If bonding is
// unsuccessful, the lanes are reset.
//
// After the bonding phase is complete, the state machine sends
// verification sequences through the channel until it is clear that
// the channel is ready to be used. If verification is successful,
// the CHANNEL_UP signal is asserted. If it is unsuccessful, the
// lanes are reset.
//
// After CHANNEL_UP goes high, the state machine is quiescent, and will
// reset only if one of the lanes goes down, a hard error is detected, or
// a general reset is requested.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 10 ps
module aurora_201_CHANNEL_INIT_SM
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP,
START_RX,
// Idle and Verification Sequence Generator Interface
DID_VER,
GEN_VER,
// Channel Error Management Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
output CHANNEL_UP;
output START_RX;
// Idle and Verification Sequence Generator Interface
input DID_VER;
output GEN_VER;
// Channel Init State Machine Interface
input RESET_CHANNEL;
//***************************External Register Declarations***************************
reg START_RX;
//***************************Internal Register Declarations***************************
reg free_count_done_r;
reg [0:15] verify_watchdog_r;
reg all_lanes_v_r;
reg got_first_v_r;
reg [0:31] v_count_r;
reg bad_v_r;
reg [0:2] rxver_count_r;
reg [0:7] txver_count_r;
// State registers
reg wait_for_lane_up_r;
reg verify_r;
reg ready_r;
//*********************************Wire Declarations**********************************
wire free_count_1_r;
wire free_count_2_r;
wire insert_ver_c;
wire verify_watchdog_done_r;
wire rxver_3d_done_r;
wire txver_8d_done_r;
wire reset_lanes_c;
// Next state signals
wire next_verify_c;
wire next_ready_c;
//*********************************Main Body of Code**********************************
//________________Main state machine for bonding and verification________________
// State registers
always @(posedge USER_CLK)
if(RESET|RESET_CHANNEL)
begin
wait_for_lane_up_r <= `DLY 1'b1;
verify_r <= `DLY 1'b0;
ready_r <= `DLY 1'b0;
end
else
begin
wait_for_lane_up_r <= `DLY 1'b0;
verify_r <= `DLY next_verify_c;
ready_r <= `DLY next_ready_c;
end
// Next state logic
assign next_verify_c = wait_for_lane_up_r |
(verify_r & (!rxver_3d_done_r|!txver_8d_done_r));
assign next_ready_c = (verify_r & txver_8d_done_r & rxver_3d_done_r)|
ready_r;
// Output Logic
// Channel up is high as long as the Global Logic is in the ready state.
assign CHANNEL_UP = ready_r;
// Turn the receive engine on as soon as all the lanes are up.
always @(posedge USER_CLK)
if(RESET) START_RX <= `DLY 1'b0;
else START_RX <= `DLY !wait_for_lane_up_r;
// Generate the Verification sequence when in the verify state.
assign GEN_VER = verify_r;
//__________________________Channel Reset _________________________________
// Some problems during channel bonding and verification require the lanes to
// be reset. When this happens, we assert the Reset Lanes signal, which gets
// sent to all Aurora Lanes. When the Aurora Lanes reset, their LANE_UP signals
// go down. This causes the Channel Error Detector to assert the Reset Channel
// signal.
assign reset_lanes_c = (verify_r & verify_watchdog_done_r)|
(verify_r & bad_v_r & !rxver_3d_done_r)|
(RESET_CHANNEL & !wait_for_lane_up_r)|
RESET;
defparam reset_lanes_flop_i.INIT = 1'b1;
FD reset_lanes_flop_i
(
.D(reset_lanes_c),
.C(USER_CLK),
.Q(RESET_LANES)
);
//___________________________Watchdog timers____________________________________
// We create a free counter out of SRLs to count large values without excessive cost.
defparam free_count_1_i.INIT = 16'h8000;
SRL16 free_count_1_i
(
.Q(free_count_1_r),
.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CLK(USER_CLK),
.D(free_count_1_r)
);
defparam free_count_2_i.INIT = 16'h8000;
SRL16E free_count_2_i
(
.Q(free_count_2_r),
.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CLK(USER_CLK),
.CE(free_count_1_r),
.D(free_count_2_r)
);
// Finally we have logic that registers a pulse when both the inner and the
// outer SRLs have a bit in their last position. This should map to carry logic
// and a register.
always @(posedge USER_CLK)
free_count_done_r <= `DLY free_count_2_r & free_count_1_r;
// We use the freerunning count as a CE for the verify watchdog. The
// count runs continuously so the watchdog will vary between a count of 4096
// and 3840 cycles - acceptable for this application.
always @(posedge USER_CLK)
if(free_count_done_r | !verify_r)
verify_watchdog_r <= `DLY {verify_r,verify_watchdog_r[0:14]};
assign verify_watchdog_done_r = verify_watchdog_r[15];
//_____________________________Channel Bonding_______________________________
// We don't use channel bonding for the single lane case, so we tie the
// EN_CHAN_SYNC signal low.
assign EN_CHAN_SYNC = 1'b0;
//________________________________Verification__________________________
// Vs need to appear on all lanes simultaneously.
always @(posedge USER_CLK)
all_lanes_v_r <= `DLY GOT_V;
// Vs need to be decoded by the aurora lane and then checked by the
// Global logic. They must appear periodically.
always @(posedge USER_CLK)
if(!verify_r) got_first_v_r <= `DLY 1'b0;
else if(all_lanes_v_r) got_first_v_r <= `DLY 1'b1;
assign insert_ver_c = all_lanes_v_r & !got_first_v_r | (v_count_r[31] & verify_r);
// Shift register for measuring the time between V counts.
always @(posedge USER_CLK)
v_count_r <= `DLY {insert_ver_c,v_count_r[0:30]};
// Assert bad_v_r if a V does not arrive when expected.
always @(posedge USER_CLK)
bad_v_r <= `DLY (v_count_r[31] ^ all_lanes_v_r) & got_first_v_r;
// Count the number of Ver sequences received. You're done after you receive four.
always @(posedge USER_CLK)
if((v_count_r[31] & all_lanes_v_r) |!verify_r)
rxver_count_r <= `DLY {verify_r,rxver_count_r[0:1]};
assign rxver_3d_done_r = rxver_count_r[2];
// Count the number of Ver sequences transmitted. You're done after you send eight.
always @(posedge USER_CLK)
if(DID_VER |!verify_r)
txver_count_r <= `DLY {verify_r,txver_count_r[0:6]};
assign txver_8d_done_r = txver_count_r[7];
endmodule
|
module top(input clk, ce, sr, d, output q);
/*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
cliff didn't have constrained, also got annoyed
he is using slightly later version
ERROR: [Place 30-1008] Instance roi/ffs[0].genblk1.genblk1.ff
has an inverted D pin which is unsupported in the UltraScale and UltraScale+ architectures.
which is fine except...he's using 7 series
and now...
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-488] Failed to commit 1 instances:
ff with block Id: 4 (FF) at SLICE_X0Y104
ERROR: [Place 30-99] Placer failed with error: 'failed to commit all instances'
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
failed with same message
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
built!
diff design_fdce.segd design_fdce_inv.segd
> tag CLBLL_L.SLICEL_X0.CLKINV
expected
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b0,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors.
Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
*/
(*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH
*)
FDCE ff (
.C(clk),
.CE(ce),
.CLR(sr),
.D(d),
.Q(q)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int hops[n + 1]; bool vis[n + 1]; int change[n + 1]; for (int i = 1; i <= n; ++i) { cin >> hops[i]; vis[i] = 0; } int cnt = 0; int cnt1 = 0; for (int i = 1; i <= n; ++i) { cin >> change[i]; if (change[i]) cnt1++; } for (int i = 1; i <= n; ++i) { if (!vis[i]) { int j = i; cnt++; while (vis[hops[j]] == false) { j = hops[j]; vis[j] = true; } } } if (cnt1 % 2) cnt1 = 0; else cnt1 = 1; if (cnt == 1) cnt = 0; cout << cnt + cnt1 << endl; }
|
#include <bits/stdc++.h> using namespace std; inline long long mod(long long n, long long m) { long long ret = n % m; if (ret < 0) ret += m; return ret; } long long gcd(long long a, long long b) { return (b == 0LL ? a : gcd(b, a % b)); } long long exp(long long a, long long b, long long m) { if (b == 0LL) return 1LL; if (b == 1LL) return mod(a, m); long long k = mod(exp(a, b / 2, m), m); if (b & 1LL) { return mod(a * mod(k * k, m), m); } else return mod(k * k, m); } vector<int> z_function(string s) { int n = s.size(); vector<int> z(n); int L = 0, R = 0; for (int i = 1; i < n; i++) { if (i <= R) { if (i - L + z[i - L] > i - L + (R - i)) { z[i] = R - i + 1; while (i + z[i] < n and s[z[i]] == s[z[i] + i]) { z[i]++; } } else z[i] = z[i - L]; } else { while (i + z[i] < n and s[z[i]] == s[z[i] + i]) { z[i]++; } } if (i + z[i] - 1 > R) { L = i, R = i + z[i] - 1; } } return z; } const int N = 1000100; int n, m, k; vector<int> order[N]; vector<int> get(string s, string t) { string aux = t + # + s; vector<int> z = z_function(aux); for (int i = 0; i < N; i++) order[i].clear(); for (int i = 0; i < n; i++) { if (z[i + m + 1] > 0) order[z[i + m + 1]].push_back(i); } set<int> best; vector<int> res((int)s.size() + 10, -1); for (int x = m; x > 0; x--) { for (int id : order[x]) { best.insert(id); } auto it = best.lower_bound(k - x); if (it == best.end()) continue; res[x] = *it; } return res; } vector<int> lpos, rpos; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> m >> k; string s, t; cin >> s >> t; string aux = t + # + s; vector<int> z = z_function(aux); for (int i = 0; i < n; i++) { if (z[i + 1 + m] >= m) { cout << Yes << n ; int l = min(i + 1, n - 2 * k + 1); int r = l + k; cout << l << << r << n ; return 0; } } lpos = get(s, t); reverse(s.begin(), s.end()); reverse(t.begin(), t.end()); rpos = get(s, t); for (int i = 1; i <= min(m - 1, k); i++) { if (m - i > k) continue; int id1 = lpos[i], id2 = rpos[m - i]; if (id1 == -1 or id2 == -1) continue; int L = lpos[i] + i - 1, R = rpos[m - i] + (m - i) - 1; if (L + R >= n - 1) continue; id1 = lpos[i] + i - (k - 1); id2 = n - rpos[m - i] - (m - i) + 1; if (id1 + k - 1 < id2 and id2 + k - 1 <= n) { cout << Yes << n ; cout << id1 << << id2 << n ; return 0; } } cout << No << n ; }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2016 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Export NumPrelude NZAxioms.
Require Import NZBase NZOrder NZAddOrder Plus Minus.
(** In this file, we investigate the shape of domains satisfying
the [NZDomainSig] interface. In particular, we define a
translation from Peano numbers [nat] into NZ.
*)
Local Notation "f ^ n" := (fun x => nat_rect _ x (fun _ => f) n).
Instance nat_rect_wd n {A} (R:relation A) :
Proper (R==>(R==>R)==>R) (fun x f => nat_rect (fun _ => _) x (fun _ => f) n).
Proof.
intros x y eq_xy f g eq_fg; induction n; [assumption | now apply eq_fg].
Qed.
Module NZDomainProp (Import NZ:NZDomainSig').
Include NZBaseProp NZ.
(** * Relationship between points thanks to [succ] and [pred]. *)
(** For any two points, one is an iterated successor of the other. *)
Lemma itersucc_or_itersucc n m : exists k, n == (S^k) m \/ m == (S^k) n.
Proof.
revert n.
apply central_induction with (z:=m).
{ intros x y eq_xy; apply ex_iff_morphism.
intros n; apply or_iff_morphism.
+ split; intros; etransitivity; try eassumption; now symmetry.
+ split; intros; (etransitivity; [eassumption|]); [|symmetry];
(eapply nat_rect_wd; [eassumption|apply succ_wd]).
}
exists 0%nat. now left.
intros n. split; intros [k [L|R]].
exists (Datatypes.S k). left. now apply succ_wd.
destruct k as [|k].
simpl in R. exists 1%nat. left. now apply succ_wd.
rewrite nat_rect_succ_r in R. exists k. now right.
destruct k as [|k]; simpl in L.
exists 1%nat. now right.
apply succ_inj in L. exists k. now left.
exists (Datatypes.S k). right. now rewrite nat_rect_succ_r.
Qed.
(** Generalized version of [pred_succ] when iterating *)
Lemma succ_swap_pred : forall k n m, n == (S^k) m -> m == (P^k) n.
Proof.
induction k.
simpl; auto with *.
simpl; intros. apply pred_wd in H. rewrite pred_succ in H. apply IHk in H; auto.
rewrite <- nat_rect_succ_r in H; auto.
Qed.
(** From a given point, all others are iterated successors
or iterated predecessors. *)
Lemma itersucc_or_iterpred : forall n m, exists k, n == (S^k) m \/ n == (P^k) m.
Proof.
intros n m. destruct (itersucc_or_itersucc n m) as (k,[H|H]).
exists k; left; auto.
exists k; right. apply succ_swap_pred; auto.
Qed.
(** In particular, all points are either iterated successors of [0]
or iterated predecessors of [0] (or both). *)
Lemma itersucc0_or_iterpred0 :
forall n, exists p:nat, n == (S^p) 0 \/ n == (P^p) 0.
Proof.
intros n. exact (itersucc_or_iterpred n 0).
Qed.
(** * Study of initial point w.r.t. [succ] (if any). *)
Definition initial n := forall m, n ~= S m.
Lemma initial_alt : forall n, initial n <-> S (P n) ~= n.
Proof.
split. intros Bn EQ. symmetry in EQ. destruct (Bn _ EQ).
intros NEQ m EQ. apply NEQ. rewrite EQ, pred_succ; auto with *.
Qed.
Lemma initial_alt2 : forall n, initial n <-> ~exists m, n == S m.
Proof. firstorder. Qed.
(** First case: let's assume such an initial point exists
(i.e. [S] isn't surjective)... *)
Section InitialExists.
Hypothesis init : t.
Hypothesis Initial : initial init.
(** ... then we have unicity of this initial point. *)
Lemma initial_unique : forall m, initial m -> m == init.
Proof.
intros m Im. destruct (itersucc_or_itersucc init m) as (p,[H|H]).
destruct p. now simpl in *. destruct (Initial _ H).
destruct p. now simpl in *. destruct (Im _ H).
Qed.
(** ... then all other points are descendant of it. *)
Lemma initial_ancestor : forall m, exists p, m == (S^p) init.
Proof.
intros m. destruct (itersucc_or_itersucc init m) as (p,[H|H]).
destruct p; simpl in *; auto. exists O; auto with *. destruct (Initial _ H).
exists p; auto.
Qed.
(** NB : We would like to have [pred n == n] for the initial element,
but nothing forces that. For instance we can have -3 as initial point,
and P(-3) = 2. A bit odd indeed, but legal according to [NZDomainSig].
We can hence have [n == (P^k) m] without [exists k', m == (S^k') n].
*)
(** We need decidability of [eq] (or classical reasoning) for this: *)
Section SuccPred.
Hypothesis eq_decidable : forall n m, n==m \/ n~=m.
Lemma succ_pred_approx : forall n, ~initial n -> S (P n) == n.
Proof.
intros n NB. rewrite initial_alt in NB.
destruct (eq_decidable (S (P n)) n); auto.
elim NB; auto.
Qed.
End SuccPred.
End InitialExists.
(** Second case : let's suppose now [S] surjective, i.e. no initial point. *)
Section InitialDontExists.
Hypothesis succ_onto : forall n, exists m, n == S m.
Lemma succ_onto_gives_succ_pred : forall n, S (P n) == n.
Proof.
intros n. destruct (succ_onto n) as (m,H). rewrite H, pred_succ; auto with *.
Qed.
Lemma succ_onto_pred_injective : forall n m, P n == P m -> n == m.
Proof.
intros n m. intros H; apply succ_wd in H.
rewrite !succ_onto_gives_succ_pred in H; auto.
Qed.
End InitialDontExists.
(** To summarize:
S is always injective, P is always surjective (thanks to [pred_succ]).
I) If S is not surjective, we have an initial point, which is unique.
This bottom is below zero: we have N shifted (or not) to the left.
P cannot be injective: P init = P (S (P init)).
(P init) can be arbitrary.
II) If S is surjective, we have [forall n, S (P n) = n], S and P are
bijective and reciprocal.
IIa) if [exists k<>O, 0 == S^k 0], then we have a cyclic structure Z/nZ
IIb) otherwise, we have Z
*)
(** * An alternative induction principle using [S] and [P]. *)
(** It is weaker than [bi_induction]. For instance it cannot prove that
we can go from one point by many [S] _or_ many [P], but only by many
[S] mixed with many [P]. Think of a model with two copies of N:
0, 1=S 0, 2=S 1, ...
0', 1'=S 0', 2'=S 1', ...
and P 0 = 0' and P 0' = 0.
*)
Lemma bi_induction_pred :
forall A : t -> Prop, Proper (eq==>iff) A ->
A 0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) ->
forall n, A n.
Proof.
intros. apply bi_induction; auto.
clear n. intros n; split; auto.
intros G; apply H2 in G. rewrite pred_succ in G; auto.
Qed.
Lemma central_induction_pred :
forall A : t -> Prop, Proper (eq==>iff) A -> forall n0,
A n0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) ->
forall n, A n.
Proof.
intros.
assert (A 0).
destruct (itersucc_or_iterpred 0 n0) as (k,[Hk|Hk]); rewrite Hk; clear Hk.
clear H2. induction k; simpl in *; auto.
clear H1. induction k; simpl in *; auto.
apply bi_induction_pred; auto.
Qed.
End NZDomainProp.
(** We now focus on the translation from [nat] into [NZ].
First, relationship with [0], [succ], [pred].
*)
Module NZOfNat (Import NZ:NZDomainSig').
Definition ofnat (n : nat) : t := (S^n) 0.
Notation "[ n ]" := (ofnat n) (at level 7) : ofnat.
Local Open Scope ofnat.
Lemma ofnat_zero : [O] == 0.
Proof.
reflexivity.
Qed.
Lemma ofnat_succ : forall n, [Datatypes.S n] == succ [n].
Proof.
now unfold ofnat.
Qed.
Lemma ofnat_pred : forall n, n<>O -> [Peano.pred n] == P [n].
Proof.
unfold ofnat. destruct n. destruct 1; auto.
intros _. simpl. symmetry. apply pred_succ.
Qed.
(** Since [P 0] can be anything in NZ (either [-1], [0], or even other
numbers, we cannot state previous lemma for [n=O]. *)
End NZOfNat.
(** If we require in addition a strict order on NZ, we can prove that
[ofnat] is injective, and hence that NZ is infinite
(i.e. we ban Z/nZ models) *)
Module NZOfNatOrd (Import NZ:NZOrdSig').
Include NZOfNat NZ.
Include NZBaseProp NZ <+ NZOrderProp NZ.
Local Open Scope ofnat.
Theorem ofnat_S_gt_0 :
forall n : nat, 0 < [Datatypes.S n].
Proof.
unfold ofnat.
intros n; induction n as [| n IH]; simpl in *.
apply lt_succ_diag_r.
apply lt_trans with (S 0). apply lt_succ_diag_r. now rewrite <- succ_lt_mono.
Qed.
Theorem ofnat_S_neq_0 :
forall n : nat, 0 ~= [Datatypes.S n].
Proof.
intros. apply lt_neq, ofnat_S_gt_0.
Qed.
Lemma ofnat_injective : forall n m, [n]==[m] -> n = m.
Proof.
induction n as [|n IH]; destruct m; auto.
intros H; elim (ofnat_S_neq_0 _ H).
intros H; symmetry in H; elim (ofnat_S_neq_0 _ H).
intros. f_equal. apply IH. now rewrite <- succ_inj_wd.
Qed.
Lemma ofnat_eq : forall n m, [n]==[m] <-> n = m.
Proof.
split. apply ofnat_injective. intros; now subst.
Qed.
(* In addition, we can prove that [ofnat] preserves order. *)
Lemma ofnat_lt : forall n m : nat, [n]<[m] <-> (n<m)%nat.
Proof.
induction n as [|n IH]; destruct m; repeat rewrite ofnat_zero; split.
intro H; elim (lt_irrefl _ H).
inversion 1.
auto with arith.
intros; apply ofnat_S_gt_0.
intro H; elim (lt_asymm _ _ H); apply ofnat_S_gt_0.
inversion 1.
rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith.
rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith.
Qed.
Lemma ofnat_le : forall n m : nat, [n]<=[m] <-> (n<=m)%nat.
Proof.
intros. rewrite lt_eq_cases, ofnat_lt, ofnat_eq.
split.
destruct 1; subst; auto with arith.
apply Lt.le_lt_or_eq.
Qed.
End NZOfNatOrd.
(** For basic operations, we can prove correspondance with
their counterpart in [nat]. *)
Module NZOfNatOps (Import NZ:NZAxiomsSig').
Include NZOfNat NZ.
Local Open Scope ofnat.
Lemma ofnat_add_l : forall n m, [n]+m == (S^n) m.
Proof.
induction n; intros.
apply add_0_l.
rewrite ofnat_succ, add_succ_l. simpl. now f_equiv.
Qed.
Lemma ofnat_add : forall n m, [n+m] == [n]+[m].
Proof.
intros. rewrite ofnat_add_l.
induction n; simpl. reflexivity.
now f_equiv.
Qed.
Lemma ofnat_mul : forall n m, [n*m] == [n]*[m].
Proof.
induction n; simpl; intros.
symmetry. apply mul_0_l.
rewrite plus_comm.
rewrite ofnat_add, mul_succ_l.
now f_equiv.
Qed.
Lemma ofnat_sub_r : forall n m, n-[m] == (P^m) n.
Proof.
induction m; simpl; intros.
apply sub_0_r.
rewrite sub_succ_r. now f_equiv.
Qed.
Lemma ofnat_sub : forall n m, m<=n -> [n-m] == [n]-[m].
Proof.
intros n m H. rewrite ofnat_sub_r.
revert n H. induction m. intros.
rewrite <- minus_n_O. now simpl.
intros.
destruct n.
inversion H.
rewrite nat_rect_succ_r.
simpl.
etransitivity. apply IHm. auto with arith.
eapply nat_rect_wd; [symmetry;apply pred_succ|apply pred_wd].
Qed.
End NZOfNatOps.
|
#include <bits/stdc++.h> using namespace std; struct Point { int x; int y; }; struct Rect { int left; int top; int right; int bottom; }; bool FindBoundary(const vector<Point> &pts, Rect *getRect) { if (pts.empty()) { return false; } auto it = pts.begin(); getRect->left = it->x; getRect->right = it->x; getRect->top = it->y; getRect->bottom = it->y; for (auto it = pts.begin(); it != pts.end(); ++it) { if (getRect->left > it->x) { getRect->left = it->x; } if (getRect->right < it->x) { getRect->right = it->x; } if (getRect->top < it->y) { getRect->top = it->y; } if (getRect->bottom > it->y) { getRect->bottom = it->y; } } return true; } bool IsSquare(const Rect *rect) { return rect->right - rect->left == rect->top - rect->bottom; } bool CheckPoints(const vector<Point> &pts, const Rect *rect, int n) { int left = 0, top = 0, right = 0, bottom = 0; bool notAny = true; for (auto it = pts.begin(); it != pts.end(); ++it) { notAny = true; if (it->x == rect->left) { notAny = false; ++left; } if (it->x == rect->right) { notAny = false; ++right; } if (it->y == rect->top) { notAny = false; ++top; } if (it->y == rect->bottom) { notAny = false; ++bottom; } if (notAny) { return false; } } if (left < n || right < n || top < n || bottom < n) { return false; } return true; } int main(int argc, char *argv[]) { int n = 0; cin >> n; int amount = 4 * n + 1; vector<Point> points; for (int i = 0; i < amount; ++i) { Point pt; cin >> pt.x >> pt.y; points.push_back(pt); } bool found = false; for (int i = 0; i < amount; ++i) { vector<Point> sqPoints; for (int j = 0; j < amount; ++j) { if (j != i) { sqPoints.push_back(points[j]); } } Rect rect; if (!FindBoundary(sqPoints, &rect)) { continue; } if (!IsSquare(&rect)) { continue; } if (!CheckPoints(sqPoints, &rect, n)) { continue; } printf( %d %d , points[i].x, points[i].y); break; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, m, m1, arr[9] = {0}, num = 0, num1 = 0; cin >> n >> m, m1 = m; if (n == 1 && m == 0) cout << 0 0 ; else if (9 * n < m || m == 0) cout << -1 -1 ; else { num1 = 1; while (m - (num1) > (n - 1) * 9) num1++; cout << num1; num += num1; num1 = 0; for (int i = 1; i < n; i++) { while (m - (num1 + num) > (n - (i + 1)) * 9) num1++; cout << num1; num += num1; num1 = 0; } num = 0; cout << ; for (int i = 8; i >= 0; i--) { arr[i] = m1 / (i + 1); m1 %= (i + 1); num += arr[i]; } for (int i = 8; i >= 0; i--) while (arr[i]--) cout << i + 1; while (num < n) cout << 0 , num++; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long int fact[2 * 100005]; long long int func() { fact[0] = fact[1] = 1; for (long long int i = 2; i < 200001; i++) { fact[i] = (fact[i - 1] * i) % 1000000007; } return 0; } set<pair<int, int> > m; set<int> k; set<pair<int, int> > h; int arr[100005], pp[100005]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; if (x == 1) { k.insert(i + 1); } else { h.insert(make_pair(x, i + 1)); } arr[i + 1] = x; pp[i + 1] = x; } set<int>::iterator it; set<pair<int, int> >::iterator ii, iii; set<pair<int, int> > ans; int cnt = 0; int mm = 0; ii = h.begin(); iii = h.begin(); if (h.size() == 0) { if (k.size() > 2) { cout << NO ; return 0; } cout << YES 1 n1 n1 2 ; return 0; } for (ii = h.begin(); iii != h.end();) { pair<int, int> p1 = *ii; iii = ++ii; if (iii == h.end()) break; pair<int, int> p2 = *iii; ans.insert(make_pair(p1.second, p2.second)); arr[p1.second]--; arr[p2.second]--; mm++; } if (k.size() && h.size()) { pair<int, int> p = *(h.begin()); int x = *(k.begin()); ans.insert(make_pair(x, p.second)); arr[x]--; arr[p.second]--; k.erase(x); mm++; } if (k.size() && h.size()) { pair<int, int> p = *(--h.end()); int x = *(k.begin()); ans.insert(make_pair(x, p.second)); arr[x]--; arr[p.second]--; k.erase(x); mm++; } for (int i = 1; i <= n; i++) { if (arr[i] && k.find(i) == k.end()) m.insert(make_pair(arr[i], i)); } int gg = 0; for (it = k.begin(); it != k.end(); it++) { if (arr[*it] == 0) continue; m.erase(make_pair(arr[*it], *it)); if (m.size() == 0) break; pair<int, int> p = *(m.rbegin()); ans.insert(make_pair(*it, p.second)); m.erase(make_pair(arr[p.second], p.second)); arr[p.second]--; if (arr[p.second]) m.insert(make_pair(arr[p.second], p.second)); } int sum = 0; for (int i = 0; i < n; i++) { sum += pp[i + 1]; } if (sum < 2 * n - 2) { cout << NO ; return 0; } cout << YES << mm << endl; cout << ans.size() << endl; for (set<pair<int, int> >::iterator i = ans.begin(); i != ans.end(); i++) { cout << (*i).first << << (*i).second << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n; int s[100005], num[100005]; bool cmp(int a, int b) { return a < b; } int main() { while (scanf( %d , &n) != EOF) { int i; for (i = 0; i < n; i++) scanf( %d , &s[i]); sort(s, s + n, cmp); bool flag = true; for (i = 1; i < n - 1; i++) { if (s[i] == s[i - 1]) continue; if (s[i] != s[i - 1] + 1) flag = false; if (s[i] == s[i - 1] + 1 && s[i] == s[i + 1] - 1) flag = false; } if (s[n - 1] != s[n - 2] && s[n - 1] != s[n - 2] + 1) flag = false; if (!flag) { printf( NO n ); continue; } int ma = 0; memset(num, 0, sizeof(num)); for (i = 0; i < n; i++) { num[s[i] - s[0] + 1]++; ma = max(s[i] - s[0] + 1, ma); } num[1]--; num[ma]--; for (i = 2; i < ma; i++) num[i] -= 2; for (i = 1; flag && i < ma; i++) { if (num[i] > 0 && num[i + 1] < num[i]) flag = false; num[i + 1] -= num[i]; num[i] = 0; } if (num[ma] > 0) flag = false; if (!flag) printf( NO n ); else printf( YES n ); } return 0; }
|
// file: SysMon_tb.v
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// System Monitor wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// System Monitor wizard. Input clock is generated in this testbench.
//----------------------------------------------------------------------------
// This testbench does not implement checking of averaging and calibration
// Bipolar signals are applied with Vn = 0
`timescale 1ps/1ps
`define wait_eoc @(negedge EOC_TB)
`define wait_eos @(posedge EOS_TB)
`define wait_drdy @(negedge DRDY_TB)
`define wait_done @(posedge BUSY_TB)
`define wait_busy @(negedge BUSY_TB)
module SysMon_tb ();
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam time PER1 = 20*ONE_NS;
// Declare the input clock signals
reg DCLK_TB = 1;
wire [6:0] DADDR_TB;
wire DEN_TB;
wire DWE_TB;
wire [15:0] DI_TB;
wire [15:0] DO_TB;
wire DRDY_TB;
wire [2:0] ALM_unused;
wire FLOAT_VCCAUX_ALARM;
wire FLOAT_VCCINT_ALARM;
wire FLOAT_USER_TEMP_ALARM;
wire BUSY_TB;
wire [4:0] CHANNEL_TB;
wire EOC_TB;
wire EOS_TB;
wire JTAGBUSY_TB;
wire JTAGLOCKED_TB;
wire JTAGMODIFIED_TB;
// Input clock generation
always begin
DCLK_TB = #(PER1/2) ~DCLK_TB;
end
assign DADDR_TB = {2'b00, CHANNEL_TB};
assign DI_TB = 16'b0000000000000000;
assign DWE_TB = 1'b0;
assign DEN_TB = EOC_TB;
// Start of the testbench
initial
begin
$display ("Single channel avereraging is enabled");
$display ("This TB does not verify averaging");
$display ("Please increase the simulation duration to see complete waveform") ;
//// Single Channel setup
/////////////////////////////////////////////////////////////
//// Single Channel Mode - Temperature channel selected ////
/////////////////////////////////////////////////////////////
/// Channel selected is Temp. channel
`wait_done;
`wait_eoc;
$display("EOC is asserted");
if (CHANNEL_TB == 0) begin
$display ("Monitored Temperature");
end
else begin
$display ("Temperature is not monitored");
$display ("ERROR !!!");
$finish;
end
`wait_drdy;
$display ("DRDY is asserted. Valid data is on the DO bus");
$display ("Averaging Complete") ;
$finish;
`wait_eoc;
$display ("EOC is asserted.");
if( CHANNEL_TB == 0) begin
$display ("Monitored Temperature.");
end
else begin
$display ("USER TEMP is not monitored.");
$display ("ERROR !!!");
$finish;
end
`wait_drdy;
$display ("DRDY is asserted. Valid data is on the DO bus");
$display ("Averaging Complete") ;
$finish;
end
// Instantiation of the example design
//---------------------------------------------------------
SysMon_exdes dut (
.DADDR_IN(DADDR_TB[6:0]),
.DCLK_IN(DCLK_TB),
.DEN_IN(DEN_TB),
.DI_IN(DI_TB[15:0]),
.DWE_IN(DWE_TB),
.BUSY_OUT(BUSY_TB),
.CHANNEL_OUT(CHANNEL_TB[4:0]),
.DO_OUT(DO_TB[15:0]),
.DRDY_OUT(DRDY_TB),
.EOC_OUT(EOC_TB),
.EOS_OUT(EOS_TB),
.JTAGBUSY_OUT(JTAGBUSY_TB),
.JTAGLOCKED_OUT(JTAGLOCKED_TB),
.JTAGMODIFIED_OUT(JTAGMODIFIED_TB),
.VP_IN(1'b0),
.VN_IN(1'b0)
);
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_pio_aliveTest_cpu_s0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 1: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] data_out;
wire [ 1: 0] out_port;
wire [ 1: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[1 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// part of NeoGS project
//
// (c) NedoPC 2007-2009
//
// ZX dma controller
//
// includes dma address regs, dma control reg
//
// CURRENTLY ONLY READ ON ZXBUS SIDE FROM NGS MEM, error in WAIT generation! zx_dma2.v - further development
module dma_zx(
input clk,
input rst_n,
// ZXBUS-related signals
input zxdmaread, // async strobes made directly from zxbus signals
input zxdmawrite, //
input [7:0] dma_wr_data, // data written by ZXBUS here
output reg [7:0] dma_rd_data, // to be output to the ZXBUS from here
output reg wait_ena, // for zxbus module, to stop temporarily ZX Z80
// different global & control signals
output reg dma_on,
// signals from ports.v
input [7:0] din, // input and output from ports.v
output reg [7:0] dout,
input module_select, // =1 - module selected for read-write operations from ports.v
input write_strobe, // one-cycle positive write strobe - writes to the selected registers from din
input [1:0] regsel, // 2'b00 - high address, 2'b01 - middle address, 2'b10 - low address, 2'b11 - control register
// signals for DMA controller
output reg [20:0] dma_addr,
output reg [7:0] dma_wd,
input [7:0] dma_rd,
output reg dma_rnw,
output reg dma_req,
input dma_ack,
input dma_end
);
reg [7:0] dma_rd_temp; // temporarily buffered read data from DMA module
reg [2:0] zxdmaread_sync; // syncing appropriate zxbus signals
reg [2:0] zxdmawrite_sync;
reg zxread_begin, zxwrite_begin; // 1-cycle positive pulses based on synced in zxdmaread and zxdmawrite
reg zxread_end, zxwrite_end; //
reg dma_prereq; // to help assert dma_req one cycle earlier
reg [1:0] waena_state,waena_next; // and wait_ena generation
reg [1:0] dmarq_state,dmarq_next; // DMA req gen
localparam _HAD = 2'b00; // high address
localparam _MAD = 2'b01; // mid address
localparam _LAD = 2'b10; // low address
localparam _CST = 2'b11; // control and status
// control dout bus
always @*
case( regsel[1:0] )
_HAD: dout = { 3'b000, dma_addr[20:16] };
_MAD: dout = dma_addr[15:8];
_LAD: dout = dma_addr[7:0];
_CST: dout = { dma_on, 7'bXXXXXXX };
endcase
// ports.v write access & dma_addr control
always @(posedge clk, negedge rst_n)
if( !rst_n ) // async reset
begin
dma_on <= 1'b0;
end
else // posedge clk
begin
// dma_on control
if( module_select && write_strobe && (regsel==_CST) )
dma_on <= din[7];
// dma_addr control
if( dma_ack && dma_on )
dma_addr <= dma_addr + 21'd1; // increment on beginning of DMA transfer
else if( module_select && write_strobe )
begin
if( regsel==_HAD )
dma_addr[20:16] <= din[4:0];
else if( regsel==_MAD )
dma_addr[15:8] <= din[7:0];
else if( regsel==_LAD )
dma_addr[7:0] <= din[7:0];
end
end
// syncing in zxdmaread and zxdmawrite, making _begin and _end pulses
always @(posedge clk)
begin
zxdmaread_sync[2:0] <= { zxdmaread_sync[1:0], zxdmaread };
zxdmawrite_sync[2:0] <= { zxdmawrite_sync[1:0], zxdmawrite };
end
always @*
begin
zxread_begin <= zxdmaread_sync[1] && (!zxdmaread_sync[2]);
zxwrite_begin <= zxdmawrite_sync[1] && (!zxdmawrite_sync[2]);
zxread_end <= (!zxdmaread_sync[1]) && zxdmaread_sync[2];
zxwrite_end <= (!zxdmawrite_sync[1]) && zxdmawrite_sync[2];
end
// temporary: dma_rnw always at read state
always @* dma_rnw = 1'b1;
// FSM for wait_enable
localparam waenaIDLE = 0;
localparam waenaWAIT = 1;
always @(posedge clk, negedge rst_n)
if( !rst_n )
waena_state <= waenaIDLE;
else if( !dma_on )
waena_state <= waenaIDLE;
else
waena_state <= waena_next;
always @*
case( waena_state )
waenaIDLE:
if( zxread_end && (!dma_end) )
waena_next <= waenaWAIT;
else
waena_next <= waenaIDLE;
waenaWAIT:
if( dma_end )
waena_next <= waenaIDLE;
else
waena_next <= waenaWAIT;
endcase
always @(posedge clk, negedge rst_n)
if( !rst_n )
wait_ena <= 1'b0;
else if( !dma_on )
wait_ena <= 1'b0;
else
case( waena_next )
waenaIDLE:
wait_ena <= 1'b0;
waenaWAIT:
wait_ena <= 1'b1;
endcase
// FSM for dma request
localparam dmarqIDLE = 0;
localparam dmarqREQ1 = 1;
localparam dmarqREQ2 = 2;
always @(posedge clk, negedge rst_n)
if( !rst_n )
dmarq_state <= dmarqIDLE;
else if( !dma_on )
dmarq_state <= dmarqIDLE;
else
dmarq_state <= dmarq_next;
always @*
case( dmarq_state )
dmarqIDLE:
if( zxread_begin )
dmarq_next <= dmarqREQ1;
else
dmarq_next <= dmarqIDLE;
dmarqREQ1:
if( dma_ack && (!zxread_begin) )
dmarq_next <= dmarqIDLE;
else if( (!dma_ack) && zxread_begin )
dmarq_next <= dmarqREQ2;
else // nothing or both zxread_begin and dma_ack
dmarq_next <= dmarqREQ1;
dmarqREQ2:
if( dma_ack )
dmarq_next <= dmarqREQ1;
else
dmarq_next <= dmarqREQ2;
endcase
always @(posedge clk, negedge rst_n)
if( !rst_n )
dma_prereq <= 1'b0;
else
case( dmarq_next )
dmarqIDLE:
dma_prereq <= 1'b0;
dmarqREQ1:
dma_prereq <= 1'b1;
dmarqREQ2:
dma_prereq <= 1'b1;
endcase
always @* dma_req <= (dma_prereq | zxread_begin) & dma_on;
// pick up data from DMA
always @(posedge clk) if( dma_end ) dma_rd_temp <= dma_rd;
always @(posedge clk)
begin
if( zxread_end && dma_end ) // simultaneously coming zxread_end and dma_end: get data directly from dma
dma_rd_data <= dma_rd;
else if( dma_end && wait_ena ) // dma_end was after zxread_end: get data directly from dma
dma_rd_data <= dma_rd;
else if( zxread_end )
dma_rd_data <= dma_rd_temp; // we can always corrupt dma_rd_data at zxread_end strobe, even if we
// will overwrite it with newer arrived data later
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
package testpackage;
localparam PARAM = 1024 >> 3;
endpackage
import testpackage::*;
module t;
localparam P4 = f_add(P3,1);
localparam P8 = f_add2(P3,P3,f_add(1,1));
localparam P5 = f_while(7);
localparam P16 = f_for(P4);
localparam P18 = f_case(P4);
localparam P6 = f_return(P4);
localparam P3 = 3;
localparam P128 = f_package();
typedef struct packed {
logic [7:0] data;
} type_t;
typedef type_t [1:0] flist;
localparam flist PLIST = {8'd4,8'd8};
localparam flist PARR = f_list_swap_2(PLIST);
typedef struct packed {
logic first;
logic second;
logic [31:0] data;
} bigstruct_t;
localparam bigstruct_t bigparam = f_return_struct(1'b1, 1'b0, 32'hfff12fff);
initial begin
`ifdef TEST_VERBOSE
$display("P5=%0d P8=%0d P16=%0d P18=%0d",P5,P8,P16,P18);
`endif
if (P3 !== 3) $stop;
if (P4 !== 4) $stop;
if (P5 !== 5) $stop;
if (P6 !== 6) $stop;
if (P8 !== 8) $stop;
if (P16 !== 16) $stop;
if (P18 !== 18) $stop;
if (PARR[0] != PLIST[1]) $stop;
if (PARR[1] != PLIST[0]) $stop;
if (bigparam.first != 1'b1) $stop;
if (bigparam.second != 1'b0) $stop;
if (bigparam.data != 32'hfff12fff) $stop;
if (P128 != 128) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
function integer f_package();
return PARAM;
endfunction
function integer f_add(input [31:0] a, input [31:0] b);
f_add = a+b;
endfunction
// Speced ok: function called from function
function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
f_add2 = f_add(a,b)+c;
endfunction
// Speced ok: local variables
function integer f_for(input [31:0] a);
integer i;
integer times;
begin
times = 1;
for (i=0; i<a; i=i+1) times = times*2;
f_for = times;
end
endfunction
function integer f_while(input [31:0] a);
integer i;
begin
i=0;
begin : named
f_while = 1;
end : named
while (i<=a) begin
if (i[0]) f_while = f_while + 1;
i = i + 1;
end
end
endfunction
// Speced ok: local variables
function integer f_case(input [31:0] a);
case(a)
32'd1: f_case = 1;
32'd0, 32'd4: f_case = 18;
32'd1234: begin $display("never get here"); $stop; end
default: f_case = 99;
endcase
endfunction
function integer f_return(input [31:0] a);
integer out = 2;
while (1) begin
out = out+1;
if (a>1) break;
end
while (1) begin
out = out+1;
if (a>1) return 2+out;
end
f_return = 0;
endfunction
function flist f_list_swap_2(input flist in_list);
f_list_swap_2[0].data = in_list[1].data;
f_list_swap_2[1].data = in_list[0].data;
endfunction
function bigstruct_t f_return_struct(input first, input second, input [31:0] data);
bigstruct_t result;
result.data = data;
result.first = first;
result.second = second;
return result;
endfunction
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_9_0 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(15)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The Regfile module to implement the core's general purpose registers file
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_regfile(
input [`E203_RFIDX_WIDTH-1:0] read_src1_idx,
input [`E203_RFIDX_WIDTH-1:0] read_src2_idx,
output [`E203_XLEN-1:0] read_src1_dat,
output [`E203_XLEN-1:0] read_src2_dat,
input wbck_dest_wen,
input [`E203_RFIDX_WIDTH-1:0] wbck_dest_idx,
input [`E203_XLEN-1:0] wbck_dest_dat,
output [`E203_XLEN-1:0] x1_r,
input test_mode,
input clk,
input rst_n
);
wire [`E203_XLEN-1:0] rf_r [`E203_RFREG_NUM-1:0];
wire [`E203_RFREG_NUM-1:0] rf_wen;
`ifdef E203_REGFILE_LATCH_BASED //{
// Use DFF to buffer the write-port
wire [`E203_XLEN-1:0] wbck_dest_dat_r;
sirv_gnrl_dffl #(`E203_XLEN) wbck_dat_dffl (wbck_dest_wen, wbck_dest_dat, wbck_dest_dat_r, clk);
wire [`E203_RFREG_NUM-1:0] clk_rf_ltch;
`endif//}
genvar i;
generate //{
for (i=0; i<`E203_RFREG_NUM; i=i+1) begin:regfile//{
if(i==0) begin: rf0
// x0 cannot be wrote since it is constant-zeros
assign rf_wen[i] = 1'b0;
assign rf_r[i] = `E203_XLEN'b0;
`ifdef E203_REGFILE_LATCH_BASED //{
assign clk_rf_ltch[i] = 1'b0;
`endif//}
end
else begin: rfno0
assign rf_wen[i] = wbck_dest_wen & (wbck_dest_idx == i) ;
`ifdef E203_REGFILE_LATCH_BASED //{
e203_clkgate u_e203_clkgate(
.clk_in (clk ),
.test_mode(test_mode),
.clock_en(rf_wen[i]),
.clk_out (clk_rf_ltch[i])
);
//from write-enable to clk_rf_ltch to rf_ltch
sirv_gnrl_ltch #(`E203_XLEN) rf_ltch (clk_rf_ltch[i], wbck_dest_dat_r, rf_r[i]);
`else//}{
sirv_gnrl_dffl #(`E203_XLEN) rf_dffl (rf_wen[i], wbck_dest_dat, rf_r[i], clk);
`endif//}
end
end//}
endgenerate//}
assign read_src1_dat = rf_r[read_src1_idx];
assign read_src2_dat = rf_r[read_src2_idx];
// wire [`E203_XLEN-1:0] x0 = rf_r[0];
// wire [`E203_XLEN-1:0] x1 = rf_r[1];
// wire [`E203_XLEN-1:0] x2 = rf_r[2];
// wire [`E203_XLEN-1:0] x3 = rf_r[3];
// wire [`E203_XLEN-1:0] x4 = rf_r[4];
// wire [`E203_XLEN-1:0] x5 = rf_r[5];
// wire [`E203_XLEN-1:0] x6 = rf_r[6];
// wire [`E203_XLEN-1:0] x7 = rf_r[7];
// wire [`E203_XLEN-1:0] x8 = rf_r[8];
// wire [`E203_XLEN-1:0] x9 = rf_r[9];
// wire [`E203_XLEN-1:0] x10 = rf_r[10];
// wire [`E203_XLEN-1:0] x11 = rf_r[11];
// wire [`E203_XLEN-1:0] x12 = rf_r[12];
// wire [`E203_XLEN-1:0] x13 = rf_r[13];
// wire [`E203_XLEN-1:0] x14 = rf_r[14];
// wire [`E203_XLEN-1:0] x15 = rf_r[15];
// `ifdef E203_RFREG_NUM_IS_32 //{
// wire [`E203_XLEN-1:0] x16 = rf_r[16];
// wire [`E203_XLEN-1:0] x17 = rf_r[17];
// wire [`E203_XLEN-1:0] x18 = rf_r[18];
// wire [`E203_XLEN-1:0] x19 = rf_r[19];
// wire [`E203_XLEN-1:0] x20 = rf_r[20];
// wire [`E203_XLEN-1:0] x21 = rf_r[21];
// wire [`E203_XLEN-1:0] x22 = rf_r[22];
// wire [`E203_XLEN-1:0] x23 = rf_r[23];
// wire [`E203_XLEN-1:0] x24 = rf_r[24];
// wire [`E203_XLEN-1:0] x25 = rf_r[25];
// wire [`E203_XLEN-1:0] x26 = rf_r[26];
// wire [`E203_XLEN-1:0] x27 = rf_r[27];
// wire [`E203_XLEN-1:0] x28 = rf_r[28];
// wire [`E203_XLEN-1:0] x29 = rf_r[29];
// wire [`E203_XLEN-1:0] x30 = rf_r[30];
// wire [`E203_XLEN-1:0] x31 = rf_r[31];
// `endif//}
assign x1_r = rf_r[1];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } int n, arr[109]; vector<int> odd, even; int main() { scanf( %d , &n); for (int i = 0; i < (int)(n); i++) { scanf( %d , &arr[i]); if (arr[i] % 2 == 0) even.push_back(i); else odd.push_back(i); } if (even.size() == n - 1) printf( %d n , odd[0] + 1); else printf( %d n , even[0] + 1); }
|
/*
* Copyright (c) 2014, Franck Jullien <>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`timescale 1ns / 1ps
module wb_ddr_ctrl_tb;
localparam MEMORY_SIZE_WORDS = ;
localparam WB_PORTS = 3;
localparam BA_WIDTH = 2;
initial begin
if($test$plusargs("vcd")) begin
$dumpfile("ddr_ctrl.vcd");
$dumpvars(0);
end
end
wire init_done;
wire wbm_rst;
reg wb_clk = 1'b1;
reg wb_rst = 1'b1;
assign wbm_rst = ~init_done;
always @(posedge init_done)
begin
if (init_done)
$display("DDR initialization done\n");
end
initial #200 wb_rst <= 1'b0;
always #10 wb_clk <= !wb_clk;
wire [1:0] ba;
wire [12:0] a;
wire cs_n;
wire ras;
wire cas;
wire we;
wire [1:0] dqm;
wire cke;
tri [15:0] dq;
wire [1:0] dqs;
wire ddr_clk;
wire ddr_clk_n;
wire [WB_PORTS*32-1:0] wb_adr;
wire [WB_PORTS-1:0] wb_stb;
wire [WB_PORTS-1:0] wb_cyc;
wire [WB_PORTS*3-1:0] wb_cti;
wire [WB_PORTS*2-1:0] wb_bte;
wire [WB_PORTS-1:0] wb_we;
wire [WB_PORTS*4-1:0] wb_sel;
wire [WB_PORTS*32-1:0] wb_m2s_dat;
wire [WB_PORTS*32-1:0] wb_s2m_dat;
wire [WB_PORTS-1:0] wb_ack;
wire [31:0] slave_writes;
wire [31:0] slave_reads;
wire [WB_PORTS-1:0] done_int;
genvar i;
generate
for(i = 0; i < WB_PORTS; i = i + 1) begin : masters
wb_bfm_transactor
#(.MEM_HIGH (MEMORY_SIZE_WORDS*(i+1)-1),
.MEM_LOW (MEMORY_SIZE_WORDS*i),
.VERBOSE (1))
wb_bfm_transactor0 (
.wb_clk_i (wb_clk),
.wb_rst_i (wbm_rst),
.wb_adr_o (wb_adr[i*32+:32]),
.wb_dat_o (wb_m2s_dat[i*32+:32]),
.wb_sel_o (wb_sel[i*4+:4]),
.wb_we_o (wb_we[i] ),
.wb_cyc_o (wb_cyc[i]),
.wb_stb_o (wb_stb[i]),
.wb_cti_o (wb_cti[i*3+:3]),
.wb_bte_o (wb_bte[i*2+:2]),
.wb_dat_i (wb_s2m_dat[i*32+:32]),
.wb_ack_i (wb_ack[i]),
.wb_err_i (1'b0),
.wb_rty_i (1'b0),
//Test Control
.done(done_int[i]));
end // block: slaves
endgenerate
integer idx;
time start_time[WB_PORTS-1:0];
time ack_delay[WB_PORTS-1:0];
integer num_transactions[WB_PORTS-1:0];
assign done = &done_int;
always @(done) begin
if(done === 1) begin
$display("Average wait times");
for(idx=0;idx<WB_PORTS;idx=idx+1)
$display("Master %0d : %f",idx, ack_delay[idx]/num_transactions[idx]);
$display("All tests passed!");
$finish;
end
end
generate
for(i=0;i<WB_PORTS;i=i+1) begin : wait_time
initial begin
wait (init_done);
ack_delay[i] = 0;
num_transactions[i] = 0;
while(1) begin
@(posedge wb_cyc[i]);
start_time[i] = $time;
@(posedge wb_ack[i]);
ack_delay[i] = ack_delay[i] + $time-start_time[i];
num_transactions[i] = num_transactions[i]+1;
end
end
end
endgenerate
wire [22:0] local_address;
wire local_write_req;
wire local_read_req;
wire local_burstbegin;
wire [31:0] local_wdata;
wire [3:0] local_be;
wire [6:0] local_size;
wire [31:0] local_rdata;
wire local_rdata_valid;
wire local_reset_n;
wire local_clk;
wire local_ready;
wb_ddr_ctrl
#(
.ADDR_WIDTH (25), // Memory size = 2^ADDR_WIDTH = 32MB
.WB_PORTS (3), // Number of wishbone ports
.BUF_WIDTH ({3'd3, 3'd3, 3'd5}) // Buffer size = 2^BUF_WIDTH
)
wb_ddr_ctrl0
(
// Wishbone interface
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_adr_i (wb_adr),
.wb_stb_i (wb_stb),
.wb_cyc_i (wb_cyc),
.wb_cti_i (wb_cti),
.wb_bte_i (wb_bte),
.wb_we_i (wb_we),
.wb_sel_i (wb_sel),
.wb_dat_i (wb_m2s_dat),
.wb_dat_o (wb_s2m_dat),
.wb_ack_o (wb_ack),
// DDR controller local interface
.local_address_o (local_address),
.local_write_req_o (local_write_req),
.local_read_req_o (local_read_req),
.local_burstbegin_o (local_burstbegin),
.local_wdata_o (local_wdata),
.local_be_o (local_be),
.local_size_o (local_size),
.local_rdata_i (local_rdata),
.local_rdata_valid_i (local_rdata_valid),
.local_reset_n_i (local_reset_n),
.local_clk_i (local_clk),
.local_ready_i (local_ready)
);
ddr_ctrl_ip ddr_ctrl_ip
(
.local_address (local_address),
.local_write_req (local_write_req),
.local_read_req (local_read_req),
.local_burstbegin (local_burstbegin),
.local_wdata (local_wdata),
.local_be (local_be),
.local_size (local_size),
.global_reset_n (~wb_rst),
.pll_ref_clk (wb_clk),
.soft_reset_n (1'b1),
.local_ready (local_ready),
.local_rdata (local_rdata),
.local_rdata_valid (local_rdata_valid),
.local_refresh_ack (),
.local_init_done (init_done),
.reset_phy_clk_n (local_reset_n),
.mem_cs_n (cs_n),
.mem_cke (cke),
.mem_addr (a),
.mem_ba (ba),
.mem_ras_n (ras),
.mem_cas_n (cas),
.mem_we_n (we),
.mem_dm (dqm),
.phy_clk (local_clk),
.aux_full_rate_clk (),
.aux_half_rate_clk (),
.reset_request_n (),
.mem_clk (ddr_clk),
.mem_clk_n (ddr_clk_n),
.mem_dq (dq),
.mem_dqs (dqs)
);
ddr
#(
.DEBUG (0)
)
ddr0
(
.Clk (ddr_clk),
.Clk_n (ddr_clk_n),
.Cke (cke),
.Cs_n (cs_n),
.Ras_n (ras),
.Cas_n (cas),
.We_n (we),
.Ba (ba),
.Addr (a),
.Dm (dqm),
.Dq (dq),
.Dqs (dqs)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const bool debug = 0; int main() { if (!debug) { cin.tie(0); cout.tie(0); ios::sync_with_stdio(0); } int q; cin >> q; while (q--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; reverse(a.begin(), a.end()); for (int i = 0; i * 2 < n; i++) a[i] *= -1; for (int i = 0; i < n; i++) cout << a[i] << ; cout << n ; } return 0; }
|
module scbd_feeder(
valid_wf,
ins_half_reqd,
ins_half_wfid,
issue_vacant,
q_empty,
q_reset,
feed_valid,
feed_wfid,
clk,
rst
);
input [39:0] valid_wf;
input ins_half_reqd;
input [5:0] ins_half_wfid;
input [39:0] issue_vacant;
input [39:0] q_empty;
input [39:0] q_reset;
output feed_valid;
output [5:0] feed_wfid;
input clk;
input rst;
wire [39:0] ins_half_reqd_bitwise;
wire [39:0] selected_instr_bitwise;
wire [39:0] hungry;
wire [39:0] next_hungry;
wire [39:0] sb_candidates;
decoder_6_to_40 ins_half_dec(.out(ins_half_reqd_bitwise), .in(ins_half_wfid));
assign next_hungry = (issue_vacant | (ins_half_reqd_bitwise & {40{ins_half_reqd}}) | q_reset | hungry) & (~ ({40{feed_valid}} & selected_instr_bitwise));
reg_40b_set scbd_hungry(.out(hungry), .in(next_hungry), .wr_en(1'b1), .clk(clk), .set(rst));
assign sb_candidates = hungry & (~ q_empty) & valid_wf;
priority_encoder_40to6 select_enc(.binary_out(feed_wfid), .valid(feed_valid), .encoder_in(sb_candidates), .enable(1'b1));
decoder_6_to_40 update_dec(.out(selected_instr_bitwise), .in(feed_wfid));
endmodule
|
#include<bits/stdc++.h> using namespace std; #define f first #define s second using ll = long long; const int mxN = 200000; const int lgN = 18; const int mod = 1e9 + 7; const ll inf = 1e15; void solve() { int n; cin >> n; int a[n + 1]; int check = true; for (int i = 1; i <= n; i++) { cin >> a[i]; if (i > 1 && a[i] < a[i - 1]) check = false; } if (check) cout << 0 ; else if (a[1] == 1 || a[n] == n) cout << 1 ; else if (a[1] != n || a[n] != 1) cout << 2 ; else cout << 3 ; } int main() { /*if (fopen( input.txt , r )) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); }*/ ios_base::sync_with_stdio(0); cin.tie(0); int n_test = 1; cin >> n_test; for (int test = 1; test <= n_test; test++) { //cout << Case # << test << : ; solve(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> int min(int a, int b) { return a < b ? a : b; } int n, m, t1, t2, val[1024]; long long ans; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &val[i]); } for (int i = 1; i <= m; i++) { scanf( %d%d , &t1, &t2); ans += min(val[t1], val[t2]); } printf( %lld , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double eps = 1e-8; const int mod = 1e9 + 7; const int inf = 1061109567; const int dir[][2] = {{-1, 0}, {1, 0}, {0, -1}, {0, 1}}; double dp[205][205][405], p[205]; int a[205]; int main() { int n, l, tmp; cin >> n >> l >> tmp; for (int i = 1; i <= n; i++) { cin >> p[i]; p[i] /= 100; } for (int i = 1; i <= n; i++) { cin >> a[i]; } dp[0][0][200 + tmp] = 1; for (int i = 0; i < n; i++) { for (int j = 0; j <= i; j++) { for (int k = 0; k <= 400; k++) { if (a[i + 1] == -1) { if (k > 0) dp[i + 1][j + 1][k - 1] += dp[i][j][k] * p[i + 1]; dp[i + 1][j][k] += dp[i][j][k] * (1 - p[i + 1]); } else { int val = min(400, k + a[i + 1]); if (k > 0) dp[i + 1][j + 1][val] += dp[i][j][k] * p[i + 1]; dp[i + 1][j][k] += dp[i][j][k] * (1 - p[i + 1]); } } } } double ans = 0; for (int i = l; i <= n; i++) { for (int j = 200; j <= 400; j++) { ans += dp[n][i][j]; } } printf( %.8f n , ans); return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_tx.v
// Version : 2.4
//----------------------------------------------------------------------------//
// File: axi_basic_tx.v //
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_TB_V
`define SKY130_FD_SC_LP__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_TB_V
|
#include <bits/stdc++.h> using namespace std; vector<int> nxt[1 << 13], G[15]; vector<pair<int, int> > lca[13]; bool a[14][14], ok[14][1 << 13]; long long int dp[14][1 << 13][2]; int n; long long int solve(int root, int mask, int check) { if (check == 0) { int i; for (i = 0; i < lca[root].size(); i++) { int x = lca[root][i].first, y = lca[root][i].second; if ((mask & (1 << x)) == 0 && x != root) return 0; if ((mask & (1 << y)) == 0 && y != root) return 0; } } long long int &ret = dp[root][mask][check]; if (ret != -1) return ret; if (mask == 0) return ret = 1; ret = 0; int i, j, k; for (i = 0; i < nxt[mask].size(); i++) { int newmask = nxt[mask][i]; if (!ok[root][newmask]) continue; int msb = -1, ch = -1; for (k = 0; k < n; k++) { if (mask & (1 << k)) msb = k; if ((newmask & (1 << k)) && a[root][k]) { if (ch == -1) ch = k; else ch = -2; } } if (ch == -2 || (newmask & (1 << msb)) == 0) continue; if (ch == -1) { for (k = 0; k < n; k++) { if (newmask & (1 << k)) ret += solve(k, newmask ^ (1 << k), 0) * solve(root, mask ^ newmask, 1); } } else ret += solve(ch, newmask ^ (1 << ch), 0) * solve(root, mask ^ newmask, 1); } return ret; } int main() { int i, j, m, k, k1, q; scanf( %d%d , &n, &m); ; scanf( %d , &q); ; while (m--) { int x, y; scanf( %d%d , &x, &y); ; x--; y--; G[x].push_back(y); G[y].push_back(x); a[x][y] = 1; a[y][x] = 1; } while (q--) { int x, y, z; scanf( %d%d , &x, &y); ; scanf( %d , &z); ; x--; y--; z--; lca[z].push_back(make_pair(x, y)); } for (i = 0; i < 1 << n; i++) for (j = 0; j < i + 1; j++) if ((i & j) == j) nxt[i].push_back(j); for (i = 0; i < n; i++) { for (j = 0; j < 1 << n; j++) { bool f = 1; if (j & (1 << i)) continue; for (k = 0; k < n; k++) { if ((j & (1 << k)) == 0) continue; for (k1 = 0; k1 < G[k].size(); k1++) if ((j & (1 << G[k][k1])) == 0 && G[k][k1] != i) f = 0; } for (k = 0; k < lca[i].size(); k++) { int x = lca[i][k].first, y = lca[i][k].second; if ((j & (1 << x)) && (j & (1 << y))) f = 0; } ok[i][j] = f; } } memset(dp, -1, sizeof(dp)); cout << solve(0, ((1 << (n - 1)) - 1) << 1, 0) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; double PI = 3.1415926535897932384626433; double DP[(1 << 20)]; vector<double> fx, fy, lg; double calc(double px, double py, double t, double al) { double d = sqrt((px - t) * (px - t) + py * py); double sina = sin(al * (PI / 180.0)); double sinb = fabs(py) / d; double bt = asin(sinb) * (180.0 / PI); if (px < t) bt = 180 - bt; if (al + bt >= 180) return t + 300000.0; double gm = 180 - bt - al; double sinc = sin(gm * (PI / 180.0)); return t + (sina * (d / sinc)); } int main() { int i, mask, n, l, r, cr; cin >> n >> l >> r; int xx, yy, al; double cl = l; bool hasp = false; for (i = 0; i < n; ++i) { cin >> xx >> yy >> al; if (yy == 0) { if (hasp || xx >= r || xx <= l) { cout << r - l << n ; return 0; } hasp = true; cl = xx; } else { fx.push_back(xx); fy.push_back(yy); lg.push_back(al); } } n = fx.size(); DP[0] = cl; for (mask = 1; mask < (1 << n); ++mask) { DP[mask] = cl; for (i = 0; i < n; ++i) { if (mask & (1 << i)) { cr = mask - (1 << i); DP[mask] = max(DP[mask], calc(fx[i], fy[i], DP[cr], lg[i])); } } } printf( %.8lf n , min((double)r, DP[(1 << n) - 1]) - l); return 0; }
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#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const double eps = 1e-9; const int N = 1 << 19; const int P = (int)1e9 + 7; const int Z = 239; inline int add(int a, int b) { a += b; if (a >= P) a -= P; return a; } int powP[2 * N]; inline int shift(int a, int n) { return (a * (long long)powP[n]) % P; } int hash1[2 * N]; int hash2[2 * N]; int len[2 * N]; inline void upd(int x, int dx) { x += N; hash1[x] = dx; hash2[x] = dx; while (x > 1) { x >>= 1; hash1[x] = add(hash1[2 * x], shift(hash1[2 * x + 1], len[2 * x])); hash2[x] = add(hash2[2 * x + 1], shift(hash2[2 * x], len[2 * x])); } } int vleft[2 * N], vleftc = 0; int vright[2 * N], vrightc = 0; inline int get1(int l, int r) { if (l > r) return 0; l += N; r += N; vleftc = 0; vrightc = 0; while (l <= r) { if ((l & 1) == 1) vleft[vleftc++] = l; if ((r & 1) == 0) vright[vrightc++] = r; l = (l + 1) >> 1; r = (r - 1) >> 1; } int res = 0; int toshift = 0; for (int i = 0; i < vleftc; ++i) { int v = vleft[i]; res = add(res, shift(hash1[v], toshift)); toshift += len[v]; } for (int i = vrightc - 1; i >= 0; --i) { int v = vright[i]; res = add(res, shift(hash1[v], toshift)); toshift += len[v]; } return res; } inline int get2(int l, int r) { if (l > r) return 0; l += N; r += N; vleftc = 0; vrightc = 0; while (l <= r) { if ((l & 1) == 1) vleft[vleftc++] = l; if ((r & 1) == 0) vright[vrightc++] = r; l = (l + 1) >> 1; r = (r - 1) >> 1; } int res = 0; int toshift = 0; for (int i = 0; i < vrightc; ++i) { int v = vright[i]; res = add(res, shift(hash2[v], toshift)); toshift += len[v]; } for (int i = vleftc - 1; i >= 0; --i) { int v = vleft[i]; res = add(res, shift(hash2[v], toshift)); toshift += len[v]; } return res; } int a[N]; int main() { powP[0] = 1; for (int i = 1; i <= N; ++i) powP[i] = (powP[i - 1] * (long long)Z) % P; for (int i = 2 * N - 1; i >= 1; --i) { if (i >= N) len[i] = 1; else len[i] = 2 * len[2 * i]; } int n; scanf( %d , &n); for (int i = 0; (i) < (n); ++i) scanf( %d , &a[i]); for (int i = 0; (i) < (n); ++i) a[i] -= 1; bool res = false; for (int i = 0; (i) < (n); ++i) { int val = a[i]; if (val <= n - val - 1) { int left = get1(0, val - 1); int right = get2(val + 1, 2 * val); if (left != right) { res = true; } } else { int left = get1(val - (n - 1 - val), val - 1); int right = get2(val + 1, n - 1); if (left != right) { res = true; } } upd(val, 1); } if (res) printf( YES n ); else printf( NO n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int NMAX = 1e5; int t; int n, m, k; vector<int> graph[NMAX + 5]; int gr[NMAX + 5]; bool active[NMAX + 5]; bool in[NMAX + 5]; bool exists(int i, int j) { vector<int>::iterator it = lower_bound(graph[i].begin(), graph[i].end(), j); if (it != graph[i].end() && *it == j) { return true; } return false; } int main() { scanf( %d , &t); while (t--) { scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) { gr[i] = 0; graph[i].clear(); active[i] = 1; in[i] = 0; } for (int i = 1; i <= m; i++) { int u, v; scanf( %d %d , &u, &v); graph[u].push_back(v); graph[v].push_back(u); gr[u]++; gr[v]++; } if (1LL * k * (k - 1) > 2 * m) { printf( -1 n ); continue; } queue<int> q; for (int i = 1; i <= n; i++) { sort(graph[i].begin(), graph[i].end()); if (gr[i] < k) { q.push(i); in[i] = 1; } } while (!q.empty()) { int nod = q.front(); active[nod] = 0; q.pop(); for (auto it : graph[nod]) { gr[it]--; if (in[it] == 0 && gr[it] < k) { in[it] = 1; q.push(it); } } } vector<int> ans; for (int i = 1; i <= n; i++) { if (active[i] == 1) { ans.push_back(i); } } if (ans.empty() == false) { printf( 1 %d n , (int)ans.size()); for (auto it : ans) { printf( %d , it); } printf( n ); continue; } for (int i = 1; i <= n; i++) { gr[i] = graph[i].size(); active[i] = 1; in[i] = 0; } for (int i = 1; i <= n; i++) { if (gr[i] < k) { in[i] = 1; q.push(i); } } bool found = false; while (!q.empty()) { int nod = q.front(); q.pop(); active[nod] = 0; if (gr[nod] == k - 1) { vector<int> nodes = {nod}; for (auto it : graph[nod]) { if (active[it] == 1) { nodes.push_back(it); } } bool ok = true; for (int i = 0; i < (int)nodes.size() && ok; i++) { for (int j = i + 1; j < (int)nodes.size() && ok; j++) { ok &= exists(nodes[i], nodes[j]); } } if (ok == true) { found = true; printf( 2 n ); for (auto it : nodes) { printf( %d , it); } printf( n ); break; } } for (auto it : graph[nod]) { gr[it]--; if (in[it] == 0 && gr[it] < k) { in[it] = 1; q.push(it); } } } if (found == false) { printf( -1 n ); continue; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100005; vector<int> v[2][N]; int a[N], q[N], n; bool vst[2][N]; void bfs(int val) { int i, j, qh = 0, qe = 0, k = val - 1, s, out; for (i = 1; i <= n; i++) if (a[i] == val) q[qe++] = i, vst[k][i] = 1; while (qh < qe) { out = q[qh++]; if (val != 2 || a[out] != 1) for (i = 0, s = v[k][out].size(); i < s; i++) if (!vst[k][j = v[k][out][i]]) q[qe++] = j, vst[k][j] = 1; } } int main() { int i, j, e; while (2 == scanf( %d%d , &n, &e)) { for (i = 1; i <= n; i++) scanf( %d , a + i), v[0][i].clear(), v[1][i].clear(); while (e--) { scanf( %d%d , &i, &j); v[0][i].push_back(j); v[1][j].push_back(i); } memset(vst, 0, sizeof vst); bfs(1); bfs(2); for (i = 1; i <= n; i++) puts(vst[0][i] && vst[1][i] ? 1 : 0 ); } return 0; }
|
// Icarus 0.6, snapshot 20020907
// ==================================================
// -- confused by disables from within a fork -- vvp fails
//
// -- to run, incant
// iverilog tt.v
// vvp a.out
module top;
integer simple_fail, loop_fail, fork_fail, tlp_fail, tfk_fail;
integer loop_cntr, tlp_cntr;
reg fred, abort;
initial begin
#1;
simple_fail = 0;
loop_fail = 0;
fork_fail = 0;
tlp_fail = 0;
tfk_fail = 0;
fred = 0;
abort = 1;
#4;
fred = 1;
#4
if(simple_fail) $display("\n***** simple block disable FAILED *****");
else $display("\n***** simple block disable PASSED *****");
if(loop_fail) $display("***** block with loop disable FAILED *****");
else $display("***** block with loop disable PASSED *****");
if(fork_fail) $display("***** forked block disable FAILED *****");
else $display("***** forked block disable PASSED *****");
if(tlp_fail) $display("***** task with loop disable FAILED *****");
else $display("***** task with loop disable PASSED *****");
if(tfk_fail) $display("***** task with forked block disable FAILED ****\n");
else $display("***** task with forked block disable PASSED ****\n");
$finish(0);
end
// simple block disable
initial begin: block_name
#2;
disable block_name;
simple_fail = 1;
end
// more complex: block disable inside for-loop
initial begin
#2;
begin: configloop
for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin
wait (fred);
if (abort) begin
disable configloop;
end
loop_fail = 1;
end
end // configloop block
if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr);
end
// still more complex: disable from within a forked block
initial begin
#2;
begin: forked_tasks
fork
begin
#5;
fork_fail = 1;
end
begin
@(fred);
disable forked_tasks;
fork_fail = 1;
end
join
fork_fail = 1;
end //forked_tasks
end
// disables inside tasks
initial begin
task_with_loop;
end
initial begin
task_with_fork;
end
task task_with_loop;
begin
#2;
begin: configtlp
for (tlp_cntr = 0; tlp_cntr < 3; tlp_cntr=tlp_cntr+1) begin
wait (fred);
if (abort) begin
disable configtlp;
end
tlp_fail = 1;
end
end // configloop block
end
endtask // task_with_loop
task task_with_fork;
begin
#2;
begin: forked_tasks_in_task
fork
begin
#5;
tfk_fail = 1;
end
begin
@(fred);
disable forked_tasks_in_task;
tfk_fail = 1;
end
join
tfk_fail = 1;
end //forked_tasks_in_task
end
endtask // task_with_fork
endmodule
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#include <bits/stdc++.h> const int N = 1e5 + 5; int n, k, a[N]; int ans[N], top; int main() { scanf( %d%d , &n, &k); int sum = 0; for (int i = 1; i <= n; i++) scanf( %d , a + i), sum += a[i]; if (sum % k) return !printf( No ); int num = sum / k; top = 0; int now = 0, l = 1; for (int i = 1; i <= n; i++) { now += a[i]; if (now > num) return !printf( No ); if (now == num) { ans[++top] = i - l + 1; l = i + 1; now = 0; } } printf( Yes n ); for (int i = 1; i <= top; i++) printf( %d , ans[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while ( 0 <= ch && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x; } int t; int main() { t = read(); while (t--) { int n = read(), d = read(); int ans = d; d--; int x = sqrt(d); if (x + d / (x + 1) + 1 < ans) ans = x + d / (x + 1) + 1; if (x + 1 + d / (x + 2) + 1 < ans) ans = x + 1 + d / (x + 2) + 1; if (ans <= n) puts( Yes ); else puts( No ); } }
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#include <bits/stdc++.h> using namespace std; int main() { long long int i, j, k, m = 0, n, cnt = 0, x = 0, ans = 0, y, sum = 0, l = 0, r = 0; cin >> n >> m; string a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (a[i][j] == B ) { for (k = j; k < m; k++) { if (a[i][k] == B ) { cnt++; } else { break; } } cnt = cnt / 2; i += cnt; j += cnt; i++; j++; cout << i << << j; return 0; } } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BLACKBOX_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
X,
A
);
output X;
input A;
// Voltage supply signals
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BLACKBOX_V
|
#include <stdio.h> #include<iomanip> #include<iostream> #include<iostream> #include <algorithm> #include<string.h> #include<string> #include<cmath> #include<queue> #include<map> #include<set> #include<bits/stdc++.h> using namespace std; #pragma warning(disable:4996) #define inf 0x3f3f3f3f #define PI 3.1415926535898 const double eps = 1e-7; typedef long long LL; #define ll long long //LL GCD(LL a, LL b) //{ // if (b == 0) // return a; // return GCD(b, a % b); //} //LL fac[N], inv[N]; //LL quick_pow(LL a, LL b) //{ // LL ans = 1 % mod; // while (b) { // if (b & 1) ans = (ans * a) % mod; // b >>= 1; // a = (a * a) % mod; // } // return ans; //} //void init() //{ // fac[0] = 1; // inv[0] = 1; // for (int i = 1; i <= N - 2; i++) // { // fac[i] = (fac[i - 1] * i) % mod; // inv[i] = quick_pow(fac[i], mod - 2); // } //} //LL C(LL a, LL b) //计算组合数C(a, b) //{ // if (a < b || b < 0) return 0; // return fac[a] * ((inv[a - b] * inv[b]) % mod) % mod; //} //LL n; //LL a[N], c[N], d[N]; //void add(LL x, LL v) //{ // LL i = x; // while (x <= (n << 1)) // { // c[x] += v; // d[x] += v * (i - 1); // x += (x & -x); // } //} //LL sum(LL x) //{ // LL res = 0, i = x; // while (x > 0) // { // res += i * c[x] - d[x]; // x -= x & -x; // } // return res; //} //int prime[N]; //int vis[N]; //void get_prime() //{ // for (int i = 2; i < N; i++) // { // if (!vis[i]) // { // prime[++prime[0]] = i; // } // for (int j = 1; j <= prime[0] && i * prime[j] < N; j++) // { // vis[i * prime[j]] = 1; // if (i % prime[j] == 0) // break; // } // } //} //struct no { // LL first; // int id; // no() {} // no(LL first, int id) :first(first), id(id) {} // bool operator<(const no& a)const // { // return first < a.first;//da顶堆 // } //}; LL mod = 1e9 + 7; const LL N = 3e5 + 10; LL n, m, t; LL a[N], b[N], c[N], aa[3]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); /*srand((int)time(0));*/ //freopen( C: Users Lenovo Desktop test in.txt , r , stdin); //freopen( C: Users Lenovo Desktop test out.txt , w , stdout); int n1, n2, n3; cin >> n1 >> n2 >> n3; LL sum1 = 0, sum2 = 0, sum3 = 0; LL m1 = 1e17, m2 = 1e17, m3 = 1e17; for (int i = 0; i < n1; i++) { cin >> a[i]; m1 = min(a[i], m1); sum1 += a[i]; } for (int i = 0; i < n2; i++) { cin >> b[i]; m2 = min(b[i], m2); sum2 += b[i]; } for (int i = 0; i < n3; i++) { cin >> c[i]; m3 = min(c[i], m3); sum3 += c[i]; } LL all = sum1 + sum2 + sum3; LL ans=-1e17; ans = max(ans, sum1 + sum2 - sum3); ans = max(ans, sum1 + sum3 - sum2); ans = max(ans, sum2 + sum3 - sum1); ans = max(ans, all - 2 * (m1 + m2)); ans = max(ans, all - 2 * (m1 + m3)); ans = max(ans, all - 2 * (m3 + m2)); cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1000000000 + 7; const int N = 200000 + 10; const int NUMHASH = 3; const long long hashNum[3] = {M, M + 2, M + 14}; struct re { int x, y; }; int n, q; string s; int cnt[26][N], f[26][N], g[26][N]; long long h[NUMHASH][26][N], p[NUMHASH][N]; int countLetter(int x, int y, int c) { return cnt[c][x] - cnt[c][y + 1]; } int getHash(int x, int l, int c, int k) { return (h[k][c][x + l - 1] - (h[k][c][x - 1] * p[k][l] % hashNum[k]) + hashNum[k]) % hashNum[k]; } bool equalHash(int x, int i, int y, int j, int l) { for (int k = (0); (k <= (NUMHASH - 1)); ++k) { if (getHash(x, l, i, k) != getHash(y, l, j, k)) return false; } return true; } bool iso(int x, int y, int l) { for (int i = (0); (i <= (25)); ++i) { int pos = f[i][x]; if (pos < l) { int j = s[y - 1 + pos] - a ; if (f[j][y] != pos) return false; if (countLetter(x, x + l - 1, i) != countLetter(y, y + l - 1, j)) return false; if (!equalHash(x, i, y, j, l)) return false; } } return true; } int main() { cin >> n >> q; cin >> s; for (int i = (n); (i >= (1)); --i) { for (int j = (0); (j <= (25)); ++j) cnt[j][i] = cnt[j][i + 1], f[j][i] = f[j][i + 1] + 1; int j = s[i - 1] - a ; cnt[j][i] = cnt[j][i + 1] + 1; f[j][i] = 0; g[j][i] = 1; } for (int k = (0); (k <= (NUMHASH - 1)); ++k) { p[k][0] = 1; for (int i = (1); (i <= (n)); ++i) p[k][i] = (p[k][i - 1] * 2) % hashNum[k]; for (int j = (0); (j <= (25)); ++j) { for (int i = (1); (i <= (n)); ++i) h[k][j][i] = (h[k][j][i - 1] * 2 + g[j][i]) % hashNum[k]; } } while (q--) { int x, y, len; cin >> x >> y >> len; if (iso(x, y, len)) cout << YES ; else cout << NO ; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 400010; const long long mod = 1000000007; const long double eps = 1e-9; const long long inf = ((1ll << 31ll) - 1ll); const long long INF = 2000000000000000000ll; const long double pi = acos(-1); long long qpow(long long b, long long e) { if (!e) return 1; if (e & 1) return qpow(b, e - 1) * b % mod; long long pwur = qpow(b, e >> 1); return pwur * pwur % mod; } long long modinv(long long x) { return qpow(x, mod - 2); } long long tc, n, a[maxn]; vector<long long> ans; bool sorted() { for (long long i = 1; i < n; i++) if (a[i] > a[i + 1]) return 0; return 1; } void shft(long long x) { swap(a[x + 2], a[x + 1]); swap(a[x + 1], a[x]); } void tryl() { for (long long i = 1; i <= n - 2; i++) { pair<long long, long long> mn = {mod, -1}; for (long long j = i; j <= n; j++) { if (mn.first > a[j]) { mn = {a[j], j}; } } while (mn.second != i) { if (mn.second - 2 >= i) { shft(mn.second - 2); mn.second -= 2; ans.push_back(mn.second); } else { shft(mn.second - 1); shft(mn.second - 1); mn.second -= 1; ans.push_back(mn.second); ans.push_back(mn.second); } } } } void tryr() { for (long long i = n; i >= 3; i--) { pair<long long, long long> mx = {-1, -1}; for (long long j = 1; j <= i; j++) { if (mx.first <= a[j]) { mx = {a[j], j}; } } while (mx.second != i) { if (mx.second + 2 <= i) { shft(mx.second); ans.push_back(mx.second); mx.second += 2; } else { shft(mx.second - 1); ans.push_back(mx.second - 1); mx.second += 1; } } } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.setf(ios::fixed); cout.precision(0); srand(time(NULL)); cin >> tc; while (tc--) { ans.clear(); cin >> n; for (long long i = 1; i <= n; i++) cin >> a[i]; long long bu = 10; while (bu--) { tryl(); tryr(); } for (long long i = 0; i <= 3; i++) { if (i) shft(n - 2); if (a[n - 2] <= a[n - 1] && a[n - 1] <= a[n]) { for (long long j = 1; j <= i; j++) ans.push_back(n - 2); break; } } if (!sorted()) { cout << -1 << n ; continue; } cout << ans.size() << n ; for (auto i : ans) cout << i << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200000 + 10; int a[MAXN]; int sum[MAXN]; int cnt[100 + 10]; vector<int> vc; unordered_map<int, int> mp; int exist[MAXN]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); cnt[a[i]]++; } int D = -1; bool flag = false; for (int i = 1; i <= 100; ++i) { if (cnt[i]) { vc.push_back(i); if (D == -1 || cnt[D] < cnt[i]) { D = i; flag = false; } else if (D != -1 && cnt[i] == cnt[D] && i != D) { flag = true; } } } if (flag) { printf( %d n , n); return 0; } sum[0] = 0; int ans = 0; for (int x : vc) { if (x == D) continue; mp.clear(); exist[0] = 0; mp[0] = 0; for (int i = 1; i <= n; ++i) { if (a[i] == D) sum[i] = sum[i - 1] + 1; else if (a[i] == x) sum[i] = sum[i - 1] - 1; else sum[i] = sum[i - 1] + 0; if (mp.count(sum[i]) == 0) mp[sum[i]] = i; if (a[i] == D) { exist[i] = exist[i - 1] + 1; } else { exist[i] = exist[i - 1]; } } int L = 0; for (int r = 1; r <= n; ++r) { if (mp.count(sum[r])) { int l = mp[sum[r]] + 1; if (l <= r && exist[r] - exist[l - 1] >= 1) { L = max(L, r - l + 1); } } } ans = max(ans, L); } printf( %d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O311A_FUNCTIONAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, sum[3] = {0}; cin >> n; int *x = new int[n], *y = new int[n], *z = new int[n]; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i] >> z[i]; sum[0] += x[i]; sum[1] += y[i]; sum[2] += z[i]; } if (sum[0] == 0 && sum[1] == 0 && sum[2] == 0) cout << YES ; else cout << NO ; delete[] x; delete[] y; delete[] z; return 0; }
|
/*
* stack_tv.v
* Testbench for stack.v
*
* Copyright (C) 2013 James Cowgill
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module stack_tb;
// Inputs
reg clk;
reg rst;
reg [15:0] pushd;
reg push_en;
reg pop_en;
// Outputs
wire [15:0] top;
// Instantiate the Unit Under Test (UUT)
stack uut (
.top(top),
.clk(clk),
.rst(rst),
.pushd(pushd),
.push_en(push_en),
.pop_en(pop_en)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
pushd = 0;
push_en = 0;
pop_en = 0;
// Reset the UUT
rst = 1;
clk = 1;
#10 clk = 0;
rst = 0;
// Push some stuff onto the stack
pushd = 16'hBEEF;
push_en = 1;
#10 clk = 1;
#10 clk = 0;
pushd = 16'hDEAD;
push_en = 1;
#10 clk = 1;
#10 clk = 0;
// Pop it off
push_en = 0;
pop_en = 1;
#10 clk = 1;
#10 clk = 0;
#10 clk = 1;
#10 clk = 0;
end
endmodule
|
module IRRecive(
input clk,
input ir,
output reg [7:0]Code,
output reg press
);
reg [2:0]IR_reg;
initial IR_reg = 3'b0;
always @ (posedge clk) //1us
begin
IR_reg[0] <= ir;
IR_reg[1] <= IR_reg[0];
IR_reg[2] <= IR_reg[1];
end
wire IR_pos = (IR_reg[0]==1'b1) & (IR_reg[1]==1'b0);
wire IR_pos2= (IR_reg[1]==1'b1) & (IR_reg[2]==1'b0);
wire IR_neg = (IR_reg[0]==1'b0) & (IR_reg[1]==1'b1);
wire IR_neg2= (IR_reg[1]==1'b0) & (IR_reg[2]==1'b1);
//状态
parameter ST_START_L = 3'b000, ST_CODE_P = 3'b001 , ST_VALUE_P = 3'b010;
parameter ST_START_H = 3'b011, ST_CODE_N = 3'b100 , ST_VALUE_N = 3'b101;
//宽度
parameter START_H = 16'd4096; //us
parameter START_L = 16'd8192; //us
parameter CODE_0 = 16'd512 + 16'd512 ; //us
parameter CODE_1 = 16'd1536 + 16'd512 ; //us
reg [2:0]state;
reg [15:0]cnt_h;
reg [15:0]cnt_l;
reg [31:0]IR_Value;
reg [15:0]cnt_val;
reg Flag_LVL;
reg Flag_HVL;
always @ (posedge clk or posedge ir)
begin
if(ir) //高电平复位
cnt_l <= 16'b0;
else if(cnt_l[15] & cnt_l[10]) //低计数溢出复位
cnt_l <= 16'b0;
else
cnt_l <= cnt_l + 1'b1; //低电平计数
end
always @ (negedge clk)
begin
if(cnt_l == START_L)
Flag_LVL <= 1'b1;
else if(IR_pos2)
Flag_LVL <= 1'b0;
end
always @ (posedge clk or negedge ir)
begin
if(!ir) //低电平复位
cnt_h <= 16'b0;
else if(cnt_h[15] & cnt_h[10]) //高计数溢出复位
cnt_h <= 16'b0;
else
cnt_h <= cnt_h + 1'b1; //高电平计数
end
always @ (negedge clk)
begin
if(cnt_h == START_H)
Flag_HVL <=1;
else if(IR_neg2)
Flag_HVL <= 1'b0;
end
reg [15:0]IR_code;
always @ (posedge clk or posedge IR_neg)
begin
if(IR_neg)
begin
cnt_val <= 16'b0;
end
else if(state == ST_CODE_P)
begin
if(cnt_val == CODE_0)
begin
IR_code <= CODE_0;
cnt_val <= cnt_val + 1'b1;
end
else if(cnt_val == CODE_1)
begin
IR_code <= CODE_1;
cnt_val <= cnt_val + 1'b1;
end
else
cnt_val <= cnt_val + 1'b1;
end
end
wire fault = cnt_h[15] | cnt_l[15]; //错误
reg [5:0]cnt_num;
initial cnt_num = 6'b0;
reg [19:0]cnt_press;
always @ (posedge clk) //1us
begin
if(press == 1'b1)
cnt_press <= cnt_press + 1;
if(cnt_press == 20'd100000)
begin
press <= 0;
cnt_press <=0;
end
case(state)
ST_START_L:
begin
//press <= 0;
cnt_num <= 6'b0;
if((IR_pos == 1'b1) & (Flag_LVL==1'b1))
begin
state <= ST_START_H;
end
else if(fault)
state <= ST_START_L;
end
ST_START_H :
begin
//press <= 0;
cnt_num <= 6'b0;
if((IR_neg == 1'b1) & (Flag_HVL==1'b1))
begin
state <= ST_CODE_P;
end
else if(fault)
state <= ST_START_L;
end
ST_CODE_P :
begin
if((IR_neg)&(IR_code == CODE_1))
begin
cnt_num = cnt_num + 1'b1;
IR_Value <= {IR_Value[30:0],1'b1};
end
else if((IR_neg)&(IR_code == CODE_0))
begin
cnt_num = cnt_num + 1'b1;
IR_Value <= {IR_Value[30:0],1'b0};
end
else if(cnt_num==6'd32)
begin
press <= 1'b1;
cnt_num <= 6'b0;
state <= ST_START_L;
Code <= {IR_Value[8],IR_Value[9],IR_Value[10],IR_Value[11],IR_Value[12],IR_Value[13],IR_Value[14],IR_Value[15]};
end
end
default : state <= ST_START_L;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline int countbit(T n) { return (n == 0) ? 0 : (1 + countbit(n & (n - 1))); } template <class T> inline T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } const double EPS = 1e-9; const double PI = acos(-1.0); int n, k, h; int ind[100005]; int vel[100005]; int mass[100005]; int ret[100005]; bool can(double mid) { int cnt = 0; double step = k; for (int j = n - 1; j >= 0 && cnt <= k; j--) { double tempo = step * h / ((double)vel[ind[j]]); if (tempo < mid - EPS || fabs(tempo - mid) < EPS) cnt++, step--; } return cnt >= k; } bool cmp(int i, int j) { if (mass[i] != mass[j]) return mass[i] < mass[j]; return vel[i] < vel[j]; } int main(void) { scanf( %d %d %d , &n, &k, &h); for (int i = (0); i < int(n); i++) scanf( %d , &mass[i]); for (int i = (0); i < int(n); i++) scanf( %d , &vel[i]); for (int i = (0); i < int(n); i++) ind[i] = i; sort(ind, ind + n, cmp); double l = 0, r = 10E9 + 100; for (int i = (0); i < int(100); i++) { double mid = (l + r) / 2; if (can(mid)) r = mid; else l = mid; } double mid = r, step = k; int p = k - 1; for (int j = n - 1; j >= 0 && p >= 0; j--) { double tempo = step * h / ((double)vel[ind[j]]); if (tempo < mid - EPS || fabs(tempo - mid) < EPS) { step--; ret[p--] = ind[j] + 1; } } for (int i = (0); i < int(k); i++) { if (i) printf( ); printf( %d , ret[i]); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[101], dif[100], i, unique[101], c = 0; int min = 0, n, dif1, dif2; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); unique[c] = a[0]; c++; for (i = 1; i < n; i++) { if (a[i] != a[i - 1]) { unique[c] = a[i]; c++; } } if (c >= 4) { cout << -1; } else if (c == 1) { cout << 0 << endl; } else if (c == 2) { if ((unique[1] - unique[0]) % 2) { cout << unique[1] - unique[0]; } else { cout << (unique[1] - unique[0]) / 2; } } else { if (unique[2] - unique[1] == unique[1] - unique[0]) { cout << unique[2] - unique[1]; } else { cout << -1 << endl; } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a31o (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_fifo;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_fifo.lxt");
$dumpvars(0, test_axis_fifo);
end
axis_fifo #(
.ADDR_WIDTH(2),
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
test tt();
defparam foo = 3; /* This should generate an error. */
endmodule // main
module test;
parameter foo = 10;
reg [foo-1:0] bar;
endmodule // test
|
//----------------------------------------------------------------
//-- Inicializador
//-- (c) BQ. August 2015. Written by Juan Gonzalez (obijuan)
//-- GPL license
//----------------------------------------------------------------
//-- Generacion de una señal escalo (0 -> 1) para inicializar
//-- circuitos digitales
//----------------------------------------------------------------
//-- Version optimizada
//-- Entrada: Señal de reloj
//-- Salida: Señal escalón de inicialización
module init(input wire clk, output ini);
//-- Inicializar la salida a 0 (se pone para que funcione en simulación)
//-- En síntesis siempre estará a cero con independencia del valor que pongamos
reg ini = 0;
//-- En cada flanco de subida se saca un "1" por la salida
always @(posedge(clk))
ini <= 1;
endmodule
/*
//-- Implementacion natural
module init(input wire clk, output wire ini);
wire din;
reg dout = 0;
//-- Registro
always @(posedge(clk))
dout <= din;
//-- Entrada conectadad a 1
assign din = 1;
//-- Conectar la salida
assign ini = dout;
endmodule
*/
|
#include <bits/stdc++.h> using namespace std; template <class T> bool ckmax(T& x, T y) { return x < y ? x = y, 1 : 0; } template <class T> bool ckmin(T& x, T y) { return x > y ? x = y, 1 : 0; } inline int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = 0; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f ? x : -x; } inline char rdopt() { char ch = getchar(); while (!isalpha(ch)) ch = getchar(); return ch; } const int N = 1 << 20; int n, m, t1, t2, nq, pre[N]; long long tr[N], ans[N]; vector<int> e1[N], e2[N], u2[N]; vector<pair<int, int> > u1[N], q[N]; struct dsu { int F[N], siz[N]; inline void init(const int& n = N - 1) { for (int i = 1, iend = n; i <= iend; ++i) F[i] = i, siz[i] = 1; } inline int anc(int x) { return x == F[x] ? x : F[x] = anc(F[x]); } } d1, d2; inline void add(int x, long long d) { for (int i = x; i <= m; i += i & -i) tr[i] += d; } inline long long ask(int x) { long long res = 0; for (int i = x; i > 0; i -= i & -i) res += tr[i]; return res; } inline int query(int tim) { int res = 0, lim = ask(tim); for (int i = 19; i >= 0; --i) if (res + (1 << i) <= m && tr[res + (1 << i)] < lim) res += 1 << i, lim -= tr[res]; return res; } void dfs2(int u) { for (int i : u2[u]) add(i, 1); for (pair<int, int> i : q[u]) pre[i.second] = query(i.first); for (int v : e2[u]) dfs2(v); for (int i : u2[u]) add(i, -1); } void dfs1(int u) { for (pair<int, int> i : u1[u]) add(i.first, i.second); for (pair<int, int> i : q[u]) ans[i.second] = ask(i.first) - ask(pre[i.second]); for (int v : e1[u]) dfs1(v); for (pair<int, int> i : u1[u]) add(i.first, -i.second); } signed main() { n = read(), m = read(); d1.init(n), d2.init(n), t1 = t2 = n; for (int i = 1; i <= m; ++i) { char op = rdopt(); if (op == U ) { int x = read(), y = read(), fx = d1.anc(x), fy = d1.anc(y); ++t1, d1.F[fx] = d1.F[fy] = d1.F[t1] = t1, d1.siz[t1] = d1.siz[fx] + d1.siz[fy]; e1[t1].push_back(fx), e1[t1].push_back(fy); } else if (op == M ) { int x = read(), y = read(), fx = d2.anc(x), fy = d2.anc(y); ++t2, d2.F[fx] = d2.F[fy] = d2.F[t2] = t2; e2[t2].push_back(fx), e2[t2].push_back(fy); } else if (op == A ) { int x = read(), fx = d1.anc(x); u1[fx].push_back(make_pair(i, d1.siz[fx])); } else if (op == Z ) { int x = read(), fx = d2.anc(x); u2[fx].push_back(i); } else if (op == Q ) { int x = read(); q[x].push_back(make_pair(i, ++nq)); } } for (int i = 1, iend = t2; i <= iend; ++i) if (d2.F[i] == i) dfs2(i); for (int i = 1, iend = t1; i <= iend; ++i) if (d1.F[i] == i) dfs1(i); for (int i = 1; i <= nq; ++i) printf( %lld n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; void go() { ios_base::sync_with_stdio(0); cin.tie(0); cout << fixed; cout << setprecision(6); } void solve() { string s; cin >> s; long long n = s.size(); vector<long long> arr(n); long long cur = 0; for (long long i = 0; i < n; i++) { if (s[i] == + ) cur++; else cur--; arr[i] = cur; } map<long long, long long> mp; for (long long i = n - 1; i >= 0; i--) { if (arr[i] < 0) mp[arr[i]] = i + 1; } long long ans = n; for (auto x : mp) { ans += x.second; } cout << ans << n ; } signed main() { go(); long long t = 1; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 5; map<pair<int, long long>, bool> vis; map<pair<int, long long>, int> memo; int grundy(int x, long long mask) { for (int i = 61; i > x; i--) { if ((mask >> i) & 1) mask ^= (1ll << i); } if (vis[{x, mask}]) return memo[{x, mask}]; vis[{x, mask}] = 1; set<int> s; for (int i = 1; i <= x; i++) { if ((mask >> i) & 1) { s.insert(grundy(x - i, mask ^ (1ll << i))); } } int res = 0; while (s.find(res) != s.end()) res++; return memo[{x, mask}] = res; } int n; int s[MAXN]; int main() { scanf( %d , &n); int res = 0; for (int i = 1; i <= n; i++) { scanf( %d , s + i); res ^= grundy(s[i], (1ll << 61) - 1); } if (res) puts( NO ); else puts( YES ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { int n, h; cin >> h >> n; int a[n]; for (int i = 0; i < n; ++i) cin >> a[i]; int cnt = 1; vector<int> v; for (int i = 1; i < n; ++i) { if (a[i] == a[i - 1] - 1) { ++cnt; } else { v.push_back(cnt); cnt = 1; } } v.push_back(cnt); int sm = 0; if (v.size() == 1) { if (a[n - 1] < 2) sm = 0; else { if (v[0] % 2 == 0) sm = 1; else sm = 0; } } else { for (int i = 0; i < v.size(); ++i) { if (i == 0) { if (v[i] % 2 == 0) ++sm; } else if (i == v.size() - 1) { ++v[i]; if (a[n - 1] >= 2 && v[i] % 2 == 0) ++sm; } else { ++v[i]; if (v[i] % 2 == 0) ++sm; } } } cout << sm << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 505; int a[maxn][maxn], b[maxn][maxn]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &a[i][j]); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &b[i][j]); bool flag = 1; for (int i = 1; i <= n; i++) { int cnt = 0; for (int j = 1; j <= m; j++) if (a[i][j] != b[i][j]) cnt++; if (cnt % 2) flag = 0; } for (int j = 1; j <= m; j++) { int cnt = 0; for (int i = 1; i <= n; i++) if (a[i][j] != b[i][j]) cnt++; if (cnt % 2) flag = 0; } if (flag) printf( Yes n ); else printf( No n ); }
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; using namespace std::chrono; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; string s; cin >> s; long long int a[26]; for (int i = 0; i < 26; i++) cin >> a[i]; long long int maxx = -1, len = 0, minn; vector<long long int> dp(n + 1, 0), dp2(n + 1, 1e12); for (int i = 0; i < n; i++) { minn = 1e12; for (int j = i; j >= 0; j--) { len = i - j + 1; minn = min(minn, a[s[j] - a ]); if (minn < len) break; long long int x = j - 1 >= 0 ? dp[j - 1] : 1; dp[i] = (dp[i] + x) % mod; maxx = max(maxx, len); x = j - 1 >= 0 ? dp2[j - 1] : 0; dp2[i] = min(dp2[i], x + 1); } } cout << dp[n - 1] % mod << endl << maxx << endl << dp2[n - 1]; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> inline istream& operator>>(istream& fin, pair<T1, T2>& pr) { fin >> pr.first >> pr.second; return fin; } template <class T0, class T1, class T2> inline istream& operator>>(istream& fin, tuple<T0, T1, T2>& t) { fin >> get<0>(t) >> get<1>(t) >> get<2>(t); return fin; } template <class T> inline istream& operator>>(istream& fin, vector<T>& a) { for (auto& u : a) fin >> u; return fin; } template <class T, size_t n> inline istream& operator>>(istream& fin, array<T, n>& a) { for (auto& u : a) fin >> u; return fin; } int f542() { size_t n, time; cin >> n >> time; typedef struct { size_t buf, val; } value_t; const auto comp = [](const value_t& a, const value_t& b) { return a.buf < b.buf || (a.buf == b.buf && a.val < b.val); }; priority_queue<value_t, vector<value_t>, decltype(comp)> heap(comp); for (size_t i = 0; i < n; ++i) { size_t val, lag; cin >> lag >> val; if (lag < time + 1) heap.push({time - lag, val}); } size_t val = 0; while (!heap.empty()) { const auto top = heap.top(); heap.pop(); if (top.buf == 0 || heap.empty()) val = max(val, top.val); else { const auto next = heap.top(); if (top.buf != next.buf) heap.push({next.buf, top.val}); else { heap.pop(); heap.push({top.buf - 1, top.val + next.val}); } } } return val; } int main(const int argc, char* argv[]) { cout << f542(); return EXIT_SUCCESS; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_PP_BLACKBOX_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb16to1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input [15:0] D ;
input [15:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 100005; char en = n ; long long inf = 1e16; long long mod = 1e9 + 7; long long power(long long x, long long n, long long mod) { long long res = 1; x %= mod; while (n) { if (n & 1) res = (res * x) % mod; x = (x * x) % mod; n >>= 1; } return res; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, k; cin >> n >> k; long long curr = n * (n + 1) / 2; if (curr > k) { cout << -1 << en; return 0; } long long arr[n + 5]; for (long long i = 1; i <= n; i++) arr[i] = i; long long rem = k - curr; long long start = 1; while (rem) { long long end1 = n - start + 1; long long max1 = end1 - start; if (max1 <= 0) break; if (rem >= max1) { swap(arr[start], arr[end1]); rem -= max1; } else { swap(arr[start], arr[start + rem]); break; } start++; } long long ans = 0; for (long long i = 1; i <= n; i++) { ans += max(i, arr[i]); } cout << ans << en; for (long long i = 1; i <= n; i++) cout << i << ; cout << en; for (long long i = 1; i <= n; i++) cout << arr[i] << ; cout << en; return 0; }
|
#include <bits/stdc++.h> using namespace std; string st; vector<long> v; long r; int main() { ios_base::sync_with_stdio(0); cin >> st; st += + ; for (int i = 0; i < st.size(); i++) { if (st[i] == + ) { v.push_back(r); r = 0; } else r = r * 10 + st[i] - 48; } sort(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) { if (i) cout << + ; cout << v[i]; } cout << endl; cin.get(); cin.get(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353, MAX = 100003, INF = 1 << 30; long long rui(long long a, long long b) { if (b == 1) return a % mod; else if (b == 0) return 1; else if (b % 2 == 0) return (rui(a, b / 2) * rui(a, b / 2)) % mod; else return (rui(a, b - 1) * a) % mod; } int main() { int Q; cin >> Q; for (int q = 0; q < Q; q++) { int N, M; cin >> N >> M; vector<int> S[N], color(N, 0); for (int i = 0; i < M; i++) { int a, b; cin >> a >> b; a--; b--; S[a].push_back(b); S[b].push_back(a); } long long ans = 1; for (int i = 0; i < N; i++) { if (color[i]) continue; int odd = 1, even = 0; color[i] = 1; queue<int> Q; Q.push(i); while (!Q.empty()) { int a = Q.front(); Q.pop(); for (int j = 0; j < S[a].size(); j++) { int b = S[a][j]; if (color[b] == 0) { color[b] = 3 - color[a]; if (color[b] % 2) odd++; else even++; Q.push(b); } else if (color[a] == color[b]) { ans = 0; } } } ans *= (rui(2, odd) + rui(2, even)) % mod; ans %= mod; } cout << ans << endl; } }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 11:22:00 10/24/2016
// Module Name: I_DECODE_tb
// Project Name: MIPS
// Description: Tests the MIPS ID (DECODE) pipeline stage.
//
// Dependencies: I_DECODE.v
//
////////////////////////////////////////////////////////////////////////////////
module I_DECODE_tb;
// Inputs
reg clk;
reg RegWrite;
reg [31:0] IF_ID_Instr;
reg [31:0] IF_ID_NPC;
reg [4:0] MEM_WB_Writereg;
reg [31:0] MEM_WB_Writedata;
// Outputs
wire [1:0] WB;
wire [2:0] M;
wire [3:0] EX;
wire [31:0] NPC;
wire [31:0] rdata1out;
wire [31:0] rdata2out;
wire [31:0] IR;
wire [4:0] instrout_2016;
wire [4:0] instrout_1511;
// Instantiate the I_DECODE module
I_DECODE decode(.clk(clk), .RegWrite(RegWrite), .IF_ID_Instr(IF_ID_Instr),
.IF_ID_NPC(IF_ID_NPC), .MEM_WB_Writereg(MEM_WB_Writereg),
.MEM_WB_Writedata(MEM_WB_Writedata), .WB(WB), .M(M), .EX(EX),
.NPC(NPC), .rdata1out(rdata1out), .rdata2out(rdata2out),
.IR(IR), .instrout_2016(instrout_2016), .instrout_1511(instrout_1511));
initial begin
// Initialize Inputs
clk = 1;
RegWrite = 0;
IF_ID_Instr = 0;
IF_ID_NPC = 0;
MEM_WB_Writereg = 0;
MEM_WB_Writedata = 0;
// Wait 100 ns for global reset to finish
$display("Initializing and waiting for reset...");
#100;
// Write test data to the first nine locations
$display("Writing data...");
RegWrite = 1;
MEM_WB_Writedata = 32'h002300AA;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h10654321;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h00100022;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h8C123456;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h8F123456;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'hAD654321;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h13012345;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'hAC654321;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h12012345;
// Read test data from the nine test locations.
// rs will read evens and rt will read odds until the last register,
// where both will read the ninth register together.
#20;
$display("Reading data...");
RegWrite = 0;
IF_ID_instr = 32'b00000000000000010000000000000000;
#20
IF_ID_instr = 32'b00000000010000110000000000000000;
#20
IF_ID_instr = 32'b00000000100001010000000000000000;
#20
IF_ID_instr = 32'b00000000110001110000000000000000;
#20
IF_ID_instr = 32'b00000001000010000000000000000000;
#20 $finish;
end
initial begin
$monitor("INPUTS: IF_ID_instr = %b | IF_ID_NPC = %h | RegWrite = %d | ",
IF_ID_instr, IF_ID_NPC, RegWrite,
"MEM_WB_Writereg = %d | MEM_WB_Writedata = %h | ",
MEM_WB_Writereg, MEM_WB_Writedata,
"OUTPUTS: WB = %b | M = %b | EX = %b | NPC = %h | ",
WB, M, EX, NPC,
"rdata1out = %h | rdata2out = %h | IR = %d | ",
rdata1out, rdata2out, IR,
"instrout_2016 = %d | instrout_1511 = %d",
instrout_2016, instrout_1511);
forever begin
#10 clk = ~clk;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:30:44 03/22/2015
// Design Name: fulladder1bit
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW1/fulladder1bit_test.v
// Project Name: HW1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fulladder1bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fulladder1bit_test;
// Inputs
reg A;
reg B;
reg Cin;
// Outputs
wire S;
wire Cout;
// Variables
integer i;
// Instantiate the Unit Under Test (UUT)
fulladder1bit uut (
.S(S),
.Cout(Cout),
.A(A),
.B(B),
.Cin(Cin)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
Cin = 0;
// Loop Through All Possible Inputs
for(i=1; i<=8; i=i+1)
begin
#20 {A, B, Cin} = {A, B, Cin} + 1;
end
end
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for subtype definitions.
module vhdl_subtypes_test;
int a, b, c;
time d;
int e;
vhdl_subtypes dut(a, b, c, d, e);
initial
begin
#1;
if(a !== 1) begin
$display("FAILED");
$finish();
end
if(b !== 2) begin
$display("FAILED");
$finish();
end
if(c !== 3) begin
$display("FAILED");
$finish();
end
if(d !== 4) begin
$display("FAILED");
$finish();
end
if(e !== 5) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, first, a[1111]; int b[1111], ub = -1, pos; vector<int> c[1111]; vector<int> d; int can[1111]; void go(int p, int v) { if (v == -1) return; if (v == first) ub = p; c[p].push_back(v); go(p, a[v]); } int main() { scanf( %d%d , &n, &first); --first; for (int i = 0; i < n; ++i) b[i] = -1; for (int i = 0; i < n; ++i) { scanf( %d , a + i); a[i]--; b[a[i]] = i; } for (int i = 0; i < n; ++i) { c[i].clear(); if (b[i] == -1) { go(i, i); } } assert(ub >= 0); d.clear(); for (int i = 0; i < c[ub].size(); ++i) { if (c[ub][i] == first) pos = c[ub].size() - i; } for (int i = 0; i < n; ++i) { if (i == ub) continue; if (c[i].size() != 0) d.push_back(c[i].size()); } sort(d.begin(), d.end()); for (int i = 0; i < n; ++i) can[i] = 0; can[0] = 1; for (int i = 0; i < d.size(); ++i) { for (int j = n - 1; j >= 0; --j) { if ((j + d[i] < n) && (can[j] == 1)) can[j + d[i]] = 1; } } for (int i = 0; i < n; ++i) { if (can[i]) cout << i + pos << endl; } return 0; }
|
/**
* sseg_driver.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
/* seven segment display driver */
module sseg_driver(
input wire [ 3 : 0] digit, /* digit to show */
input wire [ 1 : 0] sel, /* place to show */
output reg [ 3 : 0] anode, /* common anode enable */
output reg [ 6 : 0] cathode /* cathode enable */
);
/* decode anode enable signal */
always @(sel) begin
case(sel)
2'b00: anode = 4'b1110;
2'b01: anode = 4'b1101;
2'b10: anode = 4'b1011;
2'b11: anode = 4'b0111;
endcase
end
/* decode digit into 7-segment driver output */
always @(digit) begin
case(digit) /* ABCDEFG */
4'h0: cathode = 7'b0000001;
4'h1: cathode = 7'b1001111;
4'h2: cathode = 7'b0010010;
4'h3: cathode = 7'b0000110;
4'h4: cathode = 7'b1001100;
4'h5: cathode = 7'b0100100;
4'h6: cathode = 7'b0100000;
4'h7: cathode = 7'b0001111;
4'h8: cathode = 7'b0000000;
4'h9: cathode = 7'b0000100;
4'ha: cathode = 7'b0001000;
4'hb: cathode = 7'b1100000;
4'hc: cathode = 7'b0110001;
4'hd: cathode = 7'b1000010;
4'he: cathode = 7'b0110000;
4'hf: cathode = 7'b0111000;
endcase
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: None
// Engineer: Dai Tianyu (dtysky)
//
// Create Date: 2015/04/07 18:01:07
// Design Name:
// Module Name: Mux8
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependenrgb24es:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux8(sel, i0, i1, i2, i3, i4, i5, i6, i7, o);
parameter data_width = 8;
input[2 : 0] sel;
input[data_width - 1 : 0] i0;
input[data_width - 1 : 0] i1;
input[data_width - 1 : 0] i2;
input[data_width - 1 : 0] i3;
input[data_width - 1 : 0] i4;
input[data_width - 1 : 0] i5;
input[data_width - 1 : 0] i6;
input[data_width - 1 : 0] i7;
output[data_width - 1 : 0] o;
reg[data_width - 1 : 0] reg_o;
always @(*) begin
case (sel)
0 : reg_o <= i0;
1 : reg_o <= i1;
2 : reg_o <= i2;
3 : reg_o <= i3;
4 : reg_o <= i4;
5 : reg_o <= i5;
6 : reg_o <= i6;
7 : reg_o <= i7;
default : /* default */;
endcase
end
assign o = reg_o;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } bool isPrime(long long n) { if (n < 2) return 0; if (n < 4) return 1; if (n % 2 == 0 or n % 3 == 0) return 0; for (long long i = 5; i * i <= n; i += 6) if (n % i == 0 or n % (i + 2) == 0) return 0; return 1; } long long modexpo(long long x, long long p) { long long res = 1; x = x % 1000000007; while (p) { if (p % 2) res = res * x; p >>= 1; x = x * x % 1000000007; res %= 1000000007; } return res; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) { long long n, g, b; cin >> n >> g >> b; long long x = n / 2 + (n % 2); long long ans = 0; ans += (x / g) * g + ((x / g + (x % g ? 1 : 0)) - 1) * b; ans += x % g; if (n > ans) ans += n - ans; cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; void print(int x) { cerr << x; } void print(long x) { cerr << x; } void print(long long x) { cerr << x; } void print(unsigned x) { cerr << x; } void print(unsigned long x) { cerr << x; } void print(unsigned long long x) { cerr << x; } void print(float x) { cerr << x; } void print(double x) { cerr << x; } void print(long double x) { cerr << x; } void print(char x) { cerr << << x << ; } void print(const char *x) { cerr << << x << ; } void print(const string &x) { cerr << << x << ; } void print(bool x) { cerr << (x ? true : false ); } const long long int MOD = 1e9 + 7; const long long int INF = 1e18; const long long int maxn = 1e6 + 4; void answer() { long long int a; cin >> a; vector<long long int> v; long long int sum = 0; for (long long int i = 0; i < a; ++i) { long long int temp; cin >> temp; v.push_back(temp); sum += temp; } long long int k = sum / a; long long int ans = 0; if (a == 1) { cout << 0; } else { for (long long int i = 0; i < a - 1; ++i) { if (v[i] < k) { long long int real = k - v[i]; ans += real; v[i + 1] -= real; v[i] = k; } else { long long int real = v[i] - k; ans += real; v[i + 1] += real; v[i] = k; } } cout << ans; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t-- > 0) { answer(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<long long> a(n + 1); for (int i = 1; i <= n; i++) { cin >> a[i]; } int m; cin >> m; long long ans = 0; long long wt = 0, ht = 0; while (m--) { long long w, h; cin >> w >> h; ans = max(ans + ht, a[w]); wt = w; ht = h; cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxint = -1u >> 1; template <class T> bool get_max(T& a, const T& b) { return b > a ? a = b, 1 : 0; } template <class T> bool get_min(T& a, const T& b) { return b < a ? a = b, 1 : 0; } int main() { int f[21]; int a, b, c; cin >> a >> b >> c; f[0] = a; f[1] = b; for (int i = 2; i < 21; i++) f[i] = f[i - 1] + f[i - 2]; cout << f[c] << endl; return 0; }
|
/*TODO:
Test byte masks
Add timeout
Add FIFO mode
*/
module wb_bfm_transactor
#(parameter aw = 32,
parameter dw = 32,
parameter VERBOSE = 0,
parameter MAX_BURST_LEN = 5,
parameter MEM_LOW = 0,
parameter MEM_HIGH = 32'hffffffff)
(input wb_clk_i,
input wb_rst_i,
output [aw-1:0] wb_adr_o,
output [dw-1:0] wb_dat_o,
output [3:0] wb_sel_o,
output wb_we_o,
output wb_cyc_o,
output wb_stb_o,
output [2:0] wb_cti_o,
output [1:0] wb_bte_o,
input [dw-1:0] wb_dat_i,
input wb_ack_i,
input wb_err_i,
input wb_rty_i,
output reg done);
`include "wb_bfm_params.v"
integer SEED = 2;
integer TRANSACTIONS;
initial
if(!$value$plusargs("transactions=%d", TRANSACTIONS))
TRANSACTIONS = 1000;
wb_bfm_master
#(.MAX_BURST_LENGTH (MAX_BURST_LEN))
bfm
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wb_adr_o),
.wb_dat_o (wb_dat_o),
.wb_sel_o (wb_sel_o),
.wb_we_o (wb_we_o),
.wb_cyc_o (wb_cyc_o),
.wb_stb_o (wb_stb_o),
.wb_cti_o (wb_cti_o),
.wb_bte_o (wb_bte_o),
.wb_dat_i (wb_dat_i),
.wb_ack_i (wb_ack_i),
.wb_err_i (wb_err_i),
.wb_rty_i (wb_rty_i));
/*Return a 2*aw array with the highest and lowest accessed addresses
based on starting address and burst type
TODO: Account for short wrap bursts. Fix for 8-bit mode*/
function [2*aw-1:0] adr_range;
input [aw-1:0] adr_i;
input [$clog2(MAX_BURST_LEN)-1:0] len_i;
input [2:0] burst_type_i;
parameter bpw = 4; //Bytes per word. Hardcoded to 4 (32-bit)
reg [aw-1:0] adr;
reg [aw-1:0] adr_high;
reg [aw-1:0] adr_low;
begin
if(bpw==4)
adr = adr_i[aw-1:2];
case (burst_type_i)
LINEAR_BURST : begin
adr_high = (adr+len_i)*bpw-1;
adr_low = adr*bpw;
end
WRAP_4_BURST : begin
adr_high = (adr[aw-1:2]*4+4)*bpw-1;
adr_low = adr[aw-1:2]*4*bpw;
end
WRAP_8_BURST : begin
adr_high = (adr[aw-1:3]*8+8)*bpw-1;
adr_low = adr[aw-1:3]*8*bpw;
end
WRAP_16_BURST : begin
adr_high = (adr[aw-1:4]*16+16)*bpw-1;
adr_low = adr[aw-1:4]*16*bpw;
end
CONSTANT_BURST : begin
adr_high = (adr+1)*bpw-1;
adr_low = adr*bpw;
end
default : begin
$error("%d : Illegal burst type (%b)", $time, burst_type);
adr_range = {2*aw{1'bx}};
end
endcase // case (burst_type)
adr_range = {adr_high, adr_low};
end
endfunction
reg [dw*MAX_BURST_LEN-1:0] write_data;
reg [dw*MAX_BURST_LEN-1:0] read_data;
reg [dw*MAX_BURST_LEN-1:0] expected_data;
integer word;
integer burst_length;
reg [2:0] burst_type;
integer transaction;
integer tmp, burst_wrap;
reg err;
reg [aw-1:0] address;
reg [aw-1:0] adr_high;
reg [aw-1:0] adr_low;
initial begin
bfm.reset;
done = 0;
$display("%m : Running %0d transactions", TRANSACTIONS);
$display("Max burst length=%0d", MAX_BURST_LEN);
for(transaction = 0 ; transaction < TRANSACTIONS; transaction = transaction + 1) begin
address = (MEM_LOW + ($random(SEED) % (MEM_HIGH-MEM_LOW))) & {{aw-2{1'b1}},2'b00};
burst_length = ({$random(SEED)} % MAX_BURST_LEN) + 1;
burst_type = ({$random(SEED)} % 4);
{adr_high, adr_low} = adr_range(address, burst_length, burst_type);
while((adr_high > MEM_HIGH) || (adr_low < MEM_LOW)) begin
address = (MEM_LOW + ($random(SEED) % (MEM_HIGH-MEM_LOW))) & {{aw-2{1'b1}},2'b00};
burst_length = ({$random(SEED)} % MAX_BURST_LEN) + 1;
burst_type = ({$random(SEED)} % 4);
{adr_high, adr_low} = adr_range(address, burst_length, burst_type);
end
case (burst_type)
LINEAR_BURST : burst_wrap = burst_length;
WRAP_4_BURST : burst_wrap = 4;
WRAP_8_BURST : burst_wrap = 8;
WRAP_16_BURST : burst_wrap = 16;
CONSTANT_BURST : burst_wrap = 1;
default : $error("%d : Illegal burst type (%b)", $time, burst_type);
endcase
for(word = 0; word < burst_length; word = word + 1)
write_data[dw*word+:dw] = $random;
bfm.write_burst(address, write_data, 4'hf, burst_length, burst_type, err);
@(posedge wb_clk_i);
bfm.read_burst(address, read_data, 4'hf, burst_length, burst_type, err);
@(posedge wb_clk_i);
if(VERBOSE>0)
if(!(transaction%(TRANSACTIONS/10)))
$display("%m : %0d/%0d", transaction, TRANSACTIONS);
tmp = burst_length-1;
for(word = burst_length-1 ; word >= 0 ; word = word - 1) begin
expected_data[dw*word+:dw] = write_data[dw*tmp+:dw];
tmp = tmp - 1;
if(tmp < burst_length - burst_wrap)
tmp = burst_length-1;
end
for(word = 0 ; word < burst_length ; word = word +1)
if(read_data[word*dw+:dw] !== expected_data[word*dw+:dw]) begin
$error("Transaction %0d failed!", transaction);
$error("Read data mismatch on address %h (burst length=%0d, burst_type=%0d, iteration %0d)", address, burst_length, burst_type, word);
$error("Expected %h", expected_data[word*dw+:dw]);
$error("Got %h", read_data[word*dw+:dw]);
#3 $finish;
end
if (VERBOSE>1) $display("Read ok from address %h (burst length=%0d, burst_type=%0d)", address, burst_length, burst_type);
end
done = 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4e5 + 5; int fa[maxn]; int m, n, q, i, x, y; int getfa(int x) { if (x == fa[x]) return x; return fa[x] = getfa(fa[x]); } int main() { scanf( %d%d%d , &n, &m, &q); for (i = 1; i <= m + n; i++) fa[i] = i; for (i = 1; i <= q; i++) { scanf( %d%d , &x, &y); fa[getfa(x)] = getfa(y + n); } int num = 0; for (i = 1; i <= m + n; i++) { if (fa[i] == i) num++; } cout << num - 1 << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_hd__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(false); ; cin.tie(NULL); ; long long int t = 1; while (t--) { long long int n; cin >> n; pair<long long int, long long int> tree[n]; long long int i, j, k; map<pair<long long int, long long int>, long long int> mp; for (i = 0; i < n; i++) { cin >> j >> k; tree[i].first = j; tree[i].second = k; } list<long long int> l; for (i = 0; i < n; i++) { if (tree[i].first == 1) l.push_back(i); } vector<pair<long long int, long long int> > edges; while (!l.empty()) { long long int node = l.front(); l.pop_front(); if (tree[node].first == 0) continue; long long int xors = tree[node].second; tree[xors].first--; tree[xors].second ^= node; edges.push_back({node, xors}); if (tree[xors].first == 1) l.push_back(xors); } cout << edges.size() << endl; for (auto x : edges) cout << x.first << << x.second << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void doRoutine() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); srand(322179); } signed main() { doRoutine(); long long n; cin >> n; long long res = 0; while (n > 0) { ++res; n /= 2; } cout << res << endl; return 0; }
|
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