text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1 << 18; int a[MAXN]; long long s[MAXN << 2]; int h[MAXN << 2]; void build(int id, int l, int r) { if (l == r) { s[id] = a[l]; h[id] = 0; return; } int mid = (l + r) >> 1; build(id << 1, l, mid); build(id << 1 | 1, mid + 1, r); s[id] = s[id << 1] + s[id << 1 | 1]; h[id] = h[id << 1] + 1; } long long query(int id, int l, int r, int ll, int rr) { if (ll <= l && r <= rr) return s[id]; int mid = (l + r) >> 1; long long ret = 0; if (ll <= mid) ret += query(id << 1, l, mid, ll, rr); if (rr > mid) ret += query(id << 1 | 1, mid + 1, r, ll, rr); return ret; } void modify(int id, int l, int r, int pos, int v) { if (l == r) { s[id] = v; return; } int mid = (l + r) >> 1; if (pos <= mid) modify(id << 1, l, mid, pos, v); else modify(id << 1 | 1, mid + 1, r, pos, v); s[id] = s[id << 1] + s[id << 1 | 1]; } int S; int v = 0; long long query1(int id, int l, int r, int ll, int rr) { if (ll <= l && r <= rr) { int LLL = ((v & (S - (1 << h[id]))) ^ l), RRR = ((v & (S - (1 << h[id]))) ^ r); if (LLL > RRR) swap(LLL, RRR); return query(1, 0, S - 1, LLL, RRR); } int mid = (l + r) >> 1; long long ret = 0; if (ll <= mid) ret += query1(id << 1, l, mid, ll, rr); if (rr > mid) ret += query1(id << 1 | 1, mid + 1, r, ll, rr); return ret; } int main() { int n, q; scanf( %d%d , &n, &q); for (int i = 0; i < (1 << n); ++i) scanf( %d , &a[i]); build(1, 0, (1 << n) - 1); S = (1 << n); for (int i = 1; i <= q; ++i) { int tp; scanf( %d , &tp); if (tp == 1) { int x, k; scanf( %d%d , &x, &k); x--; x ^= v; modify(1, 0, (1 << n) - 1, x, k); } else if (tp == 2) { int k; scanf( %d , &k); v ^= (1 << k) - 1; } else if (tp == 3) { int k; scanf( %d , &k); v ^= (1 << k); } else { int l, r; scanf( %d%d , &l, &r); l--; r--; printf( %lld n , query1(1, 0, (1 << n) - 1, l, r)); } } return 0; }
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone RAM
*/
module wb_ram #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 16, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
input wire clk,
input wire [ADDR_WIDTH-1:0] adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] dat_o, // DAT_O() data out
input wire we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] sel_i, // SEL_I() select input
input wire stb_i, // STB_I strobe input
output wire ack_o, // ACK_O acknowledge output
input wire cyc_i // CYC_I cycle input
);
// for interfaces that are more than one word wide, disable address lines
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(SELECT_WIDTH);
// width of data port in words (1, 2, 4, or 8)
parameter WORD_WIDTH = SELECT_WIDTH;
// size of words (8, 16, 32, or 64 bits)
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
reg [DATA_WIDTH-1:0] dat_o_reg = {DATA_WIDTH{1'b0}};
reg ack_o_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
wire [VALID_ADDR_WIDTH-1:0] adr_i_valid = adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
assign dat_o = dat_o_reg;
assign ack_o = ack_o_reg;
integer i, j;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 2**(VALID_ADDR_WIDTH/2)) begin
for (j = i; j < i + 2**(VALID_ADDR_WIDTH/2); j = j + 1) begin
mem[j] = 0;
end
end
end
always @(posedge clk) begin
ack_o_reg <= 1'b0;
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (cyc_i & stb_i & ~ack_o) begin
if (we_i & sel_i[i]) begin
mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= dat_i[WORD_SIZE*i +: WORD_SIZE];
end
dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
ack_o_reg <= 1'b1;
end
end
end
endmodule
|
/*
** Copyright (C) 2009 Onno Kortmann <>
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License along
** with this program; if not, write to the Free Software Foundation, Inc.,
** 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA..
**
*/
/* SPI slave Verilog example code. */
`timescale 1ns / 1ns
module test;
reg CLK;
wire nCS, SCK, MOSI;
wire MISO;
wire [7:0] pb;
wire [7:0] pc;
wire [7:0] pd;
assign MISO=pb[4];
assign MOSI=pb[3];
assign SCK=pb[5];
assign nCS=pb[2];
defparam avr.progfile="spi-waveforms.elf";
ATmega8 avr(CLK, pb, pc, pd);
initial begin
$avr_trace("spi-waveforms.trace");
$dumpfile("spi-waveforms.vcd");
$dumpvars(0, test);
# 100000 $finish;
end // initial begin
always begin
#100 CLK<=0;
#100 CLK<=1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<unsigned int> vc; unsigned long long n, T; void LIS(unsigned int ll, unsigned int hh, unsigned long long &len, unsigned long long &offset) { vector<unsigned int> dp_nn; vector<unsigned int> dp_nn_plus_n; dp_nn.resize(ll); dp_nn_plus_n.resize(hh); for (unsigned int i = 0; i < hh; ++i) dp_nn_plus_n[i] = 1; for (unsigned int i = 0; i < ll; ++i) dp_nn[i] = 1; for (unsigned int i = 0; i < hh; ++i) { for (unsigned int j = 0; j < i; ++j) { if (vc[i % n] >= vc[j % n]) { dp_nn_plus_n[i] = max(dp_nn_plus_n[i], dp_nn_plus_n[j] + 1); if (i < ll) dp_nn[i] = max(dp_nn[i], dp_nn[j] + 1); } } } sort(dp_nn_plus_n.begin(), dp_nn_plus_n.end()); sort(dp_nn.begin(), dp_nn.end()); unsigned long long h = dp_nn_plus_n[dp_nn_plus_n.size() - 1]; unsigned long long l = dp_nn[dp_nn.size() - 1]; offset = h - l; len = l; return; } int main() { cin >> n >> T; for (unsigned long long i = 0; i < n; ++i) { unsigned int x; cin >> x; vc.push_back(x); } unsigned long long mx = max(n, T); unsigned long long mn = min(n, T); unsigned long long lim = mn * n + n; unsigned long long delta = 0; unsigned long long L = 0; LIS(mn * n, lim, L, delta); unsigned long long pad = (mx - n) * delta; cout << L + pad << endl; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_buffered_fifo(clock, resetn,
data_in, valid_in, stall_out,
data_out, valid_out, stall_in);
parameter DATA_WIDTH = 32;
parameter DEPTH = 64;
parameter EXTRA_FIFO_SPACE = 32; //256;
parameter IMPLEMENTATION_MODE = "MLAB";
localparam REAL_DEPTH=DEPTH-EXTRA_FIFO_SPACE;
input clock, resetn;
input [DATA_WIDTH-1:0] data_in;
input valid_in;
output stall_out;
output [DATA_WIDTH-1:0] data_out;
output valid_out;
input stall_in;
wire fifo_almost_full;
generate
if (IMPLEMENTATION_MODE == "RAM")
begin
acl_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(data_in), .data_out(data_out), .valid_in(valid_in),
.valid_out( valid_out ), .stall_in(stall_in), .stall_out(),
.almost_full( fifo_almost_full ) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = DEPTH;
defparam fifo_a.ALMOST_FULL_VALUE = REAL_DEPTH;
end
else
begin
acl_mlab_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(data_in), .data_out(data_out), .valid_in(valid_in),
.valid_out( valid_out ), .stall_in(stall_in), .stall_out(),
.almost_full( fifo_almost_full ) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = DEPTH;
defparam fifo_a.ALMOST_FULL_VALUE = REAL_DEPTH;
end
endgenerate
assign stall_out = fifo_almost_full;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e3 + 10; const long long M = 1e9 + 7; long long Max(long long a, long long b) { if (a > b) return a; return b; } long long Min(long long a, long long b) { if (a > b) return b; return a; } long long big_mul(long long a, long long b, long long m) { long long x = 0, y = a % m; while (b > 0) { if (b & 1) x = (x + y) % m; y = (2 * y) % m; b >>= 1; } return x % m; } long long big_mod(long long a, long long b, long long m) { long long x = 1, y = a % m; while (b > 0) { if (b & 1) x = (x * y) % m; y = (y * y) % m; b >>= 1; } return x % m; } long long Big_mod(long long a, long long b, long long m) { long long x = 1, y = a % m; while (b > 0) { if (b & 1) x = big_mul(x, y, m); y = big_mul(y, y, m); b >>= 1; } return x % m; } long long mod_inverse(long long a, long long m) { return big_mod(a, m - 2, m); } unordered_map<string, bool> Map; int a, b, c, d, e, f, g, h; vector<pair<int, int> > vec; vector<pair<pair<int, int>, int> > save; void fnct(int x1, int y1, int x2, int y2) { if (x1 < x2 && y1 > y2) { a = x1; b = y2; c = x1; d = y1; e = x2; f = y1; g = x2; h = y2; } else if (x1 > x2 && y1 < y2) { a = x2; b = y1; c = x2; d = y2; e = x1; f = y2; g = x1; h = y1; } else if (x1 < x2 && y1 < y2) { a = x1; b = y1; c = x1; d = y2; e = x2; f = y2; g = x2; h = y1; } else { a = x2; b = y2; c = x2; d = y1; e = x1; f = y1; g = x1; h = y2; } } double dis(double w, double z, double p, double q) { double n = w - p; double m = z - q; return sqrt(n * n + m * m); } bool check(double p, double q) { for (int i = 0; i < save.size(); i++) { double w = (double)(save[i].first.first); double z = (double)(save[i].first.second); double r = (double)(save[i].second); if (dis(w, z, p, q) <= r) return true; } return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; fnct(x1, y1, x2, y2); int n; cin >> n; for (int i = 0; i < n; i++) { int w, z, r; cin >> w >> z >> r; if (Map[to_string(w) + to_string(z) + to_string(r)] == false) save.push_back(make_pair(make_pair(w, z), r)); Map[to_string(w) + to_string(z) + to_string(r)] = true; } for (int i = c; i <= e; i++) vec.push_back(make_pair(i, d)); for (int i = a; i <= g; i++) vec.push_back(make_pair(i, b)); for (int i = d - 1; i > b; i--) vec.push_back(make_pair(a, i)); for (int i = f - 1; i > h; i--) vec.push_back(make_pair(e, i)); int ans = 0; for (int i = 0; i < vec.size(); i++) { double p = (double)(vec[i].first); double q = (double)(vec[i].second); if (check(p, q) == false) ans++; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, p, q, x = 0, y = 0, ans; cin >> n >> k; p = q = n; while (p % 2 == 0) { p /= 2; x++; } while (q % 5 == 0) { q /= 5; y++; } p = k - x; q = k - y; if (p < 0) p = 0; if (q < 0) q = 0; ans = n * pow(2, p) * pow(5, q); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int v; cin >> v; if (v == 2) { cout << 2 << endl; return 0; } cout << 1 << endl; return 0; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_CSR_CONTROLLER
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_csr_controller (
// To/From System
clock,
reset_n,
// To/From Avalon_MM csr slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_readdata,
// To/From Avalon_MM data slave interface
csr_status,
csr_control
);
parameter AVMM_CSR_DATA_WIDTH = 32;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
// To/From System
input clock;
input reset_n;
// To/From Avalon_MM csr slave interface
input avmm_read;
input avmm_write;
input avmm_addr;
input [AVMM_CSR_DATA_WIDTH-1:0] avmm_writedata;
output [AVMM_CSR_DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM data slave interface
input [9:0] csr_status;
output [31:0] csr_control;
reg [22:0] csr_sector_page_erase_addr_reg;
reg [4:0] csr_wp_mode;
reg [1:0] csr_erase_state;
reg csr_control_access;
reg reset_n_reg1;
reg reset_n_reg2;
wire reset_n_w;
wire is_idle;
wire is_erase_busy;
wire valid_csr_erase_addr;
wire valid_csr_write;
wire [31:0] csr_control_signal;
wire [22:0] csr_erase_addr;
assign is_idle = (csr_status[1:0] == STATUS_IDLE);
assign is_erase_busy = (csr_status[1:0] == STATUS_BUSY_ERASE);
assign csr_erase_addr = avmm_writedata[22:0];
assign valid_csr_erase_addr = (csr_erase_addr != {(23){1'b1}});
assign valid_csr_write = (avmm_write & avmm_addr);
assign csr_control_signal = { csr_erase_state, {(2){1'b1}}, csr_wp_mode, csr_sector_page_erase_addr_reg };
assign csr_control = csr_control_signal;
assign avmm_readdata = (csr_control_access) ? csr_control_signal : { {(22){1'b1}}, csr_status[9:0] };
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// Initiate register value for simulation. The initiate value can't be xx
initial begin
csr_sector_page_erase_addr_reg <= {(23){1'b1}};
csr_wp_mode = {(5){1'b1}};
csr_erase_state = ERASE_ST_IDLE;
csr_control_access = 1'b0;
reset_n_reg1 = 1'b0;
reset_n_reg2 = 1'b0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Avalon_MM read/write
// -------------------------------------------------------------------
always @ (posedge clock) begin
// synchronous reset
if (~reset_n_w) begin
// reset all register
csr_sector_page_erase_addr_reg <= {(23){1'b1}};
csr_wp_mode <= {(5){1'b1}};
csr_erase_state <= ERASE_ST_IDLE;
csr_control_access <= 1'b0;
end
else begin
// store read address
if (avmm_read) begin
csr_control_access <= avmm_addr;
end
// write control register
if (valid_csr_write) begin
csr_wp_mode <= avmm_writedata[27:23];
if (is_idle) begin
csr_sector_page_erase_addr_reg <= avmm_writedata[22:0];
end
end
// erase control fsm
case (csr_erase_state)
ERASE_ST_IDLE:
if (is_idle && valid_csr_write && valid_csr_erase_addr) begin
csr_erase_state <= ERASE_ST_PENDING;
end
ERASE_ST_PENDING:
if (is_erase_busy) begin
csr_erase_state <= ERASE_ST_BUSY;
end
ERASE_ST_BUSY:
if (is_idle) begin
csr_erase_state <= ERASE_ST_IDLE;
end
default: begin
csr_erase_state <= ERASE_ST_IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e7; vector<long long> primes; vector<long long> p(N, 1); signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, p, w, d; cin >> n >> p >> w >> d; long long l = 0, r = n; while (r - l > 10000000) { long long wins = (l + r) / 2; if (w * wins > p) { r = wins - 1; continue; } long long draws = (p - (wins * w)) / d; if (draws < 0) { l = wins + 1; continue; } long long points = w * wins + d * draws; cerr << wins << << draws << << points << n ; if (points == p) { if (wins + draws <= n) { cout << wins << << draws << << n - wins - draws << n ; return 0; } else { l = wins + 1; } } else { if (points < p) { l = wins + 1; } else { r = wins - 1; } } } for (long long wins = l; wins <= r; wins++) { if (w * wins > p) { continue; } long long draws = (p - (wins * w)) / d; if (draws < 0) { continue; } long long points = w * wins + d * draws; if (points == p) { if (wins + draws <= n) { cout << wins << << draws << << n - wins - draws << n ; return 0; } } } cout << -1 << n ; return 0; }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_idelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2008/12/23 14:26:00 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates the IDELAYCTRL primitive of the Virtex-5 device
// which continuously calibrates the IDELAY elements in the region in case of
// varying operating conditions. It takes a 200MHz clock as an input
//Reference:
//Revision History:
// Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
// on IOELAYCTRL primitive. Generate logic on IDELAYCTRL removed
// since tools will replicate idelactrl primitives.PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_idelay_ctrl #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter IODELAY_GRP = "IODELAY_MIG"
)
(
input clk200,
input rst200,
output idelay_ctrl_rdy
);
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY(idelay_ctrl_rdy),
.REFCLK(clk200),
.RST(rst200)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_adrgen #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [10:0] dx_c,
input [10:0] dy_c,
input [16:0] tx_c,
input [16:0] ty_c,
input [fml_depth-1-1:0] dst_fbuf, /* in 16-bit words */
input [10:0] dst_hres,
input [fml_depth-1-1:0] tex_fbuf, /* in 16-bit words */
input [10:0] tex_hres,
output pipe_stb_o,
input pipe_ack_i,
output [fml_depth-1-1:0] dadr, /* in 16-bit words */
output [fml_depth-1-1:0] tadra,
output [fml_depth-1-1:0] tadrb,
output [fml_depth-1-1:0] tadrc,
output [fml_depth-1-1:0] tadrd,
output [5:0] x_frac,
output [5:0] y_frac
);
/* Arithmetic pipeline. Enable signal is shared to ease usage of hard macros. */
wire pipe_en;
reg valid_1;
reg [fml_depth-1-1:0] dadr_1;
reg [fml_depth-1-1:0] tadra_1;
reg [5:0] x_frac_1;
reg [5:0] y_frac_1;
reg valid_2;
reg [fml_depth-1-1:0] dadr_2;
reg [fml_depth-1-1:0] tadra_2;
reg [5:0] x_frac_2;
reg [5:0] y_frac_2;
reg valid_3;
reg [fml_depth-1-1:0] dadr_3;
reg [fml_depth-1-1:0] tadra_3;
reg [fml_depth-1-1:0] tadrb_3;
reg [fml_depth-1-1:0] tadrc_3;
reg [fml_depth-1-1:0] tadrd_3;
reg [5:0] x_frac_3;
reg [5:0] y_frac_3;
always @(posedge sys_clk) begin
if(sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
end else if(pipe_en) begin
valid_1 <= pipe_stb_i;
dadr_1 <= dst_fbuf + dst_hres*dy_c + dx_c;
tadra_1 <= tex_fbuf + tex_hres*ty_c[16:6] + tx_c[16:6];
x_frac_1 <= tx_c[5:0];
y_frac_1 <= ty_c[5:0];
valid_2 <= valid_1;
dadr_2 <= dadr_1;
tadra_2 <= tadra_1;
x_frac_2 <= x_frac_1;
y_frac_2 <= y_frac_1;
valid_3 <= valid_2;
dadr_3 <= dadr_2;
tadra_3 <= tadra_2;
tadrb_3 <= tadra_2 + 1'd1;
tadrc_3 <= tadra_2 + tex_hres;
tadrd_3 <= tadra_2 + tex_hres + 1'd1;
x_frac_3 <= x_frac_2;
y_frac_3 <= y_frac_2;
end
end
/* Glue logic */
assign pipe_stb_o = valid_3;
assign dadr = dadr_3;
assign tadra = tadra_3;
assign tadrb = tadrb_3;
assign tadrc = tadrc_3;
assign tadrd = tadrd_3;
assign x_frac = x_frac_3;
assign y_frac = y_frac_3;
assign pipe_en = ~valid_3 | pipe_ack_i;
assign pipe_ack_o = ~valid_3 | pipe_ack_i;
assign busy = valid_1 | valid_2 | valid_3;
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module timer_1 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD3_TB_V
`define SKY130_FD_SC_HS__DLYGATE4SD3_TB_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlygate4sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__dlygate4sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD3_TB_V
|
#include <bits/stdc++.h> int main() { int T; scanf( %d , &T); while (T--) { int n; scanf( %d , &n); int sum = 0; for (int i = 0; i < n; i++) { int t; scanf( %d , &t); if (t <= 2048) { sum += t; } } printf( %s n , sum >= 2048 ? YES : NO ); } return 0; }
|
`timescale 1ns / 1ps
module InstructionMem(Pc,clk,OpCode,RS,RT,RD,IMM,JADDR,UsableInstruc,NEWPC);
input clk;
input [31:0] Pc;
output [4:0] OpCode;
output [4:0] RS, RT, RD;
output reg [31:0] UsableInstruc;
output [31:0] NEWPC;
output [16:0] IMM;
output [31:0] JADDR;
reg [0:0] ended;
reg [31:0] mem [0:127];
initial begin
ended=1'd0;
UsableInstruc =32'b11111000000000000000000000000000;
$readmemb("test.txt",mem);
/*
mem[0]=32'b11111000000000000000000000000000; //NOP
mem[1]=32'b00010000010000100000000000000001; //ADDI R1,R1,1
mem[2]=32'b00010000100001000000000000000011; //ADDI R2,R2,3
mem[3]=32'b11111000000000000000000000000000; //NOP
mem[4]=32'b11111000000000000000000000000000; //NOP
mem[5]=32'b11111000000000000000000000000000; //NOP
mem[6]=32'b00100000110000100010000000000000; //MLT R3,R1,R2
mem[7]=32'b11111000000000000000000000000000; //NOP
mem[8]=32'b11111000000000000000000000000000; //NOP
mem[9]=32'b11111000000000000000000000000000; //NOP
mem[10]=32'b01110000010001100000000000001111; //BEQ R1,R3,15
mem[11]=32'b11111000000000000000000000000000; //NOP
mem[12]=32'b11111000000000000000000000000000; //NOP
mem[13]=32'b11111000000000000000000000000000; //NOP
mem[14]=32'b10000000000000000000000000010010; //J 18
mem[15]=32'b10001001000001000001000000000000; //CMP R4,R2,R1
mem[16]=32'b11111000000000000000000000000000; //NOP
mem[17]=32'b11111000000000000000000000000000; //NOP
mem[18]=32'b11111000000000000000000000000000; //NOP
mem[19]=32'b11111111111111111111111111111111; //END*/
end
always @ (posedge clk) begin
if (ended) UsableInstruc<=32'b11111000000000000000000000000000;
else if (mem[Pc]==32'b11111111111111111111111111111111) ended=1'd1;
else UsableInstruc<=mem[Pc];
end
assign OpCode = UsableInstruc[31:27];
assign RS = UsableInstruc[21:17];
assign RT = UsableInstruc[16:12];
assign RD = UsableInstruc[26:22];
assign IMM = UsableInstruc[16:0];
assign JADDR[26:0] = UsableInstruc[26:0];
assign JADDR[31:27]=5'd0;
assign NEWPC = (OpCode==5'd16)? JADDR: Pc+1;
endmodule
|
#include <bits/stdc++.h> int main() { int n, k, i, j, swap; scanf( %d %d , &n, &k); int ara[n + 1][3]; for (i = 1; i <= n; i++) { scanf( %d , &ara[i][1]); ara[i][2] = i; } for (i = 1; i <= n; i++) { for (j = 1; j <= (n - i); j++) { if (ara[j][1] > ara[j + 1][1]) { swap = ara[j][1]; ara[j][1] = ara[j + 1][1]; ara[j + 1][1] = swap; swap = ara[j][2]; ara[j][2] = ara[j + 1][2]; ara[j + 1][2] = swap; } } } int sum = 0, p = 0; for (i = 1; i <= n; i++) { sum = sum + ara[i][1]; if (sum <= k) p++; else break; } if (p == 0) printf( 0 n ); else { printf( %d n , p); for (i = 1; i <= p; i++) printf( %d , ara[i][2]); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFXTP_PP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; double maxoo(double, double); int main() { int p1, p2, t1, t2; cin >> p1 >> p2 >> t1 >> t2; double p11, p12, p21, p22, misha, vasya; p11 = (3 * p1) / 10; p12 = (p1 - (p1 / 250) * t1); p21 = (3 * p2) / 10; p22 = p2 - (p2 / 250) * t2; misha = maxoo(p11, p12); vasya = maxoo(p21, p22); if (misha > vasya) cout << Misha ; else if (misha == vasya) cout << Tie ; else if (misha < vasya) cout << Vasya ; return 0; } double maxoo(double m, double n) { if (m >= n) return m; else return n; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_ms__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_ms__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_2_V
`define SKY130_FD_SC_HS__A32O_2_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_2_V
|
#include <bits/stdc++.h> const int N = 1000001; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; vector<pair<int, int>> a[n + 1]; int ans = 0; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; a[u].push_back(make_pair(v, i + 1)); a[v].push_back(make_pair(u, i + 1)); ans = max({ans, (int)a[u].size(), (int)a[v].size()}); } cout << ans << n ; int final[n], vis[n + 1]; memset(final, -1, sizeof final); memset(vis, 0, sizeof vis); queue<int> q; q.push(1); vis[1] = 1; while (!q.empty()) { int u = q.front(); q.pop(); map<int, int> d; for (auto [v, ind] : a[u]) { d[final[ind]] = 1; } int day = 1; for (auto [v, ind] : a[u]) { if (final[ind] == -1) { while (d[day]) { ++day; } final[ind] = day++; } if (vis[v] == 0) { vis[v] = 1; q.push(v); } } } vector<int> f1[ans + 1]; for (int i = 1; i < n; i++) { f1[final[i]].push_back(i); } for (int i = 1; i < ans + 1; i++) { cout << f1[i].size() << ; for (int e : f1[i]) { cout << e << ; } cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 123; const long long INF = (long long)1e18 + 123; const int inf = (int)1e9 + 123; const int MOD = (int)1e9 + 7; int n; int main() { cin >> n; if (n % 2 == 0) { cout << white n ; cout << 1 2 ; } else cout << black ; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_ccx_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_CLK
`endif
module bw_clk_cl_ccx_cmp(so ,grst_l ,gdbginit_l ,gclk ,dbginit_l ,
cluster_grst_l,rclk ,si ,se, se2,adbginit_l ,arst_l ,arst2_l ,
cluster_cken );
output so ;
input grst_l ;
input gdbginit_l ;
input [1:0] gclk ;
input si ;
output dbginit_l ;
output cluster_grst_l ;
output rclk ;
input se ;
input se2 ;
input adbginit_l ;
input arst_l ;
input arst2_l ;
input cluster_cken ;
wire net73 ;
wire net74 ;
wire net75 ;
wire so0_2_si1 ;
cluster_header_dup Iprimary (
.rclk (rclk ),
.so (so0_2_si1 ),
.dbginit_l (dbginit_l ),
.cluster_grst_l (cluster_grst_l ),
.si (si ),
.se (se ),
.adbginit_l (adbginit_l ),
.gdbginit_l (gdbginit_l ),
.arst_l (arst_l ),
.grst_l (grst_l ),
.cluster_cken (cluster_cken ),
.gclk (gclk[0] ) );
`ifdef FPGA_SYN_CLK
`else
cluster_header_dup Iseconadry (
.rclk (rclk ),
.so (so ),
.dbginit_l (net75 ),
.cluster_grst_l (net73 ),
.si (so0_2_si1),
.se (se2 ),
.adbginit_l (1'b1 ),
.gdbginit_l (1'b1 ),
.arst_l (arst2_l ),
.grst_l (1'b1 ),
.cluster_cken (cluster_cken ),
.gclk (gclk[1] ) );
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Dinic { struct Edge { int to, flow, next; }; vector<Edge> edges; vector<int> head, act, h; int S, D; void AddEdge(int from, int to, int f, int rev_f = 0) { edges.push_back({to, f, (int)edges.size()}); swap(edges.back().next, head[from]); edges.push_back({from, rev_f, (int)edges.size()}); swap(edges.back().next, head[to]); } bool bfs() { fill(h.begin(), h.end(), -1); h[S] = 0; vector<int> q = {S}; for (int it = 0; it < q.size() && h[D] == -1; it++) { int nod = q[it]; for (int i = head[nod]; i != -1; i = edges[i].next) if (edges[i].flow && h[edges[i].to] == -1) h[edges[i].to] = 1 + h[nod], q.push_back(edges[i].to); } return h[D] != -1; } int dfs(int nod, int flow) { if (flow == 0 || nod == D) return flow; while (act[nod] != -1) { Edge& e = edges[act[nod]]; int d; if (e.flow && h[e.to] == 1 + h[nod] && (d = dfs(e.to, min(flow, e.flow))) != 0) { e.flow -= d; edges[act[nod] ^ 1].flow += d; return d; } act[nod] = edges[act[nod]].next; } return 0; } int GetFlow() { int f = 0; while (bfs()) { act = head; int d; while ((d = dfs(S, 1e9)) != 0) f += d; } return f; } Dinic(int dim = 0, int s = 0, int d = 0) : head(dim + 1, -1), h(dim + 1), S(s), D(d) {} }; struct FlowWithMinRestrictions { struct Edge { int from, to, flowmin, flowmax, id; }; vector<Edge> edges; int S, D, n; void AddEdge(int from, int to, int flowmin, int flowmax) { edges.push_back({from, to, flowmin, flowmax, 0}); } vector<int> Solve(bool& feasible, int& flow) { feasible = 1; flow = 0; int news = n + 1, newd = n + 2; Dinic first_flow(n + 2, news, newd); first_flow.AddEdge(D, S, 1e9); int s_minime = 0; for (auto& i : edges) { if (i.flowmax < i.flowmin) { feasible = 0; return vector<int>(); } s_minime += i.flowmin; i.id = first_flow.edges.size(); first_flow.AddEdge(i.from, i.to, i.flowmax - i.flowmin); first_flow.AddEdge(news, i.to, i.flowmin); first_flow.AddEdge(i.from, newd, i.flowmin); } if (first_flow.GetFlow() != s_minime) { feasible = 0; return vector<int>(); } Dinic curent_flow(n, S, D); for (auto& i : edges) { int dif = i.flowmax - i.flowmin; int passed = dif - first_flow.edges[i.id].flow; int nid = curent_flow.edges.size(); curent_flow.AddEdge(i.from, i.to, first_flow.edges[i.id].flow, passed); i.id = nid; } curent_flow.GetFlow(); vector<int> ans(edges.size()); for (int i = 0; i < edges.size(); i++) { int cntflow = curent_flow.edges[edges[i].id ^ 1].flow + edges[i].flowmin; ans[i] = cntflow; if (edges[i].from == S) flow += cntflow; if (edges[i].to == S) flow -= cntflow; } return ans; } FlowWithMinRestrictions(int n = 0, int s = 0, int d = 0) : n(n), S(s), D(d) {} }; namespace ProbD { const int NMAX = 200010; map<int, int> nrmx, nrmy; FlowWithMinRestrictions flow; pair<int, int> shields[NMAX]; int idshield[NMAX]; int n, S, D; int difmax[NMAX]; int nr_on_poz[NMAX]; int cnt = 0; void normalize() { for (int i = 0; i < n; i++) nrmx[shields[i].first] = nrmy[shields[i].second] = 0; for (auto& i : nrmx) i.second = cnt++; for (auto& i : nrmy) i.second = cnt++; S = cnt++; D = cnt; fill(difmax, difmax + cnt + 1, 1e9); } void solve() { int r, b; int nrc; cin >> n >> nrc >> r >> b; for (int i = 0; i < n; i++) cin >> shields[i].first >> shields[i].second; normalize(); flow = FlowWithMinRestrictions(cnt, S, D); for (int i = 0; i < n; i++) { shields[i].first = nrmx[shields[i].first], shields[i].second = nrmy[shields[i].second]; idshield[i] = flow.edges.size(); nr_on_poz[shields[i].first]++, nr_on_poz[shields[i].second]++; flow.AddEdge(shields[i].first, shields[i].second, 0, 1); } while (nrc--) { int t, p, val; cin >> t >> p >> val; if (t == 1 && nrmx.find(p) != nrmx.end()) difmax[nrmx[p]] = min(difmax[nrmx[p]], val); else if (t == 2 && nrmy.find(p) != nrmy.end()) difmax[nrmy[p]] = min(difmax[nrmy[p]], val); } vector<pair<int, pair<int, int>>> verif; for (auto i : nrmx) { int nr = nr_on_poz[i.second]; int dmax = difmax[i.second]; int vmax = (dmax + nr) / 2; int vmin = max(0, (nr - dmax + 1) / 2); verif.push_back({(int)flow.edges.size(), {vmin, vmax}}); flow.AddEdge(S, i.second, vmin, vmax); } for (auto i : nrmy) { int nr = nr_on_poz[i.second]; int dmax = difmax[i.second]; int vmax = (dmax + nr) / 2; int vmin = max(0, (nr - dmax + 1) / 2); verif.push_back({(int)flow.edges.size(), {vmin, vmax}}); flow.AddEdge(i.second, D, vmin, vmax); } int f; bool posibil; auto ans = flow.Solve(posibil, f); if (!posibil) { cout << -1 n ; return; } for (auto i : verif) assert(ans[i.first] >= i.second.first && ans[i.first] <= i.second.second); cout << 1LL * f * min(r, b) + 1LL * (n - f) * max(r, b) << n ; string s = rb ; if (r < b) s = br ; for (int i = 0; i < n; i++) cout << s[ans[idshield[i]]]; cout << n ; } } // namespace ProbD int main() { ios_base::sync_with_stdio(0); ProbD::solve(); return 0; FILE* in = fopen( cuplaj.in , r ); int n, m; fscanf(in, %d%d , &n, &m); FlowWithMinRestrictions flow(n, 1, n); while (m--) { int a, b, c, d; fscanf(in, %d%d%d%d , &a, &b, &c, &d); flow.AddEdge(a, b, c, d); } bool feasible; int f; auto ans = flow.Solve(feasible, f); ofstream out( flux.out ); out << feasible << n << f << n ; for (auto i : ans) out << i << ; return 0; }
|
#include <bits/stdc++.h> int t, n, a[200010], tot, cnt[200010]; int f[200010]; int find_f(int x) { return f[x] ^ x ? f[x] = find_f(f[x]) : x; } int main() { scanf( %d , &t); for (int _ = 0; _ < t; ++_) { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , a + i); for (int i = 1; i <= n; ++i) f[i] = i, cnt[i] = 0; for (int i = 1; i <= n; ++i) if (find_f(i) != find_f(a[i])) f[find_f(i)] = find_f(a[i]); for (int i = 1; i <= n; ++i) ++cnt[find_f(i)]; for (int i = 1; i <= n; ++i) printf( %d , cnt[find_f(i)]); puts( ); } return 0; }
|
/****************************************
Adder Unit
- 32bit Adder
Make : 2010/12/07
Update :
****************************************/
`default_nettype none
`include "core.h"
module adder_n
#(
parameter N = 32
)(
//iDATA
input [N-1:0] iDATA_0,
input [N-1:0] iDATA_1,
input [4:0] iADDER_CMD,
//oDATA
output [N-1:0] oDATA,
output oSF,
output oOF,
output oCF,
output oPF,
output oZF
);
/****************************************
This -> Output
****************************************/
assign {oZF, oPF, oOF, oSF, oCF, oDATA} = func_adder_execution(iADDER_CMD, iDATA_0, iDATA_1);
//ZF, PF, OF, SF, CF, Data
function [36:0] func_adder_execution;
input [4:0] func_cmd;
input [31:0] func_data0;
input [31:0] func_data1;
reg [32:0] func_pri_op0;
reg [32:0] func_pri_op1;
reg [32:0] func_pri_out;
begin
case(func_cmd)
`EXE_ADDER_ADD :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = func_pri_op0 + func_pri_op1;//func_data0 + func_data1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_op0[31] == func_pri_op1[31] && func_pri_op0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_SUB :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = ({1'b0, ~func_data1} + 32'h1);
func_pri_out = func_pri_op0 + func_pri_op1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0],( func_data0[31] != func_data1[31] && func_data0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_NEG:
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = ~func_data0 + {{N-1{1'b0}}, 1'b1};
func_adder_execution = {5'h0, func_pri_out[31:0]};//{(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_out[32] ^ func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_COUT :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = func_pri_op0 + func_pri_op1;//func_data0 + func_data1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_op0[31] == func_pri_op1[31] && func_pri_op0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], 31'h0 , func_pri_out[32]};
end
`EXE_ADDER_SEXT8 :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {1'b0, {24{func_data1[7]}}, func_data1[7:0]};
func_adder_execution = {5'h0, func_pri_out[31:0]};//{(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_out[32] ^ func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_SEXT16 :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {1'b0, {16{func_data1[15]}}, func_data1[15:0]};
func_adder_execution = {5'h0, func_pri_out[31:0]};//{(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_out[32] ^ func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
default:
begin/*
//$display("[ERROR] : adder_n.v func_addder_execution Error");
func_pri_out = {33{1'b0}};
func_adder_execution = {37{1'b0}};
*/
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {33{1'b0}};
func_adder_execution = {37{1'h0}};
end
endcase
end
endfunction
endmodule
`default_nettype wire
|
// megafunction wizard: %ALTSYNCRAM%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: altera_dpram_16x32.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 216 03/06/2006 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_dpram_16x32 (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken1 (1'b1),
.clocken0 (1'b1),
.q_a (),
.data_b ({32{1'b1}}),
.rden_b (1'b1),
.wren_b (1'b0),
.byteena_b (1'b1),
.addressstall_a (1'b0),
.byteena_a (1'b1),
.addressstall_b (1'b0),
.clock1 (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0]
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32_bb.v TRUE
|
#include <bits/stdc++.h> using namespace std; int main() { long long sum = 0; int d[1000000 + 1] = {0}; for (int i = 1; i <= 1000000; i++) { for (int j = i; j <= 1000000; j += i) { d[j]++; } } int a, b, c; cin >> a >> b >> c; for (auto(i) = (1); (i) < (a + 1); ++(i)) for (auto(j) = (1); (j) < (b + 1); ++(j)) for (auto(k) = (1); (k) < (c + 1); ++(k)) sum = (sum + d[i * j * k]) % 1073741824; cout << sum % 1073741824; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, temp, prev, A[100005]; bool f = false; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> A[i]; } for (int i = 0; i < k; i++) { cin >> temp; } if (k == 1) { if (n == 1) { cout << Yes ; f = true; } else { int prevMax; for (int i = 0; i < n; i++) { if (A[i] == 0) { A[i] = temp; } if (i != 0) { if (A[i] <= prevMax) { cout << Yes ; f = true; break; } prevMax = A[i]; } else { prevMax = A[0]; } } } } else { cout << Yes ; f = true; } if (!f) { cout << No ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 512345, lgN = 20, rootN = 1123; const double eps = 1e-18; int r[N], w[N]; vector<double> positive, negative; double p[N]; int main() { int n, c, d; cin >> n >> c >> d; for (int i = 1; i <= n; ++i) { cin >> r[i] >> w[i]; r[i] -= c, w[i] -= d; p[i] = (((double)r[i]) / (double)w[i]); } for (int i = 1; i <= n; ++i) { double x = (((double)r[i]) / (double)w[i]); if (w[i] > 0) { positive.push_back(x); } else if (w[i] < 0) { negative.push_back(x); } } sort(positive.begin(), positive.end()); sort(negative.begin(), negative.end()); long long first = 0, second = 0; for (int i = 0; i < positive.size(); ++i) { first += (lower_bound(negative.begin(), negative.end(), positive[i]) - negative.begin()); } for (int i = 0; i < negative.size(); ++i) { second += (lower_bound(positive.begin(), positive.end(), negative[i]) - positive.begin()); } long long ans = 0; for (int i = 1; i <= n; ++i) { if (w[i] > 0) { ans += ((long long)(negative.end() - upper_bound(negative.begin(), negative.end(), p[i]))) * (lower_bound(negative.begin(), negative.end(), p[i]) - negative.begin()); } else if (w[i] < 0) { ans += ((long long)(positive.end() - upper_bound(positive.begin(), positive.end(), p[i]))) * (lower_bound(positive.begin(), positive.end(), p[i]) - positive.begin()); } else if (w[i] == 0) { if (r[i] < 0) ans += first; else ans += second; } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long int gcd(long long int a, long long int b) { return b ? gcd(b, a % b) : a; } inline long long int fast_pow(long long int a, long long int b, long long int mod) { long long int res = 1; a %= mod; while (b > 0) { if (b & 1) res = res * a % mod; b >>= 1; a = a * a % mod; } return res; } inline bool isPrime(long long int a) { for (long long int i = 2; i * i <= a; i++) if (a % i == 0) return 0; return 1; } int n, a, b, c, ans, cnt, anss = INT_MAX; string person1, likes, person2, temp; pair<string, string> arr[42]; map<string, int> nametoidx; vector<string> per; int main() { ios::sync_with_stdio(0); cin.tie(NULL); nametoidx[ Anka ] = 0; nametoidx[ Chapay ] = 1; nametoidx[ Cleo ] = 2; nametoidx[ Troll ] = 3; nametoidx[ Dracul ] = 4; nametoidx[ Snowy ] = 5; nametoidx[ Hexadecimal ] = 6; cin >> n; for (int i = 0; i < n; i++) { cin >> person1 >> likes >> person2; arr[i] = make_pair(person1, person2); } cin >> a >> b >> c; for (int i = 0; i < 5; i++) { for (int j = 0; j < 5 - i; j++) { int t = max(a / (i + 1), max(b / (j + 1), c / (5 - i - j))) - min(a / (i + 1), min(b / (j + 1), c / (5 - i - j))); temp = ; if (anss > t) { per.clear(); anss = t; for (int k = 0; k < i + 1; k++) temp += 0 ; for (int k = 0; k < j + 1; k++) temp += 1 ; for (int k = 0; k < 5 - i - j; k++) temp += 2 ; per.push_back(temp); } else if (anss == t) { for (int k = 0; k < i + 1; k++) temp += 0 ; for (int k = 0; k < j + 1; k++) temp += 1 ; for (int k = 0; k < 5 - i - j; k++) temp += 2 ; per.push_back(temp); } } } cout << anss << ; for (int j = 0; j < per.size(); j++) { temp = per[j]; do { cnt = 0; for (int i = 0; i < n; i++) { if (temp[nametoidx[arr[i].first]] == temp[nametoidx[arr[i].second]]) cnt++; } ans = max(ans, cnt); } while (next_permutation(temp.begin(), temp.end())); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using uint64 = unsigned long long; const int N = 100, seed = 65537; char s[N]; std::unordered_map<uint64, int> words; std::unordered_set<uint64> mark; int dfs(int d, uint64 hs) { if (s[d] == 0) { if (mark.count(hs)) return 0; mark.insert(hs); auto it = words.find(hs); if (it == words.end()) return 0; else return it->second; } int ret = 0; if (s[d] == ? ) { ret += dfs(d + 1, hs); for (char c = a ; c <= e ; ++c) { ret += dfs(d + 1, hs * seed + c); } } else { ret += dfs(d + 1, hs * seed + s[d]); } return ret; } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %s , s); uint64 hs = 0; for (int j = 0; s[j]; ++j) { hs = hs * seed + s[j]; } words[hs] += 1; } for (int i = 0; i < m; ++i) { scanf( %s , s); mark.clear(); printf( %d n , dfs(0, 0)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool debug = 0; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; long long ln, lk, lm; char s[100005]; void fmain() { scanf( %d%d%d , &n, &m, &k); scanf( %s , s + 1); for (int ty, l, r, x, i = 0; i < m + k; i++) { scanf( %d%d%d%d , &ty, &l, &r, &x); if (ty == 1) { memset(s + l, 0 + x, r - l + 1); } else { bool fg = memcmp(s + l, s + l + x, r - x - l + 1) == 0; puts(fg ? YES : NO ); } } } int main() { fmain(); return 0; }
|
module dv_top ();
parameter DW = 64; // Memory width
parameter MAW = 15; // Memory address width
//regs/wires
reg [1023:0] filename;
wire [DW-1:0] ext_packet;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire nreset; // From dv_ctrl of dv_ctrl.v
wire start; // From dv_ctrl of dv_ctrl.v
wire stim_access; // From stimulus of stimulus.v
wire stim_done; // From stimulus of stimulus.v
wire [DW-1:0] stim_packet; // From stimulus of stimulus.v
wire vdd; // From dv_ctrl of dv_ctrl.v
wire vss; // From dv_ctrl of dv_ctrl.v
// End of automatics
assign test_done = 1'b1;
assign dut_active = 1'b1;
//Reset and clocks
dv_ctrl dv_ctrl(.clk1 (ext_clk),
.clk2 (dut_clk),
/*AUTOINST*/
// Outputs
.nreset (nreset),
.start (start),
.vdd (vdd),
.vss (vss),
// Inputs
.dut_active (dut_active),
.stim_done (stim_done),
.test_done (test_done));
//Stimulus
assign ext_start = start;
assign ext_access = 'b0;
assign ext_packet = 'b0;
assign dut_wait = 'b0;
stimulus #(.DW(DW),.MAW(MAW),.HEXFILE("firmware.hex"))
stimulus(
/*AUTOINST*/
// Outputs
.stim_access (stim_access),
.stim_packet (stim_packet[DW-1:0]),
.stim_done (stim_done),
// Inputs
.nreset (nreset),
.ext_start (ext_start),
.ext_clk (ext_clk),
.ext_access (ext_access),
.ext_packet (ext_packet[DW-1:0]),
.dut_clk (dut_clk),
.dut_wait (dut_wait));
endmodule // unmatched end(function|task|module|primitive|interface|package|class|clocking)
|
#include <bits/stdc++.h> using namespace std; const int M = 100100; long long mabs(long long x) { return x < 0 ? -x : x; } int n, m; long long a[M], h[M]; long long q[M], c[M], qf, qs, sum; void read() { cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> h[i]; } for (int i = 0; i + 1 < n; ++i) { a[i] = mabs(h[i + 1] - h[i]); } } void ini() { qf = qs = 0; sum = 0; } void pop() { --qf; sum -= q[qf] * c[qf]; } void push(long long x, long long cnt) { assert(qs == qf || q[qf - 1] > x); sum += x * cnt; q[qf] = x; c[qf] = cnt; ++qf; } void add(long long x) { long long cur = 1; while (qs < qf && q[qf - 1] <= x) { pop(); cur += c[qf]; } push(x, cur); } long long get(long long l, long long r) { long long ans = 0; ini(); for (int i = l; i < r; ++i) { add(a[i]); ans += sum; } return ans; } void kill() { for (int i = 0; i < m; ++i) { int l, r; cin >> l >> r; --l; --r; cout << get(l, r) << n ; } } int main() { ios_base::sync_with_stdio(false); cout.precision(13); cout << fixed; read(); kill(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e2 + 10; const int maxm = 22; const int mod = 1e9 + 7; vector<int> G[maxn]; int dp[maxn][maxn][maxm]; int sum[maxn][maxn][maxm]; int n, k; void init() { for (int i = 0; i <= n; ++i) G[i].clear(); } void addEdge(int a, int b) { G[a].push_back(b); G[b].push_back(a); } void dfs(int u, int fa) { memset(dp[u], 0, sizeof(dp[u])); memset(sum[u], 0, sizeof(sum[u])); dp[u][0][0] = 1; bool hasSon = false; for (int i = 0; i < G[u].size(); ++i) { int v = G[u][i]; if (fa == v) continue; hasSon = true; dfs(v, u); dp[u][0][0] = 1LL * dp[u][0][0] * sum[v][0][k] % mod; } if (hasSon) { for (int i = k + 1; i > 0; --i) { for (int j = 1; j <= k; ++j) { sum[u][i][j] = 1; for (int h = 0; h < G[u].size(); ++h) { int v = G[u][h]; if (v == fa) continue; sum[u][i][j] = 1LL * sum[u][i][j] * sum[v][i - 1][j - 1] % mod; } dp[u][i][j] = (sum[u][i][j] - sum[u][i + 1][j] - sum[u][i][j - 1] + sum[u][i + 1][j - 1]) % mod; if (dp[u][i][j] < 0) dp[u][i][j] += mod; if (i + j - 1 <= k) { dp[u][i][0] = (dp[u][i][0] + dp[u][i][j]) % mod; dp[u][i][j] = 0; } } } } else { dp[u][k][1] = 1; } for (int i = k + 1; i >= 0; --i) { for (int j = 0; j <= k; ++j) { sum[u][i][j] = dp[u][i][j]; if (i + 1 <= k + 1) (sum[u][i][j] += sum[u][i + 1][j]) %= mod; if (j) (sum[u][i][j] += sum[u][i][j - 1]) %= mod; if (i + 1 <= k + 1 && j) (sum[u][i][j] -= sum[u][i + 1][j - 1] - mod) %= mod; } } } void debug() { for (int i = 1; i <= n; ++i) { for (int j = 0; j <= k; ++j) { for (int h = 0; h <= k; ++h) { printf( p[%d][%d][%d] = %d , i, j, h, sum[i][j][h]); } puts( ); } puts( ); } } int main() { while (~scanf( %d%d , &n, &k)) { init(); for (int i = 0; i < n - 1; ++i) { int a, b; scanf( %d%d , &a, &b); addEdge(a, b); } dfs(1, 0); printf( %d n , sum[1][0][0]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[100500]; vector<long long> pfx[100500], vtx[100500]; long long proc(long long x, long long sum) { int n = vtx[x].size(); int mid = n / 2; long long res = sum; for (int i = mid, _n = n; i < _n; i++) res += vtx[x][i] - vtx[x][mid]; for (int i = 0, _n = mid; i < _n; i++) res += vtx[x][mid] - vtx[x][i]; for (int i = 0, _n = n; i < _n; i++) res -= abs(x - vtx[x][i]); return res; } int main() { int n, m; long long sum = 0LL; scanf( %d %d , &n, &m); for (int i = 0, _n = m; i < _n; i++) scanf( %I64d , a + i); for (int i = 1, _n = m; i < _n; i++) { if (a[i] == a[i - 1]) continue; vtx[a[i]].push_back(a[i - 1]); vtx[a[i - 1]].push_back(a[i]); sum += abs(a[i] - a[i - 1]); } for (int i = 1, _n = n + 1; i < _n; i++) sort(vtx[i].begin(), vtx[i].end()); long long ans = sum; for (int i = 1, _n = n + 1; i < _n; i++) ans = min(ans, proc(i, sum)); printf( %I64d n , ans); return 0; }
|
#pragma GCC optimize( Ofast , unroll-loops , no-stack-protector ) #include <bits/stdc++.h> using namespace std; #define all(a) (a).begin(), (a).end() #define sz(a) (int)(a).size() using ll = long long; using ld = long double; // using ld = __float128; using pii = pair<int, int>; using pll = pair<ll, ll>; using uint = unsigned int; using ull = unsigned long long; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); default_random_engine generator; void solve(); int main() { #ifdef LOCAL freopen( input.txt , r , stdin); // freopen( output.txt , w , stdout); #endif ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout << setprecision(10) << fixed; cerr << setprecision(10) << fixed; int tests = 1; // cin >> tests; for (int test = 1; test <= tests; ++test) { // cout << Case # << test << : ; solve(); } #ifdef LOCAL cerr << Time: << double(clock()) / CLOCKS_PER_SEC << endl; #endif } // ----------------------------------------------------------------- const int MAXN = 200200; vector<int> g[MAXN]; int w[MAXN]; vector<int> arr; int dfs(int v, int p = -1) { arr.push_back(v); w[v] = 1; for (int u : g[v]) { if (u == p) { continue; } w[v] += dfs(u, v); } return w[v]; } vector<int> f; bool check(int root, int k) { arr.clear(); dfs(root); if (sz(arr) != f[k]) { return false; } if (k <= 1) { return true; } for (int v : arr) { if (w[v] == f[k - 1] || w[v] == f[k - 2]) { int u; for (int uu : g[v]) { if (w[uu] > w[v]) { u = uu; } } for (int i = 0; i < sz(g[u]); ++i) { if (g[u][i] == v) { swap(g[u][i], g[u].back()); g[u].pop_back(); break; } } for (int i = 0; i < sz(g[v]); ++i) { if (g[v][i] == u) { swap(g[v][i], g[v].back()); g[v].pop_back(); break; } } if (w[v] == f[k - 1]) { if (!check(v, k - 1)) { return false; } if (!check(u, k - 2)) { return false; } } else { if (!check(v, k - 2)) { return false; } if (!check(u, k - 1)) { return false; } } return true; } } return false; } void solve() { int n; cin >> n; int k = 2; f = {1, 1}; for (; f.back() < n; ++k) { f.push_back(f[k - 2] + f[k - 1]); } for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; --u; --v; g[u].push_back(v); g[v].push_back(u); } cout << (check(0, sz(f) - 1) ? YES n : NO n ); }
|
#include <bits/stdc++.h> using namespace std; int a[400100]; int b[400100]; int main() { int n; cin >> n; int k = 0; for (int i = 1; i <= n; i++) { int l; cin >> l; if (l == 0) { k = 1; } else { if (k == 1) a[i - 1] = l; else a[i] = l; } } k = 0; for (int i = 1; i <= n; i++) { int l; cin >> l; if (l == 0) { k = 1; } else { if (k == 1) b[i - 1] = l; else b[i] = l; } } int uk = n; int uk1 = 1; for (int i = 1; i < n; i++) { if (b[i] != a[1]) { b[uk] = b[i]; uk++; } else { uk1 = i; break; } } for (int i = 1; i < n; i++) { if (a[i] != b[uk1]) { cout << NO ; exit(0); } uk1++; } cout << YES ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, l, r; cin >> n >> l >> r; long long int dp[n][3]; long long int a = r / 3 - (l - 1) / 3; long long int b = (r + 2) / 3 - (l + 1) / 3; long long int c = (r + 1) / 3 - l / 3; dp[0][0] = r / 3 - (l - 1) / 3; dp[0][1] = (r + 2) / 3 - (l + 1) / 3; dp[0][2] = (r + 1) / 3 - l / 3; for (int i = 1; i < n; i++) { dp[i][0] = (dp[i - 1][0] * a + dp[i - 1][1] * c + dp[i - 1][2] * b) % 1000000007; dp[i][1] = (dp[i - 1][0] * b + dp[i - 1][1] * a + dp[i - 1][2] * c) % 1000000007; dp[i][2] = (dp[i - 1][0] * c + dp[i - 1][1] * b + dp[i - 1][2] * a) % 1000000007; } cout << dp[n - 1][0]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[1010][1010]; vector<int> arr; int m; int solve(int idx, int mod) { if (idx == (int)arr.size()) return (mod == 0); else if (dp[idx][mod] != -1) return dp[idx][mod]; int ret = solve(idx + 1, mod); if (ret) return (dp[idx][mod] = ret); ret = solve(idx + 1, (mod + arr[idx]) % m); return (dp[idx][mod] = ret); } int main() { ios_base::sync_with_stdio(false); for (int i = (int)(0); i < (int)(1010); i++) for (int j = (int)(0); j < (int)(1010); j++) dp[i][j] = -1; int n; cin >> n >> m; arr.resize(n); for (int i = (int)(0); i < (int)(n); i++) cin >> arr[i]; if (n > m) cout << YES << endl; else { int yes = 0; for (int i = (int)(0); i < (int)(n); i++) yes |= solve(i + 1, arr[i] % m); if (yes) cout << YES << endl; else cout << NO << endl; } return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block2.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block2
// Source Path: controllerHdl/Field_Oriented_Control/MATLAB Function
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block2
(
CLK_IN,
reset,
enb_1_2000_0,
cMode,
index,
reset_1
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input [1:0] cMode; // ufix2
output [1:0] index; // ufix2
output reset_1;
parameter [1:0] controllerModeEnum_VelocityControl = 2; // ufix2
parameter [1:0] controllerModeEnum_OpenLoopVelocityControl = 3; // ufix2
reg [1:0] index_1; // ufix2
reg reset_2;
reg [1:0] index_n1; // ufix2
reg [1:0] index_n1_next; // ufix2
reg [1:0] index_2; // ufix2
always @(posedge CLK_IN)
begin : MATLAB_Function_process
if (reset == 1'b1) begin
index_n1 <= 2'b10;
end
else if (enb_1_2000_0) begin
index_n1 <= index_n1_next;
end
end
always @(cMode, index_n1) begin
//MATLAB Function 'Field_Oriented_Control/MATLAB Function': '<S14>:1'
//.
if (cMode == controllerModeEnum_OpenLoopVelocityControl) begin
//'<S14>:1:17'
index_2 = 2'b00;
end
else if (cMode == controllerModeEnum_VelocityControl) begin
//'<S14>:1:19'
index_2 = 2'b01;
end
else begin
//'<S14>:1:21'
index_2 = 2'b10;
end
if (index_2 != index_n1) begin
//'<S14>:1:25'
reset_2 = 1'b1;
end
else begin
//'<S14>:1:27'
reset_2 = 1'b0;
end
//'<S14>:1:29'
index_n1_next = index_2;
index_1 = index_2;
end
assign index = index_1;
assign reset_1 = reset_2;
endmodule // controllerHdl_MATLAB_Function_block2
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A41OI_PP_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long int max(long long int a, long long int b) { if (a > b) return a; else return b; } long long int min(long long int a, long long int b) { if (a < b) return a; else return b; } const int dx[4] = {-1, 1, 0, 0}; const int dy[4] = {0, 0, -1, 1}; int XX[] = {-1, -1, -1, 0, 0, 1, 1, 1}; int YY[] = {-1, 0, 1, -1, 1, -1, 0, 1}; vector<pair<long long int, long long int> > edges; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int n, m, i, j, k, l, r, ind, c, d, x; cin >> n >> k; j = k + 1; long long int z = n / k; long long int count = 0, ans = 2 * z; j = 2; vector<long long int> vec, vec2; for (i = 1; i <= k; i++) { count = 0; while (count < z && j <= n) { if (count == 0) edges.push_back(make_pair(1, j)); else edges.push_back(make_pair(j - 1, j)); j++; count++; } vec2.push_back(count); vec.push_back(j - 1); } if (j == n + 1) { sort(vec2.begin(), vec2.end()); long long int sum = vec2[vec2.size() - 1]; if (vec2.size() >= 2) sum += vec2[vec2.size() - 2]; cout << sum << n ; for (i = 0; i < edges.size(); i++) { cout << edges[i].first << << edges[i].second << n ; } return 0; } long long int flag = 0; for (i = 0; i < vec.size(); i++) { if (j == n + 1) break; edges.push_back(make_pair(vec[i], j)); j++; flag++; } if (flag == 1) ans++; else if (flag > 1) ans += 2; cout << ans << n ; for (i = 0; i < edges.size(); i++) { cout << edges[i].first << << edges[i].second << n ; } }
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
input [4:0] sa1_bmaps_sbm,
input sa1_dma_cc1_en,
input [11:0] sa1_xxb,
input [3:0] sa1_xxb_en,
// output srtc_enable,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable,
output sa1_enable
);
parameter [2:0]
//FEAT_DSPX = 0,
//FEAT_ST0010 = 1,
//FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
// Static Inputs
reg [23:0] ROM_MASK_r = 0;
reg [23:0] SAVERAM_MASK_r = 0;
reg iram_battery_r = 0;
always @(posedge CLK) begin
ROM_MASK_r <= ROM_MASK;
SAVERAM_MASK_r <= SAVERAM_MASK;
iram_battery_r <= ~SAVERAM_MASK_r[1] & SAVERAM_MASK_r[0];
end
wire [23:0] SRAM_SNES_ADDR;
wire [2:0] xxb[3:0];
assign {xxb[3], xxb[2], xxb[1], xxb[0]} = sa1_xxb;
wire [3:0] xxb_en = sa1_xxb_en;
assign IS_ROM = ~SNES_ROMSEL;
assign IS_SAVERAM = SAVERAM_MASK_r[0]
& ( // 40-4F:0000-FFFF
( ~SNES_ADDR[23]
& SNES_ADDR[22]
& ~SNES_ADDR[21]
& ~SNES_ADDR[20]
& ~sa1_dma_cc1_en
)
// 00-3F/80-BF:6000-7FFF
| ( ~SNES_ADDR[22]
& ~SNES_ADDR[15]
& &SNES_ADDR[14:13]
)
| ( iram_battery_r
& ~SNES_ADDR[22]
& ~SNES_ADDR[15]
& ~SNES_ADDR[14]
& SNES_ADDR[13]
& SNES_ADDR[12]
& ~SNES_ADDR[11]
)
);
assign IS_WRITABLE = IS_SAVERAM;
// TODO: add programmable address map
assign SRAM_SNES_ADDR = (IS_SAVERAM
// 40-4F:0000-FFFF or 00-3F/80-BF:6000-7FFF (first 8K mirror). Mask handles mirroring. 60 is sa1-only
? (24'hE00000 + (iram_battery_r ? SNES_ADDR[10:0] : ((SNES_ADDR[22] ? SNES_ADDR[19:0] : {sa1_bmaps_sbm,SNES_ADDR[12:0]}) & SAVERAM_MASK_r)))
// C0-FF:0000-FFFF or 00-3F/80-BF:8000-FFFF
: ((SNES_ADDR[22] ? {1'b0, xxb[SNES_ADDR[21:20]], SNES_ADDR[19:0]} : {1'b0, (xxb_en[{SNES_ADDR[23],SNES_ADDR[21]}] ? xxb[{SNES_ADDR[23],SNES_ADDR[21]}] : {1'b0,SNES_ADDR[23],SNES_ADDR[21]}), SNES_ADDR[20:16], SNES_ADDR[14:0]}) & ROM_MASK_r)
);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: Reset_Delay
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2,oRST_3,oRST_4);
input iCLK;
input iRST;
output reg oRST_0;
output reg oRST_1;
output reg oRST_2;
output reg oRST_3;
output reg oRST_4;
reg [31:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
Cont <= 0;
oRST_0 <= 0;
oRST_1 <= 0;
oRST_2 <= 0;
oRST_3 <= 0;
oRST_4 <= 0;
end
else
begin
if(Cont!=32'h01FFFFFF)
Cont <= Cont+1;
if(Cont>=32'h001FFFFF)
oRST_0 <= 1;
if(Cont>=32'h002FFFFF)
oRST_1 <= 1;
if(Cont>=32'h011FFFFF)
oRST_2 <= 1;
if(Cont>=32'h016FFFFF)
oRST_3 <= 1;
if(Cont>=32'h01FFFFFF)
oRST_4 <= 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_no_pg/sky130_fd_sc_hs__u_df_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrbp (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; for (int i = 0; i < a.size(); i++) { a[i] = tolower(a[i]); b[i] = tolower(b[i]); } if (a.compare(b) == 0) cout << 0 << n ; else { for (int i = 0; i < a.size(); i++) { if (a[i] < b[i]) { cout << -1 << n ; break; } if (a[i] > b[i]) { cout << 1 << n ; break; } } } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nco_sine_lut_V_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 16;
parameter AWIDTH = 12;
parameter MEM_SIZE = 4096;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./nco_sine_lut_V_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module nco_sine_lut_V(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
nco_sine_lut_V_rom nco_sine_lut_V_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long r; vector<long long> a; cin >> r; for (int i = 0; i < r; i++) { long long aux; cin >> aux; a.push_back(aux); } a.push_back(a[0]); long long n = 0, m = 1; long long min = abs(a[0] - a[1]); for (int i = 1; i < r; i++) { if (abs(a[i] - a[i + 1]) < min) { n = i % r; m = (i + 1) % r; min = abs(a[i] - a[i + 1]); } } cout << n + 1 << << m + 1; return 0; }
|
module Hipercubo (
input RST, // Reset maestro
input CLK, // Reloj maestro
input[3:0] A00,A01, // Coef Matriz A
input[3:0] A10,A11,
input[3:0] B00,B01, // Coef Matriz B
input[3:0] B10,B11,
input[7:0] ENa, // Habilitaciones Ra
input[7:0] ENb, // Habilitaciones Rb
input[7:0] ENc, // Habilitaciones Rc
input[7:0] SEL, // Selectores Mux
output[7:0] MTX00,MTX01,// Salida
output[7:0] MTX10,MTX11
);
wire[3:0] Ra000,Ra001,Ra010,Ra011;
wire[3:0] Ra100,Ra101,Ra110,Ra111;
wire[3:0] Rb000,Rb001,Rb010,Rb011;
wire[3:0] Rb100,Rb101,Rb110,Rb111;
wire[7:0] Rc000,Rc001,Rc010,Rc011;
wire[7:0] Rc100,Rc101,Rc110,Rc111;
wire[3:0] Ya001,Ya011,Ya100,Ya110;
wire[3:0] Yb010,Yb011,Yb100,Yb101;
wire[7:0] M000,M001,M010,M011;
wire[7:0] M100,M101,M110,M111;
Registro_4b RA000(RST,CLK,ENa[0],A00,Ra000);
Registro_4b RB000(RST,CLK,ENb[0],B00,Rb000);
Multiplicador_4x4 M1(Ra000,Rb000,M000);
Registro_8b RC000(RST,CLK,ENc[0],M000,Rc000);
Mux4_2_1 Mux1(A01,Ra000,SEL[0],Ya001);
Registro_4b RA001(RST,CLK,ENa[1],Ya001,Ra001);
Registro_4b RB001(RST,CLK,ENb[1],B01,Rb001);
Multiplicador_4x4 M2(Ra001,Rb001,M001);
Registro_8b RC001(RST,CLK,ENc[1],M001,Rc001);
Registro_4b RA010(RST,CLK,ENa[2],A10,Ra010);
Mux4_2_1 Mux2(B10,Rb000,SEL[1],Yb010);
Registro_4b RB010(RST,CLK,ENb[2],Yb010,Rb010);
Multiplicador_4x4 M3(Ra010,Rb010,M010);
Registro_8b RC010(RST,CLK,ENc[2],M010,Rc010);
Mux4_2_1 Mux3(A11,Ra010,SEL[2],Ya011);
Registro_4b RA011(RST,CLK,ENa[3],Ya011,Ra011);
Mux4_2_1 Mux4(B11,Rb001,SEL[3],Yb011);
Registro_4b RB011(RST,CLK,ENb[3],Yb011,Rb011);
Multiplicador_4x4 M4(Ra011,Rb011,M011);
Registro_8b RC011(RST,CLK,ENc[3],M011,Rc011);
Mux4_2_1 Mux5(Ra000,Ra101,SEL[4],Ya100);
Registro_4b RA100(RST,CLK,ENa[4],Ya100,Ra100);
Mux4_2_1 Mux6(Rb000,Rb110,SEL[5],Yb100);
Registro_4b RB100(RST,CLK,ENb[4],Yb100,Rb100);
Multiplicador_4x4 M5(Ra100,Rb100,M100);
Registro_8b RC100(RST,CLK,ENc[4],M100,Rc100);
Registro_4b RA101(RST,CLK,ENa[5],Ra001,Ra101);
Mux4_2_1 Mux7(Rb001,Rb111,SEL[6],Yb101);
Registro_4b RB101(RST,CLK,ENb[5],Yb101,Rb101);
Multiplicador_4x4 M6(Ra101,Rb101,M101);
Registro_8b RC101(RST,CLK,ENc[5],M101,Rc101);
Mux4_2_1 Mux8(Ra010,Ra111,SEL[7],Ya110);
Registro_4b RA110(RST,CLK,ENa[6],Ya110,Ra110);
Registro_4b RB110(RST,CLK,ENb[6],Rb010,Rb110);
Multiplicador_4x4 M7(Ra110,Rb110,M110);
Registro_8b RC110(RST,CLK,ENc[6],M110,Rc110);
Registro_4b RA111(RST,CLK,ENa[7],Ra011,Ra111);
Registro_4b RB111(RST,CLK,ENb[7],Rb011,Rb111);
Multiplicador_4x4 M8(Ra111,Rb111,M111);
Registro_8b RC111(RST,CLK,ENc[7],M111,Rc111);
Sumador_8b SUM1(Rc000,Rc100,MTX00);
Sumador_8b SUM2(Rc001,Rc101,MTX01);
Sumador_8b SUM3(Rc010,Rc110,MTX10);
Sumador_8b SUM4(Rc011,Rc111,MTX11);
endmodule
|
module Uart_top(
input clk,
input rst_n,
input rs232_rx,
output rs232_tx
);
wire rx_en;
wire sel_data,sel_data_rx,sel_data_tx;
wire tx_en;
wire [3:0] num,num_rx,num_tx;
wire [7:0] rx_data;
Bps_select Bps_rx(
.clk (clk), //系统时钟50MHz
.rst_n (rst_n), //低电平复位
.en (rx_en), //使能信号：串口接收活发送开始
.sel_data (sel_data_rx), //波特率计数中心点（采集数据的使能信号）
.num (num_rx) //一帧数据bit0~bit9
);
Uart_rx Uart_rx_inst( //串口接收模块例化
.clk (clk),
.rst_n (rst_n),
.rs232_rx (rs232_rx),
.num (num_rx),
.sel_data (sel_data_rx),
.rx_en (rx_en),
.tx_en (tx_en),
.rx_data (rx_data)
);
Bps_select Bps_tx(
.clk (clk), //系统时钟50MHz
.rst_n (rst_n), //低电平复位
.en (tx_en), //使能信号：串口接收活发送开始
.sel_data (sel_data_tx), //波特率计数中心点（采集数据的使能信号）
.num (num_tx) //一帧数据bit0~bit9
);
Uart_tx Uart_tx_inst( //串口发送模块例化
.clk (clk),
.rst_n (rst_n),
.num (num_tx),
.sel_data (sel_data_tx),
.rx_data (rx_data),
.rs232_tx (rs232_tx)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k; vector<long long> v; long long dp[1001][2001][4]; long long rec(long long i, long long mask, long long comp) { if (i == n && comp == k) return 1; else if (i == n) return 0; else if (comp > k) return 0; if (dp[i][comp][mask] != -1) return dp[i][comp][mask]; if (i == 0) { return dp[i][comp][mask] = (rec(i + 1, 0, comp + 1) + rec(i + 1, 1, comp + 2) + rec(i + 1, 2, comp + 2) + rec(i + 1, 3, comp + 1)) % 998244353; } if (mask == 0) { return dp[i][comp][mask] = (rec(i + 1, 0, comp) + rec(i + 1, 3, comp + 1) + rec(i + 1, 1, comp + 1) + rec(i + 1, 2, comp + 1)) % 998244353; } else if (mask == 1) { return dp[i][comp][mask] = (rec(i + 1, 0, comp) + rec(i + 1, 1, comp) + rec(i + 1, 2, comp + 2) + rec(i + 1, 3, comp)) % 998244353; } else if (mask == 2) { return dp[i][comp][mask] = (rec(i + 1, 0, comp) + rec(i + 1, 1, comp + 2) + rec(i + 1, 2, comp) + rec(i + 1, 3, comp)) % 998244353; } else if (mask == 3) { return dp[i][comp][mask] = (rec(i + 1, 0, comp + 1) + rec(i + 1, 1, comp + 1) + rec(i + 1, 2, comp + 1) + rec(i + 1, 3, comp)) % 998244353; } } void solve() { memset(dp, -1, sizeof(dp)); cin >> n >> k; cout << rec(0, 0, 0); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long q = 1; while (q--) { v.clear(); solve(); } }
|
#include <bits/stdc++.h> using namespace std; long long i, n, m, a[1000001], t1, t2, sum; int main() { cin >> n >> m; for (i = 0; i < m; i++) { scanf( %I64d %I64d , &t1, &t2); a[t1]++; a[t2]++; } for (i = 1; i <= n; i++) sum += a[i] * (n - 1LL - a[i]); sum /= 2LL; cout << n * (n - 1LL) * (n - 2LL) / 6LL - sum << endl; }
|
#include <bits/stdc++.h> #define pb push_back using namespace std; typedef long long ll; void solve() { int n; cin >> n; int adad[n]; map<int, int> cnt; for (int i = 0; i < n; i++) { cin >> adad[i]; cnt[adad[i]]++; } int mini; mini = *min_element(adad, adad + n); cout << n - cnt[mini] << endl; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; for (int i = 0; i < n; i++) { cout << 1 << ; } cout << endl; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout << setprecision(32); int t; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; long long n, u, v, w, res = 0, par[N]; vector<pair<long long, long long> > a[N]; long long root(long long x) { if (par[x] < 0) return x; return (par[x] = root(par[x])); } void Merge(long long u, long long v) { long long a = root(u), b = root(v); if (a == b) return; if (par[a] > par[b]) swap(a, b); par[a] += par[b], par[b] = a; } bool check(long long n) { while (n > 0) { long long a = n % 10; if (a != 4 && a != 7) return false; n /= 10; } return true; } void in() { cin >> n; for (long long i = 1; i <= n; i++) par[i] = -1; for (long long i = 1; i <= n - 1; i++) { cin >> u >> v >> w; if (!check(w)) Merge(u, v); a[u].push_back({v, w}), a[v].push_back({u, w}); } } void process() { for (long long i = 1; i <= n; i++) { if (par[i] < 0) { long long tmp = -par[i]; res += (tmp * (n - tmp - 1) * (n - tmp)); } } cout << res; } int main() { if (fopen( trau.inp , r )) freopen( trau.inp , r , stdin), freopen( trau.out , w , stdout); in(); process(); }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return x * f; } const int N = 500005, INF = 1e9; const double DINF = 1e18; struct Edge { int fr, to, nxt, cap; double cost; } e[N << 1]; int head[N], pre[N], q[N], En = 1, S, T, n; double dis[N]; bool vis[N]; inline void add_edge(int u, int v, int f, double w) { ++En; e[En].fr = u, e[En].to = v, e[En].nxt = head[u], e[En].cap = f, e[En].cost = w; head[u] = En; ++En; e[En].fr = v, e[En].to = u, e[En].nxt = head[v], e[En].cap = 0, e[En].cost = -w; head[v] = En; } bool spfa() { for (int i = 0; i <= T; ++i) dis[i] = DINF, vis[i] = false, pre[i] = 0; int L = 1, R = 0; dis[S] = 0, q[++R] = S, vis[S] = true, pre[S] = 0; while (L <= R) { int u = q[L++]; vis[u] = false; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (dis[v] > dis[u] + e[i].cost && e[i].cap > 0) { dis[v] = dis[u] + e[i].cost; pre[v] = i; if (!vis[v]) q[++R] = v; } } } return dis[T] != DINF; } void mcf() { int Flow = 0; double Cost = 0; while (spfa()) { int now = INF; for (int i = T; i != S; i = e[pre[i]].fr) now = min(now, e[pre[i]].cap); for (int i = T; i != S; i = e[pre[i]].fr) e[pre[i]].cap -= now, e[pre[i] ^ 1].cap += now; Flow += now; Cost += 1.0 * now * dis[T]; } if (Flow >= n - 1) printf( %.10lf , Cost); else puts( -1 ); } struct Node { int x, y; } A[N]; int sqr(int x) { return x * x; } double dist(const Node &A, const Node &B) { return sqrt(1.0 * (sqr(A.x - B.x) + sqr(A.y - B.y))); } int main() { n = read(); for (int i = 1; i <= n; ++i) A[i].x = read(), A[i].y = read(); S = 0, T = n + n + 1; for (int i = 1; i <= n; ++i) add_edge(S, i, 2, 0), add_edge(i + n, T, 1, 0); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) if (A[j].y > A[i].y) add_edge(j, i + n, 1, dist(A[i], A[j])); mcf(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SEDFXTP_PP_BLACKBOX_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_PP_BLACKBOX_V
|
module queue_param_1r_1w(
in_wr_en,
in_wr_addr,
in_wr_data,
in_rd_addr,
out_rd_data,
clk,
rst
);
parameter BITS = 2;
parameter SIZE = 4;
parameter WIDTH = 32;
input in_wr_en;
input [BITS - 1:0] in_wr_addr;
input [WIDTH - 1:0] in_wr_data;
input [BITS - 1:0] in_rd_addr;
output [WIDTH - 1:0] out_rd_data;
input clk;
input rst;
wire [(SIZE * WIDTH) - 1:0] word_out;
wire [SIZE - 1:0] wr_word_select;
wire [SIZE - 1:0] wr_en_word;
mux_param #(.BITS(BITS), .SIZE(SIZE), .WIDTH(WIDTH)) mux_rd_port (.out(out_rd_data), .in(word_out), .select(in_rd_addr));
decoder_param #(.BITS(BITS), .SIZE(SIZE)) decoder_wr_port (.out(wr_word_select), .in(in_wr_addr));
assign wr_en_word = {SIZE{in_wr_en}} & wr_word_select;
reg_param #(.WIDTH(WIDTH)) word[SIZE - 1:0] (.out(word_out), .in(in_wr_data), .wr_en(wr_en_word), .clk(clk), .rst(rst));
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( 03 ) using namespace std; int n, m, q, x[200100], y[200100], dad[400100]; bool viz[400100]; int find(int p) { if (dad[p] == p) return p; return dad[p] = find(dad[p]); } void join(int a, int b) { dad[find(a)] = find(b); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> n >> m >> q; for (int i = 1; i <= n + m; i++) dad[i] = i; for (int i = 1; i <= q; i++) cin >> x[i] >> y[i]; for (int i = 1; i <= q; i++) join(x[i], y[i] + n); int rs = 0; for (int i = 1; i <= n + m; i++) { int p = find(i); if (!viz[p]) rs++; viz[p]++; } cout << rs - 1; return 0; }
|
//======================================================================
//
// blake2_G.v
// -----------
// Verilog 2001 implementation of the G function in the
// blake2 hash function core. This is pure combinational logic in a
// separade module to allow us to build versions with 1, 2, 4
// and even 8 parallel compression functions.
//
//
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blake2_G(
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
input wire [63 : 0] m0,
input wire [63 : 0] m1,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
//----------------------------------------------------------------
// The actual G function.
//----------------------------------------------------------------
wire [63 : 0] a0 = a + b + m0;
wire [63 : 0] d0 = d ^ a0;
wire [63 : 0] d1 = {d0[31 : 0], d0[63 : 32]};
wire [63 : 0] c0 = c + d1;
wire [63 : 0] b0 = b ^ c0;
wire [63 : 0] b1 = {b0[23 : 0], b0[63 : 24]};
wire [63 : 0] a1 = a0 + b1 + m1;
wire [63 : 0] d2 = d1 ^ a1;
wire [63 : 0] d3 = {d2[15 : 0], d2[63 : 16]};
wire [63 : 0] c1 = c0 + d3;
wire [63 : 0] b2 = b1 ^ c1;
wire [63 : 0] b3 = {b2[62 : 0], b2[63]};
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = a1;
assign b_prim = b3;
assign c_prim = c1;
assign d_prim = d3;
endmodule // blake2_G
//======================================================================
// EOF blake2_G.v
//======================================================================
|
module counter_n (clk,sig,n_clk_out);
/*This module takes an input signal and implements a period counter,
taking the reciprocal to deliver the frequency in kHz.
USAGE:
counter c(clk,sig,f);
clk and sig are 1-bit inputs representing the clock and RF signal whose frequency
is to be measured.
f is a 4-bit output corresponding to the frequency of sig, IN UNITS OF HUNDREDS
OF Hz. This is because hundreds of Hz is the highest requeired frequency
resolution, and we want to use integer arithmetic.
Reference: Agilent Technologies. "Fundamentals of the Electronic Counters".
Application Note 200, Electronic Counter Series.
Design notes:
In a period counter, pulses of the clock are counted in a register, with the
totaling (counting) action gated by pulses from the RF input whose frequency
is being measured. Averaging over multiple RF cycles reduces error.
The total time elapsed between RF edges will be
n_clk*tau_c+err = m/f
=>f= m/(n_clk*tau_c+err)
where tau_c is the clock period, n_clk is the number of clock cycles actually counted
by the register, err is the error in the time estimate, m is the number of RF
positive edges, and f is the RF frequency.
Contributions to error include the +-1 count error, timebase deviations, etc.
The +-1 count error, or quantization error, arises because time is only measured
in discrete steps, and a measurement of four clock time units may be produced by
RF pulses which are acutally separated by 3+delta or 5-delta clock units.
The nominal frequency estimate
f_nominal=m/(n_clk*tau_c)
converges with the value that would arise from an average after many cycles
if n_clk is very large.
With just the +-1 count error, the spread in maximum and minimum possible
frequency estimates
fmax-fmin=m/tau_c*(1/(n_clk-1)-1/(n_clk+1))=2*m/tau_c * 1/(n_clk^2-1) ~= 2*f_nom^2*tau_c/m
=2*f_nom^2/(f_clk*m)
The error increases with frequency for a fixed number of RF pulses, but decreases
as the clock frequency increases and as the number of RF pulses averaged over
increases.
We require about 3 kHz resolution at the highest frequencies (around 300 kHz)
and about 500 Hz resolution at the lowest frequencies - these values are about
half the frequency interval between adjacent bins in these sub-bands. With
a clock speed of 4 MHz,
m=2*f_high^2/(f_clk*Delta_f_high)=2*(3E5^2)/(4E6*3E3)=18E10/(12E9)=15
with m=15, at the lower frequencies,
fmax-fmin=2*5E4^2/(4E6*15) = Delta_f_high/36 ~= 83 Hz
while m/5E4=15/5E4=3.0E-4=300 us is the maximum time elapsed per measurement.
At high frequency, Delta_t = m/300E3=50 us.
Since we are willing to accept a reaction time on the order of 1 ms, we can
actually improve accuracy by increasing m such that Delta_t_max = 1 ms = m/5E4
=>m=50.
So choose m=50, which gives fmax-fmin~=900 Hz at f_rf=300 kHz.
f_nom = m*f_clk/n_clk => n_clk = m*f_clk/f_nom,
n_clk_max=50*4E6/5E4=80E2=4000
=>n_clk needs to be at least 12 bits. Make 13.
13 Jan 2012
In general, the phase of clk edges relative sig edges will change. Some phases produce floor(M*tau_s/tau_c) clock counts, while others produce floor(M*tau_s/tau_c)+1 clock counts. This results in a jitter in n_clk. By itself, this might not be so bad, but when many bits are changing (since we are not using a Gray code), this can be problematic. Further, in practice, the spread in clock counts seems to reach +0+2, instead of +0+1.
The fix implemented is to compare the value of n_clk at the 50th sig interval to the value of n_clk used in the last frequency calculation. If the absolute value of the difference is larger than MIN_CHANGE=2, then the frequency is re-computed. Otherwise, the frequency is not changed. This seems to take care of the jitter.
//Error (10239): Verilog HDL Always Construct error at counter.v(102): event control cannot test for both positive and negative edges of variable "clk"
*/
`define CLK_COUNTER_SIZE 14 //Number of bits in clock edge counter.
`define SIG_COUNTER_SIZE 7 //Number of bits in signal edge counter.
input clk,sig;
output reg [13:0] n_clk_out; //Output clock counts.
reg [13:0] n_clk; //Register to hold number of clock counts between RF signal.
reg [13:0] n_clk_last; //Holds value of n_clk used in the last frequency computation. Compared with current value to determine whether frequency should be recomputed.
reg [6:0] n_sig; //Register to count the number of RF cycles.
reg cnt_flg; //Counter flag.
reg reset; //Internal flag to reset clock counter.
//Clock frequency in hundreds of Hz.
parameter F_CLK=40000;
//parameter F_CLK=35795; //This clock was used to test whether incorrect firing of state happens at different frequencies depending on clock frequency and precession of this with sync signal freq.
//Number of cycles of RF signal over which to average period.
parameter M=50;
//Define macros to set counter sizes for convenience (so that don't have to make multiple changes if counter size needs to be adjusted).
parameter MIN_CHANGE=`CLK_COUNTER_SIZE'b10; //n_clk must change by at least this amount (up or down) from last n_clk in order for a change in computed frequency to be allowed.
initial begin
#0
n_clk=`CLK_COUNTER_SIZE'b0; //Initialize clock edge counter.
n_sig=`SIG_COUNTER_SIZE'b0; //RF Cycle counter.
reset=1'b1; //Initialize reset flag to block clock counter until signal counter gate opens.
end
//Clock loop
//always @(posedge clk) begin //Triggering on reset was there in case there were two sig edges before the next clk edge, in which case the reset call would get skipped. But maybe false triggers are causing clock count to drift or flicker. Remove this edge detector and see what happens. Result - no, that didn't fix the problem.
always @(posedge clk or posedge reset) begin
if (reset) begin
n_clk=`CLK_COUNTER_SIZE'b0; //Reset clk counter.
end else begin
n_clk=n_clk+`CLK_COUNTER_SIZE'b1; //Increment clk counter.
end
end
//Gate on positive edges of signal
always @(posedge sig) begin
//Initially, the gate is closed and n_sig=0.
//When the gate is opened, n_sig is incremented, so n_sig=1.
//The gate is closed again at the (M+1)th positive edge on n_sig, but before n_sig is incremented,
//so n_sig=M still.
//As such, the gate is open between the 1st and (M+1)th positive edges of n_sig, corresponding to M sig intervals.
//The gate is closed between the (M+1)th=0th and 1st signal edges.
//THEN dt = (M)*tau_sig = (M)/f_sig = (n_clk-1+[-0+2])/f_clk
//It is n_clk-1 because this is the number of clock time intervals in n_clk positive edges.
// [-0+2]=error on time measurement - time is at least (n_clk-1)*tau_c, but could be as much as
// (n_clk-1+2-delta)*tau_c, so on average, elapsed time is actually (n_clk-1 - (average error = (0+2)/2=1))*tau_c
// => f_sig = f_clk * (M)/(n_clk-1-(0+2)/2) = f_clk * (M)/n_clk
if (n_sig==M) begin //This is actually the M+1th edge, and the Mth interval
//After M sig edges and n_clk clock edges,
//Handle case where n_clk=0 by saturating frequency at f=M*F_CLK.
if(n_clk==`CLK_COUNTER_SIZE'b0) n_clk_out=n_clk; //Case where no counts on clock are registered.
//Disallow jitter from changes in n_clk by +-2; only update frequency
//when clock counter is different by a number other than +-MIN_CHANGE.
else if ((n_clk>n_clk_last && n_clk-n_clk_last>MIN_CHANGE) || ( n_clk_last>n_clk && n_clk_last-n_clk>MIN_CHANGE) ) begin
n_clk_last=n_clk; //Store clock counter at last frequency change.
n_clk_out=n_clk; //Re-compute RF frequency.
end
n_sig=`SIG_COUNTER_SIZE'b0; //Zero out rf cycle counter.
reset=1'b1; //Set reset flag high to restart clock counter.
end else begin //Start incrementing signal positive edge counter.
reset=1'b0; //Set reset low and start counting clock cycles again.
n_sig=n_sig+`SIG_COUNTER_SIZE'b1; //Increment RF cycle counter.
end
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: fb_block.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module fb_block (
address,
clock,
data,
wren,
q);
input [7:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_block_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; set<long long> f, l, s; long long sf = 0, sl = 0; long long ksum = 0, cnt = 0, kmin = 0; void update(long long b, long long t) { int c = l.size(); if (t == 1) s.insert(b); else s.erase(b); if (c == 1 && cnt == 0) { ksum = kmin = *s.rbegin(); cnt = 1; return; } if (c > cnt) { if (b > kmin) { ksum += b; } else { kmin = *(--s.find(kmin)); ksum += kmin; } cnt++; } else if (c < cnt) { ksum -= max(b, kmin); if (b <= kmin) { kmin = *s.upper_bound(kmin); } cnt--; } else { if (c == 0) return; if (b >= kmin) { if (t == 1) { ksum += b - kmin; kmin = *s.upper_bound(kmin); } else { kmin = *(--s.lower_bound(kmin)); ksum -= b - kmin; } } } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; while (n--) { long long a, b; cin >> a >> b; if (a == 0) { if (b < 0) { f.erase(f.find(-b)); } else { f.insert(b); } sf += b; } else { if (b < 0) { l.erase(l.find(-b)); } else { l.insert(b); } sl += b; } if (b < 0) update(-b, -1); else update(b, 1); if (l.size() == 0) { cout << sf << endl; } else if (f.size() == 0) { cout << 2 * sl - *l.begin() << endl; } else { if (*f.rbegin() > *l.begin()) { cout << sf + sl + ksum << endl; } else { cout << sf + 2 * sl - *l.begin() + *f.rbegin() << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; const long long N = 11111111; const long long INF = (long long)(1e12); const long long mod = 998244353; const double eps = 1e-9; long long n, mx = -1, inv[N], a[N], k, all, cnt, ans; map<long long, long long, greater<long long> > M, S; long long get(long long x) { return (x) * (x + 1) / 2; } int main() { ios_base ::sync_with_stdio(false); cin >> n >> k; all = (1ll << k) - 1; ans = get(n); M[0]++; for (long long i = 1; i <= n; ++i) { cin >> a[i]; a[i] ^= a[i - 1]; inv[i] = (all ^ a[i]); if (M[a[i]] < M[inv[i]]) { ans -= M[a[i]]; M[a[i]]++; } else { ans -= M[inv[i]]; M[inv[i]]++; } } cout << ans; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:02:42 05/13/2015
// Design Name: processor_16
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_processor.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: processor_16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_processor;
// Inputs
reg clock;
reg IRQ;
reg [15:0] processor_input;
// Outputs
wire [15:0] processor_output;
// Instantiate the Unit Under Test (UUT)
processor_16 uut (
.clock(clock),
.IRQ(IRQ),
.processor_output(processor_output),
.processor_input(processor_input)
);
initial begin
// Initialize Inputs
clock = 0;
IRQ = 0;
processor_input = 0;
// Add stimulus here
#20;
processor_input = 0;
end
always #10 clock = !clock;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; long long power(long long x, int y) { long long res = 1; x = x % mod; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % mod; y = y >> 1; x = (x * x) % mod; } return res; } int modInverse(long long a) { return power(a, mod - 2); } long long factmod(long long a) { long long val = 1; while (a > 0) { val = (val * a) % mod; a--; } return val; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m, ans; cin >> n >> m; ans = (factmod(n + 2 * m - 1) * modInverse(factmod(2 * m)) % mod * modInverse(factmod(n - 1) % mod)) % mod; cout << ans; }
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
// IP Revision: 8
(* X_CORE_INFO = "axis_data_fifo_v1_1_8_axis_data_fifo,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_axis_data_fifo_2_0,axis_data_fifo_v1_1_8_axis_data_fifo,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_axis_data_fifo_2_0,axis_data_fifo_v1_1_8_axis_data_fifo,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_data_fifo,x_ipVersion=1.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000011011,C_FIFO_DEPTH=32,C_FIFO_MODE=1,C_IS_ACLK_ASYNC=0,C_SYNCHRONIZER_STAGE=2,C_ACLKEN_CONV_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_axis_data_fifo_2_0 (
s_axis_aresetn,
s_axis_aclk,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input wire [3 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output wire [3 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
output wire [31 : 0] axis_data_count;
output wire [31 : 0] axis_wr_data_count;
output wire [31 : 0] axis_rd_data_count;
axis_data_fifo_v1_1_8_axis_data_fifo #(
.C_FAMILY("zynq"),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00000000000000000000000000011011),
.C_FIFO_DEPTH(32),
.C_FIFO_MODE(1),
.C_IS_ACLK_ASYNC(0),
.C_SYNCHRONIZER_STAGE(2),
.C_ACLKEN_CONV_MODE(0)
) inst (
.s_axis_aresetn(s_axis_aresetn),
.m_axis_aresetn(1'H0),
.s_axis_aclk(s_axis_aclk),
.s_axis_aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(4'HF),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_aclk(1'H0),
.m_axis_aclken(1'H1),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axis_data_count(axis_data_count),
.axis_wr_data_count(axis_wr_data_count),
.axis_rd_data_count(axis_rd_data_count)
);
endmodule
|
/**
# SmallBsf - 2-pole IIR Bandstop Filter #
Small 2-Pole IIR band-stop filter, made using just adders and bit shifts. Set
the frequency using the K0_SHIFT and K1_SHIFT parameters. It can be slowed down
by strobing the `en` bit to run at a lower rate.
By using power of two feedback terms, this filter is alsways stable and is
immune to limit cycling.
Clamping is necessary if the full input range will be used. Clamping is
unnecessary if the input word will never go beyond '+/- (2^(WIDTH-2)-1)'. Keep
in mind that clamping will cause nonlinear distortion in high-amplitude signals.
## Design Equations ##
Let w0 be the desired center frequency in radians/second, let f_clk be the
filter run rate (defined by clk and en), and let Q be the desired quality
factor. Quality factor can be defined as the center frequency divided by the
bandwidth.
```
s^2 + w0^2
H(s) = -----------------------
s^2 + (w0/Q)*s + w0^2
w0 = 2*pi*f0
Q = f0 / f_bandwidth
K0_SHIFT = -log2(w0/Q / f_clk)
K1_SHIFT = -log2(w0*Q / f_clk)
w0/Q = 2^-K0_SHIFT * f_clk
w0*Q = 2^-K1_SHIFT * f_clk
w0 = sqrt(2^-K0_SHIFT * 2^-K1_SHIFT * f_clk^2)
Q = sqrt(2^-K1_SHIFT / 2^-K0_SHIFT)
```
Since the SHIFT parameters must be integers, the final filter will not perfectly
match the desired one. The true filter response will also be different from the
continuous-time approximation.
## Block Diagram ##
Key:
- ACCUM: accumulator
- SUB: subtract signal on bottom from the signal on the left
- 2^-X: Right arithmetic shift by X
```
dataIn --->(SUB)---------------------------------------+--> dataOut
^ |
| |
+----[2^-K0_SHIFT]<---[ACCUM]<--(SUB)-----/
| ^
| |
\----[ACCUM]--->[2^-K1_SHIFT]-----/
```
*/
module SmallBsf #(
parameter WIDTH = 16, ///< Data width
parameter K0_SHIFT = 10, ///< Gain on forward path accumulator
parameter K1_SHIFT = 18, ///< Gain on feedback path accumulator
parameter CLAMP = 1 ///< Set to 1 to clamp the accumulators
)
(
input clk, ///< System clock
input rst, ///< Reset, active high and synchronous
input en, ///< Filter enable
input signed [WIDTH-1:0] dataIn, ///< Filter input
output signed [WIDTH-1:0] dataOut ///< Filter output
);
reg signed [WIDTH+K0_SHIFT-1:0] acc0;
reg signed [WIDTH+K1_SHIFT-1:0] acc1;
reg signed [WIDTH-1:0] forwardPath;
wire signed [WIDTH-1:0] acc0Out;
wire signed [WIDTH-1:0] acc1Out;
wire signed [WIDTH+K0_SHIFT:0] acc0In;
wire signed [WIDTH+K1_SHIFT:0] acc1In;
assign acc0In = acc0 + forwardPath - acc1Out;
assign acc1In = acc1 + acc0Out;
always @(posedge clk) begin
if (rst) begin
forwardPath <= 'd0;
acc0 <= 'd0;
acc1 <= 'd0;
end
else if (en) begin
forwardPath <= dataIn - acc0Out;
if (CLAMP) begin
acc0 <= (^acc0In[WIDTH+K0_SHIFT-:2])
? {acc0In[WIDTH+K0_SHIFT], {(WIDTH+K0_SHIFT-1){acc0In[WIDTH+K0_SHIFT-1]}}}
: acc0In;
acc1 <= (^acc1In[WIDTH+K1_SHIFT-:2])
? {acc1In[WIDTH+K1_SHIFT], {(WIDTH+K1_SHIFT-1){acc1In[WIDTH+K1_SHIFT-1]}}}
: acc1In;
end
else begin
acc0 <= acc0In;
acc1 <= acc1In;
end
end
end
assign dataOut = forwardPath;
assign acc0Out = acc0 >>> K0_SHIFT;
assign acc1Out = acc1 >>> K1_SHIFT;
// Test Code: Check to see if clamping ever occurs
reg clamp0;
reg clamp1;
always @(posedge clk) begin
if (rst) begin
clamp0 <= 1'b0;
clamp1 <= 1'b0;
end
else begin
clamp0 <= clamp0 | (^acc0In[WIDTH+K0_SHIFT-:2]);
clamp1 <= clamp1 | (^acc1In[WIDTH+K1_SHIFT-:2]);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string text; map<int, int> cache; string to_bin(int v) { string res = ; for (int i = 128; i >= 1; i /= 2) { if (v - i >= 0) { res += 1 ; v -= i; } else { res += 0 ; } } return move(res); } int reverse_bin(int v) { if (cache.count(v)) { return cache[v]; } int res = 0; string bin = to_bin(v); for (int i = 0, k = 1; i < 8; ++i, k *= 2) { if (bin[i] == 1 ) { res += k; } } cache[res] = v; cache[v] = res; return res; } int intercal(int prev, int ch) { int rprev = reverse_bin(prev); int rch = reverse_bin(ch); return (256 - rch + rprev) % 256; } int main() { getline(cin, text); cout << intercal(0, (int)text[0]) << endl; for (int i = 1; i < text.size(); ++i) { cout << intercal((int)text[i - 1], (int)text[i]) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 100000005; const int p = 31; const int mod = (1 << 8) - 1; char s[200005]; const int siz = 5; struct node { public: int c[5][5]; void out() { for (int i = 0; i < siz; i++) { for (int j = 0; j < siz; j++) { printf( %8d , c[i][j]); } puts( ); } puts( ); } node operator^(long long m) { int i; node tmp, a = (*this); memset(tmp.c, 0, sizeof(tmp.c)); for (i = 1; i <= siz; i++) tmp.c[i][i] = 1; while (m) { if (m & 1) { tmp = (tmp * a); } a = (a * a); m >>= 1; } return tmp; } node operator*(node& b) { node tmp; int i, j, k; for (i = 0; i < siz; i++) for (j = i; j < siz; j++) { tmp.c[i][j] = INF; for (k = i; k <= j; k++) tmp.c[i][j] = min(tmp.c[i][j], c[i][k] + b.c[k][j]); if (tmp.c[i][j] > INF) tmp.c[i][j] = INF; } return tmp; } node operator+(node& b) { node tmp; int i, j; for (i = 1; i <= siz; i++) for (j = 1; j <= siz; j++) { tmp.c[i][j] = (c[i][j] + b.c[i][j]) % mod; } return tmp; } void init() { for (int i = 0; i < siz; i++) for (int j = i; j < siz; j++) c[i][j] = INF; } }; struct Tree { node a; int l, r; } tr[200005 << 2]; int n; void upd(int x, int num) { int i, j; for (i = 0; i < siz; i++) tr[x].a.c[i][i] = 0; if (num == 6) tr[x].a.c[3][3] = tr[x].a.c[4][4] = 1; if (num == 2) tr[x].a.c[0][1] = 0, tr[x].a.c[0][0] = 1; if (num == 0) tr[x].a.c[1][2] = 0, tr[x].a.c[1][1] = 1; if (num == 1) tr[x].a.c[2][3] = 0, tr[x].a.c[2][2] = 1; if (num == 7) tr[x].a.c[3][4] = 0, tr[x].a.c[3][3] = 1; } void pushup(int x) { tr[x].a = tr[x << 1].a * tr[x << 1 | 1].a; } void build(int l, int r, int x) { tr[x].l = l, tr[x].r = r; tr[x].a.init(); if (l == r) { upd(x, s[l] - 0 ); return; } int mid = (l + r) / 2; build(l, mid, x << 1); build(mid + 1, r, x << 1 | 1); pushup(x); } node query(int L, int R, int x) { int l = tr[x].l, r = tr[x].r; if (l == L && R == r) { return tr[x].a; } int mid = (l + r) / 2; if (R <= mid) return query(L, R, x << 1); else if (L > mid) return query(L, R, x << 1 | 1); else { node nw, n1, n2; nw.init(); n1 = query(L, mid, x << 1); n2 = query(mid + 1, R, x << 1 | 1); nw = n1 * n2; return nw; } } int main() { int l, r, i, j, m; scanf( %d %d , &n, &m); scanf( %s , s + 1); build(1, n, 1); while (m--) { scanf( %d %d , &l, &r); node nw; nw = query(l, r, 1); if (nw.c[0][4] == INF) printf( -1 n ); else printf( %d n , nw.c[0][4]); } }
|
#include <bits/stdc++.h> int main() { double n, r; std::cin >> n >> r; double ang = 180 / n; ang = 3.1415926536 * ang / 180.0; double R = sin(ang) / (1 - sin(ang)) * r; printf( %0.7lf n , R); return 0; }
|
// Cutiepie is a hoe! #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize ( Ofast ) #pragma GCC target ( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx ) #include <bits/stdc++.h> using namespace std; #define TRACE #ifdef TRACE #define trace(...) __f(#__VA_ARGS__, __VA_ARGS__) template <typename Arg1> void __f(const char* name, Arg1&& arg1){ cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args){ const char* comma = strchr(names + 1, , );cerr.write(names, comma - names) << : << arg1<< | ;__f(comma+1, args...); } #else #define trace(...) #endif #define rep(i, a) for(int i = 0; i < (a); ++i) #define repp(i, a, b) for(int i = a; i < (b); ++i) #define trav(a, x) for(auto& a : x) #define all(x) x.begin(), x.end() #define sz(x) (int)(x).size() #define fst first #define snd second #define mp make_pair #define pb push_back typedef long long ll; typedef long double ld; typedef pair<int, int> pii; typedef vector<int> vi; int a[1005][1005]; int ee[3][1005]; ll s[1005]; ll s2[1005]; void solve() { int n, k; cin>>n>>k; rep(i, k){ s[i] = 0; rep(j, n) { cin>>a[i][j]; s[i] += 1LL*a[i][j]; s2[i] += 1LL*a[i][j]*a[i][j]; } } fflush(stdout); int kk = 1; ll change, vdif; if(2*s[1] == s[0]+s[2]){ vdif = s[1]-s[0]; }else{ vdif = s[k-1]-s[k-2]; } repp(i, 1, k) { if(vdif != s[i]-s[i-1]){ change = s[i]-s[i-1]-vdif; kk = i; break; } } ll v2; if(kk<=2){ v2 = s2[k-1]+s2[k-3]-2LL*s2[k-2]; }else{ v2 = s2[2]+s2[0]-2LL*s2[1]; } ll v2_ = s2[kk+1]+s2[kk-1]-2LL*s2[kk]; rep(i, n) { ll x = a[kk][i]; ll y = x - change; ll v2__ = v2_ + 2LL*x*x - 2LL*y*y; if(v2 == v2__){ cout<<kk<< <<y<<endl; fflush(stdout); return; } } } int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_TB_V
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_TB_V
/**
* lpflow_bleeder: Current bleeder (weak pulldown to ground).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_bleeder.v"
module top();
// Inputs are registered
reg SHORT;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
SHORT = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
#20 SHORT = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 SHORT = 1'b1;
#120 VGND = 1'b1;
#140 VNB = 1'b1;
#160 VPB = 1'b1;
#180 SHORT = 1'b0;
#200 VGND = 1'b0;
#220 VNB = 1'b0;
#240 VPB = 1'b0;
#260 VPB = 1'b1;
#280 VNB = 1'b1;
#300 VGND = 1'b1;
#320 SHORT = 1'b1;
#340 VPB = 1'bx;
#360 VNB = 1'bx;
#380 VGND = 1'bx;
#400 SHORT = 1'bx;
end
sky130_fd_sc_hd__lpflow_bleeder dut (.SHORT(SHORT), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int j, i, k, n, m, x; float d[6000], a[5008], b[5009]; cin >> n >> m; for (i = 0; i < n; i++) { cin >> a[i] >> b[i]; d[i] = (float)(1.0 * a[i]) / b[i]; } sort(d, d + n); printf( %.8f , d[0] * m); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O21A_FUNCTIONAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_BLACKBOX_V
`define SKY130_FD_SC_HS__A32O_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_TB_V
`define SKY130_FD_SC_HD__SDFSBP_TB_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_BLACKBOX_V
`define SKY130_FD_SC_LS__FAH_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_BLACKBOX_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_2_w_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_2_w_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=3,NUM_PORTS=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_2_w_0 (
In0,
In1,
In2,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
input wire [0 : 0] In2;
output wire [2 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(3),
.NUM_PORTS(3)
) inst (
.In0(In0),
.In1(In1),
.In2(In2),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: RAW2RGB
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module RAW2RGB( oRed,
oGreen,
oBlue,
oDVAL,
iX_Cont,
iY_Cont,
iDATA,
iDVAL,
iCLK,
iRST
);
input [10:0] iX_Cont;
input [10:0] iY_Cont;
input [11:0] iDATA;
input iDVAL;
input iCLK;
input iRST;
output [11:0] oRed;
output [11:0] oGreen;
output [11:0] oBlue;
output oDVAL;
wire [11:0] mDATA_0;
wire [11:0] mDATA_1;
reg [11:0] mDATAd_0;
reg [11:0] mDATAd_1;
reg [11:0] mCCD_R; // Bayer red (12b)
reg [12:0] mCCD_G; // Bayer has 2 green pixels for 1 red and 1 blue(13b)
reg [11:0] mCCD_B; // Bayer blue (12b)
reg mDVAL;
reg [12:0] mDATA_green_0;
reg [12:0] mDATA_green_1;
assign oRed = mCCD_R[11:0];
assign oGreen = mCCD_G[12:1];
assign oBlue = mCCD_B[11:0];
assign oDVAL = mDVAL;
// Line buffer with:
// NUMBER_OF_TAPS = 2
// TAP_DISTANCE = 1280
// WIDTH = 12 bits
Line_Buffer u0 ( .clken(iDVAL),
.clock(iCLK),
.shiftin(iDATA),
.taps0x(mDATA_1),
.taps1x(mDATA_0) );
// Bayer demosaicing RG / GB -> RGB
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
mCCD_R <= 0;
mCCD_G <= 0;
mCCD_B <= 0;
mDATAd_0 <= 0;
mDATAd_1 <= 0;
mDVAL <= 0;
end
else
begin
mDATAd_0 <= mDATA_0;
mDATAd_1 <= mDATA_1;
mDVAL <= {iY_Cont[0]|iX_Cont[0]} ? 1'b0 : iDVAL;
if({iY_Cont[0],iX_Cont[0]}==2'b10)
begin
mCCD_R <= mDATA_0;
mCCD_G <= mDATAd_0 + mDATA_1; // Obtaining green from 2 Bayer pixels
mCCD_B <= mDATAd_1;
end
else if({iY_Cont[0],iX_Cont[0]}==2'b11)
begin
mCCD_R <= mDATAd_0;
mCCD_G <= mDATA_0 + mDATAd_1; // Obtaining green from 2 Bayer pixels
mCCD_B <= mDATA_1;
end
else if({iY_Cont[0],iX_Cont[0]}==2'b00)
begin
mCCD_R <= mDATA_1;
mCCD_G <= mDATA_0 + mDATAd_1; // Obtaining green from 2 Bayer pixels
mCCD_B <= mDATAd_0;
end
else if({iY_Cont[0],iX_Cont[0]}==2'b01)
begin
mCCD_R <= mDATAd_1;
mCCD_G <= mDATAd_0 + mDATA_1; // Obtaining green from 2 Bayer pixels
mCCD_B <= mDATA_0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long vectorMult(pair<int, int> a, pair<int, int> b, pair<int, int> c) { return (c.first - a.first) * 1ll * (b.second - a.second) - (c.second - a.second) * 1ll * (b.first - a.first); } bool cmp(pair<int, int> a, pair<int, int> b) { return a.first < b.first || a.first == b.first && a.second < b.second; } vector<pair<int, int> > convex_hull(vector<pair<int, int> > t) { if (t.size() == 1) return t; sort(t.begin(), t.end(), cmp); vector<pair<int, int> > up, down; auto l = t[0]; auto r = t.back(); up.push_back(t[0]); down.push_back(t[0]); for (int i = 1; i < t.size(); i++) { if (vectorMult(l, r, t[i]) <= 0) { while (up.size() >= 2 && vectorMult(up[up.size() - 2], up.back(), t[i]) <= 0) { up.pop_back(); } up.push_back(t[i]); } if (vectorMult(l, r, t[i]) >= 0) { while (down.size() >= 2 && vectorMult(down[down.size() - 2], down.back(), t[i]) >= 0) { down.pop_back(); } down.push_back(t[i]); } } up.insert(up.end(), down.rbegin() + 1, down.rend() - 1); if (up.size() == 2 && up[0] == up[1]) up.pop_back(); return up; } int main() { ios_base::sync_with_stdio(0); while (true) { int n; cin >> n; if (n == 0) break; vector<string> v; for (int i = 0; i < n; i++) { string x; cin >> x; v.push_back(x); } for (int i = 0; i < n - i - 1; i++) { swap(v[i], v[n - i - 1]); } vector<pair<int, int> > t; for (int i = 0; i < n - 1; i++) { for (int j = 0; j < n - 1; j++) { if (v[i][j] > 0 && v[i][j + 1] > 0 && v[i + 1][j] > 0 && v[i + 1][j + 1] > 0 ) { t.push_back(make_pair(j + 1, i + 1)); } } } t = convex_hull(t); int mn = 0; for (int i = 1; i < t.size(); i++) if (t[i] < t[mn]) { mn = i; } vector<pair<int, int> > ans; ans.insert(ans.end(), t.begin() + mn, t.end()); ans.insert(ans.end(), t.begin(), t.begin() + mn); cout << ans.size() << endl; for (auto it : ans) cout << it.first << << it.second << endl; } return 0; }
|
#include <bits/stdc++.h> int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); int n; std::cin >> n; std::vector<std::vector<std::pair<int, int>>> g(n); for (int i = 1; i < n; ++i) { int u, v, w; std::cin >> u >> v >> w; --u; --v; g[u].push_back(std::make_pair(v, w)); g[v].push_back(std::make_pair(u, w)); } std::vector<int> sz(n); std::vector<long long> w(n); long long ans = 0; std::function<void(int, int)> dfs = [&](int u, int fa) { sz[u] = 1; std::vector<int> adj; for (auto p : g[u]) { int v = p.first, l = p.second; if (v == fa) { continue; } w[v] += l * 2; dfs(v, u); w[u] += w[v]; sz[u] += sz[v]; ans += l * sz[v]; adj.push_back(v); } std::sort(adj.begin(), adj.end(), [&](int u, int v) { return w[u] * sz[v] < w[v] * sz[u]; }); long long sum = 0; for (auto v : adj) { ans += sum * sz[v]; sum += w[v]; } }; dfs(0, -1); std::cout << std::setprecision(20) << 1.0 * ans / (n - 1) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mo = 998244353; const long long g = 3; const int N = 500000; int n, ax, bx, rev[N + 10]; long long aa[N + 10], bb[N + 10], c[N + 10], fac[N + 10], inv[N + 10]; long long mul(long long x, long long y) { long long z = 1; while (y) { if (y & 1) z = z * x % mo; y >>= 1; x = x * x % mo; } return z; } struct poly { vector<int> a; void pre(int n) { rev[0] = 0; for (int i = 1; i < n; i++) if (i & 1) rev[i] = rev[i ^ 1] + (n >> 1); else rev[i] = rev[i >> 1] >> 1; } void FFT(long long *a, int n) { for (int i = 0; i < n; i++) c[rev[i]] = a[i]; for (int i = 2; i <= n; i <<= 1) { long long wn = mul(g, (mo - 1) / i); for (int j = 0; j < n; j += i) { long long w = 1; for (int k = j; k < j + i / 2; k++, w = wn * w % mo) { long long ck = c[k]; c[k] = (ck + w * c[k + i / 2]) % mo; c[k + i / 2] = (ck - w * c[k + i / 2]) % mo; } } } for (int i = 0; i < n; i++) a[i] = (c[i] + mo) % mo; } void IFFT(long long *a, int n) { FFT(a, n); for (int i = 1; i < n / 2; i++) swap(a[i], a[n - i]); long long invn = mul(n, mo - 2); for (int i = 0; i < n; i++) a[i] = a[i] * invn % mo; } poly operator*(poly &p) { int sz = a.size() + p.a.size() - 1; int nx = 1; while (nx < sz) nx <<= 1; pre(nx); for (int i = 0; i < nx; i++) { if (i < (int)a.size()) aa[i] = a[i]; else aa[i] = 0; if (i < (int)p.a.size()) bb[i] = p.a[i]; else bb[i] = 0; } FFT(aa, nx); FFT(bb, nx); for (int i = 0; i < nx; i++) aa[i] = aa[i] * bb[i] % mo; IFFT(aa, nx); poly ans; ans.a.clear(); for (int i = 0; i < sz; i++) ans.a.push_back(aa[i]); return ans; } }; void prework() { fac[0] = 1; for (int i = 1; i <= N; i++) fac[i] = fac[i - 1] * i % mo; inv[N] = mul(fac[N], mo - 2); for (int i = N - 1; i >= 0; i--) inv[i] = inv[i + 1] * (i + 1) % mo; } poly Calc_Stirling(int l, int r) { poly f; f.a.clear(); if (l > r) { f.a.push_back(1); return f; } if (l == r) { f.a.push_back(l); f.a.push_back(1); return f; } int mid = (l + r) / 2; f = Calc_Stirling(l, mid); poly g = Calc_Stirling(mid + 1, r); f = f * g; return f; } int main() { scanf( %d%d%d , &n, &ax, &bx); if (ax == 0 || bx == 0) { printf( 0 n ); return 0; } prework(); poly f = Calc_Stirling(0, n - 2); long long ans; if (ax + bx - 2 < (int)f.a.size()) ans = f.a[ax + bx - 2]; else ans = 0; ans = (ans * fac[ax + bx - 2] % mo * inv[ax - 1] % mo * inv[bx - 1] % mo + mo) % mo; printf( %lld n , ans); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/07/04 09:50:20
// Design Name:
// Module Name: pwm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pwm(clk,rst,pwm_duty,pwm_offset,pwm_out);
input clk;//->clock_100kHz
input rst;//->clock_50Hz,posedge trigger
input [7:0] pwm_duty;//Duty Cycle:50(0.5ms)-250(2.5ms)
input [7:0] pwm_offset;//Offset Correction Signal.It's point to the default position of servo
output pwm_out;//It's just the output wire signal,the signal in the always@ block is **pwm_buffer**
reg pwm_buffer;//it's a buffer of pwm signal.
reg [7:0] counter;
parameter [7:0] PWM_DEFAULT = 8'd150;
wire [7:0] duty_temp;
wire [7:0] duty_check;
assign duty_temp = pwm_duty + ( pwm_offset - PWM_DEFAULT );//Corrected Signal by pwm_offset
assign duty_check = ( duty_temp >= 50 && duty_temp <= 250) ? duty_temp : PWM_DEFAULT;//In case of duty cycle is out of range
always @ (posedge clk or posedge rst)
if(rst)
begin
counter <= 0;
pwm_buffer <= 1;
end
else
begin
if( counter <= duty_check )
begin
pwm_buffer <= 1;
counter <= counter + 1;
end
else
begin
pwm_buffer <= 0;
counter <= counter;//lock counter
end
end
assign pwm_out = pwm_buffer;
endmodule
|
`timescale 1 ns / 1 ps
module s2mm_adv #
(
// Users to add parameters here
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_IMG_WBITS = 12,
parameter integer C_IMG_HBITS = 12,
parameter integer C_DATACOUNT_BITS = 12,
parameter integer C_PIXEL_STORE_WIDTH = 8,
parameter integer C_IMG_STRIDE_SIZE = 1024,
// User parameters ends
// Parameters of Axi Master Bus Interface M_AXI
parameter integer C_M_AXI_BURST_LEN = 16,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
)
(
input wire [C_IMG_WBITS-1:0] img_width,
input wire [C_IMG_HBITS-1:0] img_height,
input wire [C_M_AXI_ADDR_WIDTH-1:0] img_stride,
input wire clk,
input wire resetn,
/// @NOTE: resetting will keep until current transaction done.
/// if under idle state when negedge of soft_resetn,
/// don't need resetting, i.e. resetting will keep zero.
input wire soft_resetn,
output wire resetting,
/// sream to fifo
input wire s_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
input wire s2mm_full,
input wire s2mm_almost_full,
output wire [C_PIXEL_WIDTH+1 : 0] s2mm_wr_data,
output wire s2mm_wr_en,
/// fifo to memory
output wire s2mm_sof,
input wire [C_M_AXI_ADDR_WIDTH-1:0] s2mm_addr,
input wire [C_M_AXI_DATA_WIDTH/C_PIXEL_STORE_WIDTH*(C_PIXEL_WIDTH+2)-1 : 0] s2mm_rd_data,
input wire s2mm_empty,
output wire s2mm_rd_en,
input wire [C_DATACOUNT_BITS-1:0] s2mm_rd_data_count,
// Ports of Axi Master Bus Interface M_AXI
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr,
output wire [7 : 0] m_axi_awlen,
output wire [2 : 0] m_axi_awsize,
output wire [1 : 0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3 : 0] m_axi_awcache,
output wire [2 : 0] m_axi_awprot,
output wire [3 : 0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [1 : 0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready
);
localparam C_PM1 = C_PIXEL_WIDTH - 1;
localparam C_PP1 = C_PIXEL_WIDTH + 1;
localparam C_PP2 = C_PIXEL_WIDTH + 2;
localparam C_ADATA_PIXELS = C_M_AXI_DATA_WIDTH/C_PIXEL_STORE_WIDTH;
function integer reverseI(input integer i);
begin
reverseI = C_ADATA_PIXELS-1-i;
end
endfunction
function integer sofIdx(input integer i);
begin
sofIdx = i * C_PP2 + C_PIXEL_WIDTH;
end
endfunction
function integer eolIdx(input integer i);
begin
eolIdx = i * C_PP2 + C_PP1;
end
endfunction
// stream to fifo
wire working;
assign working = (resetn && soft_resetn);
assign resetting = ~working;
/// use s2f_aclk
assign s2mm_wr_data = {s_axis_tlast, s_axis_tuser, s_axis_tdata};
assign s2mm_wr_en = s_axis_tvalid && s_axis_tready;
reg sready;
assign s_axis_tready = sready;
always @ (posedge clk) begin
if (resetting)
sready <= 0;
else if (s2mm_wr_en && s2mm_almost_full)
sready <= 0;
else
sready <= 1;
end
// fifo to mm
/// use f2m_aclk
wire [C_M_AXI_DATA_WIDTH-1 : 0] s2mm_pixel_data;
generate
genvar i;
for (i = 0; i < C_M_AXI_DATA_WIDTH/C_PIXEL_WIDTH; i = i+1) begin: single_pixel
assign s2mm_pixel_data[i*C_PIXEL_STORE_WIDTH + C_PM1 : i*C_PIXEL_STORE_WIDTH]
= s2mm_rd_data[reverseI(i)*C_PP2 + C_PM1 : reverseI(i)*C_PP2];
end
endgenerate
wire f2mm_resetting;
wire f2mm_write_resp_error;
FIFO2MM_adv # (
.C_DATACOUNT_BITS(C_DATACOUNT_BITS),
.C_M_AXI_BURST_LEN(C_M_AXI_BURST_LEN),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_IMG_WBITS(C_IMG_WBITS),
.C_IMG_HBITS(C_IMG_HBITS),
.C_ADATA_PIXELS(C_ADATA_PIXELS)
) FIFO2MM_inst (
.img_width(img_width),
.img_height(img_height),
.img_stride(C_IMG_STRIDE_SIZE),
.soft_resetn(soft_resetn),
.resetting(f2mm_resetting),
//.sof(s2mm_rd_data[sofIdx(reverseI(0))]),
.din(s2mm_pixel_data),
//.empty(s2mm_empty),
.rd_en(s2mm_rd_en),
.rd_data_count(s2mm_rd_data_count),
.frame_pulse(s2mm_sof),
.base_addr(s2mm_addr),
.M_AXI_ACLK(clk),
.M_AXI_ARESETN(resetn),
.M_AXI_AWADDR(m_axi_awaddr),
.M_AXI_AWLEN(m_axi_awlen),
.M_AXI_AWSIZE(m_axi_awsize),
.M_AXI_AWBURST(m_axi_awburst),
.M_AXI_AWLOCK(m_axi_awlock),
.M_AXI_AWCACHE(m_axi_awcache),
.M_AXI_AWPROT(m_axi_awprot),
.M_AXI_AWQOS(m_axi_awqos),
.M_AXI_AWVALID(m_axi_awvalid),
.M_AXI_AWREADY(m_axi_awready),
.M_AXI_WDATA(m_axi_wdata),
.M_AXI_WSTRB(m_axi_wstrb),
.M_AXI_WLAST(m_axi_wlast),
.M_AXI_WVALID(m_axi_wvalid),
.M_AXI_WREADY(m_axi_wready),
.M_AXI_BRESP(m_axi_bresp),
.M_AXI_BVALID(m_axi_bvalid),
.M_AXI_BREADY(m_axi_bready),
.write_resp_error(f2mm_write_resp_error)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double long EPS = 1e-10; struct wor { double long x = 0, y = 0; }; double long dist(wor a, wor b) { double long answer = sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); return answer; } pair<vector<double long>, vector<long long>> djkstra( long long from, long long n, vector<vector<pair<double long, long long>>> &adj) { vector<bool> used(n); vector<double long> d(n, 1e15); vector<long long> f(n); d[from] = 0; f[from] = from; for (int i = 0; i < n; i++) { long long mi = -1; for (int i = 0; i < n; i++) { if (!used[i]) { mi = i; break; } } for (int j = 0; j < n; j++) { if (!used[j] && d[j] < d[mi]) { mi = j; } } used[mi] = true; for (auto e : adj[mi]) { if (!used[e.second] && d[mi] + e.first < d[e.second]) { d[e.second] = d[mi] + e.first; f[e.second] = mi; } } } return {d, f}; } struct Kun1 { long long n; vector<vector<long long>> adj; vector<long long> used; vector<bool> is_l; vector<long long> mt; Kun1(long long n) { this->n = n; adj.resize(n); used.resize(n); mt.resize(n); is_l.resize(n); } void add_edge(long long u, long long v) { adj[u].push_back(v); adj[v].push_back(u); } void make_left(long long v) { is_l[v] = true; } bool try_kun(long long v, long long cur) { if (used[v] == cur) return false; used[v] = cur; for (auto e : adj[v]) { if (mt[e] == -1 || try_kun(mt[e], cur)) { mt[e] = v; return true; } } return false; } long long max_matching() { vector<bool> usel(n); for (int i = 0; i < n; i++) { if (!is_l[i]) mt[i] = -1; } long long answer = 0; for (int i = 0; i < n; i++) { if (is_l[i]) { for (auto e : adj[i]) { if (mt[e] == -1) { mt[e] = i; answer++; usel[i] = true; break; } } } } long long z = 1; for (int i = 0; i < n; i++) { if (is_l[i] && !usel[i] && try_kun(i, z++)) answer++; } return answer; } }; struct MCMF { struct edge { long long from, to, flow, cap, cost; }; vector<edge> edges; vector<vector<long long>> adj; vector<long long> d; vector<long long> p; deque<long long> q; vector<long long> state; const long long levit_inf = 2e9; long long n, s, t; MCMF(long long _n, long long _s, long long _t) { n = _n; s = _s; t = _t; adj.resize(n); d.resize(n); p.resize(n); state.resize(n); } void add_edge(long long from, long long to, long long cap, long long cost) { edge e1 = {from, to, 0, cap, cost}; edge e2 = {to, from, 0, 0, -cost}; adj[from].push_back(edges.size()); edges.push_back(e1); adj[to].push_back(edges.size()); edges.push_back(e2); } void relax(long long v, long long dist, long long from) { if (d[v] <= dist) { return; } d[v] = dist; p[v] = from; if (state[v] == 0 || (!q.empty() && d[q.front()] > d[v])) { q.push_front(v); state[v] = 1; } else if (state[v] == 2) { q.push_back(v); state[v] = 1; } } bool levit() { fill(d.begin(), d.end(), levit_inf); fill(p.begin(), p.end(), -1); relax(s, 0, 0); while (!q.empty()) { long long v = q.front(); q.pop_front(); state[v] = 2; for (auto i = 0; i < adj[v].size(); i++) { auto e = adj[v][i]; if (edges[e].flow < edges[e].cap) { relax(edges[e].to, d[v] + edges[e].cost, e); } } } return d[t] < levit_inf; } pair<long long, long long> max_flow() { long long flow = 0; long long cost = 0; while (levit()) { long long ed = p[t]; long long mi_fl = edges[ed].cap - edges[ed].flow; while (edges[ed].from != s) { mi_fl = min(mi_fl, edges[ed].cap - edges[ed].flow); ed = p[edges[ed].from]; } mi_fl = min(mi_fl, edges[ed].cap - edges[ed].flow); ed = p[t]; while (edges[ed].from != s) { edges[ed].flow += mi_fl; edges[ed ^ 1].flow -= mi_fl; cost += edges[ed].cost * mi_fl; ed = p[edges[ed].from]; } edges[ed].flow += mi_fl; edges[ed ^ 1].flow -= mi_fl; cost += edges[ed].cost * mi_fl; flow += mi_fl; } return {cost, flow}; } }; struct MCMF1 { struct edge { long long from, to, cap, flow, cost; }; vector<edge> edges; vector<vector<long long>> adj; vector<long long> p; vector<long long> d; vector<long long> state; const long long lenin_inf = 2e9; long long n, s, t; MCMF1(long long _n, long long _s, long long _t) { n = _n; s = _s; t = _t; adj.resize(n); p.resize(n); d.resize(n); state.resize(n); } void add_edge(long long from, long long to, long long cap, long long cost) { edge e1 = {from, to, cap, 0, cost}; edge e2 = {to, from, 0, 0, -cost}; adj[from].push_back(edges.size()); edges.push_back(e1); adj[to].push_back(edges.size()); edges.push_back(e2); } deque<long long> q; void relax(long long v, long long dist, long long from) { if (d[v] <= dist) return; d[v] = dist; p[v] = from; if (state[v] == 0 || (!q.empty() && d[v] < d[q.front()])) { q.push_front(v); state[v] = 1; } else if (state[v] == 2) { q.push_back(v); state[v] = 1; } } bool lenin() { fill(d.begin(), d.end(), lenin_inf); fill(p.begin(), p.end(), -1); fill(state.begin(), state.end(), 0); relax(s, 0, 0); while (!q.empty()) { long long v = q.front(); q.pop_front(); state[v] = 2; for (auto e : adj[v]) { if (edges[e].cap - edges[e].flow == 0) continue; relax(edges[e].to, d[v] + edges[e].cost, e); } } return d[t] < lenin_inf; } pair<long long, long long> max_flow() { long long flow = 0; long long cost = 0; while (lenin()) { long long ed = p[t]; long long ma = edges[ed].cap - edges[ed].flow; while (edges[ed].from != s) { ma = min(ma, edges[ed].cap - edges[ed].flow); ed = p[edges[ed].from]; } ma = min(ma, edges[ed].cap - edges[ed].flow); ed = p[t]; while (edges[ed].from != s) { edges[ed].flow += ma; edges[ed ^ 1].flow -= ma; cost += ma * edges[ed].cost; ed = p[edges[ed].from]; } edges[ed].flow += ma; edges[ed ^ 1].flow -= ma; cost += ma * edges[ed].cost; flow += ma; } return {cost, flow}; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string t; cin >> t; long long n; cin >> n; vector<pair<string, long long>> arr(n); vector<vector<long long>> num(n); long long sum = 0; long long z = n + 1; for (int i = 0; i < n; i++) { cin >> arr[i].first >> arr[i].second; for (int j = 0; j < arr[i].first.length(); j++) { num[i].push_back(z++); } sum += arr[i].first.length(); } MCMF mcmf(2 + t.length() + n + sum, 0, 2 + t.length() + n + sum - 1); for (int i = 0; i < n; i++) { mcmf.add_edge(0, i + 1, arr[i].second, 0); } for (int i = 1; i <= n; i++) { for (auto e : num[i - 1]) { mcmf.add_edge(i, e, 1, 0); } } vector<long long> tn; for (int i = 0; i < t.length(); i++) { tn.push_back(z++); } for (int i = 1; i <= n; i++) { for (int j = 0; j < arr[i - 1].first.length(); j++) { for (int z = 0; z < t.length(); z++) { if (t[z] == arr[i - 1].first[j]) { mcmf.add_edge(num[i - 1][j], tn[z], 1, i); } } } } for (auto e : tn) { mcmf.add_edge(e, 2 + t.length() + n + sum - 1, 1, 0); } auto e = mcmf.max_flow(); if (e.second != t.length()) { cout << -1; } else { cout << e.first; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1e5 + 50; int ch(char a) { if (a == tolower(a)) return a - a ; else return a - A + 26; } int get_ans(int n) { char s[M]; scanf( %s , s); int cnt[52], mm = 0, len = strlen(s); memset(cnt, 0, sizeof(cnt)); for (int i = 0; i < len; i++) cnt[ch(s[i])]++, mm = max(mm, cnt[ch(s[i])]); if (len == 1) return 1; if (mm == len) { if (n == 1) return mm - 1; else return mm; } return min(len, mm + n); } int main() { int N, i; scanf( %d , &N); int v[3]; v[0] = get_ans(N); v[1] = get_ans(N); v[2] = get_ans(N); int mx = max(max(v[0], v[1]), v[2]); int c = 0; for (i = 0; i < 3; i++) if (v[i] == mx) c++; if (c >= 2) return !printf( Draw n ); if (v[0] == mx) printf( Kuro n ); if (v[1] == mx) printf( Shiro n ); if (v[2] == mx) printf( Katie n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-15; const long double PI = 3.14159265358979323846; inline int lg2(long long n) { int h = 0; while ((1ll << h) < n) ++h; return h; } struct configio { configio() { cin.tie(nullptr); ios_base::sync_with_stdio(false); } } cnfio; int diff(int a, int b, int mod) { return ((a - b) % mod + mod) % mod; } struct candy { int h, m; }; int main() { int n, x; cin >> n >> x; vector<candy> v1[2]; for (int i = 0; i < n; ++i) { int t, h, m; cin >> t >> h >> m; v1[t].push_back({h, m}); } long long ans = 0; for (int type = 0; type <= 1; ++type) { vector<candy> v[2]; v[0] = v1[0]; v[1] = v1[1]; int cur_ans = 0; long long cur_x = x; int cur_type = type; while (true) { int id = -1; for (int i = 0; i < v[cur_type].size(); ++i) { if (v[cur_type][i].h <= cur_x) { if (id == -1 || (v[cur_type][id].m < v[cur_type][i].m)) { id = i; } } } if (id == -1) { break; } cur_ans++; cur_x += v[cur_type][id].m; v[cur_type].erase(v[cur_type].begin() + id); cur_type ^= 1; } ans = max(ans, (long long)cur_ans); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef long long int ll; #define M 1000000007 int main() { std::ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin>>t; while(t--) { string s; cin>>s; for(int i=0; i<s.length(); i++) { if(i%2==0) { if(s[i] != a ) s[i] = a ; else s[i] = b ; } else { if(s[i] != z ) s[i] = z ; else s[i] = y ; } } cout<<s<<endl; } return 0; }
|
`timescale 1ns / 1ps
module TX
#( parameter stateA = 'b00001,
parameter stateB = 'b00010,
parameter stateC = 'b00100,
parameter stateD = 'b01000,
parameter stateE = 'b10000)
(input clk,
input baud_rate,
input [7:0]d_in,
input tx_start,
output reg tx,
output reg tx_done);
reg [4:0] state = stateA;
reg [4:0] next_state = stateA;
reg tick_enable = 0;
integer count = 0;
reg rst_count = 1;
integer bit_count = 0;
reg [7:0] d_aux;
always@(posedge clk)
begin
state=next_state;
end
always@(posedge clk)
begin
case(state)
stateA:
if(tx_start == 1) next_state = stateB;
else next_state = stateA;
stateB:
if(bit_count == 1) next_state = stateC;
else next_state = stateB;
stateC:
if(bit_count == 9) next_state = stateD;
else next_state = stateC;
stateD:
if(bit_count == 10) next_state = stateE;
else next_state = stateD;
stateE:
if(tx_done == 1) next_state = stateA;
else next_state = stateE;
endcase
end
always@(posedge clk)
begin
case(state)
stateA:
begin
tx = 1;
tx_done = 1;
rst_count = 0;
tick_enable = 0;
end
stateB:
begin
tx_done = 0;
rst_count = 1;
tick_enable = 1;
if(count == 16)
begin
tx = 0;
d_aux = d_in;
bit_count = bit_count + 1;
rst_count = 0;
end
end
stateC:
begin
rst_count = 1;
if(count == 16)
begin
tx = d_aux[0];
d_aux = d_aux >> 1;
bit_count = bit_count + 1;
rst_count = 0;
end
end
stateD:
begin
rst_count = 1;
if(count == 16)
begin
tx = 1;
bit_count = bit_count + 1;
rst_count = 0;
end
end
stateE:
begin
if(count == 16)
begin
bit_count = 0;
tx_done = 1;
end
end
endcase
end
always@(posedge baud_rate or negedge rst_count)
begin
if(rst_count == 0) count = 0;
else
begin
if(tick_enable == 1)count = count + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; int n, m, a, b, g; int dis[N]; long long ans, c[N]; long long sum(int u) { return 1LL * u * (u + 1) / 2; } long long query(int u) { return sum(u / g + 1) * g - 1LL * (u / g + 1) * ((g - ((u + 1) % g)) % g); } int gcd(int u, int v) { if (v == 0) { return u; } return gcd(v, u % v); } set<pair<int, int> > s; int main() { scanf( %d%d%d , &n, &a, &b); g = gcd(a, b); if (n > a + b - g) { ans += query(n) - query(a + b - g); n = a + b - g; } memset(dis, 0x3f, sizeof dis); dis[0] = 0; s.insert({0, 0}); while (!s.empty()) { auto u = *s.begin(); s.erase(s.begin()); if (dis[u.second] != u.first) { continue; } ++c[u.first]; if (u.second >= b && u.first < dis[u.second - b]) { dis[u.second - b] = u.first; s.insert({u.first, u.second - b}); } if (u.second + a <= n && max(u.first, u.second + a) < dis[u.second + a]) { dis[u.second + a] = max(u.first, u.second + a); s.insert({max(u.first, u.second + a), u.second + a}); } } for (int i = 1; i <= n; i++) { c[i] += c[i - 1]; } for (int i = 0; i <= n; i++) { ans += c[i]; } printf( %lld n , ans); return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
/* Uncomment this for LCU????
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
//cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
/*
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1)
(* keep *) cycloneiv_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(CO), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
//assign CO = COx[Y_WIDTH];
else
cycloneiv_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
/*assign X = AA ^ BB;
endmodule*/
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH < 6;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
cycloneiv_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = (long long)(2e5 + 1); bool bipartite = true; vector<long long> colour; vector<long long> adj[N]; vector<long long> visited; void dfs(long long node, long long par, long long col) { visited[node] = 1; colour[node] = col; for (auto it : adj[node]) { if (!visited[it]) dfs(it, node, !col); else if (it != par and colour[it] == colour[node]) bipartite = false; } } signed main() { long long n, m; cin >> n >> m; vector<pair<long long, long long>> edges; colour = vector<long long>(n, -1); visited = vector<long long>(n, 0); for (long long i = 0; i < m; i++) { long long u, v; cin >> u >> v; u--, v--; adj[v].push_back(u); adj[u].push_back(v); edges.push_back({u, v}); } dfs(0, -1, 0); if (!bipartite) { cout << NO n ; return 0; } cout << YES n ; for (long long i = 0; i < m; i++) { long long ele1 = edges[i].first; long long ele2 = edges[i].second; cout << (colour[ele1] < colour[ele2]); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_2_V
`define SKY130_FD_SC_LS__OR4B_2_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_2 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_2 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_2_V
|
#include <bits/stdc++.h> using namespace std; int c1, c2, c3, c4, n, m, bus[1009], tre[1009], x, z1, z, l, l1, y; int main() { cin >> c1 >> c2 >> c3 >> c4; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> bus[i]; if (l == 0) { if (x + bus[i] * c1 < x + c2) x += bus[i] * c1; else x += c2; if (x > c3) x = c3, l = 1; } } for (int i = 1; i <= m; i++) { cin >> tre[i]; if (l1 == 0) { if (y + tre[i] * c1 < y + c2) y += tre[i] * c1; else y += c2; if (y > c3) y = c3, l1 = 1; } } x = min(x + y, c4); cout << x; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.