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#include <bits/stdc++.h> using namespace std; int stuff(int x) { int s = 0; while (x / 10 != 0) { int r = x % 10; x /= 10; s += r; } s += x; return s; } int main() { ios_base::sync_with_stdio(false); long long int i = 0; long long int p, f, a, b, c, s, spow = 1; long long int arr[1000]; cin >> a >> b >> c; f = a; for (s = 1; s <= 81; s++) { f = a; spow = 1; while (f--) { spow *= s; } p = (b * spow) + c; if (stuff(p) == s && p < 1000000000) { arr[i] = p; i++; } } sort(arr, arr + i); cout << i << n ; for (int j = 0; j < i; j++) { cout << arr[j] << ; } }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram2_ddr2_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram2_ddr2_rptr( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Minor changes for adaptation to SDRAM: Ivan Gorodetsky, 2014
//
// Design File: rk_wxeda.v
//
// Top level design file.
module rk_wxeda(
input clk48mhz,
input [3:0] KEY,
inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits
output DRAM_LDQM, // SDRAM Low-byte Data Mask
output DRAM_UDQM, // SDRAM High-byte Data Mask
output DRAM_WE_N, // SDRAM Write Enable
output DRAM_CAS_N, // SDRAM Column Address Strobe
output DRAM_RAS_N, // SDRAM Row Address Strobe
output DRAM_CS_N, // SDRAM Chip Select
output DRAM_BA_0, // SDRAM Bank Address 0
output DRAM_BA_1, // SDRAM Bank Address 0
output DRAM_CLK, // SDRAM Clock
output DRAM_CKE, // SDRAM Clock Enable
output VGA_HS,
output VGA_VS,
output [4:0] VGA_R,
output [5:0] VGA_G,
output [4:0] VGA_B,
inout PS2_CLK,
inout PS2_DAT,
input SD_DAT, // SD Card Data (MISO)
output SD_DAT3, // SD Card Data 3 (CSn)
output SD_CMD, // SD Card Command Signal (MOSI)
output SD_CLK, // SD Card Clock (SCK)
output UART_TXD,
input UART_RXD,
output BEEP
);
assign UART_TXD = 0;
//////////////////// RESET ////////////////////
reg[3:0] reset_cnt;
reg reset_n;
wire reset = ~reset_n;
always @(posedge clk48mhz) begin
if (KEY[0] && reset_cnt==4'd14)
reset_n <= 1'b1;
else begin
reset_n <= 1'b0;
reset_cnt <= reset_cnt+4'd1;
end
end
//////////////////// STEP & GO ////////////////////
reg stepkey;
reg onestep;
always @(posedge clk48mhz) begin
stepkey <= KEY[1];
onestep <= stepkey & ~KEY[1];
end
//////////////////// MEM ////////////////////
wire sram_msb = 0;
wire[7:0] rom_o;
assign DRAM_CLK=clk48mhz; // SDRAM Clock
assign DRAM_CKE=1; // SDRAM Clock Enable
wire[15:0] dramout;
SDRAM_Controller ramd(
.clk50mhz(clk48mhz), // Clock 50MHz
.reset(reset), // System reset
.DRAM_DQ(DRAM_DQ), // SDRAM Data bus 16 Bits
.DRAM_ADDR(DRAM_ADDR), // SDRAM Address bus 12 Bits
.DRAM_LDQM(DRAM_LDQM), // SDRAM Low-byte Data Mask
.DRAM_UDQM(DRAM_UDQM), // SDRAM High-byte Data Mask
.DRAM_WE_N(DRAM_WE_N), // SDRAM Write Enable
.DRAM_CAS_N(DRAM_CAS_N), // SDRAM Column Address Strobe
.DRAM_RAS_N(DRAM_RAS_N), // SDRAM Row Address Strobe
.DRAM_CS_N(DRAM_CS_N), // SDRAM Chip Select
.DRAM_BA_0(DRAM_BA_0), // SDRAM Bank Address 0
.DRAM_BA_1(DRAM_BA_1), // SDRAM Bank Address 1
.iaddr(vid_rd ? {3'b000,vid_addr[14:0]} : {3'b000,addrbus[14:0]}),
.idata(cpu_o),
.rd(vid_rd ? 1'b1 : cpu_rd&(!addrbus[15])),
.we_n(vid_rd? 1'b1 : cpu_wr_n|addrbus[15]),
.odata(dramout)
);
wire[7:0] mem_o = dramout[7:0];
biossd rom(.address({addrbus[11]|startup,addrbus[10:0]}), .clock(clk48mhz), .q(rom_o));
//////////////////// CPU ////////////////////
wire[15:0] addrbus;
wire[7:0] cpu_o;
wire cpu_sync;
wire cpu_rd;
wire cpu_wr_n;
wire cpu_int;
wire cpu_inta_n;
wire inte;
reg[7:0] cpu_i;
reg startup;
always @(*)
casex (addrbus[15:13])
3'b0xx: cpu_i = startup ? rom_o : mem_o;
3'b100: cpu_i = ppa1_o;
3'b101: cpu_i = sd_o;
3'b110: cpu_i = crt_o;
3'b111: cpu_i = rom_o;
endcase
wire ppa1_we_n = addrbus[15:13]!=3'b100|cpu_wr_n;
wire ppa2_we_n = addrbus[15:13]!=3'b101|cpu_wr_n;
wire crt_we_n = addrbus[15:13]!=3'b110|cpu_wr_n;
wire crt_rd_n = addrbus[15:13]!=3'b110|~cpu_rd;
wire dma_we_n = addrbus[15:13]!=3'b111|cpu_wr_n;
reg[4:0] cpu_cnt;
reg cpu_ce2;
reg[10:0] hldareg;
wire cpu_ce = cpu_ce2;
always @(posedge clk48mhz) begin
if(reset) begin cpu_cnt<=0; cpu_ce2<=0; hldareg=11'd0; end
else
if((hldareg[10:9]==2'b01)&&((cpu_rd==1)||(cpu_wr_n==0))) begin cpu_cnt<=0; cpu_ce2<=1; end
else
if(cpu_cnt<27) begin cpu_cnt <= cpu_cnt + 5'd1; cpu_ce2<=0; end
else begin cpu_cnt<=0; cpu_ce2<=~hlda; end
hldareg<={hldareg[9:0],hlda};
startup <= reset|(startup&~addrbus[15]);
end
k580wm80a CPU(.clk(clk48mhz), .ce(cpu_ce), .reset(reset),
.idata(cpu_i), .addr(addrbus), .sync(cpu_sync), .rd(cpu_rd), .wr_n(cpu_wr_n),
.intr(cpu_int), .inta_n(cpu_inta_n), .odata(cpu_o), .inte_o(inte));
//////////////////// VIDEO ////////////////////
wire[7:0] crt_o;
wire[3:0] vid_line;
wire[6:0] vid_char;
wire[15:0] vid_addr;
wire[3:0] dma_dack;
wire[7:0] dma_o;
wire[1:0] vid_lattr;
wire[1:0] vid_gattr;
wire vid_cce,vid_drq,vid_irq,hlda;
wire vid_lten,vid_vsp,vid_rvv,vid_hilight;
wire dma_owe_n,dma_ord_n,dma_oiowe_n,dma_oiord_n;
wire vid_hr, vid_vr;
wire vid_rd = ~dma_oiord_n;
k580wt57 dma(.clk(clk48mhz), .ce(vid_cce), .reset(reset),
.iaddr(addrbus[3:0]), .idata(cpu_o), .drq({1'b0,vid_drq,2'b00}), .iwe_n(dma_we_n), .ird_n(1'b1),
.hlda(hlda), .hrq(hlda), .dack(dma_dack), .odata(dma_o), .oaddr(vid_addr),
.owe_n(dma_owe_n), .ord_n(dma_ord_n), .oiowe_n(dma_oiowe_n), .oiord_n(dma_oiord_n) );
k580wg75 crt(.clk(clk48mhz), .ce(vid_cce),
.iaddr(addrbus[0]), .idata(cpu_o), .iwe_n(crt_we_n), .ird_n(crt_rd_n),
.vrtc(vid_vr), .hrtc(vid_hr), .dack(dma_dack[2]), .ichar(mem_o), .drq(vid_drq), .irq(vid_irq),
.odata(crt_o), .line(vid_line), .ochar(vid_char), .lten(vid_lten), .vsp(vid_vsp),
.rvv(vid_rvv), .hilight(vid_hilight), .lattr(vid_lattr), .gattr(vid_gattr) );
rk_video vid(.clk(clk48mhz),
.hr(VGA_HS), .vr(VGA_VS),
.r(VGA_R), .g(VGA_G), .b(VGA_B),
.hr_wg75(vid_hr), .vr_wg75(vid_vr), .cce(vid_cce),
.line(vid_line), .ichar(vid_char),
.vsp(vid_vsp), .lten(vid_lten), .rvv(vid_rvv)
);
//////////////////// KBD ////////////////////
wire[7:0] kbd_o;
wire[2:0] kbd_shift;
rk_kbd kbd(.clk(clk48mhz), .reset(reset), .ps2_clk(PS2_CLK), .ps2_dat(PS2_DAT),
.addr(~ppa1_a), .odata(kbd_o), .shift(kbd_shift));
//////////////////// SYS PPA ////////////////////
wire[7:0] ppa1_o;
wire[7:0] ppa1_a;
wire[7:0] ppa1_b;
wire[7:0] ppa1_c;
k580ww55 ppa1(.clk(clk48mhz), .reset(reset), .addr(addrbus[1:0]), .we_n(ppa1_we_n),
.idata(cpu_o), .odata(ppa1_o), .ipa(ppa1_a), .opa(ppa1_a),
.ipb(~kbd_o), .opb(ppa1_b), .ipc({~kbd_shift,tapein,ppa1_c[3:0]}), .opc(ppa1_c));
//////////////////// SOUND ////////////////////
reg tapein;
soundcodec sound(
.clk(clk48mhz),
.pulse(ppa1_c[0]^inte),
.reset_n(reset_n),
.o_pwm(BEEP)
);
//////////////////// SD CARD ////////////////////
reg sdcs;
reg sdclk;
reg sdcmd;
reg[6:0] sddata;
wire[7:0] sd_o = {sddata, SD_DAT};
assign SD_DAT3 = ~sdcs;
assign SD_CMD = sdcmd;
assign SD_CLK = sdclk;
always @(posedge clk48mhz or posedge reset) begin
if (reset) begin
sdcs <= 1'b0;
sdclk <= 1'b0;
sdcmd <= 1'h1;
end else begin
if (addrbus[0]==1'b0 && ~ppa2_we_n) sdcs <= cpu_o[0];
if (addrbus[0]==1'b1 && ~ppa2_we_n) begin
if (sdclk) sddata <= {sddata[5:0],SD_DAT};
sdcmd <= cpu_o[7];
sdclk <= 1'b0;
end
if (cpu_rd) sdclk <= 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> #include <cmath> #include <regex> #define ff first #define ss second #define pb push_back #define mp make_pair #define ba back #define ppb pop_back #define eb emplace_back #define eps 1e-6 #define vec vector<long long int> #define sz(x) (int((x.size()))) #define all(x) (x).begin(),(x).end() #define FAST ios_base :: sync_with_stdio (false); cin.tie (NULL) #define ll long long #define loop(i,s,n) for(int i=s;i<n;i++) using namespace std; //----------------------------------------------------------------------------------------------------------------- const ll M = 1e9 + 7; const ll N = 2e5 + 5; const ll inf = 2e18; ll mod(ll x){ return (x%M);} ll mod_minus(ll a, ll b){ ll ans= (mod(a)-mod(b)); if(ans<0) ans=mod(ans+M); return ans;} ll mod_mul(ll a,ll b){ return mod(mod(a)*mod(b));} ll mod_add(ll a,ll b){ return mod(a+b);} ll power(ll a,ll n){ if(n==0) return 1; else if(n==1) return a; ll R=power(a,n/2)%M; if(n%2==0) { return mod(mod_mul(R,R)); } else { return mod(mod_mul(mod_mul(R,a),mod(R))); } } ll mod_inv(ll n){ return power(n,M-2);} // only if M is prime ll mod_div(ll a,ll b){ ll ans=mod(a); ll b1=power(b,M-2); ans= mod(mod_mul(ans,b1)); return ans; } ll fact_mod(ll n){ vec fact(n+1); fact[0]=1; loop(i,1,n+1){ fact[i]=mod_mul(fact[i-1],i); } return fact[n]; } unsigned long long nCr_mod(unsigned long long n, ll r) { if (r == 0) return 1; unsigned long long fac[n + 1]; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % M; return (fac[n] * mod_inv(fac[r]) % M * mod_inv(fac[n - r]) % M) % M; } //-------------------------------------------------------------------------------------------------------------- void solve(){ ll n; cin>>n; ll a[n]; ll sum=0; loop(i,0,n){ cin>>a[i]; sum+=a[i]; } sort(a,a+n); ll mx=a[n-1],mn=a[0]; ll z=(n-1)-sum%(n-1); if(z==(n-1)){ z=0; } sum+=z; if(mx<=sum/(n-1)){ cout<<z<<endl; return; } cout<<mx*(n-1)-sum+z<<endl; } int main(){ FAST; int t; cin>>t; while(t--){ solve(); } }
|
#include <bits/stdc++.h> using namespace std; int ky[8] = {-1, 1, -2, 2, -2, 2, -1, 1}; int kx[8] = {-2, -2, -1, -1, 1, 1, 2, 2}; int dy[4] = {-1, 0, 1, 0}; int dx[4] = {0, 1, 0, -1}; int ddy[8] = {-1, 0, 1, -1, 1, -1, 0, 1}; int ddx[8] = {-1, -1, -1, 0, 0, 1, 1, 1}; const double PI = acos(-1.0); int n; int c, p; int k; int num; struct Group { int c, p, idx; }; Group a[1000]; Group b[1000]; pair<int, int> t[1000]; int ret1, ret2; int cnt1, cnt2; set<int> s; vector<pair<int, int>> pos1, pos2; int ns; bool comp1(const Group &x, const Group &y) { return x.p > y.p || (x.p == y.p && x.c < y.c); } bool comp2(const Group &x, const Group &y) { return x.c < y.c || (x.c == y.c && x.p > y.p); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> c >> p; a[i].c = c; a[i].p = p; a[i].idx = i + 1; b[i].c = c; b[i].p = p; b[i].idx = i + 1; } sort(a, a + n, comp1); sort(b, b + n, comp2); cin >> k; for (int i = 0; i < k; i++) { cin >> num; t[i].first = num; t[i].second = i + 1; } sort(t, t + k); for (int i = 0; i < n; i++) { for (int j = 0; j < k; j++) { if (s.count(j)) continue; if (a[i].c <= t[j].first) { ret1 += a[i].p; cnt1++; pos1.push_back({a[i].idx, t[j].second}); s.insert(j); break; } } } s.clear(); for (int i = 0; i < n; i++) { for (int j = 0; j < k; j++) { if (s.count(j)) continue; if (b[i].c <= t[j].first) { ret2 += b[i].p; cnt2++; pos2.push_back({b[i].idx, t[j].second}); s.insert(j); break; } } } if (ret1 <= ret2) { cout << cnt2 << << ret2 << n ; ns = pos2.size(); for (int i = 0; i < ns; i++) cout << pos2[i].first << << pos2[i].second << n ; } else { cout << cnt1 << << ret1 << n ; ns = pos1.size(); for (int i = 0; i < ns; i++) cout << pos1[i].first << << pos1[i].second << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_4_V
`define SKY130_FD_SC_LP__CLKINVLP_4_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_4_V
|
/*
* Copyright (C) 2015 - 2017 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
module cosine_int
(
input c,
input [13:0] a,
input s,
input [34:0] rom_d,
output signed [NBO-1:0] o
);
parameter NBO = 23; // bits in dout
reg [2:0] sign = 0;
reg [21:0] coarse_2 = 0;
wire [47:0] dsp_o;
reg [13:0] a_del = 0;
always @ (posedge c) begin
a_del <= a;
sign <= {sign[1:0], ~s};
coarse_2 <= rom_d[34:13];
end
DSP48E1 #(.AREG(2), .BREG(1)) dsp48_i
(.OVERFLOW(), .PATTERNDETECT(), .PATTERNBDETECT(), .UNDERFLOW(),
.CARRYOUT(), .P(dsp_o),
// control
.ALUMODE({2'd0, sign[2], 1'b1}), .CARRYINSEL(3'd0),
.CLK(c), .INMODE(5'b00100), .OPMODE(7'b0110101),
// signal inputs
.A({6'b0, a_del, 10'b0}), // 4 regs to outa
.B({5'b0, rom_d[12:0]}), // 3 regs to out
.C({2'b0, coarse_2, 24'hFFFFFF}), // 2 regs to out
.CARRYIN(1'b0), .D(25'b0),
// cascade ports
.ACOUT(), .BCOUT(), .CARRYCASCOUT(), .MULTSIGNOUT(), .PCOUT(),
.ACIN(30'h0), .BCIN(18'h0), .CARRYCASCIN(1'b0), .MULTSIGNIN(1'b0), .PCIN(48'h0),
// clock enables
.CEA1(1'b1), .CEA2(1'b1), .CEAD(1'b0), .CEALUMODE(1'b1), .CEB1(1'b1), .CEB2(1'b1),
.CEC(1'b1), .CECARRYIN(1'b1), .CECTRL(1'b1), .CED(1'b0), .CEINMODE(1'b1), .CEM(1'b1), .CEP(1'b1),
.RSTA(1'b0), .RSTALLCARRYIN(1'b0), .RSTALUMODE(1'b0), .RSTB(1'b0), .RSTC(1'b0), .RSTCTRL(1'b0), .RSTD(1'b0),
.RSTINMODE(1'b0), .RSTM(1'b0), .RSTP(1'b0)
);
assign o = dsp_o[46:47-NBO];
endmodule
|
`timescale 1ns/10ps
module PressCountSim;
reg clock0;
reg clock180;
reg reset;
reg countu;
reg countd;
wire [7:0] nr_presses;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#5000 $finish;
end
initial begin
#0 clock0 = 1;
forever #2 clock0 = ~clock0;
end
initial begin
#0 clock180 = 0;
forever #2 clock180 = ~clock180;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0 countu = 0;
countd = 0;
#12 countu = 1;
#5 countu = 0;
#43 countu = 1;
#5 countu = 0;
#124 countd = 1;
#233 countd = 0;
#4 countu = 1;
#100 countu = 0;
#4 countu = 1;
#100 countu = 0;
end
PressCount
presscount (.clock0(clock0),
.clock180(clock180),
.reset(reset),
.countu(countu),
.countd(countd),
.nr_presses(nr_presses));
endmodule // PressCountSim
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam // synopsys enum En_State
EP_State_IDLE = {3'b000,5'd00},
EP_State_CMDSHIFT0 = {3'b001,5'd00},
EP_State_CMDSHIFT13 = {3'b001,5'd13},
EP_State_CMDSHIFT14 = {3'b001,5'd14},
EP_State_CMDSHIFT15 = {3'b001,5'd15},
EP_State_CMDSHIFT16 = {3'b001,5'd16},
EP_State_DWAIT = {3'b010,5'd00},
EP_State_DSHIFT0 = {3'b100,5'd00},
EP_State_DSHIFT1 = {3'b100,5'd01},
EP_State_DSHIFT15 = {3'b100,5'd15};
reg [7:0] /* synopsys enum En_State */
m_state_xr; // Last command, for debugging
/*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
m_state_xr <= EP_State_IDLE;
end
if (cyc==2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
end
if (cyc==3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
end
if (cyc==4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
end
if (cyc==9) begin
if (m_stateAscii_xr != "dwait ") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_dcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire dcm_rst;
wire [7:0] dcm_status;
wire dcm_locked;
wire dcm_clkfx_stopped = dcm_status[2];
assign dcm_rst = ~reset_n | (dcm_clkfx_stopped & ~dcm_locked);
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
DCM_SP #(
.CLKIN_PERIOD(10),
.CLK_FEEDBACK("NONE"),
.CLKDV_DIVIDE(2.0),
.CLKFX_MULTIPLY(5.0),
.CLKFX_DIVIDE(4.0),
.PHASE_SHIFT(0),
.CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.STARTUP_WAIT("FALSE"),
.CLKIN_DIVIDE_BY_2("FALSE")
)
clk_dcm_inst (
.CLKIN(clk_ibufg),
.CLKFB(1'b0),
.RST(dcm_rst),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSCLK(1'b0),
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_dcm_out),
.CLKFX180(),
.STATUS(dcm_status),
.LOCKED(dcm_locked),
.PSDONE()
);
BUFG
clk_bufg_inst (
.I(clk_dcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~dcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); unsigned n, m; vector<long long> a; vector<long long> prefix; map<long long, long long, greater<long long> > time; cin >> n >> m; prefix.resize(n + 1, 0); a.resize(n); for (unsigned i = 0; i < n; cin >> a[i++]) ; for (unsigned i = 0; i < n; ++i) prefix[i + 1] += prefix[i] + a[i]; long long time_left, fail_count, d; for (unsigned i = 0; i < n; ++i) { time_left = m - prefix[i]; fail_count = 0; for (auto item : time) { time_left = min(time_left, a[i]); d = min(item.second, static_cast<long long>( ceil(1.0 * (a[i] - time_left) / item.first))); time_left += d * item.first; fail_count += d; if (!d) break; } cout << fail_count << ; time[a[i]]++; } }
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long p, long long mod) { long long ret = 1; while (p) { if (p & 1) ret = (ret * a) % mod; a = (a * a) % mod; p /= 2; } return ret; } long long DP[1000]; int A[1000]; int main() { int n; cin >> n; for (__typeof((__typeof(n))0) i((__typeof(n))0); i < n; i++) { cin >> A[i]; A[i]--; } for (int i = 0; i < n; i++) { DP[i] = 2; for (int j = A[i]; j < i; j++) DP[i] = (DP[i] + DP[j]) % 1000000007; } long long ans = 0; for (int i = 0; i < n; i++) ans = (ans + DP[i]) % 1000000007; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n, k; cin >> n >> k; if (k > (n * n + 1) / 2) { cout << NO ; return 0; } cout << YES n ; int tmp = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (j % 2 == i % 2 && tmp != k) { cout << L ; tmp++; } else cout << S ; } cout << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_1_V
`define SKY130_FD_SC_HD__AND4BB_1_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input in; // inputs don't get flagged as undriven
output out; // outputs don't get flagged as unused
sub sub ();
// Check we don't warn about unused UDP signals
udp_mux2 udpsub (out, in, in, in);
// Check ignoreds mark as used
reg sysused;
initial $bboxed(sysused);
wire _unused_ok;
endmodule
module sub;
wire pub /*verilator public*/; // Ignore publics
wire [5:0] assunu1 = 0; // Assigned but unused
wire [3:0] assunub2 = 0; // Assigned but bit 2 unused
wire [15:10] udrb2; // [14:13,11] is undriven
assign udrb2[15] = 0;
assign udrb2[12] = 0;
assign udrb2[10] = 0;
wire unu3; // Totally unused
wire [3:0] mixed; // [3] unused & undr, [2] unused, [1] undr, [0] ok
assign mixed[2] = 0;
assign mixed[0] = 0;
localparam THREE = 3;
initial begin
if (0 && assunu1[0] != 0 && udrb2 != 0) begin end
if (0 && assunub2[THREE] && assunub2[1:0]!=0) begin end
if (0 && mixed[1:0] != 0) begin end
end
endmodule
primitive udp_mux2 (q, a, b, s);
output q;
input a, b, s;
table
//a b s : out
1 ? 0 : 1 ;
0 ? 0 : 0 ;
? 1 1 : 1 ;
? 0 1 : 0 ;
0 0 x : 0 ;
1 1 x : 1 ;
endtable
endprimitive
|
#include <bits/stdc++.h> using namespace std; int main() { long long arr[4]; for (int i = 0; i < 4; i++) cin >> arr[i]; sort(arr, arr + 4); long long w, x, y, z; w = arr[0]; x = arr[1]; y = arr[2]; long long a, b, c, d; b = (w - x + y) / 2; a = w - b; c = x - a; cout << a << << b << << c; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int a, b, c, d, m, v; cin >> a >> b >> c >> d; m = max((3 * a) / 10, a - (a / 250) * c); v = max((3 * b) / 10, b - (b / 250) * d); if (m > v) cout << Misha ; else if (v > m) cout << Vasya ; else cout << Tie ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void FastIO() { ios_base::sync_with_stdio(false); cin.tie(0); cout.precision(20); } int main() { FastIO(); int A, B; while (cin >> A >> B) { int M = min(A, B); int N = max(A - M, B - M); cout << M << << N / 2 << endl; } return 0; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n = 4; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } if (max(a[2], a[3]) - 1 > min(a[2], a[3])) { cout << -1; return 0; } string ans = ; vector<int> cnt(2, 0); if (a[2] > a[3]) { for (int i = 0; i < a[2]; i++) { ans += 47 ; } } else { if (a[2] == a[3]) { if (a[0] > a[2]) { for (int i = 0; i < a[2]; i++) { ans += 47 ; } ans += 4 ; } else { if (a[1] > a[3]) { ans += 7 ; for (int i = 0; i < a[2]; i++) { ans += 47 ; } } else { cout << -1 << n ; return 0; } } } else { for (int i = 0; i < a[3]; i++) { ans += 74 ; } } } cnt[0] = cnt[1] = 0; for (char c : ans) { if (c == 4 ) cnt[0]++; if (c == 7 ) cnt[1]++; } if (cnt[0] > a[0] || cnt[1] > a[1]) { cout << -1 << n ; return 0; } a[0] -= cnt[0]; a[1] -= cnt[1]; for (int i = 0; i < (int)ans.size(); i++) { if (ans[i] == 4 && a[0] > 0) { string nans = ; for (int j = 0; j <= i; j++) { nans += ans[j]; } for (int j = 0; j < a[0]; j++) { nans += 4 ; } for (int j = i + 1; j < (int)ans.size(); j++) { nans += ans[j]; } swap(ans, nans); break; } } for (int i = (int)ans.size() - 1; i >= 0; i--) { if (ans[i] == 7 && a[1] > 0) { string nans = ; for (int j = 0; j <= i; j++) { nans += ans[j]; } for (int j = 0; j < a[1]; j++) { nans += 7 ; } for (int j = i + 1; j < (int)ans.size(); j++) { nans += ans[j]; } swap(ans, nans); break; } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t, n, num; cin >> t; while (t--) { cin >> n; bool flag = false; unordered_map<int, vector<int>> m; for (int i = 0; i < n; ++i) { cin >> num; m[num].push_back(i); } for (auto& k : m) { if (k.second.back() - k.second.front() >= 2) { flag = true; break; } } if (flag) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> const long long int mod = 1000000007; const long long int AM = 2e5 + 5; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int t; cin >> t; while (t--) { long long int n; cin >> n; string s[n + 1]; for (__typeof(0) i = 0; i < n; ++i) cin >> s[i]; long long int cnt[200] = {0}; for (__typeof(0) i = 0; i < n; ++i) { for (__typeof(0) j = 0; j < s[i].size(); ++j) { cnt[s[i][j] - a ]++; } } long long int flag = 1; for (__typeof(0) i = 0; i < 26; ++i) { if (cnt[i] % n != 0) flag = 0; } if (flag) cout << YES n ; else cout << NO n ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O211AI_FUNCTIONAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_FUNCTIONAL_PP_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
wire wTxLast;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_64 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data. Also make sure to discard only as
// much data as is needed for a transfer (which may involve non-integral
// packets (i.e. reading only 1 word out of the packet).
tx_port_buffer_64 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.LEN_VALID(TX_REQ_ACK),
.LEN_LSB(TX_LEN[0]),
.LEN_LAST(wTxLast),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(wTxLast),
.TX_SENT(TX_SENT)
);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Basic Phase accumulator for DDS
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule // phase_acc
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 23:35:06 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_stub.v
// Design : system_zed_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_vga,Vivado 2016.4" *)
module system_zed_vga_0_0(clk, active, rgb565, vga_r, vga_g, vga_b)
/* synthesis syn_black_box black_box_pad_pin="clk,active,rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]" */;
input clk;
input active;
input [15:0]rgb565;
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int c = 200002; int n, m, maxi, pos = c, cnt, id[c], szint[c], kezd; vector<int> sz[c]; bool v[c], v2[c], jo[c]; void dfs2(int a) { v2[a] = true; bool s = jo[a]; for (int x : sz[a]) { if (!v2[x]) { dfs2(x); if (jo[x]) { s = 1; } } } jo[a] = s; cnt += jo[a] * 2; } void dfs(int a) { if (!jo[a]) { return; } v[a] = true; int x1 = a, x2 = a; for (int x : sz[a]) { if (!v[x]) { szint[x] = szint[a] + 1; dfs(x); int aa = szint[x1], bb = szint[x2], cc = szint[id[x]]; if (cc > bb || (cc == bb && id[x] < x2)) { x2 = id[x]; if (cc > aa || (cc == aa && id[x] < x1)) { swap(x1, x2); } } } } id[a] = x1; int s = szint[x1] + szint[x2] - 2 * szint[a]; if (s > maxi || (s == maxi && min(x1, x2) < pos)) { maxi = s; pos = min(x1, x2); } } int main() { ios_base::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; sz[a].push_back(b), sz[b].push_back(a); } for (int i = 1; i <= m; i++) { int x; cin >> x; kezd = x; jo[x] = 1; } dfs2(kezd), cnt -= 2; szint[kezd] = 1, dfs(kezd); cout << pos << n << cnt - maxi << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, x, y, z, d[200 + 5], nows[200 + 5], fr[200 + 5], en[200 + 5], A[200 + 5], S, T, fa[200 + 5], now, Bh, Ch, B[200 + 5], C[200 + 5], H, un, wn, ToT; struct yyy { int to, w, z; } tmp; struct ljb { int head, h[200 + 5]; yyy f[1000 + 5 << 2]; inline void add(int x, int y, int z) { f[head] = (yyy){y, z, h[x]}; h[x] = head++; } } s, G; queue<int> Q; struct ques { int x, y, z; } F[200 + 5]; inline bool cmp(ques x, ques y) { return x.z > y.z; } inline void Get(int x, int y, int z) { s.add(x, y, z); s.add(y, x, z); } inline int bfs() { while (!Q.empty()) Q.pop(); memset(d, 0x3f, sizeof(d)); d[S] = 0; Q.push(S); nows[S] = s.h[S]; while (!Q.empty()) { now = Q.front(); Q.pop(); for (int i = s.h[now]; ~i; i = tmp.z) { tmp = s.f[i]; if (!tmp.w || d[tmp.to] < 1e9) continue; d[tmp.to] = d[now] + 1; Q.push(tmp.to); nows[tmp.to] = s.h[tmp.to]; if (tmp.to == T) return 1; } } return 0; } inline int dfs(int x, int sum) { if (x == T) return sum; int i, k, pus = 0; yyy tmp; for (i = nows[x]; ~i; i = tmp.z) { tmp = s.f[i]; nows[x] = i; if (!tmp.w || d[tmp.to] != d[x] + 1) continue; k = dfs(tmp.to, ((sum) < (tmp.w) ? (sum) : (tmp.w))); if (!k) d[tmp.to] = 1e9; pus += k; sum -= k; s.f[i].w -= k; s.f[i ^ 1].w += k; if (!sum) break; } return pus; } inline void build(int l, int r) { if (l == r) return; int Ans = 0, i; S = A[l]; T = A[r]; s = G; while (bfs()) Ans += dfs(S, 1e9); F[++H] = (ques){S, T, Ans}; ToT += Ans; Bh = Ch = 0; for (i = l; i <= r; i++) (d[A[i]] < 1e9 ? B[++Bh] : C[++Ch]) = A[i]; for (i = l; i <= l + Bh - 1; i++) A[i] = B[i - l + 1]; for (i = l + Bh; i <= r; i++) A[i] = C[i - l - Bh + 1]; Ans = Bh; build(l, l + Ans - 1); build(l + Ans, r); } inline int Getfa(int x) { return x == fa[x] ? x : fa[x] = Getfa(fa[x]); } int main() { register int i; scanf( %d%d , &n, &m); memset(s.h, -1, sizeof(s.h)); for (i = 1; i <= m; i++) scanf( %d%d%d , &x, &y, &z), Get(x, y, z); for (i = 1; i <= n; i++) A[i] = i; G = s; build(1, n); sort(F + 1, F + n, cmp); for (i = 1; i <= n; i++) fa[i] = en[i] = fr[i] = i; for (i = 1; i < n; i++) un = Getfa(F[i].x), wn = Getfa(F[i].y), en[un] = fr[wn], fr[wn] = fr[un], fa[un] = wn; now = fr[Getfa(1)]; printf( %d n , ToT); while (en[now] ^ now) printf( %d , now), now = en[now]; printf( %d n , now); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKBUF_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_BLACKBOX_V
|
module instr_info_table
(/*AUTOARG*/
// Outputs
vgpr_alu_rd_data, vgpr_lsu_rd_data, sgpr_alu_rd_data,
sgpr_lsu_rd_data, issued_rd_data,
// Inputs
f_decode_valid, clk, rst, f_decode_wfid, decode_wr_data,
f_vgpr_alu_wr_done_wfid, f_vgpr_lsu_wr_done_wfid,
f_sgpr_alu_wr_done_wfid, f_sgpr_lsu_instr_done_wfid, issued_wfid
);
input f_decode_valid;
input clk, rst;
input [`WF_ID_LENGTH-1:0] f_decode_wfid;
input [`ISSUE_INSTR_INFO_LENGTH-1:0] decode_wr_data;
input [`WF_ID_LENGTH-1:0] f_vgpr_alu_wr_done_wfid, f_vgpr_lsu_wr_done_wfid,
f_sgpr_alu_wr_done_wfid, f_sgpr_lsu_instr_done_wfid,
issued_wfid;
output [`ISSUE_INSTR_INFO_LENGTH-1:0] vgpr_alu_rd_data, vgpr_lsu_rd_data,
sgpr_alu_rd_data, sgpr_lsu_rd_data,
issued_rd_data;
wire [`ISSUE_INSTR_INFO_LENGTH-1:0] vgpr_alu_rd_data_tbl, vgpr_lsu_rd_data_tbl,
sgpr_alu_rd_data_tbl, sgpr_lsu_rd_data_tbl;
wire [`WF_PER_CU-1:0] reg_wr_en;
wire [`ISSUE_INSTR_INFO_LENGTH*`WF_PER_CU-1:0] reg_in, reg_out;
assign vgpr_alu_rd_data = (f_decode_valid && f_decode_wfid == f_vgpr_alu_wr_done_wfid)?
decode_wr_data : vgpr_alu_rd_data_tbl;
assign vgpr_lsu_rd_data = (f_decode_valid && f_decode_wfid == f_vgpr_lsu_wr_done_wfid)?
decode_wr_data : vgpr_lsu_rd_data_tbl;
assign sgpr_alu_rd_data = (f_decode_valid && f_decode_wfid == f_sgpr_alu_wr_done_wfid)?
decode_wr_data : sgpr_alu_rd_data_tbl;
assign sgpr_lsu_rd_data = (f_decode_valid && f_decode_wfid == f_sgpr_lsu_instr_done_wfid)?
decode_wr_data : sgpr_lsu_rd_data_tbl;
// Decoder for the write port. Does not enable any port if wr_en is 0
decoder_6b_40b_en wr_port_decoder
(.out(reg_wr_en), .addr_in(f_decode_wfid), .en(f_decode_valid) );
// Muxes for the read ports
mux_40xPARAMb_to_1xPARAMb #(`ISSUE_INSTR_INFO_LENGTH) mux_rd0
(.out(vgpr_alu_rd_data_tbl), .in(reg_out), .select(f_vgpr_alu_wr_done_wfid));
mux_40xPARAMb_to_1xPARAMb #(`ISSUE_INSTR_INFO_LENGTH) mux_rd1
(.out(vgpr_lsu_rd_data_tbl), .in(reg_out), .select(f_vgpr_lsu_wr_done_wfid));
mux_40xPARAMb_to_1xPARAMb #(`ISSUE_INSTR_INFO_LENGTH) mux_rd2
(.out(sgpr_alu_rd_data_tbl), .in(reg_out), .select(f_sgpr_alu_wr_done_wfid));
mux_40xPARAMb_to_1xPARAMb #(`ISSUE_INSTR_INFO_LENGTH) mux_rd3
(.out(sgpr_lsu_rd_data_tbl), .in(reg_out), .select(f_sgpr_lsu_instr_done_wfid));
mux_40xPARAMb_to_1xPARAMb #(`ISSUE_INSTR_INFO_LENGTH) mux_rd5
(.out(issued_rd_data), .in(reg_out), .select(issued_wfid));
// Bank of registerss
reg_param #(`ISSUE_INSTR_INFO_LENGTH) data_bank[`WF_PER_CU-1:0]
( .out(reg_out),
.in(reg_in),
.wr_en(reg_wr_en),
.clk(clk),
.rst(rst) );
assign reg_in = {`WF_PER_CU{decode_wr_data}};
endmodule
|
module ll_crc(/*AUTOARG*/
// Outputs
crc_tx, crc_rx,
// Inputs
clk, rst_n, LLDMARXD, LLDMARXREM, LLDMARXSOFN, LLDMARXEOFN,
LLDMARXSOPN, LLDMARXEOPN, LLDMARXSRCRDYN, DMALLRXDSTRDYN, DMALLTXD,
DMALLTXREM, DMALLTXSOFN, DMALLTXEOFN, DMALLTXSOPN, DMALLTXEOPN,
DMALLTXSRCRDYN, LLDMATXDSTRDYN
);
input clk;
input rst_n;
// local link RX interface
input [31:0] LLDMARXD;
input [3:0] LLDMARXREM;
input LLDMARXSOFN;
input LLDMARXEOFN;
input LLDMARXSOPN;
input LLDMARXEOPN;
input LLDMARXSRCRDYN;
input DMALLRXDSTRDYN;
// local link TX interface
input [31:0] DMALLTXD;
input [3:0] DMALLTXREM;
input DMALLTXSOFN;
input DMALLTXEOFN;
input DMALLTXSOPN;
input DMALLTXEOPN;
input DMALLTXSRCRDYN;
input LLDMATXDSTRDYN;
// crc data out
output [31:0] crc_tx;
output [31:0] crc_rx;
/*AUTOREG*/
/*AUTOWIRE*/
reg tx_start;
reg rx_start;
reg tx_data_valid;
reg rx_data_valid;
reg [31:0] tx_data;
reg [31:0] rx_data;
wire [31:0] data_in;
/**************************************************************************/
always @(posedge clk)
begin
if (!rst_n)
begin
tx_start <= 1'b0;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXSOPN)
begin
tx_start <= 1'b1;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXEOPN)
begin
tx_start <= 1'b0;
end
end
always @(posedge clk)
begin
if (!rst_n)
begin
rx_start <= 1'b0;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXSOPN)
begin
rx_start <= 1'b1;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXEOPN)
begin
rx_start <= 1'b0;
end
end
always @(posedge clk)
begin
if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN)
tx_data <= DMALLTXD;
end
always @(posedge clk)
begin
if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN)
rx_data <= LLDMARXD;
end
always @(posedge clk)
begin
if (!rst_n)
begin
tx_data_valid = 1'b0;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && ~DMALLTXSOPN)
begin
tx_data_valid = 1'b1;
end
else if (~LLDMATXDSTRDYN && ~DMALLTXSRCRDYN && tx_start)
begin
tx_data_valid = 1'b1;
end
else
begin
tx_data_valid = 1'b0;
end
end
always @(posedge clk)
begin
if (!rst_n)
begin
rx_data_valid = 1'b0;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && ~LLDMARXSOPN)
begin
rx_data_valid = 1'b1;
end
else if (~LLDMARXSRCRDYN && ~DMALLRXDSTRDYN && rx_start)
begin
rx_data_valid = 1'b1;
end
else
begin
rx_data_valid = 1'b0;
end
end
assign crc_rst = ~rst_n;
/**************************************************************************/
wire [31:0] crc_tx;
wire [31:0] crc_rx;
crc
crc0(.crc_out(crc_tx),
.data_in(tx_data),
.data_valid(tx_data_valid),
/*AUTOINST*/
// Inputs
.clk (clk),
.crc_rst (crc_rst));
crc
crc1(.crc_out(crc_rx),
.data_in(rx_data),
.data_valid(rx_data_valid),
/*AUTOINST*/
// Inputs
.clk (clk),
.crc_rst (crc_rst));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-files:("lldma_exerciser.v")
// verilog-library-extensions:(".v" ".h")
// End:
|
#include <bits/stdc++.h> using namespace std; int v[1005]; int a[1005], b[1005]; char s[1005]; vector<int> c, d; int main() { cin >> s + 1; int len = strlen(s + 1); int num = 0; for (int i = 1; i <= len; i++) { if (s[i] == ( ) { a[i]++; c.push_back(i); } a[i] += a[i - 1]; } for (int i = len; i; i--) { if (s[i] == ) ) { d.push_back(i); b[i]++; } b[i] += b[i - 1]; } sort((d).begin(), (d).end()); int l = 0, r = d.size() - 1; while (l < c.size() && r >= 0 && c[l] < d[r]) { l++; r--; num++; } if (!num) puts( 0 ); else { puts( 1 ); cout << l + d.size() - r - 1 << endl; for (int i = 0; i < l; i++) cout << c[i] << ; for (int i = r + 1; i < d.size(); i++) cout << d[i] << ; } return 0; }
|
module act_led(
clk,
reset,
gmii_rxen,
gmii_txen,
r_act_sfp);
input clk;
input reset;
input gmii_rxen;
input gmii_txen;
output r_act_sfp;
reg [23:0] count_led;
reg r_act_sfp;
reg [1:0]current_state;
parameter idle=2'b0,
first =2'b01,
second=2'b10;
always@(posedge clk or negedge reset)
if(!reset)
begin
count_led <= 24'b0;
r_act_sfp <= 1'b1;
current_state <= idle;
end
else
begin
case(current_state)
idle:
begin
count_led <= 24'b0;
if((gmii_rxen == 1'b1)||(gmii_txen == 1'b1))
begin
r_act_sfp <= 1'b0;
current_state <= first;
end
else
begin
r_act_sfp <= 1'b1;
current_state <= idle;
end
end
first:
begin
count_led <= count_led+1'b1;
if(count_led[23] == 1'b1)
begin
r_act_sfp <= 1'b1;
count_led <= 24'b0;
current_state <= second;
end
else
begin
current_state <= first;
end
end
second:
begin
if(count_led[23] == 1'b1)
begin
current_state <= idle;
end
else
begin
count_led <= count_led+1'b1;
current_state <= second;
end
end
default:
begin
current_state <= idle;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:21:30 05/20/2014
// Design Name: alu
// Module Name: C:/Users/Deus/Windows Sync/Xilinx Workspace/Single/test_alu.v
// Project Name: Single
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_alu;
// Inputs
reg [3:0] alu_ctl;
reg [31:0] A;
reg [31:0] B;
// Outputs
wire zero;
wire [31:0] result;
// Instantiate the Unit Under Test (UUT)
alu uut (
.alu_ctl(alu_ctl),
.A(A),
.B(B),
.zero(zero),
.result(result)
);
initial begin
// Initialize Inputs
alu_ctl = 0;
A = 0;
B = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 32'h01234567;
B = 32'h3456789A;
# 100;
alu_ctl = 4'b0001;
# 100;
alu_ctl = 4'b0010;
# 100;
alu_ctl = 4'b0011;
# 100;
alu_ctl = 4'b0100;
# 100;
alu_ctl = 4'b0101;
# 100;
alu_ctl = 4'b0110;
# 100;
alu_ctl = 4'b0111;
# 100;
alu_ctl = 4'b1000;
# 100;
alu_ctl = 4'b1001;
# 100;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 10003; int32_t main() { int n, a, b, c; cin >> n >> a >> b >> c; if (n == 1) { cout << 0 ; return 0; } n--; long long ans = 0; ans += min(a, b); n--; if (min(a, b) > c) { ans += n * c; cout << ans; return 0; } ans += n * min(a, b); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1E9; int main() { int n; string s; cin >> n >> s; for (int len = 1; len <= n; len++) { bool ok = true; for (int i = 0; i < n; i++) { if (i + len * 4 < n && s[i] == * && s[i] == s[i + len] && s[i] == s[i + len + len] && s[i] == s[i + len * 3] && s[i] == s[i + len * 4]) { ok = 0; break; } } if (!ok) { puts( yes ); return 0; } } puts( no ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 500004; long long p, pos1, pos2, q, x, l, ans = 0, r, y, z, k, n, m, t, d, c = 0, sum = 0; long long int mn = 0x3f3f3f3f, len, cnt = 1, mx = -1000; std::vector<int> v[MAX]; string s[10004], s1, s2; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> s[i]; m += s[i].size(); } cin >> s1; int len = 2 * m / n; for (int i = 0; i < n; i++) s[i] += s1; sort(s, s + n); int a[n]; memset(a, (0), sizeof(a)); for (int i = 0; i < n / 2; i++) { for (int j = 0; j < n; j++) { if (!a[j]) { cout << s[j]; x = s[j].size(); ++a[j]; break; } } for (int j = 0; j < n; j++) { if (!a[j] and s[j].size() == len - x + 2) { cout << s[j].substr(0, s[j].size() - 1); ++a[j]; break; } } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, k, y, a, b, c; long long A[2005]; bool B[2005]; int main() { cin >> n >> k; priority_queue<pair<int, int> > pq; for (int i = int(0); i < int(n); i++) { cin >> A[i]; pq.push({A[i], i}); } int ans = 0; for (int i = int(0); i < int(k); i++) { B[pq.top().second] = true; ans += pq.top().first; pq.pop(); } cout << ans << n ; m = -1; int t = 0; for (int i = int(0); i < int(n); i++) { if (B[i] && t + 1 < k) { cout << i - m << ; m = i; t++; } } cout << n - 1 - m << n ; }
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Basic Function Block for VVI_VRP
//defines for state names used internally
`define STATE_Start 0
`define STATE_Wait_For_VSense 1
`define STATE_Resting 2
`define STATE_Detected_VPulse 3
`define STATE_Detected_VRefractory 4
module FB_VVI_VRP
(
input wire clk,
//input events
input wire VPulse_eI,
input wire VPace_eI,
input wire VRP_Timer_Timeout_eI,
//output events
output wire VRP_Start_Timer_eO,
output wire VSense_eO,
output wire VRefractory_eO,
//output variables
output reg signed [15:0] VRP_Timeout_Value_O ,
input reset
);
////BEGIN internal copies of I/O
//input events
wire VPulse;
assign VPulse = VPulse_eI;
wire VPace;
assign VPace = VPace_eI;
wire VRP_Timer_Timeout;
assign VRP_Timer_Timeout = VRP_Timer_Timeout_eI;
//output events
reg VRP_Start_Timer;
assign VRP_Start_Timer_eO = VRP_Start_Timer;
reg VSense;
assign VSense_eO = VSense;
reg VRefractory;
assign VRefractory_eO = VRefractory;
//output variables
reg signed [15:0] VRP_Timeout_Value ;
////END internal copies of I/O
////BEGIN internal vars
////END internal vars
//BEGIN STATE variables
reg [2:0] state = `STATE_Start;
reg entered = 1'b0;
//END STATE variables
//BEGIN algorithm triggers
reg VRP_Set_Timeout_Value_alg_en = 1'b0;
//END algorithm triggers
always@(posedge clk) begin
if(reset) begin
//reset state
state = `STATE_Start;
//reset I/O registers
VRP_Start_Timer = 1'b0;
VSense = 1'b0;
VRefractory = 1'b0;
VRP_Timeout_Value = 0;
//reset internal vars
end else begin
//BEGIN clear output events
VRP_Start_Timer = 1'b0;
VSense = 1'b0;
VRefractory = 1'b0;
//END clear output events
//BEGIN update internal inputs on relevant events
//END update internal inputs
//BEGIN ecc
entered = 1'b0;
case(state)
`STATE_Start: begin
if(1) begin
state = `STATE_Detected_VPulse;
entered = 1'b1;
end
end
`STATE_Wait_For_VSense: begin
if(VPulse) begin
state = `STATE_Resting;
entered = 1'b1;
end else if(VPace) begin
state = `STATE_Resting;
entered = 1'b1;
end
end
`STATE_Resting: begin
if(VPulse) begin
state = `STATE_Detected_VRefractory;
entered = 1'b1;
end else if(VRP_Timer_Timeout) begin
state = `STATE_Wait_For_VSense;
entered = 1'b1;
end
end
`STATE_Detected_VPulse: begin
if(VRP_Timer_Timeout) begin
state = `STATE_Wait_For_VSense;
entered = 1'b1;
end
end
`STATE_Detected_VRefractory: begin
if(1) begin
state = `STATE_Resting;
entered = 1'b1;
end
end
default: begin
state = 0;
end
endcase
//END ecc
//BEGIN triggers
VRP_Set_Timeout_Value_alg_en = 1'b0;
if(entered) begin
case(state)
`STATE_Start: begin
end
`STATE_Wait_For_VSense: begin
end
`STATE_Resting: begin
VRP_Set_Timeout_Value_alg_en = 1'b1;
VRP_Start_Timer = 1'b1;
VSense = 1'b1;
end
`STATE_Detected_VPulse: begin
VRP_Set_Timeout_Value_alg_en = 1'b1;
VRP_Start_Timer = 1'b1;
end
`STATE_Detected_VRefractory: begin
VRefractory = 1'b1;
end
default: begin
end
endcase
end
//END triggers
//BEGIN algorithms
if(VRP_Set_Timeout_Value_alg_en) begin
VRP_Timeout_Value = 300;
end
//END algorithms
//BEGIN update external output variables on relevant events
if(VRP_Start_Timer) begin
VRP_Timeout_Value_O = VRP_Timeout_Value;
end
//END update external output variables
end
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// testbench for fullchip
module decim_tb();
`include "usrp_tasks.v"
reg clk_120mhz;
reg usbclk;
reg reset;
reg [11:0] adc1_data, adc2_data;
wire [13:0] dac1_data, dac2_data;
wire [5:0] usbctl;
wire [5:0] usbrdy;
wire [15:0] usbdata;
reg WE, RD, OE;
assign usbctl[0] = WE;
assign usbctl[1] = RD;
assign usbctl[2] = OE;
assign usbctl[5:3] = 0;
reg tb_oe;
assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
reg serload, serenable, serclk, serdata;
reg enable_tx, enable_rx;
reg [15:0] usbdatareg;
///////////////////////////////////////////////
// Simulation Control
initial
begin
$dumpfile("decim_tb.vcd");
$dumpvars(0, fc_tb);
end
initial #100000 $finish;
///////////////////////////////////////////////
// Monitors
reg [7:0] counter_decim;
wire [7:0] decim_rate;
assign decim_rate = 32;
initial $monitor(dac1_data);
always @(posedge clk_120mhz)
begin
if(reset | ~enable_tx)
counter_decim <= #1 0;
else if(counter_decim == 0)
counter_decim <= #1 decim_rate - 8'b1;
else
counter_decim <= #1 counter_decim - 8'b1;
end
///////////////////////////////////////////////
// Clock and reset
initial clk_120mhz = 0;
initial usbclk = 0;
always #48 clk_120mhz = ~clk_120mhz;
always #120 usbclk = ~usbclk;
initial reset = 1'b1;
initial #500 reset = 1'b0;
initial enable_tx = 1'b1;
wire [31:0] decim_out, q_decim_out;
wire [31:0] decim_out;
wire [31:0] phase;
cic_decim #(.bitwidth(32),.stages(4))
decim_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
.strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
cic_decim #(.bitwidth(32),.stages(4))
decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
.strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
endmodule
|
//------------------------------------------- cpu.v ????? -------------------------------------------
/******************************************************************************
*** ?????CPU ?????????RISC_ CPU???, ??????????
*** ????????????????????????????
*****************************************************************************/
`include "clk_gen.v"
`include "accum.v"
`include "adr.v"
`include "alu.v"
`include "machine.v"
`include "counter.v"
`include "machinectl.v"
`include "register.v"
`include "datactl.v"
module cpu(clk,reset,halt,rd,wr,addr,data);
input clk,reset;
output rd,wr,addr,halt;
inout data;
wire clk,reset,halt;
wire [7:0] data;
wire [12:0] addr;
wire rd,wr;
wire clk1,fetch,alu_clk;
wire [2:0] opcode;
wire [12:0] ir_addr,pc_addr;
wire [7:0] alu_out,accum;
wire zero,inc_pc,load_acc,load_pc,load_ir,data_ena,contr_ena;
clk_gen m_clk_gen (.clk(clk),.clk1(clk1),.fetch(fetch),
.alu_clk(alu_clk),.reset(reset));
register m_register (.data(data),.ena(load_ir),.rst(reset),
.clk1(clk1),.opc_iraddr({opcode,ir_addr}));
accum m_accum (.data(alu_out),.ena(load_acc),
.clk1(clk1),.rst(reset),.accum(accum));
alu m_alu (.data(data),.accum(accum),.alu_clk(alu_clk),
.opcode(opcode),.alu_out(alu_out),.zero(zero));
machinectl m_machinecl(.ena(contr_ena),.fetch(fetch),.rst(reset));
machine m_machine (.inc_pc(inc_pc),.load_acc(load_acc),.load_pc(load_pc),
.rd(rd), .wr(wr), .load_ir(load_ir), .clk1(clk1),
.datactl_ena(data_ena), .halt(halt), .zero(zero),
.ena(contr_ena),.opcode(opcode));
datactl m_datactl (.in(alu_out),.data_ena(data_ena),.data(data));
adr m_adr (.fetch(fetch),.ir_addr(ir_addr),.pc_addr(pc_addr),.addr(addr));
counter m_counter (.ir_addr(ir_addr),.load(load_pc),.clock(inc_pc),
.rst(reset),.pc_addr(pc_addr));
endmodule
//--------------------------------------- cpu.v ????? -------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); template <class T> void out(const vector<T> &a) { cout << array: ; for (int i = 0; i < (int)a.size(); i++) cout << a[i] << ; cout << endl; cout.flush(); } template <class T> T gcd(T a, T b) { return (b == 0) ? a : gcd(b, a % b); } template <class T> T Abs(T x) { return x > 0 ? x : -x; } template <class T> inline bool isPrime(T n) { if (n <= 1) return false; for (T i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } template <class T> T lcm(T a, T b) { return a * (b / gcd(a, b)); } template <typename T> static T mod(T a, T b) { a %= b; if (a < 0) a += b; return a; } template <class T> string toString(T n) { ostringstream oss; oss << n; oss.flush(); return oss.str(); } template <typename T> static void splitstr(const string &s, vector<T> &out) { istringstream in(s); out.clear(); copy(istream_iterator<T>(in), istream_iterator<T>(), back_inserter(out)); } int toInt(string s) { int r = 0; istringstream sin(s); sin >> r; return r; } long long toLl(string s) { long long r = 0; istringstream sin(s); sin >> r; return r; } bool IsVowel(char ch) { ch = tolower(ch); if (ch == a || ch == e || ch == i || ch == o || ch == u ) return true; return false; } int BigMod(long long B, long long P, long long M) { long long R = 1; while (P > 0) { if (P % 2 == 1) { R = (R * B) % M; } P /= 2; B = (B * B) % M; } return (int)R; } long long mulmod(long long a, long long b, long long c) { long long x = 0, y = a % c; while (b > 0) { if (b % 2 == 1) { x = (x + y) % c; } y = (y * 2) % c; b /= 2; } return x % c; } void binprint(int mask, int n) { int i; string s = ; do { s += (mask % 2 + 0 ); mask /= 2; } while (mask); reverse(s.begin(), s.end()); s = string((n - (int)s.size() > 0 ? n - (int)s.size() : 0), 0 ) + s; for (i = (int)s.size() - n; i < (int)s.size(); i++) printf( %c , s[i]); printf( n ); } long long mpow(long long x, long long k) { if (k == 0) return 1; long long r = mpow(x, k / 2); return k % 2 ? (r * r * x) : (r * r); } int main() { long long n, k, x[500], cnt, i; cin >> n >> k; for (i = 0; i < n; i++) cin >> x[i]; cnt = 0; while (x[0] != k) { for (i = 0; i < n - 1; i++) { if (x[i] != x[i + 1]) x[i]++; } x[n - 1]++; cnt++; } cout << cnt << endl; return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
parameter CHANGE_START = 1'b0;
parameter CHANGE_CHECK = 1'b1;
reg r_change;
reg [width-1:0] r_test_expr;
reg r_state;
integer i;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=CHANGE_START;
r_change=1'b0;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
CHANGE_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (start_event == 1'b1) begin
r_change <= 1'b0;
r_state <= CHANGE_CHECK;
r_test_expr <= test_expr;
i <= num_cks;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
end
CHANGE_CHECK: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// Count clock ticks
if (start_event == 1'b1) begin
if (action_on_new_start == `OVL_IGNORE_NEW_START && i > 0)
i <= i-1;
else if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
r_change <= 1'b0;
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
ovl_cover_t("window_resets covered");
end
end
end
`endif // OVL_COVER_ON
end
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
i <= i-1;
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Start event evaluated TRUE before test expression changed");
`endif // OVL_ASSERT_ON
end
end
else if (i > 0)
i <= i-1;
if (r_test_expr != test_expr && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_change <= 1'b1;
end
// go to start state on last check
if (i == 1 && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_state <= CHANGE_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_close covered");
end
end
`endif // OVL_COVER_ON
// Check that the property is true
`ifdef OVL_ASSERT_ON
if ((r_change != 1'b1) && (r_test_expr == test_expr)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression did not change value within num_cks cycles after start event");
end
`endif // OVL_ASSERT_ON
end
r_test_expr <= test_expr;
end
endcase
end
else begin
r_state <= CHANGE_START;
r_change <= 1'b0;
i <= 0;
`ifdef OVL_INIT_REG
r_test_expr <= {width{1'b0}};
`endif
end
end // always
`endif // OVL_SHARED_CODE
|
module etx_remap (/*AUTOARG*/
// Outputs
emesh_access_out, emesh_packet_out,
// Inputs
clk, nreset, emesh_access_in, emesh_packet_in, remap_en, etx_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
//Clock
input clk;
input nreset;
//Input from arbiter
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
input remap_en; //enable tx remap (static)
//Output to TX IO
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
//Wait signals from protocol block
input etx_wait;
wire [31:0] addr_in;
wire [31:0] addr_remap;
wire [31:0] addr_out;
wire write_in;
reg emesh_access_out;
reg [PW-1:0] emesh_packet_out;
packet2emesh #(.AW(AW))
p2e (// Outputs
.write_in (write_in),
.datamode_in (),
.ctrlmode_in (),
.data_in (),
.dstaddr_in (addr_in[31:0]),
.srcaddr_in (),
// Inputs
.packet_in (emesh_packet_in[PW-1:0]));
assign addr_remap[31:0] = {addr_in[29:18], //ID
addr_in[17:16], //SPECIAL GROUP
{(2){(|addr_in[17:16])}},//ZERO IF NOT SPECIAL
addr_in[15:0]
};
assign addr_out[31:0] = remap_en ? addr_remap[31:0] :
addr_in[31:0];
//stall read/write access appropriately
always @ (posedge clk)
if(!nreset)
emesh_access_out <= 1'b0;
else if(~etx_wait)
emesh_access_out <= emesh_access_in;
always @ (posedge clk)
if(~etx_wait)
emesh_packet_out[PW-1:0] <= {emesh_packet_in[PW-1:40],
addr_out[31:0],
emesh_packet_in[7:0]
};
endmodule // etx_remap
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
|
/*
# ZUMA Open FPGA Overlay
# Alex Brant
# Email:
# 2012
# LUTRAM wrapper
*/
/* These luts are used for building configurable muxes.*/
`include "define.v"
`include "def_generated.v"
`include "primitives.v"
module lut_custom #(
parameter used = 0,
parameter LUT_MASK={2**K{1'b0}}
) (
a,
d,
dpra,
clk,
we,
dpo);
input [ZUMA_LUT_SIZE-1 : 0] a;
input [0 : 0] d;
input [ZUMA_LUT_SIZE-1 : 0] dpra;
input clk;
input we;
output dpo;
wire lut_output;
//no plattform. just for a verificational build.
`ifdef ZUMA_VERIFICATION
generate
if( used == 0)
//nothing will be generated and connected
else
//we generate a lut
LUT_K #(
.K(ZUMA_LUT_SIZE),
.LUT_MASK(LUT_MASK)
) verification_lut (
.in(dpra),
.out(lut_output)
);
endgenerate
`elsif PLATFORM_XILINX
lut_xilinx LUT (
.a(a), // input [5 : 0] a
.d(d), // input [0 : 0] d
.dpra( dpra ), // input [5 : 0] dpra
.clk(clk), // input clk
.we(we), // input we
.dpo( lut_output ));
`elsif PLATFORM_ALTERA
SDPR LUT(
.clock(clk),
.data(d),
.rdaddress(dpra),
.wraddress(a),
.wren(we),
.q(lut_output));
`endif
`ifdef SIMULATION //X'd inputs will break the simulation
assign dpo = (lut_output === 1'bx) ? 0 : lut_output ;
`else
assign dpo = lut_output;
`endif
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: trellis.vh
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The reset_controller module will safely reset a single stage
// pipeline without using an asychronous reset (bleh). It is intended for use in
// the TX engines, where it will control the output stage of the engine, and
// provide a gracefull end-of-packet reset
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`define S_RC_IDLE 3'b001
`define S_RC_WAIT 3'b010
`define S_RC_ACTIVE 3'b100
`include "trellis.vh"
module reset_controller
#(parameter C_RST_COUNT = 10)
(
input CLK,
input RST_IN,
output DONE_RST,
output WAITING_RESET,
output RST_OUT,
input SIGNAL_RST,
input WAIT_RST,
input NEXT_CYC_RST);
localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
reg [2:0] _rState,rState;
wire [C_CLOG2_RST_COUNT:0] wRstCount;
assign DONE_RST = rState[0];
assign WAITING_RESET = rState[1] & NEXT_CYC_RST;
assign RST_OUT = rState[2];
counter
#(// Parameters
.C_MAX_VALUE (C_CEIL2_RST_COUNT),
.C_SAT_VALUE (C_CEIL2_RST_COUNT),
.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
/*AUTOINSTPARAM*/)
rst_counter
(// Outputs
.VALUE (wRstCount),
// Inputs
.ENABLE (1'b1),
.RST_IN (~rState[2] | RST_IN),
/*AUTOINST*/
// Inputs
.CLK (CLK));
always @(posedge CLK) begin
if(RST_IN) begin
rState <= `S_RC_ACTIVE;
end else begin
rState <= _rState;
end
end
always @(*) begin
_rState = rState;
case(rState)
`S_RC_IDLE:begin
if(SIGNAL_RST & WAIT_RST) begin
_rState = `S_RC_WAIT;
end else if(SIGNAL_RST) begin
_rState = `S_RC_ACTIVE;
end
end
`S_RC_WAIT:begin
if(NEXT_CYC_RST) begin
_rState = `S_RC_ACTIVE;
end
end
`S_RC_ACTIVE:begin
if(wRstCount[C_CLOG2_RST_COUNT] & ~SIGNAL_RST) begin
_rState = `S_RC_IDLE;
end
end
default: _rState = rState;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_4_V
`define SKY130_FD_SC_LS__CLKINV_4_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_4_V
|
#include <bits/stdc++.h> using namespace std; int n, a[1050]; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int tens = a[0]; set<int> answer; for (int rem = 0; rem < 10000000; rem++) { double fuel = tens * 10 + static_cast<double>(rem) / 1000000; double addend = fuel; bool isValid = true; for (int i = 0; isValid and i < n; i++) { fuel -= (a[i] - (i == 0 ? 0 : a[i - 1])) * 10; if (fuel < 0 or fuel >= 10 - 1e-6) { isValid = false; } fuel += addend; } if (isValid) { answer.insert(static_cast<int>(fuel) / 10 + a[n - 1]); } } if (answer.size() > 1) cout << not unique << endl; else cout << unique << endl << *answer.begin() << endl; return 0; }
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931277432880;
wire exception_139931279890840;
wire exception_139931280051304;
wire exception_139931280661824;
wire exception_139931277613032;
wire exception_139931283220816;
wire exception_139931280153560;
wire exception_139931283967224;
wire exception_139931283888392;
wire exception_139931280075592;
wire exception_139931282543896;
wire exception_139931276992952;
wire exception_139931279971968;
wire exception_139931281943368;
wire exception_139931281898672;
wire exception_139931278253376;
wire exception_139931284125744;
main_0 main_0_139931277432880(
.clk(clk),
.rst(rst),
.exception(exception_139931277432880),
.input_rs232_rx(input_rs232_rx),
.input_rs232_rx_stb(input_rs232_rx_stb),
.input_rs232_rx_ack(input_rs232_rx_ack),
.output_rs232_tx(output_rs232_tx),
.output_rs232_tx_stb(output_rs232_tx_stb),
.output_rs232_tx_ack(output_rs232_tx_ack));
main_1 main_1_139931279890840(
.clk(clk),
.rst(rst),
.exception(exception_139931279890840),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931280051304(
.clk(clk),
.rst(rst),
.exception(exception_139931280051304),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_3 main_3_139931280661824(
.clk(clk),
.rst(rst),
.exception(exception_139931280661824),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_4 main_4_139931277613032(
.clk(clk),
.rst(rst),
.exception(exception_139931277613032),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_5 main_5_139931283220816(
.clk(clk),
.rst(rst),
.exception(exception_139931283220816),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_6 main_6_139931280153560(
.clk(clk),
.rst(rst),
.exception(exception_139931280153560),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_7 main_7_139931283967224(
.clk(clk),
.rst(rst),
.exception(exception_139931283967224),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_8 main_8_139931283888392(
.clk(clk),
.rst(rst),
.exception(exception_139931283888392),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_9 main_9_139931280075592(
.clk(clk),
.rst(rst),
.exception(exception_139931280075592),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_10 main_10_139931282543896(
.clk(clk),
.rst(rst),
.exception(exception_139931282543896),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_11 main_11_139931276992952(
.clk(clk),
.rst(rst),
.exception(exception_139931276992952),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_12 main_12_139931279971968(
.clk(clk),
.rst(rst),
.exception(exception_139931279971968),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_13 main_13_139931281943368(
.clk(clk),
.rst(rst),
.exception(exception_139931281943368),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_14 main_14_139931281898672(
.clk(clk),
.rst(rst),
.exception(exception_139931281898672),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_15 main_15_139931278253376(
.clk(clk),
.rst(rst),
.exception(exception_139931278253376),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_16 main_16_139931284125744(
.clk(clk),
.rst(rst),
.exception(exception_139931284125744),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931277432880 || exception_139931279890840 || exception_139931280051304 || exception_139931280661824 || exception_139931277613032 || exception_139931283220816 || exception_139931280153560 || exception_139931283967224 || exception_139931283888392 || exception_139931280075592 || exception_139931282543896 || exception_139931276992952 || exception_139931279971968 || exception_139931281943368 || exception_139931281898672 || exception_139931278253376 || exception_139931284125744;
endmodule
|
//#############################################################################
//# Function: Latch data when clk=0 #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_lat0 #(parameter DW = 1 // data width
)
( input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : g0
asic_lat0 ilat [DW-1:0] (.clk(clk),
.in(in[DW-1:0]),
.out(out[DW-1:0]));
end
else
begin : g0
reg [DW-1:0] out_reg;
always @ (clk or in)
if (!clk)
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
end // else: !if(ASIC)
endgenerate
endmodule // oh_lat0
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; template <class T> void dbg(const char* xn, T x) { if (0) cout << xn << : << x << n ; } template <class T, class... TA> void dbg(const char* xn, T x, TA... t) { while (*xn != , ) if (0) cout << *xn++; if (0) cout << : << x << , ; dbg(xn + 1, t...); } template <class T> inline bool upd_max(T& x, T y) { return y > x ? x = y, true : false; } template <class T> inline bool upd_min(T& x, T y) { return y < x ? x = y, true : false; } const int N = 1000007; long long n, m1 = 0, m0 = 0, n1 = 0, n0 = 0; string A, B; void solve() { cin >> n; cin >> A; A = # + A; cin >> B; B = # + B; for (long long i = 1; i <= (n); ++i) { if (A[i] == 1 ) ++n1; else if (A[i] == 0 ) ++n0; if (A[i] == 1 && B[i] == 0 ) ++m1; if (A[i] == 0 && B[i] == 0 ) ++m0; } cout << m1 * n0 + m0 * n1 - m1 * m0; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(10); solve(); return 0; }
|
`timescale 1ns/10ps
(* whitebox *)
(* keep *)
module ASSP (
WB_CLK,
WBs_ACK,
WBs_RD_DAT,
WBs_BYTE_STB,
WBs_CYC,
WBs_WE,
WBs_RD,
WBs_STB,
WBs_ADR,
SDMA_Req,
SDMA_Sreq,
SDMA_Done,
SDMA_Active,
FB_msg_out,
FB_Int_Clr,
FB_Start,
FB_Busy,
WB_RST,
Sys_PKfb_Rst,
Sys_Clk0,
Sys_Clk0_Rst,
Sys_Clk1,
Sys_Clk1_Rst,
Sys_Pclk,
Sys_Pclk_Rst,
Sys_PKfb_Clk,
FB_PKfbData,
WBs_WR_DAT,
FB_PKfbPush,
FB_PKfbSOF,
FB_PKfbEOF,
Sensor_Int,
FB_PKfbOverflow,
TimeStamp,
Sys_PSel,
SPIm_Paddr,
SPIm_PEnable,
SPIm_PWrite,
SPIm_PWdata,
SPIm_PReady,
SPIm_PSlvErr,
SPIm_Prdata,
Device_ID
);
input wire WB_CLK;
input wire WBs_ACK;
input wire [31:0] WBs_RD_DAT;
output wire [3:0] WBs_BYTE_STB;
output wire WBs_CYC;
output wire WBs_WE;
output wire WBs_RD;
output wire WBs_STB;
output wire [16:0] WBs_ADR;
input wire [3:0] SDMA_Req;
input wire [3:0] SDMA_Sreq;
output wire [3:0] SDMA_Done;
output wire [3:0] SDMA_Active;
input wire [3:0] FB_msg_out;
input wire [7:0] FB_Int_Clr;
output wire FB_Start;
input wire FB_Busy;
output wire WB_RST;
output wire Sys_PKfb_Rst;
output wire Sys_Clk0;
output wire Sys_Clk0_Rst;
output wire Sys_Clk1;
output wire Sys_Clk1_Rst;
output wire Sys_Pclk;
output wire Sys_Pclk_Rst;
input wire Sys_PKfb_Clk;
input wire [31:0] FB_PKfbData;
output wire [31:0] WBs_WR_DAT;
input wire [3:0] FB_PKfbPush;
input wire FB_PKfbSOF;
input wire FB_PKfbEOF;
output wire [7:0] Sensor_Int;
(* DELAY_MATRIX_FB_PKfbPush="{iopath_FB_PKfbPush0_FB_PKfbOverflow} {iopath_FB_PKfbPush1_FB_PKfbOverflow} {iopath_FB_PKfbPush2_FB_PKfbOverflow} {iopath_FB_PKfbPush3_FB_PKfbOverflow}" *)
output wire FB_PKfbOverflow;
output wire [23:0] TimeStamp;
input wire Sys_PSel;
input wire [15:0] SPIm_Paddr;
input wire SPIm_PEnable;
input wire SPIm_PWrite;
input wire [31:0] SPIm_PWdata;
(* DELAY_CONST_Sys_PSel="{iopath_Sys_PSel_SPIm_PReady}" *)
output wire SPIm_PReady;
(* DELAY_CONST_Sys_PSel="{iopath_Sys_PSel_SPIm_PSlvErr}" *)
output wire SPIm_PSlvErr;
(* DELAY_MATRIX_Sys_PSel= "{iopath_Sys_PSel_SPIm_Prdata0} {iopath_Sys_PSel_SPIm_Prdata1} {iopath_Sys_PSel_SPIm_Prdata2} {iopath_Sys_PSel_SPIm_Prdata3} {iopath_Sys_PSel_SPIm_Prdata4} {iopath_Sys_PSel_SPIm_Prdata5} {iopath_Sys_PSel_SPIm_Prdata6} {iopath_Sys_PSel_SPIm_Prdata7} {iopath_Sys_PSel_SPIm_Prdata8} {iopath_Sys_PSel_SPIm_Prdata9} {iopath_Sys_PSel_SPIm_Prdata10} {iopath_Sys_PSel_SPIm_Prdata11} {iopath_Sys_PSel_SPIm_Prdata12} {iopath_Sys_PSel_SPIm_Prdata13} {iopath_Sys_PSel_SPIm_Prdata14} {iopath_Sys_PSel_SPIm_Prdata15} {iopath_Sys_PSel_SPIm_Prdata16} {iopath_Sys_PSel_SPIm_Prdata17} {iopath_Sys_PSel_SPIm_Prdata18} {iopath_Sys_PSel_SPIm_Prdata19} {iopath_Sys_PSel_SPIm_Prdata20} {iopath_Sys_PSel_SPIm_Prdata21} {iopath_Sys_PSel_SPIm_Prdata22} {iopath_Sys_PSel_SPIm_Prdata23} {iopath_Sys_PSel_SPIm_Prdata24} {iopath_Sys_PSel_SPIm_Prdata25} {iopath_Sys_PSel_SPIm_Prdata26} {iopath_Sys_PSel_SPIm_Prdata27} {iopath_Sys_PSel_SPIm_Prdata28} {iopath_Sys_PSel_SPIm_Prdata29} {iopath_Sys_PSel_SPIm_Prdata30} {iopath_Sys_PSel_SPIm_Prdata31}" *)
output wire [31:0] SPIm_Prdata;
input wire [15:0] Device_ID;
// dummy assignents to mark combinational depenedencies
assign SPIm_Prdata = (Sys_PSel == 1'b1) ? 32'h00000000 : 32'h00000000;
assign SPIm_PReady = (Sys_PSel == 1'b1) ? 1'b0 : 1'b0;
assign SPIm_PSlvErr = (Sys_PSel == 1'b1) ? 1'b0 : 1'b0;
assign FB_PKfbOverflow = (FB_PKfbPush != 4'b0000) ? 1'b0 : 1'b0;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_pixelq_op_img_rows_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_pixelq_op_img_rows_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_rows_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_rows_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_0_V
`define SKY130_FD_SC_HD__EINVN_0_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvn_0 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__einvn_0 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_0_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; long long res = 0; cin >> n >> m; int v[n]; for (int i = 0; i < n; i++) { cin >> v[i]; } for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; res += min(v[x - 1], v[y - 1]); } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t[3000]; int main() { int n, k; cin >> n >> k; string s; cin >> s; for (int i = 0; i < n; i++) { t[s[i]] += 1; } int lk = t[ A ]; for (char c = A ; c < A + k; c++) { if (t[c] < lk) { lk = t[c]; } } cout << lk * k; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int N = 1234567; int x[N], y[N]; int n; double areas[N]; void line(int i, int j, double &a, double &b, double &c) { i %= n; j %= n; a = y[j] - y[i]; b = x[i] - x[j]; c = -a * x[i] - b * y[i]; } void intersect(double a, double b, double c, double aa, double bb, double cc, double &dx, double &dy) { double d = a * bb - b * aa; dx = (b * cc - c * bb) / d; dy = (c * aa - a * cc) / d; } int main() { int q; scanf( %d %d , &n, &q); for (int i = 0; i < n; i++) scanf( %d %d , x + i, y + i); reverse(x, x + n); reverse(y, y + n); areas[0] = 0; for (int i = 0; i < 4 * n; i++) areas[i + 1] = areas[i] + (x[i % n] - x[(i + 1) % n]) * 1.0 * (y[i % n] + y[(i + 1) % n]); double total_area = 0.0; for (int i = 0; i < n; i++) total_area += (x[i] - x[(i + 1) % n]) * 1.0 * (y[i] + y[(i + 1) % n]); for (int i = 0; i < q; i++) { int qx, qy; scanf( %d %d , &qx, &qy); double low = 0, high = pi; double zero = -1.0; bool found = false; double ans = -1.0; for (int it = 0; it < 120; it++) { double mid = 0.5 * (low + high); if (mid == low || mid == high) break; if (it == 0) mid = low; double dx = cos(mid); double dy = sin(mid); double a = dy; double b = -dx; double c = -a * qx - b * qy; double u0 = a * x[0] + b * y[0] + c; double u1 = a * x[1] + b * y[1] + c; bool flag = false; if (u0 > u1) { flag = true; u0 = -u0; u1 = -u1; a = -a; b = -b; c = -c; } int ll = 0, rr = n - 1; while (ll < rr) { int i = (ll + rr + 1) >> 1; int j = (i + 1) % n; double ui = a * x[i] + b * y[i] + c; double uj = a * x[j] + b * y[j] + c; if (ui <= uj && ui >= 0.5 * (u0 + u1)) ll = i; else rr = i - 1; } int id_max = (ll + 1) % n; ll = id_max + 1, rr = id_max + n - 1; while (ll < rr) { int i = (ll + rr) >> 1; int j = i + 1; double ui = a * x[i % n] + b * y[i % n] + c; double uj = a * x[j % n] + b * y[j % n] + c; if (ui > uj) ll = i + 1; else rr = i; } int id_min = ll; int last, first; { ll = id_max, rr = id_min; while (ll < rr) { int i = (ll + rr + 1) >> 1; double ui = a * x[i % n] + b * y[i % n] + c; if (ui > 0) ll = i; else rr = i - 1; } last = ll + n; } { ll = id_min, rr = id_max + n; while (ll < rr) { int i = (ll + rr) >> 1; double ui = a * x[i % n] + b * y[i % n] + c; if (ui < 0) ll = i + 1; else rr = i; } first = ll; } double xf, yf, xl, yl; double aa, bb, cc; line(first - 1, first, aa, bb, cc); intersect(a, b, c, aa, bb, cc, xf, yf); line(last, last + 1, aa, bb, cc); intersect(a, b, c, aa, bb, cc, xl, yl); double res = 0.0; res += (xf - x[first % n]) * (yf + y[first % n]); res += areas[last] - areas[first]; res += (x[last % n] - xl) * (y[last % n] + yl); res += (xl - xf) * (yl + yf); if (flag) res = total_area - res; if (it == 0) { zero = res; continue; } { double res1 = 0.5 * res; double res2 = 0.5 * (total_area - res); double diff = fabs(res1 - res2); double sum = 0.5 * total_area; if (diff / sum < 1e-6) { found = true; ans = mid; break; } } if ((res > 0.5 * total_area) == (zero > 0.5 * total_area)) low = mid; else high = mid; } printf( %.17f n , found ? ans : (0.5 * (low + high))); } return 0; }
|
#include <bits/stdc++.h> template <class T> inline void read(T &x) { x = 0; register char c = getchar(); register bool f = 0; while (!isdigit(c)) f ^= c == - , c = getchar(); while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); if (f) x = -x; } template <class T> inline void print(T x) { if (x < 0) putchar( - ), x = -x; if (x > 9) print(x / 10); putchar(x % 10 + 0 ); } template <class T> inline void print(T x, char c) { print(x), putchar(c); } template <class T> inline T gcd(T n, T m) { return m ? gcd(m, n % m) : n; } template <const int N> struct Prime : std::vector<int> { Prime() { std::vector<bool> vis(N); for (int i = 2; i < N; i++) { if (!vis[i]) this->push_back(i); for (int j : *this) { if (i * j >= N) break; vis[i * j] = true; if (!(i % j)) break; } } } }; const int N = 1e5 + 10, M = 1e7 + 10; int n, k, A, B, C, a[N], deg[N], v[N][8], l[N], f[M]; Prime<10000> prime; std::vector<int> pos; std::unordered_map<int, int> primeid; void affect(int *v, int l, int x) { std::function<void(int, int)> dfs = [&](int i, int s) { if (i == l) { if (s != 1) f[s] += x; return; } dfs(i + 1, s); dfs(i + 1, s * v[i]); }; dfs(0, 1); } int query(int *v, int l) { int res = 0; std::function<void(int, int)> dfs = [&](int i, int s) { if (i == l) { res += s < 0 ? -f[-s] : f[s]; return; } dfs(i + 1, s); dfs(i + 1, s * -v[i]); }; dfs(0, -1); return res; } int main() { read(n), read(k); for (int i = 1; i <= n; i++) read(a[i]); for (int i = 0; i < prime.size(); i++) primeid[prime[i]] = i; for (int x, i = 1; i <= n; i++) { x = a[i]; for (int j = 0; prime[j] * prime[j] <= x; j++) if (x % prime[j] == 0) { v[i][l[i]++] = prime[j]; while (x % prime[j] == 0) x /= prime[j]; } if (x != 1) v[i][l[i]++] = x; } for (int i = 1; i <= n; i++) affect(v[i], l[i], 1); for (int i = 1; i <= n; i++) deg[i] = query(v[i], l[i]) - 1; for (int i = 1; i <= n; i++) affect(v[i], l[i], -1); int fulldeg = 0; for (int i = 1; i <= n; i++) fulldeg += deg[i] == n - 1; if (fulldeg >= k) { for (int i = 1; i <= n; i++) if (deg[i] == n - 1) pos.push_back(i); } else { for (int i = 1; i <= n; i++) if (n - 1 - deg[i] >= 2) { A = i; for (int j = 1; j <= n; j++) if (j != A && gcd(a[i], a[j]) == 1) { if (!B) { B = j; continue; } if (!C) { C = j; continue; } break; } break; } if (A) { if (!(B && C)) printf( Assert: Passing [%s] in LINE %d n , __FUNCTION__, 120), exit(0); auto getp = [&](int cur) { std::vector<int> res; for (int i = 1; i <= n && res.size() < cur; i++) if (i != A && i != B && i != C) { res.push_back(i); } return res; }; auto solve = [&](int cur) { int res = 0; std::vector<int> p = getp(cur); for (int i : p) affect(v[i], l[i], 1); for (int i : p) deg[i] = query(v[i], l[i]) - 1; for (int i : p) affect(v[i], l[i], -1); for (int i : p) res += deg[i] != cur - 1; return res; }; int l = 1, r = n - 3, mid, res = -1; while (l <= r) { mid = (l + r) >> 1; solve(mid) + 3 >= k ? (res = mid, r = mid - 1) : (l = mid + 1); } if (!(~res)) printf( Assert: Passing [%s] in LINE %d n , __FUNCTION__, 144), exit(0); int now = solve(res); std::vector<int> p = getp(res); for (int i : p) if (deg[i] != res - 1) pos.push_back(i); if (pos.size() < k) pos.push_back(A); if (pos.size() < k) pos.push_back(B); if (pos.size() < k) pos.push_back(C); } else { uint64_t all = 0; std::vector<int> match(n + 1); std::vector<uint64_t> hsh(n + 1); std::map<uint64_t, int> map; std::map<int, uint64_t> sta; std::mt19937_64 rng( 20040725 ^ std::chrono::steady_clock::now().time_since_epoch().count()); for (int i = 1; i <= n; i++) hsh[i] = rng(), all ^= hsh[i], map[hsh[i]] = i; for (int i = 1; i <= n; i++) for (int x = 1; x < (1 << l[i]); x++) { int s = 1; for (int j = 0; j < l[i]; j++) if ((x >> j) & 1) s *= v[i][j]; sta[s] ^= hsh[i]; } for (int i = 1; i <= n; i++) if (deg[i] == n - 2) { uint64_t tem = all; for (int x = 1; x < (1 << l[i]); x++) { int s = 1; for (int j = 0; j < l[i]; j++) if ((x >> j) & 1) s *= v[i][j]; tem ^= sta[s]; } match[i] = map[tem]; } for (int i = 1; i <= n; i++) if (!match[i] || i < match[i]) pos.push_back(i); } } if (!(pos.size() >= k)) printf( Assert: Passing [%s] in LINE %d n , __FUNCTION__, 186), exit(0); for (int i = 0; i < k; i++) print(pos[i], n [i + 1 == k]); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUSRECEIVER_BEHAVIORAL_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busreceiver (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long lucky[1024 * 4]; long long fact[14]; int cnt; void func(long long cur, int pos, int maxpos) { if (pos == maxpos) { lucky[++cnt] = cur * 10 + 4; lucky[++cnt] = cur * 10 + 7; return; } func(cur * 10 + 4, pos + 1, maxpos); func(cur * 10 + 7, pos + 1, maxpos); } void pre() { cnt = 0; for (int d = 1; d <= 10; d++) { func(0, 1, d); } sort(lucky, lucky + cnt); fact[0] = 1; for (int i = 1; i < 14; i++) fact[i] = i * fact[i - 1]; } long long n, k; void in() { cin >> n >> k; } int arr[14] = {0}; int brr[14] = {0}; void rec(int p, long long k, int coun) { if (coun == p) return; int b = (k + fact[p - 1 - coun] - 1) / fact[p - 1 - coun]; int c = 0; for (int i = 0; i < 14; i++) { if (brr[i] == 0) c++; if (b == c) { brr[i] = 1; arr[coun] = i; rec(p, k - fact[p - 1 - coun] * (b - 1), coun + 1); break; } } return; } bool luck(long long q) { for (int i = 0; i < cnt; i++) { if (lucky[i] == q) return true; if (lucky[i] > q) return false; } return false; } void solve() { int p = 0; while (fact[p] < k) p++; if (n < 14 && k > fact[n]) { cout << -1 << endl; return; } rec(p, k, 0); for (int i = 0; i < p; i++) { arr[i] += n - p + 1; } int ans = 1; while (lucky[ans] <= n - p) { ans++; } ans--; for (long long i = n - p + 1; i <= n; i++) { if (luck(i) && luck(arr[i - n - 1 + p])) ans++; } cout << ans << endl; } int main() { pre(); in(); solve(); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:08:24 04/14/2015
// Design Name:
// Module Name: PrimeList
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PrimeList(input clk, input [12:0] index, output reg ready, output wire [8:0] data
);
reg wea;
reg next_wea;
reg [12:0] memory_index;
reg [12:0] next_memory_index;
reg next_ready;
reg is_memory_being_written;
reg next_is_memory_being_written;
wire loop;
wire [8:0] prime_number;
memory list (
.clka(clk), // input clka
.wea(wea), // input [0 : 0] wea
.addra(memory_index), // input [12 : 0] addra
.dina(prime_number), // input [8 : 0] dina
.douta(data) // output [8 : 0] douta
);
Sieve sieve (
.clk(clk),
.primeNumber(prime_number),
.loop(loop)
);
initial begin
memory_index = 0;
next_memory_index = 0;
wea = 0;
next_wea = 0;
ready = 0;
next_ready = 0;
is_memory_being_written = 0;
next_is_memory_being_written = 0;
end
always @(posedge clk)
begin
memory_index <= next_memory_index;
wea <= next_wea;
ready <= next_ready;
is_memory_being_written <= next_is_memory_being_written;
end
always @(*)
begin
if (prime_number <= 0) begin // if the current prime number is negative, meaning that the sieve is done
next_memory_index = index;
next_wea = 0;
next_ready = 1;
next_is_memory_being_written = 0;
end else begin // if the current prime number is positive, meaning the sieve is still running
if (!loop) begin // if the next prime is generated, write it to memory
if (!is_memory_being_written) begin
next_memory_index = memory_index + 1;
next_wea = 1;
next_is_memory_being_written = 1;
end else begin
next_memory_index = memory_index;
next_wea = 0;
next_is_memory_being_written = 1;
end
end else begin // if the next prime is not generated yet, just wait
next_memory_index = memory_index;
next_wea = 0;
next_is_memory_being_written = 0;
end
next_ready = 0;
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im_cache:1.0
// IP Revision: 8
(* X_CORE_INFO = "fmrv32im_cache,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "fmrv32im_artya7_fmrv32im_cache_0_0,fmrv32im_cache,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_cache_0_0 (
RST_N,
CLK,
I_MEM_WAIT,
I_MEM_ENA,
I_MEM_ADDR,
I_MEM_RDATA,
I_MEM_BADMEM_EXCPT,
D_MEM_WAIT,
D_MEM_ENA,
D_MEM_WSTB,
D_MEM_ADDR,
D_MEM_WDATA,
D_MEM_RDATA,
D_MEM_BADMEM_EXCPT,
WR_REQ_START,
WR_REQ_ADDR,
WR_REQ_LEN,
WR_REQ_READY,
WR_REQ_MEM_ADDR,
WR_REQ_MEM_WDATA,
RD_REQ_START,
RD_REQ_ADDR,
RD_REQ_LEN,
RD_REQ_READY,
RD_REQ_MEM_WE,
RD_REQ_MEM_ADDR,
RD_REQ_MEM_RDATA
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_WAIT" *)
output wire I_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ENA" *)
input wire I_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ADDR" *)
input wire [31 : 0] I_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_RDATA" *)
output wire [31 : 0] I_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_BADMEM_EXCPT" *)
output wire I_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WAIT" *)
output wire D_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ENA" *)
input wire D_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WSTB" *)
input wire [3 : 0] D_MEM_WSTB;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ADDR" *)
input wire [31 : 0] D_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WDATA" *)
input wire [31 : 0] D_MEM_WDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_RDATA" *)
output wire [31 : 0] D_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_BADMEM_EXCPT" *)
output wire D_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 WR_REQ REQ_START" *)
output wire WR_REQ_START;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 WR_REQ REQ_ADDR" *)
output wire [31 : 0] WR_REQ_ADDR;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 WR_REQ REQ_LEN" *)
output wire [15 : 0] WR_REQ_LEN;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 WR_REQ REQ_READY" *)
input wire WR_REQ_READY;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 WR_REQ REQ_MEM_ADDR" *)
input wire [9 : 0] WR_REQ_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 WR_REQ REQ_MEM_WDATA" *)
output wire [31 : 0] WR_REQ_MEM_WDATA;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 RD_REQ REQ_START" *)
output wire RD_REQ_START;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 RD_REQ REQ_ADDR" *)
output wire [31 : 0] RD_REQ_ADDR;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 RD_REQ REQ_LEN" *)
output wire [15 : 0] RD_REQ_LEN;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 RD_REQ REQ_READY" *)
input wire RD_REQ_READY;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 RD_REQ REQ_MEM_WE" *)
input wire RD_REQ_MEM_WE;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 RD_REQ REQ_MEM_ADDR" *)
input wire [9 : 0] RD_REQ_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:REQ_BUS:1.0 RD_REQ REQ_MEM_RDATA" *)
input wire [31 : 0] RD_REQ_MEM_RDATA;
fmrv32im_cache #(
.MEM_FILE("/home/hidemi/workspace/FPGAMAG18/FPGA/romdata/artya7.hex"),
.INTEL(0),
.OSRAM(0)
) inst (
.RST_N(RST_N),
.CLK(CLK),
.I_MEM_WAIT(I_MEM_WAIT),
.I_MEM_ENA(I_MEM_ENA),
.I_MEM_ADDR(I_MEM_ADDR),
.I_MEM_RDATA(I_MEM_RDATA),
.I_MEM_BADMEM_EXCPT(I_MEM_BADMEM_EXCPT),
.D_MEM_WAIT(D_MEM_WAIT),
.D_MEM_ENA(D_MEM_ENA),
.D_MEM_WSTB(D_MEM_WSTB),
.D_MEM_ADDR(D_MEM_ADDR),
.D_MEM_WDATA(D_MEM_WDATA),
.D_MEM_RDATA(D_MEM_RDATA),
.D_MEM_BADMEM_EXCPT(D_MEM_BADMEM_EXCPT),
.WR_REQ_START(WR_REQ_START),
.WR_REQ_ADDR(WR_REQ_ADDR),
.WR_REQ_LEN(WR_REQ_LEN),
.WR_REQ_READY(WR_REQ_READY),
.WR_REQ_MEM_ADDR(WR_REQ_MEM_ADDR),
.WR_REQ_MEM_WDATA(WR_REQ_MEM_WDATA),
.RD_REQ_START(RD_REQ_START),
.RD_REQ_ADDR(RD_REQ_ADDR),
.RD_REQ_LEN(RD_REQ_LEN),
.RD_REQ_READY(RD_REQ_READY),
.RD_REQ_MEM_WE(RD_REQ_MEM_WE),
.RD_REQ_MEM_ADDR(RD_REQ_MEM_ADDR),
.RD_REQ_MEM_RDATA(RD_REQ_MEM_RDATA)
);
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG
`include "test_defines.v"
`include "top.v"
module top_test;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output = 80; //'P'
wire uart_tx;
always #2 clk = !clk;
always #8 uart_clk = !uart_clk; //For sim. UART TX clock gets divided by 4
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
#9999 $display("Test timeout!\n");
#10000 $finish;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (serial_data == expected_output) begin
$display("%s\ttest pass\n", `TEST_NAME);
$finish;
end else begin
$display("%s\ttest failed!\n", `TEST_NAME);
$finish;
end
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; queue<int> s1, s2; int main() { int n, k1, k2; cin >> n; cin >> k1; int a, b; for (int i = 0; i < k1; i++) { cin >> a; s1.push(a); } cin >> k2; for (int i = 0; i < k2; i++) { cin >> b; s2.push(b); } int ans = 0; while (!s1.empty() && !s2.empty() && ans < 2e5 + 10) { int t1 = s1.front(); int t2 = s2.front(); s1.pop(); s2.pop(); if (t1 > t2) { s1.push(t2); s1.push(t1); } if (t1 < t2) { s2.push(t1); s2.push(t2); } ans++; } if (s1.empty()) { cout << ans << << 2 << endl; } if (s2.empty()) { cout << ans << << 1 << endl; } if (ans == 2e5 + 10) cout << -1 << endl; return 0; }
|
/*
* Copyright (c) 1998 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This demonstrates proper handling of unknown values in decimal output.
*/
module main();
initial
begin
$display("4'bxxxx = %d", 4'bxxxx);
$display("4'bzzxx = %d", 4'bzzxx);
$display("4'bzzzz = %d", 4'bzzzz);
$display("4'b00zz = %d", 4'b00zz);
$display("4'b0000 = %d", 4'b0000);
$display("4'b0011 = %d", 4'b0011);
$finish ;
end
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port multiplexer (64 bit datapath)
*/
module axis_mux_64_4 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid,
output wire input_0_axis_tready,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid,
output wire input_1_axis_tready,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid,
output wire input_2_axis_tready,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid,
output wire input_3_axis_tready,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
reg [1:0] select_reg = 0, select_next;
reg frame_reg = 0, frame_next;
reg input_0_axis_tready_reg = 0, input_0_axis_tready_next;
reg input_1_axis_tready_reg = 0, input_1_axis_tready_next;
reg input_2_axis_tready_reg = 0, input_2_axis_tready_next;
reg input_3_axis_tready_reg = 0, input_3_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_0_axis_tready = input_0_axis_tready_reg;
assign input_1_axis_tready = input_1_axis_tready_reg;
assign input_2_axis_tready = input_2_axis_tready_reg;
assign input_3_axis_tready = input_3_axis_tready_reg;
// mux for start of packet detection
reg selected_input_tvalid;
always @* begin
case (select)
2'd0: selected_input_tvalid = input_0_axis_tvalid;
2'd1: selected_input_tvalid = input_1_axis_tvalid;
2'd2: selected_input_tvalid = input_2_axis_tvalid;
2'd3: selected_input_tvalid = input_3_axis_tvalid;
endcase
end
// mux for incoming packet
reg [DATA_WIDTH-1:0] current_input_tdata;
reg [KEEP_WIDTH-1:0] current_input_tkeep;
reg current_input_tvalid;
reg current_input_tready;
reg current_input_tlast;
reg current_input_tuser;
always @* begin
case (select_reg)
2'd0: begin
current_input_tdata = input_0_axis_tdata;
current_input_tkeep = input_0_axis_tkeep;
current_input_tvalid = input_0_axis_tvalid;
current_input_tready = input_0_axis_tready;
current_input_tlast = input_0_axis_tlast;
current_input_tuser = input_0_axis_tuser;
end
2'd1: begin
current_input_tdata = input_1_axis_tdata;
current_input_tkeep = input_1_axis_tkeep;
current_input_tvalid = input_1_axis_tvalid;
current_input_tready = input_1_axis_tready;
current_input_tlast = input_1_axis_tlast;
current_input_tuser = input_1_axis_tuser;
end
2'd2: begin
current_input_tdata = input_2_axis_tdata;
current_input_tkeep = input_2_axis_tkeep;
current_input_tvalid = input_2_axis_tvalid;
current_input_tready = input_2_axis_tready;
current_input_tlast = input_2_axis_tlast;
current_input_tuser = input_2_axis_tuser;
end
2'd3: begin
current_input_tdata = input_3_axis_tdata;
current_input_tkeep = input_3_axis_tkeep;
current_input_tvalid = input_3_axis_tvalid;
current_input_tready = input_3_axis_tready;
current_input_tlast = input_3_axis_tlast;
current_input_tuser = input_3_axis_tuser;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_0_axis_tready_next = 0;
input_1_axis_tready_next = 0;
input_2_axis_tready_next = 0;
input_3_axis_tready_next = 0;
if (frame_reg) begin
if (current_input_tvalid & current_input_tready) begin
// end of frame detection
frame_next = ~current_input_tlast;
end
end else if (enable & selected_input_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
end
// generate ready signal on selected port
case (select_next)
2'd0: input_0_axis_tready_next = output_axis_tready_int_early & frame_next;
2'd1: input_1_axis_tready_next = output_axis_tready_int_early & frame_next;
2'd2: input_2_axis_tready_next = output_axis_tready_int_early & frame_next;
2'd3: input_3_axis_tready_next = output_axis_tready_int_early & frame_next;
endcase
// pass through selected packet data
output_axis_tdata_int = current_input_tdata;
output_axis_tkeep_int = current_input_tkeep;
output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
output_axis_tlast_int = current_input_tlast;
output_axis_tuser_int = current_input_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 0;
input_0_axis_tready_reg <= 0;
input_1_axis_tready_reg <= 0;
input_2_axis_tready_reg <= 0;
input_3_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_0_axis_tready_reg <= input_0_axis_tready_next;
input_1_axis_tready_reg <= input_1_axis_tready_next;
input_2_axis_tready_reg <= input_2_axis_tready_next;
input_3_axis_tready_reg <= input_3_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tkeep_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int iinf = 1e9 + 7; const long long linf = 1ll << 60; const double dinf = 1e60; template <typename T> inline void scf(T &x) { bool f = 0; x = 0; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) { f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } if (f) x = -x; return; } template <typename T1, typename T2> void scf(T1 &x, T2 &y) { scf(x); return scf(y); } template <typename T1, typename T2, typename T3> void scf(T1 &x, T2 &y, T3 &z) { scf(x); scf(y); return scf(z); } template <typename T1, typename T2, typename T3, typename T4> void scf(T1 &x, T2 &y, T3 &z, T4 &w) { scf(x); scf(y); scf(z); return scf(w); } inline char mygetchar() { char c = getchar(); while (c == || c == n ) c = getchar(); return c; } template <typename T> void chkmax(T &x, const T &y) { if (y > x) x = y; return; } template <typename T> void chkmin(T &x, const T &y) { if (y < x) x = y; return; } void TZL(); void RANK1(); int main() { TZL(); RANK1(); return 0; } void TZL() { long long k; int n; vector<long long> a; a.clear(); scf(n, k); for (int i = 0, _end_ = (n); i < _end_; ++i) { long long x; scf(x); a.push_back(x); } sort(a.begin(), a.end()); long long ans = 0; for (int i = 1; i < n; ++i) { long long x = a[i] - a[0]; if (x % k != 0) { puts( -1 ); return; } ans += x / k; ; } cout << ans << endl; } void RANK1() {}
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; int mx[N << 2], lz[N << 2], sum[N << 2], a[N], b[N]; void pushup(int rt) { mx[rt] = max(mx[(rt << 1)], mx[(rt << 1 | 1)]); } void pushdown(int rt) { if (lz[rt]) { lz[(rt << 1)] += lz[rt]; lz[(rt << 1 | 1)] += lz[rt]; mx[(rt << 1)] += lz[rt]; mx[(rt << 1 | 1)] += lz[rt]; lz[rt] = 0; } } void up(int L, int R, int val, int l = 1, int r = 1000000, int rt = 1) { if (L <= l && R >= r) { mx[rt] += val; lz[rt] += val; } else { pushdown(rt); if (((l + r) >> 1) >= L) up(L, R, val, l, ((l + r) >> 1), (rt << 1)); if (((l + r) >> 1) + 1 <= R) up(L, R, val, ((l + r) >> 1) + 1, r, (rt << 1 | 1)); pushup(rt); } } int f(int l = 1, int r = 1000000, int rt = 1) { if (l == r) return l; pushdown(rt); if (mx[(rt << 1 | 1)] > 0) return f(((l + r) >> 1) + 1, r, (rt << 1 | 1)); else return f(l, ((l + r) >> 1), (rt << 1)); } int main() { int n, m, q; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), up(1, a[i], 1); for (int i = 1; i <= m; i++) scanf( %d , &b[i]), up(1, b[i], -1); scanf( %d , &q); while (q--) { int x, i, j; scanf( %d %d %d , &x, &i, &j); if (x == 1) up(1, a[i], -1), up(1, j, 1), a[i] = j; else up(1, b[i], 1), up(1, j, -1), b[i] = j; printf( %d n , mx[1] > 0 ? f() : -1); } }
|
#include <bits/stdc++.h> using namespace std; vector<int> v, vv, vv2; int main() { int t, n, a[1000], k, f = 0; cin >> n; if (n == 3) { for (int i = 1; i <= n; i++) { if (i % 2 != 0) { for (int j = 1; j <= n; j++) { if (j % 2 != 0) { cout << W ; } else cout << B ; } cout << endl; } else { for (int k = 0; k < n; k++) { cout << B ; } cout << endl; } } } else { for (int i = 1; i <= n; i++) { if (i % 2 != 0) { for (int j = 1; j <= n; j++) { if (j % 2 != 0) cout << W ; else cout << B ; } cout << endl; } else { for (int j = 1; j <= n; j++) { if (j % 2 != 0) cout << B ; else cout << W ; } cout << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n; scanf( %d%d , &n, &m); printf( %d n , m * n / 2); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f3f3f3f3fll; inline long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } return x * f; } int n, x[5005], m, p[5005], c[5005], q[5005], l, r, t[5005]; long long s[5005], dp[5005][5005]; int main() { n = read(), m = read(); for (int i = 1; i <= n; ++i) { x[i] = read(); } sort(x + 1, x + n + 1); for (int i = 1; i <= m; ++i) { p[i] = read(), c[i] = read(); t[i] = i; } sort(t + 1, t + m + 1, [&](int i, int j) { return p[i] < p[j]; }); memset(dp, 0x3f, sizeof(dp)); dp[0][0] = 0; for (int j = 1; j <= m; ++j) { r = 0, l = 1; for (int i = 1; i <= n; ++i) { s[i] = s[i - 1] + abs(x[i] - p[t[j]]); } for (int i = 0; i <= n; ++i) { while (l <= r && q[l] < i - c[t[j]]) ++l; while (l <= r && dp[i][j - 1] - s[i] <= dp[q[r]][j - 1] - s[q[r]]) --r; q[++r] = i; dp[i][j] = dp[q[l]][j - 1] + s[i] - s[q[l]]; } } if (dp[n][m] == inf) { printf( -1 n ); return 0; } printf( %lld n , dp[n][m]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 300005, INF = 9999999; const long long P = 1e9 + 7; template <typename T> inline void read(T& first, char s = getchar()) { first = 0; while (s > 9 || s < 0 ) s = getchar(); while (s <= 9 && s >= 0 ) first = first * 10 + s - 0 , s = getchar(); } int k, a, b; int main() { read(k), read(a), read(b); if (a < k && b < k) { cout << -1 << endl; return 0; } if (a < k || b < k) { if (a < b) swap(a, b); if (a % k != 0) { cout << -1 << endl; return 0; } else { cout << (a / k) << endl; return 0; } } int ans = a / k + b / k; cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O311A_BEHAVIORAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B1 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 2e9; const long long LINF = 1LL << 60; const double inf = 1e15; long long mod = 1e9 + 7; char READ_DATA; int SIGNAL_INPUT; template <typename Type> inline Type ru(Type &v) { SIGNAL_INPUT = 1; while ((READ_DATA = getchar()) < 0 || READ_DATA > 9 ) if (READ_DATA == - ) SIGNAL_INPUT = -1; else if (READ_DATA == EOF) return EOF; v = READ_DATA - 0 ; while ((READ_DATA = getchar()) >= 0 && READ_DATA <= 9 ) v = v * 10 + READ_DATA - 0 ; v *= SIGNAL_INPUT; return v; } inline long long modru(long long &v) { long long p = 0; SIGNAL_INPUT = 1; while ((READ_DATA = getchar()) < 0 || READ_DATA > 9 ) if (READ_DATA == - ) SIGNAL_INPUT = -1; else if (READ_DATA == EOF) return EOF; p = v = READ_DATA - 0 ; while ((READ_DATA = getchar()) >= 0 && READ_DATA <= 9 ) { v = (v * 10 + READ_DATA - 0 ) % mod; p = (p * 10 + READ_DATA - 0 ) % (mod - 1); } v *= SIGNAL_INPUT; return p; } template <typename A, typename B> inline char ru(A &x, B &y) { if (ru(x) == EOF) return EOF; ru(y); return 2; } template <typename A, typename B, typename C> inline char ru(A &x, B &y, C &z) { if (ru(x) == EOF) return EOF; ru(y); ru(z); return 3; } template <typename A, typename B, typename C, typename D> inline char ru(A &x, B &y, C &z, D &w) { if (ru(x) == EOF) return EOF; ru(y); ru(z); ru(w); return 4; } struct Edge { int u, v, next; long long w, cap, flow; Edge(int _u = 0, int _v = 0, int nxt = -1, long long _w = 1, long long _cap = 0) { u = _u; v = _v; w = _w; cap = _cap; flow = 0; next = nxt; } int operator<(const Edge &b) const { return w < b.w; } }; const int maxn = 2e6 + 3, N = 2e7, SZ = 21; double eps = 1e-7, pi = acos(-1.0); long long seed = 131, smod = (1LL << 32) - 267; long long a, b, p, n; long long sp(long long a, long long b, long long mod) { long long ans = 1, x = a; while (b) { if (b & 1) (ans *= x) %= mod; (x *= x) %= mod; b >>= 1; } return ans; } long long c[maxn]; long long ans1, ans2; int main() { cin >> a >> b >> p >> n; c[0] = 1; for (register int j = 1; j < p; ++j) c[j] = c[j - 1] * a % p; for (register int j = 1; j < p; ++j) { long long y = c[j * (p - 2) % (p - 1)] * b % p; long long t = (j - y + p) % p; if (t * (p - 1) + j > n) continue; long long u = ((n - j) / (p - 1) - t) / p; ans2 += (u + 1); } cout << ans2; }
|
#include <bits/stdc++.h> using namespace std; const long long int siz = 3e5 + 5; map<int, vector<int>> adjList; long long int ans[siz] = {0}; long long int cum[siz] = {0}; map<long long int, long long int> q[siz]; void dfs(int cur, int parent, int level, long long int val) { for (pair<long long int, long long int> temp : q[cur]) { cum[level] += temp.second; cum[min(level + temp.first + 1, siz - 1)] -= temp.second; } val += cum[level]; ans[cur] = val; for (int child : adjList[cur]) { if (child != parent) { dfs(child, cur, level + 1, val); } } for (pair<long long int, long long int> temp : q[cur]) { cum[level] -= temp.second; cum[min(level + temp.first + 1, siz - 1)] += temp.second; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int n; cin >> n; int y; long long int x; for (int i = 0; i < (int)(n - 1); i++) { cin >> x >> y; adjList[x].push_back(y); adjList[y].push_back(x); } int m; cin >> m; int d, v; for (int i = 0; i < (int)(m); i++) { cin >> v >> d >> x; q[v][d] += x; } dfs(1, -1, 1, 0); for (int i = 1; i <= (int)(n); i++) { cout << ans[i] << ; } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int a[10005][6], n, m; map<int, int> f[10005]; int power(int x, int y) { int s = 1; for (; y; y /= 2, x = 1ll * x * x % 1000000007) if (y & 1) s = 1ll * s * x % 1000000007; return s; } int main() { scanf( %d%d , &n, &m); for (int i = 2; i <= m; i++) for (int j = 1; j < i; j++) { a[i][++a[i][0]] = j; f[i][j] = f[j][i] = 1000000007 - 1; f[i][i]++; f[j][j]++; } for (int i = m + 1; i <= n; i++) { a[i][0] = m; for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); f[i][a[i][j]] = f[a[i][j]][i] = 1000000007 - 1; f[i][i]++; f[a[i][j]][a[i][j]]++; } } int ans = 1; for (int i = n; i > 1; i--) { int t = power(f[i][i], 1000000007 - 2); ans = 1ll * ans * f[i][i] % 1000000007; for (int j = 1; j <= a[i][0]; j++) for (int k = 1; k <= a[i][0]; k++) (f[a[i][j]][a[i][k]] += 1000000007 - 1ll * f[a[i][j]][i] * f[i][a[i][k]] % 1000000007 * t % 1000000007) %= 1000000007; } printf( %d , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); vector<int> a(n); for (int i = 0; (i) < (int)(n); (i)++) { scanf( %d , &a[i]); } queue<int> que; vector<int> ans; for (int i = 0; (i) < (int)(n); (i)++) { if (i == 0 || a[i - 1] < a[i]) { ans.push_back(a[i]); int prev = (i == 0 ? 0 : a[i - 1]); prev++; while (prev != a[i]) { que.push(prev); prev++; } } else { if (que.empty()) { printf( -1 n ); goto end; } ans.push_back(que.front()); que.pop(); } } assert(ans.size() == n); for (int i = 0; (i) < (int)(n); (i)++) { printf( %d%c , ans[i], i == n - 1 ? n : ); } end:; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int level = 20; vector<int> adj[N]; bool checked[N]; int parent[N]; int sz[N]; int centroid; int sparse[N][level]; int depth[N]; void subtree(int cur, int prev) { sz[cur] = 1; for (auto &child : adj[cur]) { if (child != prev and !checked[child]) { subtree(child, cur); sz[cur] += sz[child]; } } } void decompose(int cur, int prev, int total_size) { for (auto &child : adj[cur]) { if (child != prev and !checked[child]) { decompose(child, cur, total_size); } } if (centroid != -1) { return; } if (2 * sz[cur] >= total_size) { centroid = cur; return; } } int get_centroid(int cur) { subtree(cur, 0); centroid = -1; decompose(cur, 0, sz[cur]); return centroid; } void dfs(int cur, int prev) { int root = get_centroid(cur); parent[root] = prev; checked[root] = true; for (auto &child : adj[root]) { if (!checked[child]) { dfs(child, root); } } } void dfs_sparse(int cur, int prev) { sparse[cur][0] = prev; for (auto &child : adj[cur]) { if (child != prev) { depth[child] = depth[cur] + 1; dfs_sparse(child, cur); } } } void solve() { int n, m; cin >> n >> m; for (int i = 1; i <= n - 1; i++) { int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } dfs(1, 0); dfs_sparse(1, -1); for (int l = 1; l < level; l++) { for (int node = 1; node <= n; node++) { if (sparse[node][l - 1] != -1) { sparse[node][l] = sparse[sparse[node][l - 1]][l - 1]; } } } auto lca = [&](int u, int v) -> int { if (depth[v] < depth[u]) { swap(u, v); } int diff = depth[v] - depth[u]; for (int i = 0; i < level; i++) { if ((diff >> i) & 1) { v = sparse[v][i]; } } if (u == v) { return u; } for (int i = level - 1; i >= 0; i--) { if (sparse[u][i] != sparse[v][i]) { u = sparse[u][i]; v = sparse[v][i]; } } return sparse[u][0]; }; auto get_dist = [&](int x, int y) { int lc = lca(x, y); return depth[x] + depth[y] - 2 * depth[lc]; }; vector<int> dist(n + 1, n); int node = 1; for (int i = node; i; i = parent[i]) { dist[i] = get_dist(i, node); } for (int i = 1; i <= m; i++) { int type, node; cin >> type >> node; if (type == 1) { for (int i = node; i; i = parent[i]) { dist[i] = min(dist[i], get_dist(i, node)); } } else { int ans = n; for (int i = node; i; i = parent[i]) { ans = min(ans, get_dist(i, node) + dist[i]); } cout << (dist[node] = ans) << n ; } } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); }
|
module encoder
#(
parameter logS=4
)
(
g_input,
e_input,
o
);
localparam S = 2**logS;
input [S/2-1:0] g_input;
input [S/2-1:0] e_input;
output [logS-1:0] o;
wire [S-1:0] in;
assign in[S/2-1:0] = g_input;
assign in[S-1:S/2] = e_input;
encoder_
#(
.logS(logS)
)
encoder0
(
.in(in),
.o(o)
);
endmodule
module encoder_
#(
parameter logS=4
)
(
in,
o
);
localparam S = 2**logS;
input [S-1:0] in;
output [logS-1:0] o;
generate
if(logS == 1)
begin
assign o = in[1];
end
else
begin
wire [logS-1:0] o0;
wire [logS-1:0] o1;
encoder_
#(
.logS(logS-1)
)
encoder0
(
.in(in[S/2-1:0]),
.o(o0[logS-2:0])
);
encoder_
#(
.logS(logS-1)
)
encoder1
(
.in(in[S-1:S/2]),
.o(o1[logS-2:0])
);
assign o = {|in[S-1:S/2], o0[logS-2:0]|o1[logS-2:0]};
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int freq[300]; string s; const int maxN = 2000; int primes[maxN]; int equs[maxN]; char result[maxN]; set<pair<int, char> > lets; int n; void sieve() { for (int i = 2; i < maxN; i++) { primes[i] = 1; } for (long long i = 2; i * i < maxN; i++) { if (primes[i] == 1) { for (long long j = i * i; j < maxN; j += i) { primes[j] = 0; } } } } int main(int argc, char const *argv[]) { cin >> s; sieve(); n = s.length(); for (int i = 0; i < n; i++) { freq[s[i]]++; } int tot = 0; for (int i = 0; i <= n; i++) { if (primes[i] == 1 && i * 2 <= n) { for (int j = i; j <= n; j += i) { if (equs[j] == 0) { tot++; } equs[j] = 1; } } } for (int i = 0; i < 300; i++) { if (freq[i] != 0) { lets.insert(make_pair(-freq[i], i)); } } if (-lets.begin()->first < tot) { cout << NO << endl; return 0; } for (int i = 1; i <= n; i++) { if (equs[i] == 1) { result[i] = lets.begin()->second; } } pair<int, char> tmp = *lets.begin(); tmp.first += tot; lets.erase(lets.begin()); lets.insert(tmp); for (int i = 1; i <= n; i++) { if (equs[i] == 0) { if (lets.begin()->first == 0) { lets.erase(lets.begin()); i--; continue; } result[i] = lets.begin()->second; tmp = *lets.begin(); tmp.first++; lets.erase(lets.begin()); lets.insert(tmp); } } cout << YES << endl; for (int i = 1; i <= n; i++) { cout << result[i]; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = int64_t; int main(int argc, char* argv[]) { std::ios::sync_with_stdio(false); cin.tie(nullptr); cout.precision(10); int n; cin >> n; auto g = vector<vector<ll>>(n, vector<ll>(n, 2000000000)); for (int i = 0; i < (n - 1); ++i) for (int j = 0; j < (n - i - 1); ++j) { int d; cin >> d; g[i][i + j + 1] = g[i + j + 1][i] = d; } auto min_adj = vector<ll>(n); for (int i = 0; i < (n); ++i) min_adj[i] = *min_element((g[i]).begin(), (g[i]).end()); auto smallest = *min_element((min_adj).begin(), (min_adj).end()); for (int i = 0; i < (n); ++i) for (int j = 0; j < (n); ++j) g[i][j] -= smallest; auto dist = move(min_adj); for (int i = 0; i < (n); ++i) dist[i] = 2 * (dist[i] - smallest); auto done = vector<char>(n, false); for (int _ = 0; _ < (n); ++_) { int v = -1; for (int i = 0; i < (n); ++i) if (!done[i] && (v == -1 || dist[i] < dist[v])) v = i; done[v] = true; for (int i = 0; i < (n); ++i) dist[i] = min(dist[i], dist[v] + g[i][v]); } for (int i = 0; i < (n); ++i) cout << dist[i] + (n - 1) * smallest << n ; return 0; }
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`default_nettype none
module order_module_backpressure
#(
parameter TAG_WIDTH = 6,
parameter OUT_TAG_WIDTH = 6,
parameter USER_TAG_WIDTH = 8,
parameter DATA_WIDTH = 512,
parameter ADDR_WIDTH = 58)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
// input requests
input wire [ADDR_WIDTH-1:0] usr_tx_rd_addr,
input wire [USER_TAG_WIDTH-1:0] usr_tx_rd_tag,
input wire usr_tx_rd_valid,
output wire usr_tx_rd_free,
// User Module TX RD
output wire [ADDR_WIDTH-1:0] ord_tx_rd_addr,
output wire [OUT_TAG_WIDTH-1:0] ord_tx_rd_tag,
output wire ord_tx_rd_valid,
input wire ord_tx_rd_free,
// User Module RX RD
input wire [TAG_WIDTH-1:0] ord_rx_rd_tag,
input wire [DATA_WIDTH-1:0] ord_rx_rd_data,
input wire ord_rx_rd_valid,
//
output reg [USER_TAG_WIDTH-1:0] usr_rx_rd_tag,
output reg [DATA_WIDTH-1:0] usr_rx_rd_data,
output reg usr_rx_rd_valid,
input wire usr_rx_rd_ready
);
reg [2**TAG_WIDTH-1:0] rob_valid;
reg rob_re;
reg rob_re_d1;
reg [USER_TAG_WIDTH-1:0] rob_rtag;
reg [USER_TAG_WIDTH+TAG_WIDTH-1:0] rob_raddr;
wire pend_tag_fifo_full;
wire pend_tag_fifo_valid;
wire absorb_pend_tag;
wire [USER_TAG_WIDTH+TAG_WIDTH-1:0] curr_pend_tag;
wire [DATA_WIDTH-1:0] rob_rdata;
reg [1:0] pending_valid;
reg [DATA_WIDTH-1:0] pending_data [1:0];
reg [USER_TAG_WIDTH-1:0] pending_tag [1:0];
reg [TAG_WIDTH-1:0] ord_tag;
assign ord_tx_rd_valid = usr_tx_rd_valid & ~pend_tag_fifo_full;
assign ord_tx_rd_tag = {{{OUT_TAG_WIDTH - TAG_WIDTH}{1'b0}}, ord_tag};
assign ord_tx_rd_addr = usr_tx_rd_addr;
assign usr_tx_rd_free = ord_tx_rd_free & ~pend_tag_fifo_full;
// RX_RD reorder buffer for rd data
spl_sdp_mem #(.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (TAG_WIDTH) // transfer size 1, tag width 6 -> 64 entries
) reorder_buf (
.clk (clk),
.we ( ord_rx_rd_valid ),
.waddr ( ord_rx_rd_tag[TAG_WIDTH-1:0] ),
.din ( ord_rx_rd_data ),
.re ( rob_re ),
.raddr ( rob_raddr[TAG_WIDTH-1:0] ),
.dout ( rob_rdata )
);
// FIFO of tags for sent TX RD requests
quick_fifo #(.FIFO_WIDTH(USER_TAG_WIDTH + TAG_WIDTH),
.FIFO_DEPTH_BITS(TAG_WIDTH),
.FIFO_ALMOSTFULL_THRESHOLD(32)
) pend_tag_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({usr_tx_rd_tag, ord_tag}),
.we (usr_tx_rd_valid & ord_tx_rd_free),
.re ( absorb_pend_tag),
.dout (curr_pend_tag),
.empty (),
.valid (pend_tag_fifo_valid),
.full (pend_tag_fifo_full),
.count (),
.almostfull ()
);
assign absorb_pend_tag = rob_re;
always@(posedge clk) begin
if(~rst_n) begin
rob_valid <= 0;
rob_re <= 0;
rob_re_d1 <= 0;
rob_rtag <= 0;
rob_raddr <= 0;
usr_rx_rd_valid <= 1'b0;
//usr_rx_rd_data <= 0;
usr_rx_rd_tag <= 0;
pending_valid <= 0;
ord_tag <= 0;
end
else begin
if( usr_tx_rd_valid & ord_tx_rd_free & ~pend_tag_fifo_full ) ord_tag <= ord_tag + 1'b1;
// write response in the responses memory if cannot bypass rob buffer
if(ord_rx_rd_valid) begin
rob_valid[ord_rx_rd_tag[TAG_WIDTH-1:0]] <= 1'b1;
end
// read rob buffer
rob_re <= 1'b0;
rob_re_d1 <= rob_re;
rob_rtag <= rob_raddr[USER_TAG_WIDTH+TAG_WIDTH-1 : TAG_WIDTH];
// if current pending tag has valid response then read it from the responses memory
if( rob_valid[curr_pend_tag[TAG_WIDTH-1:0]] && pend_tag_fifo_valid && (~pending_valid[0] | (~pending_valid[1] & ~rob_re_d1) )) begin
rob_re <= 1'b1;
rob_raddr <= curr_pend_tag;
rob_valid[curr_pend_tag[TAG_WIDTH-1:0]] <= 1'b0;
end
// usr rx rd:
// Advance if either new data comes from the order memory or new data is requested by the AFU
if(~pending_valid[0]) begin
pending_valid[0] <= rob_re_d1;
pending_data[0] <= rob_rdata;
pending_tag[0] <= rob_rtag;
end
else if( ~usr_rx_rd_valid | usr_rx_rd_ready) begin
if(pending_valid[1]) begin
pending_valid[0] <= 1'b1;
pending_data[0] <= pending_data[1];
pending_tag[0] <= pending_tag[1];
end
else begin
pending_valid[0] <= rob_re_d1;
pending_data[0] <= rob_rdata;
pending_tag[0] <= rob_rtag;
end
end
if( usr_rx_rd_ready) begin
if(pending_valid[1]) begin
pending_valid[1] <= rob_re_d1;
pending_data[1] <= rob_rdata;
pending_tag[1] <= rob_rtag;
end
else begin
pending_valid[1] <= 0;
end
end
else if( pending_valid[0] & ~pending_valid[1] ) begin
pending_valid[1] <= rob_re_d1;
pending_data[1] <= rob_rdata;
pending_tag[1] <= rob_rtag;
end
if(usr_rx_rd_ready | ~usr_rx_rd_valid) begin
usr_rx_rd_valid <= pending_valid[0];
usr_rx_rd_data <= pending_data[0];
usr_rx_rd_tag <= pending_tag[0];
end
// Chekc if data got consumed, in case we are not advancing anyway
//else if (usr_rx_rd_valid && usr_rx_rd_ready) begin
// usr_rx_rd_valid <= 1'b0;
//end
end
end
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_4_V
`define SKY130_FD_SC_HDLL__O221AI_4_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_4_V
|
module maple(
input clk,
input reset,
input pin1,
input pin5,
output ControllerData controller_data,
output KeyboardData keyboard_data
);
wire maple_active;
wire maple_start_detected;
wire maple_end_detected;
wire maple_data_produce;
wire maple_trigger_start;
wire maple_trigger_end;
wire [7:0] maple_data;
reg [7:0] pos;
reg trigger_start = 0;
reg triggered = 0;
reg[3:0] controller_packet_check;
reg[3:0] keyboard_packet_check;
reg[3:0] pullup_osd;
reg[3:0] trig_def_res;
ControllerData cdata_in = 0;
ControllerData cdata_out = 0;
KeyboardData keydata_in = 0;
KeyboardData keydata_out = 0;
initial begin
pos <= 0;
controller_packet_check <= 0;
keyboard_packet_check <= 0;
pullup_osd <= 0;
trig_def_res <= 0;
end
maple_in test(
.rst(reset),
.clk(clk),
.pin1(pin1),
.pin5(pin5),
.oe(1'b0),
.active(maple_active),
.start_detected(maple_start_detected),
.end_detected(maple_end_detected),
.trigger_start(maple_trigger_start),
.trigger_end(maple_trigger_end),
.fifo_data(maple_data),
.data_produce(maple_data_produce)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
// reset values
triggered <= 0;
pos <= 0;
controller_packet_check <= 0;
keyboard_packet_check <= 0;
pullup_osd <= 0;
trig_def_res <= 0;
cdata_in <= 0;
keydata_in <= 0;
end else begin
// re-trigger read loop
if (!triggered) begin
trigger_start <= 1;
triggered <= 1;
end else begin
trigger_start <= 0;
end
// re-trigger read loop on package end
if (maple_end_detected) begin
// reset values
triggered <= 0;
pos <= 0;
controller_packet_check <= 0;
keyboard_packet_check <= 0;
pullup_osd <= 0;
trig_def_res <= 0;
cdata_in <= 0;
keydata_in <= 0;
// check for controller packet, to assign output data
if (controller_packet_check == 4'b1111) begin
cdata_out[12:2] <= cdata_in[12:2];
cdata_out.trigger_osd <= (pullup_osd == 4'b1111);
cdata_out.trigger_default_resolution <= (trig_def_res == 4'b1111);
cdata_out.valid_packet <= 1'b1;
end
if (keyboard_packet_check == 4'b1111) begin
keydata_out[63:0] <= keydata_in[63:0];
keydata_out.valid_packet <= 1'b1;
end
end
// get maple bus data
if (maple_data_produce) begin
case (pos)
0: begin
if (maple_data == 8'h03) begin // 3 additional frames
controller_packet_check[0] <= 1'b1;
keyboard_packet_check[0] <= 1'b1;
end
end
1: begin
// ignore sender address
end
2: begin
if (maple_data == 8'h00) begin // receipient is dc
controller_packet_check[1] <= 1'b1;
keyboard_packet_check[1] <= 1'b1;
end
end
3: begin
if (maple_data == 8'h08) begin // command is data reply
controller_packet_check[2] <= 1'b1;
keyboard_packet_check[2] <= 1'b1;
end
end
4: begin
if (maple_data == 8'h01) begin // func is controller
controller_packet_check[3] <= 1'b1;
end else if (maple_data == 8'h40) begin // func is keyboard
keyboard_packet_check[3] <= 1'b1;
end
end
8: begin
if (maple_data == 8'hFF) begin // ltrigger must be completely engaged
pullup_osd[0] <= 1'b1;
trig_def_res[0] <= 1'b1;
end
cdata_in.ltrigger <= (maple_data == 8'hFF);
keydata_in.key2 <= maple_data;
end
9: begin
if (maple_data == 8'hFF) begin // rtrigger must be completely engaged
pullup_osd[1] <= 1'b1;
trig_def_res[1] <= 1'b1;
end
cdata_in.rtrigger <= (maple_data == 8'hFF);
keydata_in.key1 <= maple_data;
end
10: begin
if (maple_data == 8'b_1111_1011) begin // buttons[15:8] X pressed
pullup_osd[2] <= 1'b1;
end else if (maple_data == 8'b_1111_1101) begin // buttons[15:8] Y pressed
trig_def_res[2] <= 1'b1;
end else if (maple_data == 8'b_1111_1100) begin // buttons[15:8] Z pressed, Y pressed
pullup_osd[1:0] <= 2'b11;
end
cdata_in.y <= ~maple_data[1];
cdata_in.x <= ~maple_data[2];
keydata_in.leds <= maple_data;
// map arcade stick Z to ltrigger/cancel
cdata_in.ltrigger <= ~maple_data[0] | cdata_in.ltrigger;
end
11: begin
if (maple_data == 8'b_1111_0011) begin // buttons[7:0] A pressed, START pressed
pullup_osd[3] <= 1'b1;
end else if (maple_data == 8'b_1111_0101) begin // buttons[7:0] B pressed, START pressed
trig_def_res[3] <= 1'b1;
end else if (maple_data == 8'b_1111_0100) begin // buttons[7:0] C pressed, B pressed, START pressed
pullup_osd[3:2] <= 2'b11;
end
cdata_in.b <= ~maple_data[1];
cdata_in.a <= ~maple_data[2];
cdata_in.start <= ~maple_data[3];
cdata_in.up <= ~maple_data[4];
cdata_in.down <= ~maple_data[5];
cdata_in.left <= ~maple_data[6];
cdata_in.right <= ~maple_data[7];
keydata_in.shiftcode <= maple_data;
// map arcade stick C to rtrigger/ok
cdata_in.rtrigger <= ~maple_data[0] | cdata_in.rtrigger;
end
12: begin
keydata_in.key6 <= maple_data;
end
13: begin
keydata_in.key5 <= maple_data;
end
14: begin
keydata_in.key4 <= maple_data;
end
15: begin
keydata_in.key3 <= maple_data;
end
default: begin
// ignored
end
endcase
pos <= pos + 1'b1;
end
end
end
assign maple_trigger_start = trigger_start;
assign controller_data = cdata_out;
assign keyboard_data = keydata_out;
endmodule
|
// daq_dma32_debug.v
`timescale 1 ns / 1 ps
/*
register set:
offset | bits | name |access| description
-------+------+-----------+------+--------------------------------
0 | 30:0 | mem_base | R/W |memory base byte address
4 | 25:0 | mem_size | R/W |memory size in words (16 bit)
8 | 25:0 | mem_read | R/W |memory read offset in words
12 | 25:0 | mem_write | R |memory write offset in words
16 | 0 | control | W | bit 0: enable
16 | 2:0 | status | R | {fifo_ovfl, ram_ovfl, running}
*/
module daq_dma32
(
input clk,
input reset,
// avalon mm data master
input avm_data_waitrq,
output avm_data_write,
output [31:0]avm_data_writedata,
output [31:0]avm_data_address,
output [3:0]avm_data_byteenable,
// avalon mm ctrl slave
input avs_ctrl_write,
input [31:0]avs_ctrl_writedata,
input avs_ctrl_read,
output reg [31:0]avs_ctrl_readdata,
input [2:0]avs_ctrl_address,
// conduit interface
input clk_daq,
input write,
input [15:0]din,
output reg running
);
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire dreg_clear;
wire dreg_write;
wire [15:0]data;
wire [1:0]be;
wire next;
// register
reg [15:0]dreg;
reg dreg_empty;
reg [30:1]mem_base;
reg [26:1]mem_size;
reg [26:1]mem_read;
reg [26:1]mem_write;
reg next2;
reg start;
reg fifo_ovfl;
reg ram_ovfl;
reg running_int;
// --- register write -----------------------------------------------------
wire write_ctrl = avs_ctrl_write && (avs_ctrl_address == 3'd4);
wire set_start = write_ctrl && avs_ctrl_writedata[0];
wire set_stop = write_ctrl && !avs_ctrl_writedata[0];
wire [26:1]inc_addr = mem_write + 1;
wire carry = inc_addr == mem_size;
wire [26:1]next_addr = carry ? 0 : inc_addr;
wire overflow = next_addr == mem_read;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
dreg <= 0;
dreg_empty <= 1;
next2 <= 0;
mem_base <= 0;
mem_size <= 0;
mem_write <= 0;
mem_read <= 0;
start <= 0;
running_int <= 0;
fifo_ovfl <= 0;
ram_ovfl <= 0;
end
else
begin
start <= set_start;
if (running_int)
begin
if (dreg_write) {dreg, dreg_empty} = {data, 1'b0};
else if (dreg_clear) dreg_empty = 1'b1;
if (overflow) ram_ovfl <= 1;
if (fifo_full) fifo_ovfl <= 1;
if (overflow || fifo_full || set_stop) running_int <= 0;
if (next || next2) mem_write <= next_addr;
if ((be == 3) && avm_data_write && !avm_data_waitrq) next2 <= 1;
else if (!next) next2 <= 0;
if (avs_ctrl_write && (avs_ctrl_address == 2))
mem_read <= avs_ctrl_writedata[25:0];
end
else if (start)
begin
dreg_empty <= 1;
next2 <= 0;
mem_write <= 0;
mem_read <= 0;
fifo_ovfl <= 0;
ram_ovfl <= 0;
running_int <= 1;
end
else
begin
if (avs_ctrl_write)
case (avs_ctrl_address)
0: mem_base <= avs_ctrl_writedata[30:1];
1: mem_size <= avs_ctrl_writedata[25:0];
2: mem_read <= avs_ctrl_writedata[25:0];
endcase
end
end
end
// --- register read ------------------------------------------------------
always @(*)
begin
case (avs_ctrl_address)
0: avs_ctrl_readdata <= {1'b0, mem_base, 1'b0};
1: avs_ctrl_readdata <= {6'b000000, mem_size };
2: avs_ctrl_readdata <= {6'b000000, mem_read };
3: avs_ctrl_readdata <= {6'b000000, mem_write };
default: avs_ctrl_readdata <= {29'b0, fifo_ovfl, ram_ovfl, running_int};
endcase
end
// --- DMA write controller -----------------------------------------------
wire [30:1]address = mem_base + {4'b0000, mem_write};
reg [6:0]sm_out;
always @(*)
begin
if (running_int)
case ({fifo_empty, dreg_empty, address[1], avm_data_waitrq})
4'b0000: sm_out <= 7'b1011111;
4'b0001: sm_out <= 7'b0001110;
4'b0010: sm_out <= 7'b1101101;
4'b0011: sm_out <= 7'b0001100;
4'b0100: sm_out <= 7'b1100110;
4'b0101: sm_out <= 7'b1100110;
4'b0110: sm_out <= 7'b1100100;
4'b0111: sm_out <= 7'b1100100;
4'b1000: sm_out <= 7'b0011011;
4'b1001: sm_out <= 7'b0001010;
4'b1010: sm_out <= 7'b0011101;
4'b1011: sm_out <= 7'b0001100;
4'b1100: sm_out <= 7'b0000010;
4'b1101: sm_out <= 7'b0000010;
4'b1110: sm_out <= 7'b0000100;
4'b1111: sm_out <= 7'b0000100;
endcase
else sm_out <= 7'b0000000;
end
assign {fifo_read, dreg_write, dreg_clear, avm_data_write, be, next} = sm_out;
assign avm_data_byteenable = { be[1], be[1], be[0], be[0] };
assign avm_data_address = {1'b0, address[30:2], 2'b00};
assign avm_data_writedata = be[0] ? {data, dreg} : {dreg, dreg};
daq_dma_fifo buffer
(
.aclr(reset || start),
.data(din),
.rdclk(clk),
.rdreq(fifo_read),
.wrclk(clk_daq),
.wrreq(write),
.q(data),
.rdempty(fifo_empty),
.rdfull(fifo_full)
);
// clock crossing: runnning_int -> running
reg running1;
always @(posedge clk_daq or posedge reset)
begin
if (reset)
begin
running1 <= 0;
running <= 0;
end
else
begin
running1 <= running_int;
running <= running1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 5048; vector<int> adj[MAX]; bool used[MAX]; int dist[MAX][MAX]; void solve(const int test_num) { (void)test_num; int v, e; cin >> v >> e; for (int ee = 0, a, b; ee < e; ++ee) { cin >> a >> b; adj[a].push_back(b); } memset(dist, 0, sizeof(dist)); queue<int> que; for (int st = 1; st <= v; ++st) { que.push(st); while (!que.empty()) { const int at = que.front(); que.pop(); for (const int to : adj[at]) { if (dist[st][to] == 0) { dist[st][to] = dist[st][at] + 1; que.push(to); } } } } memset(used, false, sizeof(used)); int res = v; for (int at = 1; at <= v; ++at) { if (used[at]) continue; used[at] = true; int min_cycle = dist[at][at]; bool is_sink = true; for (int to = 1; to <= v; ++to) { if (dist[at][to] && dist[to][at]) { used[to] = true; min_cycle = min(min_cycle, dist[to][to]); } if (dist[at][to] && !dist[to][at]) { is_sink = false; } } if (is_sink && min_cycle) { res += 998 * min_cycle + 1; } } cout << res << endl; } void init() {} int main() { ios::sync_with_stdio(false); cin.tie(nullptr); srand(1223); init(); int tests = 1; for (int test = 1; test <= tests; ++test) { solve(test); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200020; long long int n; int main() { cin >> n; for (long long int i = 1; i <= n - 1; i++) { for (long long int j = 1; j <= n - 1; j++) { if (i == j) cout << 0 ; else cout << 1 + (i + j - 2) % (n - 1) << ; } cout << (2 * i - 2) % (n - 1) + 1 << endl; } for (long long int i = 1; i <= n - 1; i++) { cout << (2 * i - 2) % (n - 1) + 1 << ; } cout << 0 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> ft(1, 1LL); int n, ans[3], hg, xxx = 0; vector<int> graph[200005], vis(200005); queue<int> q; void dfs(int node, int par, int i, int h) { if (h >= hg) hg = h, ans[i] = node; for (auto child : graph[node]) if (child != par) dfs(child, node, i, h + 1); } int dfs2(int node, int par, int dest) { if (node == dest) { q.push(node); vis[node] = 1; return 1; } for (auto child : graph[node]) { if (child == par) continue; if (dfs2(child, node, dest)) { q.push(node), vis[node] = 1; return 1; } } return 0; } void solve() { cin >> n; for (long long i = 0; i < n - 1; i++) { int node1, node2; cin >> node1 >> node2; graph[node1].push_back(node2), graph[node2].push_back(node1); } dfs(1, 0, 0, 0); hg = 0; dfs(ans[0], 0, 1, 0); xxx = hg; dfs2(ans[0], 0, ans[1]); hg = 0; while (q.size()) { int p = q.front(); if (vis[p] >= hg and p != ans[0] and p != ans[1]) hg = vis[p], ans[2] = p; q.pop(); for (auto child : graph[p]) { if (vis[child] == 0) vis[child] = vis[p] + 1, q.push(child); } } cout << xxx + hg - 1 << n ; cout << ans[1] << << ans[2] << << ans[0]; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int N = (int)5e5 + 50; int n; int ans[N]; vector<int> G[N]; int q[N]; int dep[N]; vector<pair<int, int> > hist[N]; void upd(int u, int val) { q[u] = max(q[u], val); } void calc(int v, int p) { dep[v] = 0; for (int nxt : G[v]) { if (nxt == p) continue; calc(nxt, v); dep[v] = max(dep[nxt] + 1, dep[v]); } } void merge(vector<pair<int, int> > h1, vector<pair<int, int> > h2) { int r = 0; for (int i = 0; i < h1.size(); i++) { while (r < h2.size() && (h2[r].first >= h1[i].first)) { r++; } if (r - 1 >= 0 && h2[r - 1].second > 1) upd(2 * h1[i].first, h2[r - 1].second + h1[i].second - 2); } } void dfs(int v, int p = -1, int up_dep = -1) { vector<int> deps; if (up_dep != -1) deps.push_back(up_dep + 1); for (int nxt : G[v]) { if (nxt != p) deps.push_back(dep[nxt] + 1); } sort(deps.begin(), deps.end(), [](const int a, const int b) { return a > b; }); for (int i = 0; i < deps.size(); i++) { upd(2 * deps[i], i + 1); upd(2 * deps[i] - 1, i + 1); if (i > 0 && deps[i - 1] > deps[i]) upd(2 * deps[i] + 1, i + 1); } for (int i = 0; i < deps.size(); i++) { if (hist[v].empty() || hist[v].back().first != deps[i]) hist[v].push_back({deps[i], 1}); else hist[v].back().second++; } for (int i = 1; i < hist[v].size(); i++) hist[v][i].second += hist[v][i - 1].second; for (int nxt : G[v]) { if (nxt == p) continue; dfs(nxt, v, (deps.size() == 1 ? 0 : (deps[0] == dep[nxt] + 1 ? deps[1] : deps[0]))); merge(hist[nxt], hist[v]); merge(hist[v], hist[nxt]); } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--, b--; G[a].push_back(b); G[b].push_back(a); } for (int i = 0; i < n; i++) { ans[1] = max(ans[1], (int)G[i].size() + 1); } calc(0, -1); dfs(0); int rmax = 0; for (int i = (n - 1) / 2 * 2 + 1; i >= 2; i -= 2) { rmax = max(rmax, q[i]); ans[i] = rmax; } rmax = 0; for (int i = n / 2 * 2; i >= 2; i -= 2) { rmax = max(rmax, q[i]); ans[i] = rmax; } for (int i = 1; i <= n; i++) cout << max(ans[i], 1) << ; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module timestamp
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IDENTIFIER = 4'b0001
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK,
input wire DI,
input wire [63:0] EXT_TIMESTAMP,
output wire [63:0] TIMESTAMP_OUT,
input wire EXT_ENABLE,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
timestamp_core
#(
.ABUSWIDTH(ABUSWIDTH),
.IDENTIFIER(IDENTIFIER)
) i_timestamp_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK(CLK),
.DI(DI),
.TIMESTAMP_OUT(TIMESTAMP_OUT),
.EXT_TIMESTAMP(EXT_TIMESTAMP),
.EXT_ENABLE(EXT_ENABLE),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA)
);
endmodule
|
/*64 bit wide byte addressable memory*/
module ememory(/*AUTOARG*/
// Outputs
wait_out, access_out, write_out, datamode_out, ctrlmode_out,
dstaddr_out, data_out, srcaddr_out,
// Inputs
clk, reset, access_in, write_in, datamode_in, ctrlmode_in,
dstaddr_in, data_in, srcaddr_in, wait_in
);
parameter DW = 32;
parameter AW = 32;
parameter MAW = 10;
//Basic Interface
input clk;
input reset;
//incoming read/write
input access_in;
input write_in;
input [1:0] datamode_in;
input [3:0] ctrlmode_in;
input [AW-1:0] dstaddr_in;
input [DW-1:0] data_in;
input [AW-1:0] srcaddr_in;
output wait_out; //pushback
//back to mesh (readback data)
output access_out;
output write_out;
output [1:0] datamode_out;
output [3:0] ctrlmode_out;
output [AW-1:0] dstaddr_out;
output [DW-1:0] data_out;
output [AW-1:0] srcaddr_out;
input wait_in; //pushback
wire [MAW-1:0] addr;
wire [63:0] din;
wire [63:0] dout;
wire en;
wire mem_rd;
wire mem_wr;
reg [7:0] wen;
//State
reg access_out;
reg write_out;
reg [1:0] datamode_out;
reg [3:0] ctrlmode_out;
reg [AW-1:0] dstaddr_out;
reg [AW-1:0] srcaddr_out;
reg hilo_sel;
//Access-in
assign mem_rd = (access_in & ~write_in & ~wait_in);
assign mem_wr = (access_in & write_in );
assign en = mem_rd | mem_wr;
//Pushback Circuit (pass through problems?)
assign wait_out = access_in & wait_in;
//Address-in (shifted by three bits, 64 bit wide memory)
assign addr[MAW-1:0] = dstaddr_in[MAW+2:3];
//Data-in (hardoded width)
assign din[63:0] =(datamode_in[1:0]==2'b11) ? {srcaddr_in[31:0],data_in[31:0]}:
{data_in[31:0],data_in[31:0]};
//Write mask
always@*
casez({write_in, datamode_in[1:0],dstaddr_in[2:0]})
//Byte
6'b100000 : wen[7:0] = 8'b00000001;
6'b100001 : wen[7:0] = 8'b00000010;
6'b100010 : wen[7:0] = 8'b00000100;
6'b100011 : wen[7:0] = 8'b00001000;
6'b100100 : wen[7:0] = 8'b00010000;
6'b100101 : wen[7:0] = 8'b00100000;
6'b100110 : wen[7:0] = 8'b01000000;
6'b100111 : wen[7:0] = 8'b10000000;
//Short
6'b10100? : wen[7:0] = 8'b00000011;
6'b10101? : wen[7:0] = 8'b00001100;
6'b10110? : wen[7:0] = 8'b00110000;
6'b10111? : wen[7:0] = 8'b11000000;
//Word
6'b1100?? : wen[7:0] = 8'b00001111;
6'b1101?? : wen[7:0] = 8'b11110000;
//Double
6'b111??? : wen[7:0] = 8'b11111111;
default : wen[7:0] = 8'b00000000;
endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
//Single ported memory
defparam mem.DW=2*DW;//TODO: really fixed to 64 bits
defparam mem.AW=MAW;
memory_sp mem(
// Inputs
.clk (clk),
.en (en),
.wen (wen[7:0]),
.addr (addr[MAW-1:0]),
.din (din[63:0]),
.dout (dout[63:0])
);
//Outgoing transaction
always @ (posedge clk)
access_out <= mem_rd;
//Other emesh signals "dataload"
always @ (posedge clk)
if(mem_rd)
begin
write_out <= 1'b1;
hilo_sel <= dstaddr_in[2];
datamode_out[1:0] <= datamode_in[1:0];
ctrlmode_out[3:0] <= ctrlmode_in[3:0];
srcaddr_out[AW-1:0] <= dout[63:32];
dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
end
assign data_out[DW-1:0] = hilo_sel ? dout[63:32] :
dout[31:0];
endmodule // emesh_memory
// Local Variables:
// verilog-library-directories:("." )
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fifo_w8_d2_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module fifo_w8_d2_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w8_d2_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w8_d2_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using pii = pair<int, int>; const int mod = 998244353; const int maxn = 2e5 + 10; struct edge { int st, ed; int w; bool operator<(const edge &b) const { return w < b.w; } edge() {} edge(int st, int ed, int w) : st(st), ed(ed), w(w) {} }; edge e[maxn]; int vet[805]; ll dis[805][805]; int temp[805], cnt; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); for (int i = 0; i < m; ++i) { int x, y, w; scanf( %d %d %d , &x, &y, &w); e[i] = edge(x, y, w); } sort(e, e + m); for (int i = 0; i < min(m, k); ++i) { temp[cnt++] = e[i].st; temp[cnt++] = e[i].ed; } sort(temp, temp + cnt); cnt = unique(temp, temp + cnt) - temp; memset(dis, 0x3f, sizeof(dis)); for (int i = 0; i < min(m, k); ++i) { int x, y; x = lower_bound(temp, temp + cnt, e[i].st) - temp; y = lower_bound(temp, temp + cnt, e[i].ed) - temp; dis[x][y] = min(dis[x][y], (ll)e[i].w); dis[y][x] = dis[x][y]; } for (int a = 0; a < cnt; ++a) { for (int i = 0; i < cnt; ++i) { for (int j = i + 1; j < cnt; ++j) { dis[i][j] = min(dis[i][j], dis[i][a] + dis[a][j]); dis[j][i] = dis[i][j]; } } } vector<ll> ans; for (int i = 0; i < cnt; ++i) { for (int j = i + 1; j < cnt; ++j) ans.push_back(dis[i][j]); } sort(ans.begin(), ans.end()); printf( %lld n , ans[k - 1]); }
|
#include <bits/stdc++.h> int main() { puts( 1 ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_4_V
`define SKY130_FD_SC_LS__A22O_4_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22o_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_4_V
|
#include <bits/stdc++.h> using namespace std; int n, m, notFind; vector<pair<int, int>> edge[100001]; vector<int> ans[2], e[2]; int vis[100001]; void DFS(int u, int c, int vit) { vis[u] = c; e[c].push_back(u); for (auto k : edge[u]) { int v, col, nextCol; tie(v, col) = k; col = (col + c) % 2; nextCol = col == vit ? 0 : 1; if (vis[v] != -1) { if (vis[v] != nextCol) notFind = 1; continue; } DFS(v, nextCol, vit); } } bool solve(int vit) { memset(vis, -1, sizeof(vis)); notFind = 0; for (int i = 1; i <= n; ++i) { if (vis[i] != -1) continue; e[0].clear(); e[1].clear(); DFS(i, 0, vit); if (notFind) return 0; if (e[0].size() > e[1].size()) swap(e[0], e[1]); for (auto j : e[0]) ans[vit].push_back(j); } return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 0; i < m; ++i) { int u, v; char chr; cin >> u >> v >> chr; edge[u].push_back({v, chr == R }); edge[v].push_back({u, chr == R }); } bool n1, n2; int id = 0; n1 = solve(0); n2 = solve(1); if (!n1 && !n2) return cout << -1 , 0; if (!n1 || n1 && n2 && ans[0].size() > ans[1].size()) id = 1; cout << ans[id].size() << n ; for (auto k : ans[id]) cout << k << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 10; char s[N], t[N]; int n; vector<int> G; void shift(int x) { if (x == 0) return; reverse(s, s + n); reverse(s + x, s + n); G.push_back(x); } int main() { scanf( %d%s%s , &n, s, t); for (int i = 0; i < n; i++) { int j = i; while (j < n && s[j] != t[n - i - 1]) j++; if (j == n) { puts( -1 ); exit(0); } shift(n); shift(j); shift(1); } printf( %d n , G.size()); for (int i = 0; i < (int)G.size(); ++i) printf( %d , G[i]); }
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#include <bits/stdc++.h> using namespace std; long long power_mod(long long num, long long g) { if (g == 0) return 1; if (g % 2 == 1) return (num * power_mod((num * num) % 1000000007, g / 2)) % 1000000007; return power_mod((num * num) % 1000000007, g / 2); } long long power(long long num, long long g) { if (g == 0) return 1; if (g % 2 == 1) return (num * power((num * num), g / 2)); return power((num * num), g / 2); } long long a[201], b[201], c[201]; long long d[201][201][201]; long long solve(long long x, long long y, long long z) { long long e = 0; if (d[x][y][z] > -1) return d[x][y][z]; long long ans = 0; if (x > 0 && y > 0) { ans = max(ans, solve(x - 1, y - 1, z) + a[x - 1] * b[y - 1]); } if (x > 0 && z > 0) { ans = max(ans, solve(x - 1, y, z - 1) + a[x - 1] * c[z - 1]); } if (z > 0 && y > 0) { ans = max(ans, solve(x, y - 1, z - 1) + b[y - 1] * c[z - 1]); } return d[x][y][z] = ans; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; string s; cin >> s; vector<pair<long long, long long> > vec, vec1; for (long long i = 0; i < n; i++) { long long x = 1; while (i + 1 < n && s[i] == s[i + 1]) x++, i++; if (s[i] == ? ) vec.push_back(make_pair(x, 2)); else vec.push_back(make_pair(x, s[i] - 0 )); } long long l = vec.size(); long long x = 0; for (long long i = 0; i < l; i++) { if (i == 0) vec1.push_back(vec[0]); else if (i == 1 && vec1[0].second == 2) { vec1[0].first += vec[i].first; vec1[0].second = vec[i].second; } else if (vec[i].second < 2) vec1.push_back(vec[i]), x++; else { if (i + 1 < l && vec[i + 1].second == vec1[x].second) { vec1[x].first += vec[i].first + vec[i + 1].first; i++; } else vec1.push_back(vec[i]), x++; } } l = vec1.size(); if (l > 1 && vec1[l - 1].second == 2) { vec1[l - 2].first += vec1[l - 1].first; vec1.pop_back(); } vec = vec1; l = vec1.size(); if (l == 1) { for (long long i = 1; i <= n; i++) { cout << n / i << ; } cout << endl; return 0; } cout << n; for (long long i = 2; i <= n; i++) { vec1.clear(); long long ans = 0; l = vec.size(); long long prev = 0; for (long long j = 0; j < l; j++) { long long er = vec[j].first; if (j > 0 && vec[j - 1].second == 2) er += vec[j - 1].first; if (j + 1 < l && vec[j + 1].second == 2) er += vec[j + 1].first; if (er >= i) { vec1.push_back(vec[j]); if (j + 1 < l && vec[j + 1].second == 2) vec1.push_back(vec[j + 1]); } else { long long rt = vec1.size(); if (rt > 0 && vec1[rt - 1].second == 2) { vec1[rt - 2].first += vec1[rt - 1].first; vec1.pop_back(); } if (j + 1 < l && vec[j + 1].second == 2) { vec[j + 2].first += vec[j + 1].first; vec[j + 1].first = 0; } } if (j + 1 < l && vec[j + 1].second == 2) { prev += vec[j + 1].first + vec[j].first; ans += prev / i; prev = min(prev % i, vec[j + 1].first); j++; } else { prev += vec[j].first; ans += prev / i; prev = 0; } } cout << << ans; vec = vec1; } return 0; }
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#include <bits/stdc++.h> using namespace std; struct rec { int x, p; } a[101]; vector<rec> ans; int n; bool was[101]; bool cmp(rec a, rec b) { return a.x > b.x; } void dfs(int v) { was[v] = true; for (int i = v + 1; i < n; ++i) { if (a[v].x == 0) break; if (!was[i]) { a[v].x--; rec r; r.x = a[v].p; r.p = a[i].p; ans.push_back(r); dfs(i); } } } int main() { cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i].x; a[i].p = i; } sort(a + 1, a + n, cmp); dfs(0); for (int i = 0; i < n; ++i) if (!was[i]) { cout << -1; return 0; } cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) { cout << ans[i].x + 1 << << ans[i].p + 1 << endl; } return 0; }
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`timescale 1ns / 1ps
/*
-- Module Name: switch fabric -- crossbar --
-- Description: Estructura de interconexion entre puertos de entrada y
salida. El modulo implementa un crossbar por medio de un
conjunto de multiplexores.
Las señales de control provienen del camino de control,
en especifico de los modulos 'planificador de salida'.
-- Dependencies: -- system.vh
-- Parameters: -- CHANNEL_WIDTH: Ancho de palabra de los canales
de comunicacion entre routers.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 07 de Junio 2015
*/
`include "system.vh"
module switch_fabric
(
input wire clk,
input wire reset,
// -- input -------------------------------------------------- >>>>>
input wire [`CHANNEL_WIDTH-1:0] inport_pe_din,
input wire [`CHANNEL_WIDTH-1:0] inport_xpos_din,
input wire [`CHANNEL_WIDTH-1:0] inport_ypos_din,
input wire [`CHANNEL_WIDTH-1:0] inport_xneg_din,
input wire [`CHANNEL_WIDTH-1:0] inport_yneg_din,
input wire [3:0] conf_pe_din,
input wire [3:0] conf_xpos_din,
input wire [3:0] conf_ypos_din,
input wire [3:0] conf_xneg_din,
input wire [3:0] conf_yneg_din,
// -- output ------------------------------------------------- >>>>>
output reg [`CHANNEL_WIDTH-1:0] outport_pe_dout,
output reg [`CHANNEL_WIDTH-1:0] outport_xpos_dout,
output reg [`CHANNEL_WIDTH-1:0] outport_ypos_dout,
output reg [`CHANNEL_WIDTH-1:0] outport_xneg_dout,
output reg [`CHANNEL_WIDTH-1:0] outport_yneg_dout
);
/*
-- Descripcion: Nucleo de crossbar. Cada puerto de salida esta
resguardado por un multiplexor. Cada multiplexor recibe
las salidas de las colas de almacenamiento de los
puertos de entrada de direcciones opuestas a el.
Ej. El multiplexor resguardando el puerto de salida 'y-'
esta conectado a las colas de almacenamiento {pe, x+,
y+, x-}.
Cada multiplexor tiene a su salida un registro. Este
registro disminuye el retardo de propagacion de
informacion al router vecino. Sin embargo, el registro
agreaga 1 ciclo de latencia en la propagacion de datos.
Para eliminar este registro solo se debe de sustituir:
always @(posedge clk)
outport_pe_dout = output_pe;
con:
assign outport_pe_dout = output_pe;
y cambiar el tipo de señal del puerto de salida en la
declaracion del modulo de 'reg' a 'wire'.
*/
// -- Parametros locales ----------------------------------------- >>>>>
localparam RQS0 = 4'b0001;
localparam RQS1 = 4'b0010;
localparam RQS2 = 4'b0100;
localparam RQS3 = 4'b1000;
// -- MUX :: Salida PE ------------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_pe;
always @(*)
begin
output_pe = {`CHANNEL_WIDTH{1'b0}};
case (conf_pe_din)
RQS0: output_pe = inport_xpos_din;
RQS1: output_pe = inport_ypos_din;
RQS2: output_pe = inport_xneg_din;
RQS3: output_pe = inport_yneg_din;
endcase // conf_pe_din
end
// -- Registro de Puerto de Salida PE ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_pe_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_pe_dout = output_pe;
// -- MUX :: Salida X+ --------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_xpos;
always @(*)
begin
output_xpos = {`CHANNEL_WIDTH{1'b0}};
case (conf_xpos_din)
RQS0: output_xpos = inport_pe_din;
RQS1: output_xpos = inport_ypos_din;
RQS2: output_xpos = inport_xneg_din;
RQS3: output_xpos = inport_yneg_din;
endcase // conf_xpos_din
end
// -- Registro de Puerto de Salida X+ ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_xpos_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_xpos_dout = output_xpos;
// -- MUX :: Salida Y+ --------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_ypos;
always @(*)
begin
output_ypos = {`CHANNEL_WIDTH{1'b0}};
case (conf_ypos_din)
RQS0: output_ypos = inport_pe_din;
RQS1: output_ypos = inport_xpos_din;
RQS2: output_ypos = inport_xneg_din;
RQS3: output_ypos = inport_yneg_din;
endcase // conf_ypos_din
end
// -- Registro de Puerto de Salida Y+ ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_ypos_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_ypos_dout = output_ypos;
// -- MUX :: Salida X- --------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_xneg;
always @(*)
begin
output_xneg = {`CHANNEL_WIDTH{1'b0}};
case (conf_xneg_din)
RQS0: output_xneg = inport_pe_din;
RQS1: output_xneg = inport_xpos_din;
RQS2: output_xneg = inport_ypos_din;
RQS3: output_xneg = inport_yneg_din;
endcase // conf_xneg_din
end
// -- Registro de Puerto de Salida X- ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_xneg_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_xneg_dout = output_xneg;
// -- MUX :: Salida Y- --------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_yneg;
always @(*)
begin
output_yneg = {`CHANNEL_WIDTH{1'b0}};
case (conf_yneg_din)
RQS0: output_yneg = inport_pe_din;
RQS1: output_yneg = inport_xpos_din;
RQS2: output_yneg = inport_ypos_din;
RQS3: output_yneg = inport_xneg_din;
endcase // conf_yneg_din
end
// -- Registro de Puerto de Salida Y- ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_yneg_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_yneg_dout = output_yneg;
endmodule
/*-- Plantilla de Instancia -------------------------------------- >>>>>
switch_fabric xbar
(
.clk (clk),
// -- input -------------------------------------------------- >>>>>
.inport_pe_din (inport_pe_din),
.inport_xpos_din (inport_xpos_din),
.inport_ypos_din (inport_ypos_din),
.inport_xneg_din (inport_xneg_din),
.inport_yneg_din (inport_yneg_din),
.conf_pe_din (conf_pe_din),
.conf_xpos_din (conf_xpos_din),
.conf_ypos_din (conf_ypos_din),
.conf_xneg_din (conf_xneg_din),
.conf_yneg_din (conf_yneg_din),
// -- output ------------------------------------------------- >>>>>
.outport_pe_dout (outport_pe_dout),
.outport_xpos_dout (outport_xpos_dout),
.outport_ypos_dout (outport_ypos_dout),
.outport_xneg_dout (outport_xneg_dout),
.outport_yneg_dout (outport_yneg_dout)
);
*/
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