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#include <bits/stdc++.h> int n, u[1001], v[1001], dem[1001], ans = 0; using namespace std; void input() { cin >> n; for (int i = 1; i < n; i++) { cin >> u[i] >> v[i]; } } void output() { cout << ans << endl; } void solve() { for (int i = 1; i <= n; i++) { for (int j = 1; j < n; j++) { if (u[j] == i) dem[i]++; if (v[j] == i) dem[i]++; } } for (int i = 1; i <= n; i++) { if (dem[i] == 1) ans++; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); input(); solve(); output(); }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using namespace std; int a[1100][1100], pt[1100], b[] = {25, 18, 15, 12, 10, 8, 6, 4, 2, 1}, ef, n; map<string, int> m; string st[1100]; int f(int aa, int bb) { if (pt[aa] != pt[bb]) return pt[aa] > pt[bb]; else { for (int i = 0; i < 60; i++) if (a[aa][i] != a[bb][i]) return a[aa][i] > a[bb][i]; return 0; } } int f2(int aa, int bb) { if (a[aa][0] != a[bb][0]) return a[aa][0] > a[bb][0]; else return f(aa, bb); } int main() { int t; cin >> t; for (int ii = 0; ii < t; ii++) { cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; if (m.find(s) == m.end()) { m[s] = ef++; st[ef - 1] = s; } a[m[s]][i]++; if (i <= 9) pt[m[s]] += b[i]; } } int r[1100]; for (int i = 0; i < m.size(); i++) r[i] = i; sort(r, r + m.size(), f); cout << st[r[0]] << endl; sort(r, r + m.size(), f2); cout << st[r[0]] << endl; }
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/* Save Register Files Definition
Slave:
offset 0: Address: 32-bits start address
offset 2: control:
offset 1: status:
*/
module CAMERA_IF( // avalon MM slave port, ISP1362, host control
// global
//===== avalon MM s1 slave (read/write)
// read/write
avs_s1_clk,
avs_s1_address,
avs_s1_readdata,
avs_s1_read,
avs_s1_writedata,
avs_s1_write,
avs_s1_reset,
//
//===== Interface s1 to export
// read/write
avs_s1_export_clk,
avs_s1_export_address,
avs_s1_export_readdata,
avs_s1_export_read,
avs_s1_export_writedata,
avs_s1_export_write,
avs_s1_export_reset
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wire/Register *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// s1
input avs_s1_clk;
input [1:0] avs_s1_address;
output [31:0] avs_s1_readdata;
input avs_s1_read;
input [31:0] avs_s1_writedata;
input avs_s1_write;
input avs_s1_reset;
//
//===== Interface to export
// s1
output avs_s1_export_clk;
output [1:0] avs_s1_export_address;
input [31:0] avs_s1_export_readdata;
output avs_s1_export_read;
output [31:0] avs_s1_export_writedata;
output avs_s1_export_write;
output avs_s1_export_reset;
/*****************************************************************************
* Sequence logic *
*****************************************************************************/
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
// s1
assign avs_s1_export_clk = avs_s1_clk;
assign avs_s1_export_address = avs_s1_address;
assign avs_s1_readdata = avs_s1_export_readdata;
assign avs_s1_export_read = avs_s1_read;
assign avs_s1_export_writedata = avs_s1_writedata;
assign avs_s1_export_write = avs_s1_write;
assign avs_s1_export_reset = avs_s1_reset;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; long long int ans = 0; if (n < k) { cout << n << endl; continue; } while (n != 0) { if (n % k == 0) { n = n / k; ans++; } else { long long x = n % k; n -= x; ans += x; } } cout << ans << endl; } return 0; }
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#include <bits/stdc++.h> char c[99]; int i, x; int main() { for (;;) { scanf( %s , c); fflush(stdout); ; if (*c == e ) break; for (i = 2; i <= 1 << 30; i <<= 1) { printf( ? %d %d n , i, i >> 1); fflush(stdout); ; scanf( %s , c); fflush(stdout); ; if (*c == y || i == 1 << 30) break; } if (*c == x ) { puts( ! 1 ); fflush(stdout); ; continue; } int l = i >> 1, r = i, m; for (; l + 1 < r;) { m = (l + r) >> 1; printf( ? %d %d n , l, m); fflush(stdout); ; scanf( %s , c); fflush(stdout); ; if (*c == y ) l = m; else r = m; } printf( ! %d n , r); fflush(stdout); ; } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__EDFXBP_BEHAVIORAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long a, b, c; scanf( %lld%lld%lld , &a, &b, &c); long long ans = 0x7f7f7f7f7f7f7f7f; long long ca, cb, cc; for (long long i = 1ll; i <= 15000ll; i++) { long long a1, c1; long long minx1 = 0x7f7f7f7f7f7f7f7f; for (long long j = 1; j <= sqrt(i); j++) { if (i % j == 0) { if (minx1 > abs(i / j - a)) { minx1 = abs(i / j - a); a1 = i / j; } if (minx1 > abs(j - a)) { minx1 = abs(j - a); a1 = j; } } } if (abs(max(c / i, 1ll) * i - c) > abs((c / i + 1) * i - c)) { c1 = (c / i + 1) * i; } else { c1 = max(c / i, 1ll) * i; } if (abs(a1 - a) + abs(i - b) + abs(c1 - c) < ans) { ans = abs(a1 - a) + abs(i - b) + abs(c1 - c); ca = a1, cb = i, cc = c1; } } printf( %lld n , ans); printf( %lld %lld %lld n , ca, cb, cc); } }
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`timescale 1ns / 1ps
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-4-2017
*/
module jt51_phrom
(
input [4:0] addr,
input clk,
output reg [45:0] ph
);
reg [45:0] sinetable[31:0];
initial
begin
sinetable[5'd0 ] = 46'b0001100000100100010001000010101010101001010010;
sinetable[5'd1 ] = 46'b0001100000110100000100000010010001001101000001;
sinetable[5'd2 ] = 46'b0001100000110100000100110010001011001101100000;
sinetable[5'd3 ] = 46'b0001110000010000000000110010110001001101110010;
sinetable[5'd4 ] = 46'b0001110000010000001100000010111010001101101001;
sinetable[5'd5 ] = 46'b0001110000010100001001100010000000101101111010;
sinetable[5'd6 ] = 46'b0001110000010100001101100010010011001101011010;
sinetable[5'd7 ] = 46'b0001110000011100000101010010111000101111111100;
sinetable[5'd8 ] = 46'b0001110000111000000001110010101110001101110111;
sinetable[5'd9 ] = 46'b0001110000111000010100111000011101011010100110;
sinetable[5'd10] = 46'b0001110000111100011000011000111100001001111010;
sinetable[5'd11] = 46'b0001110000111100011100111001101011001001110111;
sinetable[5'd12] = 46'b0100100001010000010001011001001000111010110111;
sinetable[5'd13] = 46'b0100100001010100010001001001110001111100101010;
sinetable[5'd14] = 46'b0100100001010100010101101101111110100101000110;
sinetable[5'd15] = 46'b0100100011100000001000011001010110101101111001;
sinetable[5'd16] = 46'b0100100011100100001000101011100101001011101111;
sinetable[5'd17] = 46'b0100100011101100000111011010000001011010110001;
sinetable[5'd18] = 46'b0100110011001000000111101010000010111010111111;
sinetable[5'd19] = 46'b0100110011001100001011011110101110110110000001;
sinetable[5'd20] = 46'b0100110011101000011010111011001010001101110001;
sinetable[5'd21] = 46'b0100110011101101011010110101111001010100001111;
sinetable[5'd22] = 46'b0111000010000001010111000101010101010110010111;
sinetable[5'd23] = 46'b0111000010000101010111110111110101010010111011;
sinetable[5'd24] = 46'b0111000010110101101000101100001000010000011001;
sinetable[5'd25] = 46'b0111010010011001100100011110100100010010010010;
sinetable[5'd26] = 46'b0111010010111010100101100101000000110100100011;
sinetable[5'd27] = 46'b1010000010011010101101011101100001110010011010;
sinetable[5'd28] = 46'b1010000010111111111100100111010100010000111001;
sinetable[5'd29] = 46'b1010010111110100110010001100111001010110100000;
sinetable[5'd30] = 46'b1011010111010011111011011110000100110010100001;
sinetable[5'd31] = 46'b1110011011110001111011100111100001110110100111;
end
always @ (posedge clk)
ph <= sinetable[addr];
endmodule
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/*
###########################################################################
# Function: A mailbox FIFO with a FIFO empty/full flags that can be used as
# interrupts.
#
# E_MAILBOXLO = lower 32 bits of FIFO entry
# E_MAILBOXHI = upper 32 bits of FIFO entry
#
# Notes: 1.) System should take care of not overflowing the FIFO
# 2.) Reading the E_MAILBOXHI causes a fifo rd pointer update
# 3.) The "embox_not_empty" is a "level" interrupt signal.
#
# How to use: 1.) Connect "embox_not_empty" to interrupt input line
# 2.) Write an ISR to respond to interrupt line::
# -reads E_MAILBOXLO, then
# -reads E_MAILBOXHI, then
# -finishes ISR
#
###########################################################################
*/
//`include "emailbox_regmap.v" // is there a better way?
module emailbox (/*AUTOARG*/
// Outputs
mi_dout, mailbox_full, mailbox_not_empty,
// Inputs
reset, wr_clk, rd_clk, emesh_access, emesh_packet, mi_en, mi_we,
mi_addr, mi_din
);
parameter DW = 32; //data width of fifo
parameter AW = 32; //data width of fifo
parameter PW = 104; //packet size
parameter RFAW = 6; //address bus width
parameter ID = 12'h000; //link id
parameter WIDTH = 104;
parameter DEPTH = 16;
/*****************************/
/*RESET */
/*****************************/
input reset; //asynchronous reset
input wr_clk; //write clock
input rd_clk; //read clock
/*****************************/
/*WRITE INTERFACE */
/*****************************/
input emesh_access;
input [PW-1:0] emesh_packet;
/*****************************/
/*READ INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr;
input [63:0] mi_din; //assumes write interface is 64 bits
output [63:0] mi_dout;
/*****************************/
/*MAILBOX OUTPUTS */
/*****************************/
output mailbox_full;
output mailbox_not_empty;
/*****************************/
/*REGISTERS */
/*****************************/
reg [63:0] mi_dout;
/*****************************/
/*WIRES */
/*****************************/
wire mailbox_read;
wire mi_rd;
wire [WIDTH-1:0] mailbox_fifo_data;
wire mailbox_empty;
wire mailbox_pop;
wire [31:0] emesh_addr;
wire [63:0] emesh_din;
wire emesh__write;
/*****************************/
/*WRITE TO FIFO */
/*****************************/
assign emesh_addr[31:0] = emesh_packet[39:8];
assign emesh_din[63:0] = emesh_packet[103:40];
assign emesh_write = emesh_access &
emesh_packet[1] &
(emesh_addr[31:20]==ID) &
(emesh_addr[10:8]==3'h3) &
(emesh_addr[RFAW+1:2]==`E_MAILBOXLO);
/*****************************/
/*READ BACK DATA */
/*****************************/
assign mi_rd = mi_en & ~mi_we;
assign mailbox_pop = mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXHI); //fifo read
always @ (posedge rd_clk)
if(mi_rd)
case(mi_addr[RFAW+1:2])
`E_MAILBOXLO: mi_dout[63:0] <= mailbox_fifo_data[63:0];
`E_MAILBOXHI: mi_dout[63:0] <= {mailbox_fifo_data[2*DW-1:DW],
mailbox_fifo_data[2*DW-1:DW]};
default: mi_dout[63:0] <= 64'd0;
endcase // case (mi_addr[RFAW-1:2])
else
mi_dout[63:0] <= 64'd0;
/*****************************/
/*FIFO (64bit wide) */
/*****************************/
assign mailbox_not_empty = ~mailbox_empty;
//BUG! This fifo is currently hard coded to 16 entries
//Should be parametrized to up to 4096 entries
defparam fifo.DW = WIDTH;
defparam fifo.DEPTH = DEPTH;
fifo_async fifo(// Outputs
.dout (mailbox_fifo_data[WIDTH-1:0]),
.empty (mailbox_empty),
.full (mailbox_full),
.prog_full (),
.valid(),
//Read Port
.rd_en (mailbox_pop),
.rd_clk (rd_clk),
//Write Port
.din ({40'b0,emesh_din[63:0]}),
.wr_en (emesh_write),
.wr_clk (wr_clk),
.wr_rst (reset),
.rd_rst (reset)
);
endmodule // emailbox
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
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#include <bits/stdc++.h> using namespace std; int main() { int vp, vd, t, f, c; cin >> vp >> vd >> t >> f >> c; int vs = vd - vp; if (vp > vd) { cout << 0; return 0; } if (vp == vd) { cout << 0; return 0; } double d = vp * t; d += d / (1.0 * vs) * vp; cerr << d << endl; if (int(d) >= c) { cout << 0; return 0; } int ans = 1; while ((int)d < c) { d += (d / vd + f) * vp; d += (d / vs) * vp; if (d - c > -1e-12) { cout << ans; return 0; } ans++; } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; template <class C> void mini(C& a, C b) { a = min(a, b); } template <class C> void maxi(C& a, C b) { a = max(a, b); } void a() { int n; cin >> n; vector<int> a(n), b(n), c(n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) cin >> c[i]; vector<int> p(n); p[0] = a[0]; for (int(i) = 1; i <= n - 2; i++) { if (a[i] == p[i - 1]) p[i] = b[i]; else p[i] = a[i]; } if (a.back() != p[0] and a.back() != p[n - 2]) p[n - 1] = a.back(); else if (b.back() != p[0] and b.back() != p[n - 2]) p[n - 1] = b.back(); else p[n - 1] = c.back(); for (int i = 0; i < n; i++) cout << p[i] << ; cout << n ; } void b() { int n, k; cin >> n >> k; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; int diferentes = 1; for (int(i) = 1; i <= n - 1; i++) if (a[i] != a[i - 1]) diferentes++; if (k == 1 and diferentes != 1) { cout << -1 n ; return; } int res = 1; diferentes -= k; while (diferentes > 0) { res++; diferentes -= k - 1; } cout << res << n ; } void c() { int n; long long l; cin >> n >> l; vector<long long> a(n); for (int i = 0; i < n; i++) cin >> a[i]; double izq = 0; double izqVel = 1; double der = l; double derVel = 1; int i = 0; int j = n - 1; double time = 0.0; while (i <= j) { double ti = (double)(a[i] - izq) / (double)izqVel; double tj = (double)(der - a[j]) / (double)derVel; if (ti < tj) { izq = a[i]; i++; izqVel++; der -= ti * derVel; time += ti; } else { der = a[j]; j--; derVel++; izq += tj * izqVel; time += tj; } } time += (der - izq) / (izqVel + derVel); cout << setprecision(9) << fixed << time << n ; } void d() { int n, m; cin >> n >> m; vector<int> a(n), b(n), c(m), d(m); for (int i = 0; i < n; i++) cin >> a[i] >> b[i]; for (int i = 0; i < m; i++) cin >> c[i] >> d[i]; vector<pair<int, int> > delta; int dx, dy; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { dx = c[j] - a[i]; dy = d[j] - b[i]; if (dx >= 0 and dy >= 0) delta.push_back({dx, dy}); } sort(delta.begin(), delta.end()); if (delta.empty()) { cout << 0 << n ; return; } int x = delta.back().first + 1; int maxy = -1; int res = x; for (int(i) = delta.size() - 1; i >= 1; i--) { x = delta[i - 1].first + 1; maxi(maxy, delta[i].second); mini(res, x + maxy + 1); } maxi(maxy, delta[0].second); mini(res, maxy + 1); cout << res << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); d(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int INF = 1000000001; const long long LINF = 1000000000000000001LL; int len[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; string days[] = { monday , tuesday , wednesday , thursday , friday , saturday , sunday }; int dayId(string s) { return find(days, days + 7, s) - days; } int main() { ios_base::sync_with_stdio(0); string a, b; cin >> a >> b; int aid = dayId(a), bid = dayId(b); for (int i = (0); i <= (10); ++i) { if ((aid + len[i]) % 7 == bid) { cout << YES ; return 0; } } cout << NO ; return 0; }
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#include <bits/stdc++.h> struct help { long int money; long int friends; }; void fusion_sort(struct help *p, long int n); void bablesort(struct help *p, long int n); int main() { long int n, m; scanf( %ld %ld , &n, &m); struct help *p = (struct help *)malloc(sizeof(struct help) * n); for (int i = 0; i < n; i++) scanf( %ld %ld , &p[i].money, &p[i].friends); if (n == 1) { printf( %ld , p[0].friends); return 0; } if (n > 1000) fusion_sort(p, n); else bablesort(p, n); unsigned long long max_friend = 0; unsigned long long cur_sum = 0; for (int b = 0, e = 0; e < n;) if (p[e].money - p[b].money >= m) { if (cur_sum > max_friend) { max_friend = cur_sum; } cur_sum -= p[b].friends; b++; } else { cur_sum += p[e].friends; e++; } if (cur_sum > max_friend) max_friend = cur_sum; printf( %lld , max_friend); return 0; } void fusion_sort(struct help *p, long int n) { if (n > 2) { fusion_sort(p, n / 2); fusion_sort((p + n / 2), n / 2 + n % 2); } struct help temp; for (int i = 0, j = n / 2; i < j && j < n; i++) if (p[i].money > p[j].money) { temp.friends = p[j].friends; temp.money = p[j].money; for (int k = j; k > i; k--) { p[k].friends = p[k - 1].friends; p[k].money = p[k - 1].money; } p[i].friends = temp.friends; p[i].money = temp.money; j++; } } void bablesort(struct help *p, long int n) { long int fr; long int mo; while (n > 1) { for (int i = 0; i < n - 1; i++) if (p[i].money > p[i + 1].money) { fr = p[i].friends; mo = p[i].money; p[i].friends = p[i + 1].friends; p[i].money = p[i + 1].money; p[i + 1].friends = fr; p[i + 1].money = mo; } n--; } }
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#include <bits/stdc++.h> using namespace std; const int M = 200002; int val[M]; vector<int> vec[33]; set<int> st; struct Nod { int v; int id; bool operator<(const Nod &cmp) const { if (v == cmp.v) return id < cmp.id; return v > cmp.v; } } p[M]; int n; void init() { for (int i = 0; i < 32; i++) { for (int j = 0; j < n; j++) { if (val[j] & (1 << i)) { vec[i].push_back(j); } } } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &val[i]); p[i].v = val[i]; p[i].id = i; } sort(p, p + n); init(); long long ans = 0; for (int i = 0; i < n; i++) { Nod u = p[i]; set<int>::iterator it = st.upper_bound(u.id); int L, R; if (it == st.end()) { R = n - 1; } else R = *it - 1; if (it == st.begin()) { L = 0; } else { it--; L = *it + 1; } int l = L, r = R; for (int j = 0; j < 32; j++) { if ((u.v & (1 << j)) == 0) { int tl = upper_bound(vec[j].begin(), vec[j].end(), u.id) - vec[j].begin() - 1; if (tl >= 0) l = max(l, vec[j][tl] + 1); int tr = upper_bound(vec[j].begin(), vec[j].end(), u.id) - vec[j].begin(); if (tr < vec[j].size()) r = min(r, vec[j][tr] - 1); } } ans += 1ll * (u.id - l + 1) * (r - u.id + 1); st.insert(u.id); } printf( %I64d n , 1ll * n * (n + 1) / 2 - ans); return 0; }
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/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`include "pcie_defines.v"
`include "nysa_pcie_defines.v"
module pcie_egress (
input clk,
input rst,
input i_enable,
output reg o_finished,
input [7:0] i_command,
input [13:0] i_flags,
input [31:0] i_address,
input [15:0] i_requester_id,
input [7:0] i_tag,
//PCIE Egress
input [9:0] i_req_dword_cnt,
//AXI Stream Device 2 Host
input i_axi_egress_ready,
//output reg [31:0] o_axi_egress_data,
output [31:0] o_axi_egress_data,
output [3:0] o_axi_egress_keep,
output reg o_axi_egress_last,
output reg o_axi_egress_valid,
//Outgoing FIFO Data
input i_fifo_rdy,
output reg o_fifo_act,
input [23:0] i_fifo_size,
input [31:0] i_fifo_data,
output reg o_fifo_stb,
output reg dbg_ready_drop
);
//Local Parameters
localparam IDLE = 4'h0;
localparam WAIT_FOR_FIFO = 4'h1;
localparam WAIT_FOR_PCIE_CORE = 4'h2;
localparam SEND_HDR = 4'h3;
localparam SEND_DATA = 4'h4;
localparam SEND_NON_DATA_PKT_START = 4'h5;
localparam SEND_NON_DATA_PKT = 4'h6;
localparam SEND_NON_DATA_PKT_FIN = 4'h7;
localparam FINISHED = 4'h8;
//Registers/Wires
reg [3:0] state;
reg [23:0] r_data_count;
wire [31:0] w_hdr[0:3];
wire [2:0] w_hdr_size;
reg [2:0] r_hdr_index;
wire [9:0] w_pkt_data_count;
wire [31:0] w_hdr0;
wire [31:0] w_hdr1;
wire [31:0] w_hdr2;
wire [31:0] w_hdr3;
wire w_non_data_packet;
//Submodules
//Asynchronous Logic
assign o_axi_egress_keep = 4'hF;
//1st Dword
assign w_non_data_packet = (i_command == `PCIE_MRD_32B);
assign w_pkt_data_count = (i_command == `PCIE_MRD_32B) ? i_req_dword_cnt : i_fifo_size;
assign w_hdr[0][`PCIE_TYPE_RANGE] = i_command;
assign w_hdr[0][`PCIE_FLAGS_RANGE] = i_flags;
assign w_hdr[0][`PCIE_DWORD_PKT_CNT_RANGE] = w_pkt_data_count;
//2nd Dword
assign w_hdr[1] = (i_command == `PCIE_MRD_32B) ? {i_requester_id, i_tag, 8'h00} :
(i_fifo_size == 1) ? 32'h0000000F : //== 1 DWORD
32'h000000FF; // > 1 DWORD
assign w_hdr[2] = i_address;
assign w_hdr_size = (w_hdr[0][29]) ? 3'h4 : 3'h3; //Index Size is dependent on 64-bit vs 32-bit address space
assign w_hdr0 = w_hdr[0];
assign w_hdr1 = w_hdr[1];
assign w_hdr2 = w_hdr[2];
assign o_axi_egress_data = ((state == WAIT_FOR_PCIE_CORE) || (state == SEND_HDR) || (state == SEND_NON_DATA_PKT) || (state == SEND_NON_DATA_PKT_FIN)) ? w_hdr[r_hdr_index]:
i_fifo_data;
//Synchronous Logic
always @ (posedge clk) begin
//Clear Strobes
o_fifo_stb <= 0;
dbg_ready_drop <= 0;
if (rst) begin
state <= IDLE;
o_finished <= 0;
r_hdr_index <= 0;
o_axi_egress_valid <= 0;
o_axi_egress_last <= 0;
//o_axi_egress_data <= 0;
o_fifo_act <= 0;
r_data_count <= 0;
end
else begin
case (state)
IDLE: begin
o_axi_egress_valid <= 0;
o_finished <= 0;
r_data_count <= 0;
r_hdr_index <= 0;
if (i_enable) begin
if (w_non_data_packet) begin
state <= SEND_NON_DATA_PKT_START;
end
else begin
state <= WAIT_FOR_FIFO;
end
end
end
WAIT_FOR_FIFO: begin
if (i_fifo_rdy && !o_fifo_act) begin
r_data_count <= 0;
o_fifo_act <= 1;
state <= WAIT_FOR_PCIE_CORE;
//o_axi_egress_data <= w_hdr[r_hdr_index];
//r_hdr_index <= r_hdr_index + 1;
end
end
WAIT_FOR_PCIE_CORE: begin
if (i_axi_egress_ready && o_axi_egress_valid) begin
r_hdr_index <= r_hdr_index + 1;
if (r_hdr_index + 1 >= w_hdr_size) begin
if (w_non_data_packet) begin
o_axi_egress_last <= 1;
state <= FINISHED;
end
else begin
state <= SEND_DATA;
o_fifo_stb <= 1;
r_data_count <= r_data_count + 1;
end
end
end
o_axi_egress_valid <= 1;
end
SEND_DATA: begin
//o_axi_egress_data <= i_fifo_data;
o_fifo_stb <= 1;
if (r_data_count + 1 >= i_fifo_size) begin
state <= FINISHED;
o_axi_egress_last <= 1;
end
r_data_count <= r_data_count + 1;
end
SEND_NON_DATA_PKT_START: begin
if (i_axi_egress_ready) begin
state <= SEND_NON_DATA_PKT;
end
end
SEND_NON_DATA_PKT: begin
//if (i_axi_egress_ready && o_axi_egress_valid) begin
if (o_axi_egress_valid) begin
if (!i_axi_egress_ready) begin
dbg_ready_drop <= 1;
end
r_hdr_index <= r_hdr_index + 1;
if (r_hdr_index + 2 >= w_hdr_size) begin
o_axi_egress_last <= 1;
state <= SEND_NON_DATA_PKT_FIN;
end
end
o_axi_egress_valid <= 1;
end
SEND_NON_DATA_PKT_FIN: begin
o_axi_egress_valid <= 0;
o_axi_egress_last <= 0;
o_fifo_act <= 0;
state <= FINISHED;
end
FINISHED: begin
o_axi_egress_valid <= 0;
o_axi_egress_last <= 0;
o_fifo_act <= 0;
o_finished <= 1;
if (!i_enable) begin
o_finished <= 0;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5e4 + 10, max_node = N * 200; int n, m, q, C, c[N], a[N], size[N], heavy[N], dfn[N], dfn_t, top[N], father[N], tt, lo[max_node], ro[max_node], addv[max_node]; long long sum[max_node], sum2[max_node]; vector<int> graph[N], nodes[N]; void dfs1(int u) { size[u] = 1; for (auto v : graph[u]) { dfs1(v); size[u] += size[v]; if (size[v] > size[heavy[u]]) { heavy[u] = v; } } } void dfs2(int u, int t) { top[u] = t; dfn[u] = ++dfn_t; if (heavy[u]) { dfs2(heavy[u], t); for (auto v : graph[u]) { if (v != heavy[u]) { dfs2(v, v); } } } } void add(int l, int r, int o, int v) { addv[o] += v; sum2[o] += ((sum[o] << 1) + (r - l + 1) * v) * v; sum[o] += (r - l + 1) * v; } void push_down(int l, int r, int o) { if (addv[o]) { int mid = l + r >> 1; if (!lo[o]) { lo[o] = ++tt; } if (!ro[o]) { ro[o] = ++tt; } add(l, mid, lo[o], addv[o]); add(mid + 1, r, ro[o], addv[o]); addv[o] = 0; } } void push_up(int o) { sum[o] = sum[lo[o]] + sum[ro[o]]; sum2[o] = sum2[lo[o]] + sum2[ro[o]]; } void modify(int l, int r, int& o, int ql, int qr, int v) { if (!o) { o = ++tt; } if (ql <= l && r <= qr) { return add(l, r, o, v); } else { int mid = l + r >> 1; push_down(l, r, o); if (ql <= mid) { modify(l, mid, lo[o], ql, qr, v); } if (qr > mid) { modify(mid + 1, r, ro[o], ql, qr, v); } push_up(o); } } struct info_t { int root; void init(vector<int>& nodes) { for (auto v : nodes) { for (int x = v; x; x = father[top[x]]) { modify(1, n, root, dfn[top[x]], dfn[x], 1); } } } void update(int u, int type) { for (int x = u; x; x = father[top[x]]) { modify(1, n, root, dfn[top[x]], dfn[x], type); } } double get_answer(int c) { double result = (double)C * C; result -= 2.0 * C * c * sum[root] / n; result += 1.0 * c * c * sum2[root] / n; return result; } } info[N]; int main() { scanf( %d%d%d%d , &n, &m, &q, &C); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); nodes[a[i]].push_back(i); } for (int i = 2; i <= n; ++i) { scanf( %d , &father[i]); graph[father[i]].push_back(i); } for (int i = 1; i <= m; ++i) { scanf( %d , &c[i]); } dfs1(1); dfs2(1, 1); for (int i = 1; i <= m; ++i) { info[i].init(nodes[i]); } while (q--) { int type, x, w; scanf( %d , &type); if (type == 1) { scanf( %d%d , &x, &w); info[a[x]].update(x, -1); a[x] = w; info[a[x]].update(x, 1); } else { scanf( %d , &x); printf( %.12lf n , info[x].get_answer(c[x])); } } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, k, a, b, c, d, now, f[1001]; bool jud[1001]; int main() { cin.sync_with_stdio(false); cin >> n >> k; cin >> a >> b >> c >> d; if (k < n + 1 || n == 4) { cout << -1 << endl; return 0; } f[1] = a; f[2] = c; f[n - 1] = d; f[n] = b; jud[a] = jud[b] = jud[c] = jud[d] = true; int now = 1; for (int i = 3; i <= n - 2; i++) { while (jud[now]) now++; f[i] = now; now++; } for (int i = 1; i <= n - 1; i++) cout << f[i] << ; cout << f[n] << endl; cout << f[2] << << f[1] << ; for (int i = 3; i <= n - 2; i++) cout << f[i] << ; cout << f[n] << << f[n - 1]; }
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#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int inf = 2000000000; const long long infLL = 9000000000000000000; template <typename first, typename second> ostream &operator<<(ostream &os, const pair<first, second> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << } ; } template <typename T> ostream &operator<<(ostream &os, const set<T> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename T> ostream &operator<<(ostream &os, const multiset<T> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename first, typename second> ostream &operator<<(ostream &os, const map<first, second> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << it->first << = << it->second; } return os << ] ; } void faltu() { cerr << n ; } template <typename T> void faltu(T a[], int n) { for (int i = 0; i < n; ++i) cerr << a[i] << ; cerr << n ; } template <typename T, typename... hello> void faltu(T arg, const hello &...rest) { cerr << arg << ; faltu(rest...); } const int mx = 2e5 + 5; vector<int> adjlist[mx]; int n; bool isleaf[mx]; int deg[mx]; struct info { int leaf, child, dist; }; bool cmp(const info &lhs, const info &rhs) { return lhs.dist > rhs.dist; } vector<info> dp[mx]; void dfs(int u, int par) { vector<info> store; store.push_back({u, u, 0}); for (auto v : adjlist[u]) { if (v == par) continue; dfs(v, u); info temp = dp[v][0]; ++temp.dist; temp.child = v; store.push_back(temp); } sort(store.begin(), store.end(), cmp); while (store.size() > 3) store.pop_back(); dp[u] = store; } int ans = 0; vector<int> vec; void dfs2(int u, int par) { if (dp[u].size() >= 3) { if (ans < dp[u][0].dist + dp[u][1].dist + dp[u][2].dist) { ans = dp[u][0].dist + dp[u][1].dist + dp[u][2].dist; vec.clear(); vec.push_back(dp[u][0].leaf); vec.push_back(dp[u][1].leaf); vec.push_back(dp[u][2].leaf); } } for (auto v : adjlist[u]) { if (v == par) continue; for (int i = 0; i < dp[u].size(); ++i) { if (dp[u][i].child == v) continue; info temp = dp[u][i]; temp.child = u; ++temp.dist; dp[v].push_back(temp); sort(dp[v].begin(), dp[v].end(), cmp); dfs2(v, u); break; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int i = 0; i < n - 1; ++i) { int a, b; cin >> a >> b; adjlist[a].push_back(b); adjlist[b].push_back(a); ++deg[a]; ++deg[b]; } for (int i = 1; i <= n; ++i) { if (deg[i] == 1) isleaf[i] = 1; } dfs(1, 0); dfs2(1, 0); cout << ans << n ; for (int i = 0; i < vec.size(); ++i) cout << vec[i] << ; cout << n ; }
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#include <bits/stdc++.h> using namespace std; int min(int a, int b) { return a > b ? b : a; } int main() { int n, m; cin >> n >> m; cout << min(n, m) + 1 << endl; for (int i = 0; i <= min(n, m); i++) cout << i << << min(n, m) - i << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int N, tmp; bool flag = false; int main() { scanf( %d , &N); for (int i = 0; i < N; i++) { scanf( %d , &tmp); if (tmp == 1) flag = true; } if (flag) printf( %d , -1); else printf( %d , 1); return 0; }
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#include <bits/stdc++.h> using namespace std; struct node { node *next[26]; node() { for (int i = 0; i < 26; i++) next[i] = NULL; } }; void insert(node *root, string &str) { node *current = root; for (char ch : str) { if (current->next[ch - a ] == NULL) { current->next[ch - a ] = new node(); } current = current->next[ch - a ]; } } int canLose(node *root) { int was = 1, leaf = 0; for (int i = 0; i < 26; i++) { if (root->next[i]) { was = min(was, 1 ^ canLose(root->next[i])); leaf = 1; } } return was & leaf; } int canWin(node *root) { int was = 0; for (int i = 0; i < 26; i++) { if (root->next[i]) { was = max(was, 1 ^ canWin(root->next[i])); } } return was; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); node *root = new node(); int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { string str; cin >> str; insert(root, str); } if (canWin(root) && !canLose(root)) { cout << First << endl; } else if (canWin(root)) { if (k & 1) { cout << First << endl; } else { cout << Second << endl; } } else { cout << Second << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/18/2016 03:28:31 PM
// Design Name:
// Module Name: Round_Sgf_Dec
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dep encies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Round_Sgf_Dec(
input wire [1:0] Data_i,
input wire [1:0] Round_Type_i,
input wire Sign_Result_i,
output reg Round_Flag_o
);
always @*
case ({Sign_Result_i,Round_Type_i,Data_i})
//Round type=00; Towards zero / No round
//Round type=01; Towards - infinity
//Round type=10; Towards + infinity
//Op=0;Round type=00
/*5'b00000: Round_Flag_o <=0;
5'b00001: Round_Flag_o <=0;
5'b00010: Round_Flag_o <=0;
5'b00011: Round_Flag_o <=0;*/
//Op=1;Round type=00
/*5'b10000: Round_Flag_o <=0;
5'b10001: Round_Flag_o <=0;
5'b10010: Round_Flag_o <=0;
5'b10011: Round_Flag_o <=0; */
//Op=0;Round type=01
/*5'b00100: Round_Flag_o <=0;
5'b00101: Round_Flag_o <=0;
5'b00110: Round_Flag_o <=0;
5'b00111: Round_Flag_o <=0; */
//Op=1;Round type=01
//5'b10100: Round_Flag_o <=0;
5'b10101: Round_Flag_o <=1;
5'b10110: Round_Flag_o <=1;
5'b10111: Round_Flag_o <=1;
//Op=0;Round type=10
//5'b01000: Round_Flag_o <=0;
5'b01001: Round_Flag_o <=1;
5'b01010: Round_Flag_o <=1;
5'b01011: Round_Flag_o <=1;
//Op=1;Round type=10
/*5'b11000: Round_Flag_o <=0;
5'b11001: Round_Flag_o <=0;
5'b11010: Round_Flag_o <=0;
5'b11011: Round_Flag_o <=0; */
default: Round_Flag_o <=0;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int to_reach(long long int number, long long int moves, long long int target) { if (target == 0) { return (number / moves); } else { long long int res = (target - number) / moves; return res; } } int main() { long long int n, m, xc, yc, dxi, dyi, step; cin >> n >> m; cin >> xc >> yc; long long int k, count = 0; cin >> k; for (int i = 0; i < k; i++) { cin >> dxi >> dyi; long long int toReachX, toReachY; if (dxi == 0) toReachX = 10000000000; else if (dxi > 0) toReachX = to_reach(xc, dxi, n); else toReachX = to_reach(1 - xc, dxi, 0); if (dyi == 0) toReachY = 10000000000; else if (dyi > 0) toReachY = to_reach(yc, dyi, m); else toReachY = to_reach(1 - yc, dyi, 0); long long int tomove = min(toReachX, toReachY); xc = xc + dxi * tomove, yc = yc + dyi * tomove; count += tomove; } cout << count << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; string str; cin >> n >> str; int a = 0; int d = 0; for (int i = 0; i < n; i++) { if (str[i] == A ) { a++; } else { d++; } } if (a > d) { cout << Anton << endl; } else if (a < d) { cout << Danik << endl; } else { cout << Friendship << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int Direction[4][2] = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}}; const int Nmax = 200010; int n, k; long long a[20000], pref[20000]; long long f[60][500][500]; long long diff[500][2]; int main() { ios::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; pref[i] = pref[i - 1] + a[i]; }; for (int i = 0; i <= n; i++) diff[i][0] = diff[i][1] = -2000000000; for (int i = 1; i <= n; i++) for (int j = i; j <= n; j++) { diff[j][0] = max(diff[j][0], pref[j] - pref[i - 1]); diff[j][1] = max(pref[i - 1] - pref[j], diff[j][1]); }; long long answer = 0; for (int t = 2; t <= k; t++) { for (int i = 1; i <= n; i++) for (int j = i; j <= n; j++) f[t][i][j] = max(diff[i - 1][0] - pref[j] + pref[i - 1], diff[i - 1][1] - pref[i - 1] + pref[j]); for (int i = 0; i < n; i++) diff[i][0] = diff[i][1] = -2000000000; for (int i = 1; i <= n; i++) for (int j = i; j <= n; j++) { diff[j][0] = max(diff[j][0], f[t][i][j] + pref[j] - pref[i - 1]); diff[j][1] = max(diff[j][1], f[t][i][j] - pref[j] + pref[i - 1]); }; }; for (int i = 1; i <= n; i++) for (int j = i; j <= n; j++) answer = max(answer, (long long)f[k][i][j]); cout << answer << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 5; struct edge { int u, v, id; edge(int a = 0, int b = 0, int c = 0) { u = a, v = b, id = c; } }; vector<edge> S, M, E; struct dsu { int par[N]; vector<edge> ed; dsu() { memset(par, -1, sizeof par); } int get_par(int u) { return ~par[u] ? par[u] = get_par(par[u]) : u; } bool merge(edge e) { if (get_par(e.u) == get_par(e.v)) return false; par[get_par(e.u)] = get_par(e.v), ed.push_back(e); return true; } int size() { return ed.size(); } } A, B, C; int n, m; void notValid() { cout << -1 n , exit(0); } void readInput() { cin >> n >> m; for (int i = 0; i < m; i++) { char c; int u, v; cin >> u >> v >> c; u--, v--; if (c == S ) S.push_back(edge(u, v, i)); else M.push_back(edge(u, v, i)); } } void solve() { for (auto e : S) C.merge(e); if (n & 1 ^ 1 || C.size() < n >> 1) notValid(); for (auto e : M) if (C.merge(e)) A.merge(e); if (C.size() != n - 1) notValid(); for (auto e : M) if (A.size() < n >> 1) A.merge(e); if (A.size() != n >> 1) notValid(); E = A.ed; for (auto e : S) if (A.merge(e)) B.merge(e); E.insert(E.end(), B.ed.begin(), B.ed.end()); } void writeOutput() { cout << n - 1 << endl; for (auto e : E) cout << e.id + 1 << ; } int main() { ios_base ::sync_with_stdio(false), cin.tie(0), cout.tie(0); readInput(), solve(), writeOutput(); return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// (c) Analog Devices Inc.
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module cf_mul (
clk,
data_a,
data_b,
data_p,
ddata_in,
ddata_out);
parameter DELAY_DATA_WIDTH = 16;
parameter DW = DELAY_DATA_WIDTH - 1;
input clk;
input [16:0] data_a;
input [ 7:0] data_b;
output [24:0] data_p;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
reg p1_sign = 'd0;
reg [DW:0] p1_ddata = 'd0;
reg [23:0] p1_data_p_0 = 'd0;
reg [23:0] p1_data_p_1 = 'd0;
reg [23:0] p1_data_p_2 = 'd0;
reg [23:0] p1_data_p_3 = 'd0;
reg [23:0] p1_data_p_4 = 'd0;
reg p2_sign = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [23:0] p2_data_p_0 = 'd0;
reg [23:0] p2_data_p_1 = 'd0;
reg p3_sign = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [23:0] p3_data_p_0 = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [24:0] data_p = 'd0;
wire [16:0] p1_data_a_1p_17_s;
wire [16:0] p1_data_a_1n_17_s;
wire [23:0] p1_data_a_1p_s;
wire [23:0] p1_data_a_1n_s;
wire [23:0] p1_data_a_2p_s;
wire [23:0] p1_data_a_2n_s;
assign p1_data_a_1p_17_s = {1'b0, data_a[15:0]};
assign p1_data_a_1n_17_s = ~p1_data_a_1p_17_s + 1'b1;
assign p1_data_a_1p_s = {{7{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s};
assign p1_data_a_1n_s = {{7{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s};
assign p1_data_a_2p_s = {{6{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s, 1'b0};
assign p1_data_a_2n_s = {{6{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s, 1'b0};
always @(posedge clk) begin
p1_sign <= data_a[16];
p1_ddata <= ddata_in;
case (data_b[1:0])
2'b11: p1_data_p_0 <= p1_data_a_1n_s;
2'b10: p1_data_p_0 <= p1_data_a_2n_s;
2'b01: p1_data_p_0 <= p1_data_a_1p_s;
default: p1_data_p_0 <= 24'd0;
endcase
case (data_b[3:1])
3'b011: p1_data_p_1 <= {p1_data_a_2p_s[21:0], 2'd0};
3'b100: p1_data_p_1 <= {p1_data_a_2n_s[21:0], 2'd0};
3'b001: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
3'b010: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
3'b101: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
3'b110: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
default: p1_data_p_1 <= 24'd0;
endcase
case (data_b[5:3])
3'b011: p1_data_p_2 <= {p1_data_a_2p_s[19:0], 4'd0};
3'b100: p1_data_p_2 <= {p1_data_a_2n_s[19:0], 4'd0};
3'b001: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
3'b010: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
3'b101: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
3'b110: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
default: p1_data_p_2 <= 24'd0;
endcase
case (data_b[7:5])
3'b011: p1_data_p_3 <= {p1_data_a_2p_s[17:0], 6'd0};
3'b100: p1_data_p_3 <= {p1_data_a_2n_s[17:0], 6'd0};
3'b001: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
3'b010: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
3'b101: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
3'b110: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
default: p1_data_p_3 <= 24'd0;
endcase
case (data_b[7])
1'b1: p1_data_p_4 <= {p1_data_a_1p_s[15:0], 8'd0};
default: p1_data_p_4 <= 24'd0;
endcase
end
always @(posedge clk) begin
p2_sign <= p1_sign;
p2_ddata <= p1_ddata;
p2_data_p_0 <= p1_data_p_0 + p1_data_p_1 + p1_data_p_4;
p2_data_p_1 <= p1_data_p_2 + p1_data_p_3;
end
always @(posedge clk) begin
p3_sign <= p2_sign;
p3_ddata <= p2_ddata;
p3_data_p_0 <= p2_data_p_0 + p2_data_p_1;
end
always @(posedge clk) begin
ddata_out <= p3_ddata;
data_p <= {p3_sign, p3_data_p_0};
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int gcd(int x, int y) { if (x == 0) return y; return gcd(y % x, x); } int main() { int n, m, x, g; cin >> n >> m >> x; g = x - 1; for (int i = 1; i < n; ++i) { scanf( %d , &x); g = gcd(g, x - 1); } set<int> second; int d = 1; while (d * d <= g) { if (g % d == 0) { for (int p = 1; p * d <= m; p *= 2) second.insert(p * d); for (int p = 1; p * (g / d) <= m; p *= 2) second.insert(p * (g / d)); } ++d; } long long ans = 0; for (set<int>::iterator it = second.begin(); it != second.end(); it++) ans += m - (*it); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e3 + 10; const int INF = 99999999; const double eps = 1e-4; int dp[MAXN]; int main() { int n, m, c0, d0; cin >> n >> m >> c0 >> d0; memset(dp, 0, sizeof(dp)); for (int i = c0; i <= n; i++) dp[i] = i / c0 * d0; for (int i = 1; i <= m; i++) { int a, b, c, d; cin >> a >> b >> c >> d; for (int j = 1; j <= a / b; j++) { for (int k = n; k >= c; k--) dp[k] = max(dp[k - c] + d, dp[k]); } } cout << dp[n] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void chkmin(T &a, T b) { if (a > b) a = b; } template <class T> inline void chkmax(T &a, T b) { if (a < b) a = b; } inline int read() { int s = 0, f = 1; char ch = getchar(); while (!isdigit(ch) && ch != - ) ch = getchar(); if (ch == - ) ch = getchar(), f = -1; while (isdigit(ch)) s = s * 10 + ch - 0 , ch = getchar(); return ~f ? s : -s; } const int maxn = 1e5 + 20; int n, q, t; long long now; int fa[maxn], to[maxn]; int a[maxn]; int f[maxn], vis[maxn]; inline void init() { n = read(); q = read(); t = read(); for (int i = (1), _end_ = (n); i <= _end_; i++) a[i] = read(); for (int i = (1), _end_ = (q); i <= _end_; i++) { int x = read(), y = read(); to[x] = y; fa[y] = x; } for (int i = (1), _end_ = (n); i <= _end_; i++) if (!fa[i]) { int x = i; while (to[x]) { if (vis[x]) puts( 0 ), exit(0); vis[x] = 1; now += a[x]; a[to[x]] += a[x]; x = to[x]; } vis[x] = 1; } for (int i = (1), _end_ = (n); i <= _end_; i++) if (!vis[i]) puts( 0 ), exit(0); } const int mod = 1e9 + 7; inline void pls(int &a, int b) { a += b; a -= a >= mod ? mod : 0; } inline void doing() { f[0] = 1; for (int j = (1), _end_ = (n); j <= _end_; j++) { for (int i = a[j]; i <= t - now; i++) pls(f[i], f[i - a[j]]); } if (now <= t) printf( %d n , f[t - now]); else puts( 0 ); } int main() { init(); doing(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_2_V
`define SKY130_FD_SC_LS__AND4BB_2_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_2_V
|
#include <bits/stdc++.h> using namespace std; int ini() { int x; scanf( %d , &x); return x; } long long inl() { long long x; scanf( %lld , &x); return x; } void file_mamager() {} int arr[105], mask[105], dp[105][1 << 17]; pair<int, int> path[105][1 << 17]; vector<int> primes; void gen() { for (int i = 2; i <= 60; i++) { bool is = true; for (int j = 2; j * j <= i; j++) { if (i % j == 0) { is = false; break; } } if (is) primes.push_back(i); } } void bit_rep(int x) { for (int i = 0; i < 10; i++) cout << ((x >> i) & 1); cout << n ; } int main() { gen(); int n = ini(); for (int i = 1; i <= n; i++) { for (int j = 0; j < (1 << 17); j++) dp[i][j] = 1e8; } for (int i = 1; i <= n; i++) arr[i] = ini(); for (int i = 1; i <= 60; i++) { int x = 0, y = i; for (int j = 0; j < 17; j++) { if (y % primes[j] == 0) { x |= (1 << j); while (y % primes[j] == 0) y /= primes[j]; } } mask[i] = x; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= 60; j++) { for (int k = 0; k < (1 << 17); k++) { if ((k & mask[j]) == mask[j]) { if (dp[i - 1][k ^ mask[j]] + abs(arr[i] - j) < dp[i][k]) { dp[i][k] = dp[i - 1][k ^ mask[j]] + abs(arr[i] - j); path[i][k] = {(k ^ mask[j]), j}; } } } } } int mn = 1e8; int x = (1 << 17) - 1; for (int k = 0; k < (1 << 17); k++) { if (dp[n][k] < mn) { mn = dp[n][k]; x = k; } } vector<int> ans; for (int i = n; i >= 1; i--) { ans.push_back(path[i][x].second); x = path[i][x].first; } reverse(ans.begin(), ans.end()); for (int xx : ans) cout << xx << ; cout << n ; return 0; }
|
///////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.i (O.4)
// \ \ Description :
// / /
// /__/ /\ Filename : PLLE2_BASE.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 12/09/09 - Initial version
// 03/23/10 - Change CLKFBOUT_MULT default from 1 to 5.
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PLLE2_BASE (
CLKFBOUT,
CLKOUT0,
CLKOUT1,
CLKOUT2,
CLKOUT3,
CLKOUT4,
CLKOUT5,
LOCKED,
CLKFBIN,
CLKIN1,
PWRDWN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter integer CLKFBOUT_MULT = 5;
parameter real CLKFBOUT_PHASE = 0.000;
parameter real CLKIN1_PERIOD = 0.000;
parameter integer CLKOUT0_DIVIDE = 1;
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
parameter real CLKOUT0_PHASE = 0.000;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
parameter real CLKOUT1_PHASE = 0.000;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
parameter real CLKOUT2_PHASE = 0.000;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
parameter real CLKOUT3_PHASE = 0.000;
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
parameter real CLKOUT4_PHASE = 0.000;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
parameter real CLKOUT5_PHASE = 0.000;
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER1 = 0.010;
parameter STARTUP_WAIT = "FALSE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output CLKFBOUT;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input PWRDWN;
input RST;
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
PLLE2_ADV #(
.BANDWIDTH(BANDWIDTH),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.REF_JITTER1(REF_JITTER1)
)
plle2_adv_1 (
.CLKFBIN (CLKFBIN),
.CLKFBOUT (CLKFBOUT),
.CLKIN1 (CLKIN1),
.CLKIN2 (1'b0),
.CLKOUT0 (CLKOUT0),
.CLKOUT1 (CLKOUT1),
.CLKOUT2 (CLKOUT2),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.DWE (1'b0),
.LOCKED (LOCKED),
.CLKINSEL(1'b1),
.PWRDWN(PWRDWN),
.RST (RST)
);
endmodule
`endcelldefine
|
// Name: WcaRssi.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaRssi (
input clock,
input reset,
input strobe,
input [11:0] adc,
output [7:0] rssi
);
wire [11:0] abs_adc = adc[11] ? ~adc : adc;
reg [23:0] rssi_int;
always @(posedge clock)
if(reset )
rssi_int <= #1 24'd0;
else if (strobe)
rssi_int <= #1 rssi_int + abs_adc - {1'b0,rssi_int[23:13]};
assign rssi = rssi_int[23:16];
endmodule // WcaRssi
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 105; const long long MAXV = 2e5 + 1; const long long INF = 1e9; bool prime[MAXV]; void sieve() { memset(prime, true, sizeof(prime)); prime[0] = prime[1] = false; for (long long i = 2; i * i < MAXV; i++) { if (prime[i]) { for (long long j = i * i; j < MAXV; j += i) prime[j] = false; } } } long long n, k, p[MAX], c[MAX], l[MAX]; struct edge { int from, to, flow, index; long long cap; edge(int from, int to, long long cap, int flow, int index) : from(from), to(to), cap(cap), flow(flow), index(index) {} }; struct PushRelabel { int n; vector<vector<edge>> g; vector<long long> excess; vector<int> height, active, count; queue<int> Q; PushRelabel(int n) : n(n), g(n), excess(n), height(n), active(n), count(2 * n) {} void addEdge(int from, int to, long long cap) { g[from].push_back(edge(from, to, cap, 0, g[to].size())); if (from == to) g[from].back().index++; g[to].push_back(edge(to, from, 0, 0, g[from].size() - 1)); } void enqueue(int v) { if (!active[v] && excess[v] > 0) { active[v] = true; Q.push(v); } } void push(edge &e) { int amt = (int)min(excess[e.from], (long long)e.cap - e.flow); if (height[e.from] <= height[e.to] || amt == 0) return; e.flow += amt; g[e.to][e.index].flow -= amt; excess[e.to] += amt; excess[e.from] -= amt; enqueue(e.to); } void relabel(int v) { count[height[v]]--; int d = 2 * n; for (auto &it : g[v]) { if (it.cap - it.flow > 0) d = min(d, height[it.to] + 1); } height[v] = d; count[height[v]]++; enqueue(v); } void gap(int k) { for (int v = 0; v < n; v++) { if (height[v] < k) continue; count[height[v]]--; height[v] = max(height[v], n + 1); count[height[v]]++; enqueue(v); } } void discharge(int v) { for (int i = 0; excess[v] > 0 && i < g[v].size(); i++) push(g[v][i]); if (excess[v] > 0) { if (count[height[v]] == 1) gap(height[v]); else relabel(v); } } long long max_flow(int source, int dest) { count[0] = n - 1, count[n] = 1, height[source] = n, active[source] = active[dest] = 1; for (auto &it : g[source]) { excess[source] += it.cap; push(it); } while (!Q.empty()) { int v = Q.front(); Q.pop(); active[v] = false; discharge(v); } long long max_flow = 0; for (auto &e : g[source]) max_flow += e.flow; return max_flow; } }; bool f(long long lvl) { vector<long long> v = {0}; long long sm = 0, mx = -1, id = 0; for (long long i = 1; i <= n; i++) { if (l[i] <= lvl) { if (c[i] != 1) { sm += p[i]; v.push_back(i); } else { if (p[i] > mx) { mx = p[i]; id = i; } } } } if (mx != -1) { v.push_back(id); sm += p[id]; } long long cnt = v.size() - 1; PushRelabel Network(cnt + 2); long long s = 0, t = cnt + 1; vector<int> odd, even; odd.push_back(0), even.push_back(0); for (int i = 1; i <= cnt; i++) { if (c[v[i]] & 1) odd.push_back(v[i]); else even.push_back(v[i]); } int os = odd.size() - 1, es = even.size() - 1; for (int i = 1; i <= os; i++) Network.addEdge(s, i, p[odd[i]]); for (int i = 1; i <= es; i++) Network.addEdge(os + i, t, p[even[i]]); for (int i = 1; i <= os; i++) { for (int j = 1; j <= es; j++) { int idx1 = odd[i], idx2 = even[j]; if (prime[c[idx1] + c[idx2]]) Network.addEdge(i, os + j, INF); } } long long flow = Network.max_flow(s, t); long long mxpow = sm - flow; return mxpow >= k; } void solve() { long long l = 0, r = n + 1; while (r - l > 1) { long long mid = (l + r) / 2; if (f(mid)) r = mid; else l = mid; } if (f(r)) cout << r; else cout << -1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); sieve(); cin >> n >> k; for (long long i = 1; i <= n; i++) cin >> p[i] >> c[i] >> l[i]; solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) ifstream fin( input.txt ); ofstream fout( output.txt ); bool isPrime(int x) { if (x <= 4 || x % 2 == 0 || x % 3 == 0) return x == 2 || x == 3; for (int i = 5; i * i <= x; i += 6) if (x % i == 0 || x % (i + 2) == 0) return 0; return 1; } int NumDigits(int x) { return ( x < 10 ? 1 : (x < 100 ? 2 : (x < 1000 ? 3 : (x < 10000 ? 4 : (x < 100000 ? 5 : (x < 1000000 ? 6 : (x < 10000000 ? 7 : (x < 100000000 ? 8 : (x < 1000000000 ? 9 : 10))))))))); } inline void boostIO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(10); } long long int Pow10[19] = { (long long int)1, (long long int)1e1, (long long int)1e2, (long long int)1e3, (long long int)1e4, (long long int)1e5, (long long int)1e6, (long long int)1e7, (long long int)1e8, (long long int)1e9, (long long int)1e10, (long long int)1e11, (long long int)1e12, (long long int)1e13, (long long int)1e14, (long long int)1e15, (long long int)1e16, (long long int)1e17, (long long int)1e18}; long long int gcd(long long int a, long long int b) { return b ? gcd(b, a % b) : a; } long long int lcm(long long int a, long long int b) { return a * b / gcd(a, b); } long long Mod = 998244353; template <class T> struct Fenwick { vector<T> V; Fenwick(long long n) : V(n) {} void add(size_t i, T x) { for (; i < V.size(); i |= i + 1) V[i] += x; } T sum(long long i) { T r = T(); for (--i; i >= 0; i = (i & (i + 1)) - 1) r += V[i]; return r; } T sum(long long l, long long r) { return sum(r) - sum(l); } }; long long mul(long long a, long long b, long long c = 1, long long d = 1, long long e = 1, long long g = 1) { a %= Mod; b %= Mod; c %= Mod; d %= Mod; e %= Mod; g %= Mod; return (a * b % Mod * c % Mod * d % Mod * e % Mod * g % Mod); } long long Pow(long long a, long long b) { if (b == 0) return 1; if (b % 2 == 0) { long long x = Pow(a, b / 2); return mul(x, x); } else { long long x = Pow(a, b / 2); return mul(a, x, x); } } long long inf = 1e18; struct My { long long a = inf; long long b = inf; long long solved = 0; long long fee = 0; }; struct comp { bool operator()(My const& a, My const& b) const {} }; struct Tree { long long n = 1; vector<long long> t; Tree(long long nn) { while (n < nn) n *= 2; t.assign(n * 2, 0); } Tree(vector<long long>& A) { while (n < A.size()) n *= 2; t.assign(n * 2, 0); for (long long i = 0; i < (A.size()); ++i) { t[i + n] = A[i]; } for (long long i = A.size() - 1; i >= 1; --i) { t[i] = t[i + i] + t[i + i + 1]; } } long long get(long long i) { long long res = t[i += n]; for (i /= 2; i; i /= 2) { res += t[i]; } return res; } void set(long long l, long long r, long long x) { for (l += n, r += n; l <= r; l /= 2, r /= 2) { if (l & 1) t[l++] += x; ; if (~r & 1) t[r--] += x; } } }; long long gcdex(long long a, long long b, long long& x, long long& y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = gcdex(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } long long mypow(long long a, long long b = Mod - 2, long long k = Mod) { if (b == 0) return 1; long long tmp = mypow(a, b / 2, k); if ((b % 2) == 1) return mul(tmp, tmp, a); else return mul(tmp, tmp); } long long mypow2(long long a, long long m = Mod) { long long x, y; long long g = gcdex(a, m, x, y); x = (x % m + m) % m; return x; } int32_t main() { boostIO(); long long T; cin >> T; for (long long t = 0; t < T; ++t) { long long n; cin >> n; vector<long long> A(n); long long Sum = 0; long long Xor = 0; for (long long i = 0; i < (n); ++i) { cin >> A[i]; Sum += A[i]; Xor ^= A[i]; } vector<long long> ans; bitset<64> B = Xor; long long Add = 0; for (long long i = 1; i < 55; ++i) { if (B[i] == 0) { Add += (1LL << i); } } if (B[0] == 1) Add += 1; ans.push_back(Add); Sum += Add; Xor ^= Add; long long dif = Xor * 2 - Sum; ans.push_back(dif / 2); ans.push_back(dif / 2); Sum += dif / 2; Sum += dif / 2; Xor ^= dif / 2; Xor ^= dif / 2; if (Xor * 2 != Sum) { cerr << ERROR << n ; return 0; } cerr << ans = ; cout << ans.size() << n ; for (auto x : ans) { cout << x << ; } cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; struct Edge { int v; Edge *link; } edge[400010 * 2], *adj[200010], *tree[200010 * 2]; int totE, con, root, currT, top, top1; int totCut, totBi; int dep[200010], deps[200010], num[200010], dfn[200010], lowlink[200010], cut[200010], bi[200010], color[200010]; int temp[200010], st1[200010], st2[200010], st3[200010], st4[200010], f[200010 * 2]; int used[200010 * 2], odd[200010 * 2]; int fa[200010][20]; int LOG[200010]; void addEdge(int u, int v) { Edge *p = &edge[totE++]; p->v = v; p->link = adj[u]; adj[u] = p; } void addTree(int u, int v) { Edge *p = &edge[totE++]; p->v = v; p->link = tree[u]; tree[u] = p; } void dfs(int u, int pre) { dep[u] = dep[pre] + 1; dfn[u] = lowlink[u] = ++currT; num[u] = con; Edge *p = adj[u]; int cnt = 0; bool flag = false; while (p) { if (!dfn[p->v]) { ++cnt; dfs(p->v, u); lowlink[u] = min(lowlink[u], lowlink[p->v]); if (lowlink[p->v] >= dfn[u]) flag = true; } else if (p->v != pre) lowlink[u] = min(lowlink[u], dfn[p->v]); p = p->link; } if (flag && (u != root || cnt > 1)) cut[u] = ++totCut; } bool dfs2(int u) { Edge *p = adj[u]; while (p) { if (bi[p->v] == totBi) { if (color[p->v] == -1) { color[p->v] = !color[u]; if (!dfs2(p->v)) return false; } else if (color[p->v] == color[u]) return false; } p = p->link; } return true; } void solve() { ++totBi; int cnt = 0; for (int i = 0; i < top1; ++i) { int u = st3[i], v = st4[i]; bi[u] = totBi; bi[v] = totBi; color[u] = color[v] = -1; if (cut[u]) temp[cnt++] = cut[u]; if (cut[v]) temp[cnt++] = cut[v]; } sort(temp, temp + cnt); for (int i = 0; i < cnt; ++i) if (i == 0 || temp[i] != temp[i - 1]) { addTree(temp[i], totCut + totBi); addTree(totCut + totBi, temp[i]); } color[st3[0]] = 0; odd[totBi] = !dfs2(st3[0]); } void dfs1(int u, int pre) { dfn[u] = lowlink[u] = ++currT; Edge *p = adj[u]; while (p) { if (!dfn[p->v]) { st1[top] = u; st2[top++] = p->v; dfs1(p->v, u); lowlink[u] = min(lowlink[u], lowlink[p->v]); if (lowlink[p->v] >= dfn[u]) { top1 = 0; while (true) { --top; st3[top1] = st1[top]; st4[top1++] = st2[top]; if (st1[top] == u && st2[top] == p->v) break; } solve(); } } else { if (dfn[u] > dfn[p->v] && p->v != pre) { st1[top] = u; st2[top++] = p->v; } if (p->v != pre) lowlink[u] = min(lowlink[u], dfn[p->v]); } p = p->link; } } void dfs3(int u, int pre) { deps[u] = deps[pre] + 1; used[u] = true; fa[u][0] = pre; if (u <= totCut) f[u] = 0; else f[u] = odd[u - totCut]; f[u] += f[pre]; Edge *p = tree[u]; while (p) { if (!used[p->v]) dfs3(p->v, u); p = p->link; } } int LCA(int u, int v) { if (deps[u] < deps[v]) swap(u, v); int diff = deps[u] - deps[v]; for (int i = 0; diff; ++i, diff >>= 1) if (diff & 1) u = fa[u][i]; if (u == v) return u; int t = 19; for (int i = t; i >= 0; --i) { if (fa[u][i] != fa[v][i]) { u = fa[u][i]; v = fa[v][i]; } } return fa[u][0]; } int main() { LOG[1] = 0; for (int i = 2; i < 200010; ++i) LOG[i] = (LOG[i] >> 1) + 1; int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) { int u, v; scanf( %d%d , &u, &v); addEdge(u, v); addEdge(v, u); } dep[0] = -1; for (int i = 1; i <= n; ++i) if (!dfn[i]) { root = i; dfs(i, 0); ++con; } currT = 0; memset(dfn, 0, sizeof(dfn)); for (int i = 1; i <= n; ++i) if (!dfn[i]) dfs1(i, 0); for (int i = 1; i <= totCut + totBi; ++i) if (!used[i]) dfs3(i, 0); for (int l = 1; (1 << l) <= totCut + totBi; ++l) for (int i = 1; i <= totCut + totBi; ++i) if (fa[i][l - 1] != 0) fa[i][l] = fa[fa[i][l - 1]][l - 1]; int q; scanf( %d , &q); for (int i = 0; i < q; ++i) { int u, v; scanf( %d%d , &u, &v); if (u == v || num[u] != num[v]) puts( No ); else { int x, y; if (cut[u]) x = cut[u]; else x = totCut + bi[u]; if (cut[v]) y = cut[v]; else y = totCut + bi[v]; int lca = LCA(x, y); int sum = f[x] + f[y] - 2 * f[fa[lca][0]]; if (sum > 0) puts( Yes ); else if ((dep[u] + dep[v]) % 2 == 0) puts( No ); else puts( Yes ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFRTP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, -1, 1}; int tt[1016][1016]; int hh[1016][1016]; int n, m; int ex, ey; queue<int> q; queue<int> p; void bfs() { while (!p.empty()) { int x = p.front(); int y = q.front(); p.pop(); q.pop(); for (int i = 0; i < 4; i++) { int nx = x + dx[i]; int ny = y + dy[i]; if (nx >= 1 && nx <= n && ny >= 1 && ny <= m && tt[nx][ny] == 0 && !(nx == ex && ny == ey)) { p.push(nx); q.push(ny); tt[nx][ny] = tt[x][y] + 1; } } } } int main() { scanf( %d %d , &n, &m); getchar(); int ans = 0; memset(tt, 0, sizeof(tt)); memset(hh, 0, sizeof(hh)); char c; int zux, zuy; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %c , &c); if (c >= 0 && c <= 9 ) { hh[i][j] = c - 0 ; } if (c == S ) { zux = i; zuy = j; } if (c == E ) { tt[i][j] = 1; ex = i; ey = j; } if (c == T ) { tt[i][j] = -1; } } getchar(); } p.push(ex); q.push(ey); bfs(); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (i == zux && j == zuy) continue; if (i == ex && j == ey) continue; if (tt[i][j] <= tt[zux][zuy] && tt[i][j] != 0 && tt[i][j] != -1) { ans += hh[i][j]; } } } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxN = 1e3 + 9, lg = 19, MOD = 1e9 + 7, maxV = 1e6 + 9; pair<int, int> arr[3]; int dp[maxN][maxN]; pair<int, int> auxi[maxN][maxN]; bool vi[maxN][maxN]; int dst(pair<int, int> one, pair<int, int> two) { return abs(one.first - two.first) + abs(two.second - one.second); } const int dr[4][2] = {{0, 1}, {1, 0}, {0, -1}, {-1, 0}}; bool ins(int x, int y) { return x < maxN && y < maxN && y >= 0 && x >= 0; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n = 3; for (int i = 0; i < n; i++) cin >> arr[i].first >> arr[i].second; pair<int, int> begi = pair<int, int>(min(arr[0].first, arr[1].first), min(arr[0].second, arr[1].second)); pair<int, int> ende = pair<int, int>(max(arr[0].first, arr[1].first), max(arr[0].second, arr[1].second)); pair<int, int> clos = begi; for (int i = begi.first; i <= ende.first; i++) { for (int j = begi.second; j <= ende.second; j++) { if (dst(arr[2], clos) > dst(arr[2], pair<int, int>(i, j))) { clos = pair<int, int>(i, j); } } } queue<pair<int, int> > q; q.push(clos); memset(dp, -1, sizeof dp); dp[clos.first][clos.second] = 0; auxi[clos.first][clos.second] = pair<int, int>(-1, -1); while (q.size()) { pair<int, int> cr = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int x = cr.first + dr[i][0], y = cr.second + dr[i][1]; if (!ins(x, y) || dp[x][y] != -1) continue; dp[x][y] = dp[cr.first][cr.second] + 1; auxi[x][y] = cr; q.push(pair<int, int>(x, y)); } } for (int i = 0; i < 3; i++) { pair<int, int> strt = arr[i]; while (strt != pair<int, int>(-1, -1)) { vi[strt.first][strt.second] = 1; strt = auxi[strt.first][strt.second]; } } vector<pair<int, int> > ans; for (int i = 0; i < maxN; i++) for (int j = 0; j < maxN; j++) if (vi[i][j]) ans.push_back(pair<int, int>(i, j)); cout << ans.size() << n ; for (pair<int, int> el : ans) cout << el.first << << el.second << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a, b, i, j, t, p = 0, q = 0; int x[200001]; cin >> n >> m; for (i = 1; i <= n; ++i) { cin >> t; if (t == -1) p++; else q++; } for (i = 0; i < m; ++i) { cin >> a >> b; if ((b - a + 1) % 2 == 0 && (b - a + 1) / 2 <= p && (b - a + 1) / 2 <= q) cout << 1 << endl; else cout << 0 << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; using LL = long long; constexpr int N = 1e5 + 5; string s; int n; int f(int x, int y) { int z = x; int res = 0; for (int i = 0; i < n; i++) { if (s[i] == z) { res++; z = x + y - z; } } if (res & 1) res -= (x != y); return res; } void solve() { cin >> s; n = s.size(); for (char &c : s) c -= 0 ; int res = 0; for (int i = 0; i < 10; i++) { for (int j = 0; j < 10; j++) { res = max(res, f(i, j)); } } cout << n - res << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) { solve(); } }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sub_outputs (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300000 + 15; int n; int a[N]; char c[N]; int flag, st, bb, rr, ll, cc, dd, ee, hh; int main() { scanf( %d , &n); for (int i(1); i <= (n); ++i) scanf( %d %c , a + i, c + i); long long ans = 0; for (int i(1); i <= (n); ++i) if (c[i] == B ) { if (!bb) bb = i; dd = a[i] - a[ll] > dd ? a[i] - a[ll] : dd; ll = i; } else if (c[i] == R ) { if (!rr) rr = i; ee = a[i] - a[cc] > ee ? a[i] - a[cc] : ee; cc = i; } else { if (flag) { int tmp1 = a[i] - a[hh]; int tmp2 = (ee ? a[i] - a[hh] - max(a[i] - a[cc], ee) : 0) + (dd ? a[i] - a[hh] - max(a[i] - a[ll], dd) : 0); ans += a[i] - a[hh] + min(tmp1, tmp2); } else ans += (bb ? a[i] - a[bb] : 0) + (rr ? a[i] - a[rr] : 0); flag = 1; hh = cc = ll = i; ee = dd = 0; } if (!flag) printf( %lld n , 0ll + a[cc] - a[rr] + a[ll] - a[bb]); else printf( %lld n , ans + (cc > hh ? a[cc] - a[hh] : 0) + (ll > hh ? a[ll] - a[hh] : 0)); return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_69x256.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_69x256 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [68:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [68:0] q;
output rdempty;
output wrfull;
wire sub_wire0;
wire sub_wire1;
wire [68:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [68:0] q = sub_wire2[68:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone III",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 69,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "69"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "69"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "69"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 69 0 INPUT NODEFVAL data[68..0]
// Retrieval info: USED_PORT: q 0 0 69 0 OUTPUT NODEFVAL q[68..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 69 0 data 0 0 69 0
// Retrieval info: CONNECT: q 0 0 69 0 @q 0 0 69 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_69x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 7; const int INF = 1e9 + 7; const int MOD = 1e9 + 7; struct as { int id, x; } a[maxn]; int vis[maxn]; bool cmp(as a, as b) { return a.x < b.x; } vector<int> g[maxn]; vector<int> ans; set<int> tmp; bool check(as a) { int i, j; for (i = 0; i < g[a.id].size(); i++) { if (vis[g[a.id][i]] == a.x) return false; if (vis[g[a.id][i]]) tmp.insert(vis[g[a.id][i]]); } if (tmp.size() != a.x - 1) return false; tmp.clear(); vis[a.id] = a.x; return true; } int main() { int i, j, n, m, t, z; scanf( %d%d , &n, &m); for (i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); } for (i = 1; i <= n; i++) { scanf( %d , &a[i].x); a[i].id = i; } sort(a + 1, a + 1 + n, cmp); for (i = 1; i <= n; i++) { if (!check(a[i])) break; ans.push_back(a[i].id); } if (i <= n) { printf( -1 n ); } else { for (i = 0; i < n; i++) { printf( %d%c , ans[i], i == n - 1 ? n : ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int t[4000050], tag[4000050]; vector<int> v[1005000]; inline void refresh(int now) { t[now] = max(t[now << 1], t[now << 1 | 1]); } void pushdown(int l, int r, int now) { if (l == r) { tag[now] = 0; return; } tag[now << 1] += tag[now]; tag[now << 1 | 1] += tag[now]; int mid = (l + r) >> 1; t[now << 1] += tag[now]; t[now << 1 | 1] += tag[now]; tag[now] = 0; } void add(int l, int r, int now, int LL, int RR, int data) { if (LL <= l && r <= RR) { t[now] += data; tag[now] += data; return; } if (tag[now]) pushdown(l, r, now); int mid = (l + r) >> 1; if (LL <= mid) add(l, mid, now << 1, LL, RR, data); if (mid < RR) add(mid + 1, r, now << 1 | 1, LL, RR, data); refresh(now); } int query(int l, int r, int now, int LL, int RR) { if (LL <= l && r <= RR) { return t[now]; } if (tag[now]) pushdown(l, r, now); int mid = (l + r) >> 1; int ans = -1e9; if (LL <= mid) ans = max(query(l, mid, now << 1, LL, RR), ans); if (mid < RR) ans = max(ans, query(mid + 1, r, now << 1 | 1, LL, RR)); refresh(now); return ans; } int i, j, k, n, m, st[1005000][2], siz[1005000], id[1005000], it, sb; void dfs(int x) { siz[x]++; for (auto i : v[x]) { dfs(i); siz[x] += siz[i]; } id[x] = ++it; } int main() { scanf( %d%d , &n, &sb); for (i = 1; i <= n; i++) { scanf( %d , &k); while (m && st[m][1] < k) { v[i].push_back(st[m][0]); m--; } st[++m][0] = i; st[m][1] = k; } n++; while (m) { v[n].push_back(st[m][0]); m--; } dfs(n); for (i = 1; i <= sb; i++) { add(1, n, 1, id[i] - siz[i] + 1, id[i], 1); } for (i = sb; i < n; i++) { printf( %d , t[1]); add(1, n, 1, id[i + 1] - siz[i + 1] + 1, id[i + 1], 1); add(1, n, 1, id[i - sb + 1] - siz[i - sb + 1] + 1, id[i - sb + 1], -1); } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:18:54 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_0_stub.v
// Design : bram_1024_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; const long long mod = 1e9 + 7; long long n, m; long long fac[maxn]; long long ksm(long long a, long long b) { long long ans = 1, base = a % mod; while (b) { if (b & 1) ans = ans * base % mod; base = base * base % mod; b >>= 1; } return ans % mod; } long long C(int x, int y) { return fac[x] * ksm(fac[y] * fac[x - y] % mod, mod - 2) % mod; } int main() { cin >> n >> m; fac[0] = 1; for (int i = 1; i <= m * 2 + n + 1; ++i) fac[i] = fac[i - 1] * i % mod; cout << C(n + m * 2 - 1, n - 1); return 0; }
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_controlFlagsOut (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 1: 0] in_port;
input reset_n;
wire clk_en;
wire [ 1: 0] data_in;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
`timescale 1ns/1ns
module test_mips (/*port details*/);
reg clk,rst,clk_i;
integer i;
wire [31:2] PrAddr;
wire [3:0] PrBe;
wire [31:0] PrWD;
wire [31:0] PrRD;
wire [7:2] HWInt;
wire [31:0] Dev1_RD;
wire [31:0] Dev2_RD;
wire Dev1_Irq,Dev2_Irq;
wire [3:2] DevAddr;
wire [31:0] DevWd;
wire Dev1_WE,Dev2_WE;
mips _mips(clk,rst,PrAddr,PrBe,PrRD,PrWD,HWInt);
bridge _bridge(PrAddr,PrBe,PrWD,PrRD,HWInt,DevAddr,Dev1_WE,Dev1_RD,Dev1_Irq,Dev2_WE,Dev2_RD,Dev2_Irq,DevWd);
coco_timer _coco_timer1(clk_i,rst,DevAddr,Dev1_WE,DevWd,Dev1_RD,Dev1_Irq);
coco_timer _coco_timer2(clk_i,rst,DevAddr,Dev2_WE,DevWd,Dev2_RD,Dev2_Irq);
always #5 clk=~clk;
always #5 clk_i=~clk_i;
initial begin
clk=1;
clk_i=1;
rst=1;
#3 rst=0;
end
initial begin
#10000 $finish;
end
initial begin
/*$monitor("%t IF(%x) ID(%x) EX(%x) MEM(%x) WB(%x)",$time,
_mips.instr,_mips.instrD,_mips.instrE,_mips.instrM,_mips.instrW);*/
#9999
for (i=0; i!=2048; i=i+8) begin
$display("%x %x %x %x %x %x %x %x",
_mips._dm._dm[i],
_mips._dm._dm[i+1],
_mips._dm._dm[i+2],
_mips._dm._dm[i+3],
_mips._dm._dm[i+4],
_mips._dm._dm[i+5],
_mips._dm._dm[i+6],
_mips._dm._dm[i+7]);
end
end
initial begin
$dumpfile("test.lxt");
$dumpvars(0,test_mips);
end
endmodule // test_mips
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_TB_V
/**
* udp_dff$PR_pp$PG: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_pr_pp_pg.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PR_pp$PG dut (.D(D), .RESET(RESET), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int k, n; cin >> n >> k; long long int half, d, c; half = (n / 2); d = (half / (k + 1)); c = (k * d); cout << d << << c << << (n - c - d); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_PP_BLACKBOX_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O311AI_BLACKBOX_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<long long> L(n), R(n), A(n); for (int i = 0; i < n; ++i) { cin >> L[i]; } for (int i = 0; i < n; ++i) { cin >> R[i]; } for (int i = 0; i < n; ++i) { A[i] = n - L[i] - R[i]; } for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (A[j] > A[i]) { R[i]--; } } for (int j = 0; j < i; ++j) { if (A[j] > A[i]) { L[i]--; } } } for (int i = 0; i < n; ++i) { if (L[i] || R[i]) { cout << NO << n ; return 0; } } cout << YES << n ; for (int i : A) { cout << i << ; } cout << n ; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:05:15 08/14/2013
// Design Name: siete_segmentos_principal
// Module Name: C:/Users/Fabian/Desktop/Laboratorio 1/sietesegmentos/pruebas.v
// Project Name: sietesegmentos
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: siete_segmentos_principal
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module pruebas;
// Inputs
reg bitA;
reg bitB;
reg bitC;
reg bitD;
// Outputs
wire seg_a;
wire seg_b;
wire seg_c;
wire seg_d;
wire seg_e;
wire seg_f;
wire seg_g;
// Instantiate the Unit Under Test (UUT)
siete_segmentos_principal uut (
.bitA(bitA),
.bitB(bitB),
.bitC(bitC),
.bitD(bitD),
.seg_a(seg_a),
.seg_b(seg_b),
.seg_c(seg_c),
.seg_d(seg_d),
.seg_e(seg_e),
.seg_f(seg_f),
.seg_g(seg_g)
);
initial begin
bitA = 0;
bitB = 0;
bitC = 0;
bitD = 0;
// Wait 100 ns for global reset to finish
#100;
bitA = 0;
bitB = 0;
bitC = 0;
bitD = 1;
// Add stimulus here
end
endmodule
|
module mux_8to1_16bit(Q, S, i1, i2, i3, i4, i5, i6, i7, i8);
input [0:15] i1, i2, i3, i4, i5, i6, i7, i8;
input [0:2] S;
output [0:15] Q;
mux8to1 mux0(Q[0], S, i1[0], i2[0], i3[0], i4[0], i5[0], i6[0], i7[0], i8[0]);
mux8to1 mux1(Q[1], S, i1[1], i2[1], i3[1], i4[1], i5[1], i6[1], i7[1], i8[1]);
mux8to1 mux2(Q[2], S, i1[2], i2[2], i3[2], i4[2], i5[2], i6[2], i7[2], i8[2]);
mux8to1 mux3(Q[3], S, i1[3], i2[3], i3[3], i4[3], i5[3], i6[3], i7[3], i8[3]);
mux8to1 mux4(Q[4], S, i1[4], i2[4], i3[4], i4[4], i5[4], i6[4], i7[4], i8[4]);
mux8to1 mux5(Q[5], S, i1[5], i2[5], i3[5], i4[5], i5[5], i6[5], i7[5], i8[5]);
mux8to1 mux6(Q[6], S, i1[6], i2[6], i3[6], i4[6], i5[6], i6[6], i7[6], i8[6]);
mux8to1 mux7(Q[7], S, i1[7], i2[7], i3[7], i4[7], i5[7], i6[7], i7[7], i8[7]);
mux8to1 mux8(Q[8], S, i1[8], i2[8], i3[8], i4[8], i5[8], i6[8], i7[8], i8[8]);
mux8to1 mux9(Q[9], S, i1[9], i2[9], i3[9], i4[9], i5[9], i6[9], i7[9], i8[9]);
mux8to1 mux10(Q[10], S, i1[10], i2[10], i3[10], i4[10], i5[10], i6[10], i7[10], i8[10]);
mux8to1 mux11(Q[11], S, i1[11], i2[11], i3[11], i4[11], i5[11], i6[11], i7[11], i8[11]);
mux8to1 mux12(Q[12], S, i1[12], i2[12], i3[12], i4[12], i5[12], i6[12], i7[12], i8[12]);
mux8to1 mux13(Q[13], S, i1[13], i2[13], i3[13], i4[13], i5[13], i6[13], i7[13], i8[13]);
mux8to1 mux14(Q[14], S, i1[14], i2[14], i3[14], i4[14], i5[14], i6[14], i7[14], i8[14]);
mux8to1 mux15(Q[15], S, i1[15], i2[15], i3[15], i4[15], i5[15], i6[15], i7[15], i8[15]);
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_rate_limit
*/
module test_axis_rate_limit;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg [7:0] rate_num = 0;
reg [7:0] rate_denom = 0;
reg rate_by_frame = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready,
rate_num,
rate_denom,
rate_by_frame
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_rate_limit.lxt");
$dumpvars(0, test_axis_rate_limit);
end
axis_rate_limit #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Configuration
.rate_num(rate_num),
.rate_denom(rate_denom),
.rate_by_frame(rate_by_frame)
);
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
module jt10_adpcmb_interpol(
input rst_n,
input clk,
input cen, // 8MHz cen
input cen55, // clk & cen55 = 55 kHz
input adv,
input signed [15:0] pcmdec,
output signed [15:0] pcmout
);
localparam stages=6;
reg signed [15:0] pcmlast, delta_x;
reg signed [16:0] pre_dx;
reg start_div=1'b0;
reg [3:0] deltan, pre_dn;
reg [stages-1:0] adv2;
reg signed [15:0] pcminter;
wire [15:0] next_step;
reg [15:0] step;
reg step_sign, next_step_sign;
assign pcmout = pcminter;
always @(posedge clk) if(cen) begin
adv2 <= {adv2[stages-2:0], cen55 & adv }; // give some time to get the data from memory
end
always @(posedge clk) if(cen55) begin
if ( adv ) begin
pre_dn <= 'd1;
deltan <= pre_dn;
end else if ( pre_dn != 4'hF )
pre_dn <= pre_dn + 1'd1;
end
always @(posedge clk) if(cen) begin
start_div <= 1'b0;
if(adv2[1]) begin
pcmlast <= pcmdec;
end
if(adv2[4]) begin
pre_dx <= { pcmdec[15], pcmdec } - { pcmlast[15], pcmlast };
end
if( adv2[5] ) begin
start_div <= 1'b1;
delta_x <= pre_dx[16] ? ~pre_dx[15:0]+1'd1 : pre_dx[15:0];
next_step_sign <= pre_dx[16];
end
end
always @(posedge clk) if(cen55) begin
if( adv ) begin
step <= next_step;
step_sign <= next_step_sign;
pcminter <= pcmlast;
end
else pcminter <= ( (pcminter < pcmlast) == step_sign ) ? pcminter : step_sign ? pcminter - step : pcminter + step;
end
jt10_adpcm_div #(.dw(16)) u_div(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( cen ),
.start ( start_div ),
.a ( delta_x ),
.b ( {12'd0, deltan } ),
.d ( next_step ),
.r ( ),
.working( )
);
endmodule // jt10_adpcmb_interpol
|
module testbench;
logic clk;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) clock_gen (
.o(clk)
);
logic reset;
bsg_nonsynth_reset_gen #(
.num_clocks_p(1)
,.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
localparam els_lp = 4;
localparam lg_els_lp = `BSG_SAFE_CLOG2(els_lp);
localparam tag_width_lp = 8;
localparam data_width_lp = 16;
logic w_v_li;
logic w_nuke_li;
logic [tag_width_lp-1:0] w_tag_li;
logic [data_width_lp-1:0] w_data_li;
logic [els_lp-1:0] empty_lo;
logic r_v_li;
logic [tag_width_lp-1:0] r_tag_li;
logic [data_width_lp-1:0] r_data_lo;
logic r_v_lo;
bsg_cam_1r1w_sync
#(.els_p(els_lp)
,.tag_width_p(tag_width_lp)
,.data_width_p(data_width_lp)
)
DUT
(.clk_i(clk)
,.reset_i(reset)
,.w_v_i(w_v_li)
,.w_nuke_i(w_nuke_li)
,.w_tag_i(w_tag_li)
,.w_data_i(w_data_li)
,.r_v_i(r_v_li)
,.r_tag_i(r_tag_li)
,.r_data_o(r_data_lo)
,.r_v_o(r_v_lo)
);
initial
begin
w_v_li = '0;
w_nuke_li = '0;
w_tag_li = '0;
w_data_li = '0;
r_v_li = '0;
r_tag_li = '0;
@(negedge reset);
@(posedge clk);
@(negedge clk);
$display("Writing data 1");
w_v_li = 1'b1;
w_nuke_li = 1'b0;
w_tag_li = 8'h00;
w_data_li = 16'hdead;
@(negedge clk);
$display("Writing data 2");
w_v_li = 1'b1;
w_nuke_li = 1'b0;
w_tag_li = 8'h11;
w_data_li = 16'hbeef;
@(negedge clk);
w_v_li = 1'b0;
@(negedge clk);
@(posedge clk)
$display("Checking read data 1");
r_v_li = 1'b1;
r_tag_li = 8'h00;
@(posedge clk);
@(negedge clk);
assert (r_v_lo);
assert (r_data_lo == 16'hdead);
@(posedge clk);
$display("Checking read data 2");
r_v_li = 1'b1;
r_tag_li = 8'h11;
@(posedge clk);
@(negedge clk);
assert (r_v_lo);
assert (r_data_lo == 16'hbeef);
@(posedge clk);
r_v_li = 1'b0;
@(posedge clk);
$display("Testing nuke");
w_v_li = 1'b1;
w_nuke_li = 1'b1;
w_tag_li = 'X;
w_data_li = 'X;
@(posedge clk);
w_v_li = 1'b0;
r_v_li = 1'b1;
r_tag_li = 8'h11;
@(negedge clk);
assert (~r_v_lo);
@(posedge clk);
w_v_li = 1'b0;
r_v_li = 1'b1;
r_tag_li = 8'h00;
@(negedge clk);
assert (~r_v_lo);
$finish();
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// std_logic values test.
module vhdl_logic_test;
logic low, high, hiz, dontcare, uninitialized, unknown;
vhdl_logic dut(low, high, hiz, dontcare, uninitialized, unknown);
initial begin
if(low !== 1'b0) begin
$display("FAILED low");
$finish();
end
if(high !== 1'b1) begin
$display("FAILED high");
$finish();
end
if(hiz !== 1'bz) begin
$display("FAILED hiz");
$finish();
end
if(dontcare !== 1'bx) begin
$display("FAILED dontcare");
$finish();
end
if(uninitialized !== 1'bx) begin
$display("FAILED uninitialized");
$finish();
end
if(unknown !== 1'bx) begin
$display("FAILED unknown");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 25; long long a[MAX]; int main() { ios_base::sync_with_stdio(false); long long n, k, h; cin >> n >> h >> k; for (int i = 0; i < n; i++) cin >> a[i]; long long ans = 0; long long in = a[0]; for (int i = 1; i < n; i++) { if (in + a[i] <= h) { in += a[i]; } else { double x = (a[i] + in - h) * 1.0 / k; long long x1 = floor(x); long long x2 = ceil(x); long long t1 = in, t2 = in; t1 -= x1 * k; if (t1 < 0) t1 = 0; if (t1 + a[i] <= h) { in -= x1 * k; if (in < 0) in = 0; in += a[i]; ans += x1; continue; } t2 -= x2 * k; if (t2 < 0) t2 = 0; if (t2 + a[i] <= h) { in -= x2 * k; if (in < 0) in = 0; in += a[i]; ans += x2; } } } if (in > 0) { long long t1 = in / k; long long t2 = in % k; ans += t1; if (t2) ans++; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1000000007; long long INF = 1LL << 60; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n; cin >> n; vector<long long> l(n), r(n), m(n); for (long long i = (long long)(0); i < (n); i++) { cin >> m[i]; } stack<pair<long long, long long>> stk; stk.push(make_pair(0, -1)); stk.push(make_pair(m[0], 0)); l[0] = m[0]; for (long long i = (long long)(1); i < (n); i++) { if (m[i] > stk.top().first) { l[i] = l[i - 1] + m[i]; } else { while (!stk.empty() && m[i] < stk.top().first) { stk.pop(); } int ind = stk.top().second; long long prv; if (ind == -1) { prv = 0; } else { prv = l[ind]; } l[i] = prv + (i - ind) * m[i]; } stk.push(make_pair(m[i], i)); } while (!stk.empty()) { stk.pop(); }; reverse(m.begin(), m.end()); ; stk.push(make_pair(0, -1)); stk.push(make_pair(m[0], 0)); r[0] = m[0]; for (long long i = (long long)(1); i < (n); i++) { if (m[i] > stk.top().first) { r[i] = r[i - 1] + m[i]; } else { while (!stk.empty() && m[i] < stk.top().first) { stk.pop(); } int ind = stk.top().second; long long prv; if (ind == -1) { prv = 0; } else { prv = r[ind]; } r[i] = prv + (i - ind) * m[i]; } stk.push(make_pair(m[i], i)); }; reverse(m.begin(), m.end()); ; ; reverse(r.begin(), r.end()); ; int ind = 0; long long out = 0; long long temp; for (long long i = (long long)(0); i < (n); i++) { temp = l[i] + r[i] - m[i]; if (temp > out) { ind = i; out = temp; } } vector<long long> outt(n); outt[ind] = m[ind]; long long big = m[ind]; for (int i = ind - 1; i >= 0; i--) { if (m[i] < big) { big = m[i]; } outt[i] = big; } big = m[ind]; for (int i = ind + 1; i < n; i++) { if (m[i] < big) { big = m[i]; } outt[i] = big; } for (long long i = (long long)(0); i < (n); i++) { cout << outt[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n; cin >> n; vector<int> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; stack<int> lid, rid; vector<int> mxl(n + 1), mxr(n + 1); for (int i = 1; i <= n; i++) { while (!lid.empty() && a[i] > a[lid.top()]) lid.pop(); mxl[i] = lid.empty() ? 1 : lid.top() + 1; lid.push(i); } for (int i = n; i >= 1; i--) { while (!rid.empty() && a[i] >= a[rid.top()]) rid.pop(); mxr[i] = rid.empty() ? n : rid.top() - 1; rid.push(i); } long long ans = 0; for (int i = 1; i <= n; i++) { ans += (long long)a[i] * (mxr[i] - i + 1) * (i - mxl[i] + 1); } vector<int> mil(n + 1), mir(n + 1); while (!lid.empty()) lid.pop(); while (!rid.empty()) rid.pop(); for (int i = 1; i <= n; i++) { while (!lid.empty() && a[i] < a[lid.top()]) lid.pop(); mil[i] = lid.empty() ? 1 : lid.top() + 1; lid.push(i); } for (int i = n; i >= 1; i--) { while (!rid.empty() && a[i] <= a[rid.top()]) rid.pop(); mir[i] = rid.empty() ? n : rid.top() - 1; rid.push(i); } for (int i = 1; i <= n; i++) { ans -= (long long)a[i] * (mir[i] - i + 1) * (i - mil[i] + 1); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mxN = 1e6; int n, k, a[mxN], l[mxN]; struct dsu { int p[mxN], ld[mxN], lb[mxN]; void init() { iota(p, p + n, 0); iota(lb, lb + n, 0); } int find(int x) { return x == p[x] ? x : (p[x] = find(p[x])); } void join(int x, int y) { x = find(x), y = find(y); p[x] = y; lb[y] = lb[x]; ld[y] += ld[x]; } void upd(int i, int j) { i = find(i); ++ld[i]; if (j < n) --ld[j]; while (ld[i] >= 0 && lb[i]) join(lb[i] - 1, i); } void upd2(int i) { if (i < k) return; int j = find(i - k + 1); while (lb[j] > i - k) join(lb[j] - 1, j); } int qry() { return ld[find(0)]; } } d; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int i = 0; i < n; ++i) cin >> a[i]; d.init(); for (int i = 0; i < n; ++i) { d.upd2(i); l[i] = i - 1; while (l[i] >= 0 && a[l[i]] < a[i]) { l[i] = l[l[i]]; } d.upd(l[i] + 1, i + 1); if (i >= k - 1) cout << d.qry() << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; long long ans, dp[N]; int ed, n, m; struct node { int w, c; double val; node(int a = 0, int b = 0) : w(a), c(b) {} bool operator<(const node &b) const { return val > b.val; } } a[N], tmp[N]; long long DP() { for (int i = 1; i <= ed; i++) { for (int j = m; j >= tmp[i].w; j--) { dp[j] = max(dp[j], dp[j - tmp[i].w] + tmp[i].c); } } return dp[m]; } int main() { scanf( %d%d , &n, &m); ans = 0; for (int i = 1; i <= n; i++) scanf( %d%d , &a[i].w, &a[i].c), a[i].val = 1.0 * a[i].c / a[i].w; sort(a + 1, a + 1 + n); int tp[4]; memset(tp, -1, sizeof(tp)); for (int i = 1; i <= n; i++) { if (m < 30) { ed = 0; while (i <= n) tmp[++ed] = a[i], i++; for (int ii = 1; ii <= 3; ii++) if (~tp[ii]) tmp[++ed] = node(ii, tp[ii]), m += ii, ans -= tp[ii]; ans += DP(); break; } ans += a[i].c; m -= a[i].w; tp[a[i].w] = a[i].c; } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; void print(vector<int> v) { for (int i = 0; i < v.size(); i++) { if (v[i] != 0) { cout << v[i]; } } cout << endl; } void solve(vector<int>& v, int even, int odd) { if (v.size() == 1) { cout << -1 << endl; return; } else if (v.size() == 2) { if (odd != 2) { cout << -1 << endl; return; } else { print(v); return; } } else if (odd == 0) { cout << -1 << endl; return; } else { while (v[v.size() - 1] % 2 == 0) { v.pop_back(); even--; } if (odd == 1) { cout << -1 << endl; return; } else if (odd % 2 == 0) { print(v); return; } else { for (int i = 0; i < v.size(); i++) { if (v[i] % 2 == 1) { v.erase(v.begin() + i); print(v); return; } } } } } int main() { int t; cin >> t; while (t--) { int e = 0, o = 0; int n; cin >> n; string s; cin >> s; vector<int> v(n); for (int i = 0; i < s.size(); i++) { v[i] = s[i] - 48; if (v[i] % 2 == 0) e++; else o++; } solve(v, e, o); } }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the pipe
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
//`include "pipe.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipe();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the pipe
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire op; // Output signal out
// Declare "reg" signals: inputs to the DUT
reg ip; // Input signal - in
reg clk; // Input signal - clock
reg rst; // Input signal - reset
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pp"
*/
pipeline_buffer pp (
// instance_name(signal name),
// Signal name can be the same as the instance name
ip,op,clk,rst);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clk = 0;
#5 clk = 1;
// Period = 10 ns
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
ip = 1'd0;
rst = 1'd0;
// @t=9,
#9
ip = 1'd1;
rst = 1'd0;
// @t=19,
#10
ip = 1'd0;
rst = 1'd0;
// @t=29,
#10
ip = 1'd1;
rst = 1'd0;
// @t=39,
#10
ip = 1'd1;
rst = 1'd0;
// @t=49,
#10
ip = 1'd1;
rst = 1'd0;
// @t=59,
#10
ip = 1'd0;
rst = 1'd0;
// @t=69,
#10
ip = 1'd1;
rst = 1'd0;
// @t=79,
#10
ip = 1'd0;
rst = 1'd0;
// @t=89,
#10
ip = 1'd1;
rst = 1'd0;
// @t=99,
#10
ip = 1'd0;
rst = 1'd0;
// @t=109,
#10
ip = 1'd1;
rst = 1'd0;
// @t=119,
#10
ip = 1'd0;
rst = 1'd0;
// @t=129,
#10
ip = 1'd1;
rst = 1'd0;
// @t=139,
#10
ip = 1'd0;
rst = 1'd0;
// @t=149,
#10
ip = 1'd1;
rst = 1'd0;
// @t=159,
#10
ip = 1'd1;
rst = 1'd0;
// @t=169,
#10
ip = 1'd1;
rst = 1'd0;
// @t=179,
#10
ip = 1'd0;
rst = 1'd0;
// @t=189,
#10
ip = 1'd1;
rst = 1'd0;
// @t=199,
#10
ip = 1'd0;
rst = 1'd0;
// @t=209,
#10
ip = 1'd1;
rst = 1'd0;
// @t=219,
#10
ip = 1'd1;
rst = 1'd0;
// @t=229,
#10
ip = 1'd1;
rst = 1'd0;
// @t=239,
#10
ip = 1'd1;
rst = 1'd0;
// @t=249,
#10
ip = 1'd1;
rst = 1'd0;
// @t=259,
#10
ip = 1'd0;
rst = 1'd0;
// @t=269,
#10
ip = 1'd1;
rst = 1'd0;
// @t=279,
#10
ip = 1'd1;
rst = 1'd1;
// @t=289,
#10
ip = 1'd1;
rst = 1'd0;
// @t=299,
#10
ip = 1'd0;
rst = 1'd0;
// @t=309,
#10
ip = 1'd1;
rst = 1'd0;
// @t=319,
#10
ip = 1'd1;
rst = 1'd0;
// @t=329,
#10
ip = 1'd0;
rst = 1'd0;
// @t=339,
#10
ip = 1'd1;
rst = 1'd0;
// @t=349,
#10
ip = 1'd0;
rst = 1'd0;
// @t=359,
#10
ip = 1'd1;
rst = 1'd0;
// @t=369,
#10
ip = 1'd1;
rst = 1'd0;
// @t=379,
#10
ip = 1'd1;
rst = 1'd0;
// @t=389,
#10
ip = 1'd1;
rst = 1'd0;
// @t=399,
#10
ip = 1'd0;
rst = 1'd0;
// @t=409,
#10
ip = 1'd1;
rst = 1'd0;
// @t=419,
#10
ip = 1'd1;
rst = 1'd0;
// @t=429,
#10
ip = 1'd1;
rst = 1'd0;
// @t=439,
#10
ip = 1'd1;
rst = 1'd0;
// @t=449,
#10
ip = 1'd1;
rst = 1'd0;
// @t=459,
#10
ip = 1'd0;
rst = 1'd0;
// @t=469,
#10
ip = 1'd1;
rst = 1'd0;
// @t=479,
#10
ip = 1'd0;
rst = 1'd0;
// @t=489,
#10
ip = 1'd0;
rst = 1'd0;
// @t=499,
#10
ip = 1'd0;
rst = 1'd0;
// @t=509,
#10
ip = 1'd0;
rst = 1'd0;
// @t=519,
#10
ip = 1'd1;
rst = 1'd0;
// @t=529,
#10
ip = 1'd1;
rst = 1'd0;
// @t=539,
#10
ip = 1'd0;
rst = 1'd0;
// @t=549,
#10
ip = 1'd1;
rst = 1'd0;
// @t=559,
#10
ip = 1'd1;
rst = 1'd0;
// @t=569,
#10
ip = 1'd1;
rst = 1'd0;
// @t=579,
#10
ip = 1'd1;
rst = 1'd0;
// @t=589,
#10
ip = 1'd0;
rst = 1'd0;
// @t=599,
#10
ip = 1'd1;
rst = 1'd0;
// @t=609,
#10
ip = 1'd0;
rst = 1'd0;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:45:49 08/25/2014
// Design Name: Counter_x
// Module Name: E:/Summer Course/Top_Computer_IOBUS_VGA_PS2_N3/test_counter.v
// Project Name: Top_Computer_IOBUS_VGA_PS2_N3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Counter_x
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_counter;
// Inputs
reg clk;
reg rst;
reg clk0;
reg clk1;
reg clk2;
reg counter_we;
reg [31:0] counter_val;
reg [1:0] counter_ch;
// Outputs
wire counter0_OUT;
wire counter1_OUT;
wire counter2_OUT;
wire [31:0] counter_out;
// Instantiate the Unit Under Test (UUT)
Counter_x uut (
.clk(clk),
.rst(rst),
.clk0(clk0),
.clk1(clk1),
.clk2(clk2),
.counter_we(counter_we),
.counter_val(counter_val),
.counter_ch(counter_ch),
.counter0_OUT(counter0_OUT),
.counter1_OUT(counter1_OUT),
.counter2_OUT(counter2_OUT),
.counter_out(counter_out)
);
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
initial forever begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
initial forever begin
clk0 = 1'b0;
#(10*PERIOD-(10*PERIOD*DUTY_CYCLE)) clk0 = 1'b1;
#(10*PERIOD*DUTY_CYCLE);
end
initial forever begin
clk1 = 1'b0;
#(10*PERIOD-(10*PERIOD*DUTY_CYCLE)) clk1 = 1'b1;
#(10*PERIOD*DUTY_CYCLE);
end
initial forever begin
clk2 = 1'b0;
#(10*PERIOD-(10*PERIOD*DUTY_CYCLE)) clk2 = 1'b1;
#(10*PERIOD*DUTY_CYCLE);
end
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
clk0 = 0;
clk1 = 0;
clk2 = 0;
counter_we = 0;
counter_val = 16'h10;
counter_ch = 0;
// Wait 100 ns for global reset to finish
#100;
//#100 rst = 1;
//#100 rst = 0;
// Add stimulus here
#100 counter_we = 1;
//counter_ch = 1;
//counter_val = 10;
#100 counter_we = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100 * 1000 + 17; long long n, a[MAXN], ans; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i < n; i++) { int t = log2(n - i); a[i + (1 << t)] += a[i]; ans += a[i]; a[i] = 0; cout << ans << endl; } return 0; }
|
module s27_path (
G1,
G2,
clk_net,
reset_net,
G3,
G0,
G17);
// Start PIs
input G1;
input G2;
input clk_net;
input reset_net;
input G3;
input G0;
// Start POs
output G17;
// Start wires
wire G1;
wire net_5;
wire net_15;
wire net_27;
wire G17;
wire reset_net;
wire net_14;
wire G3;
wire net_26;
wire clk_net;
wire net_13;
wire G2;
wire net_19;
wire net_3;
wire net_22;
wire net_16;
wire net_6;
wire net_24;
wire net_11;
wire net_1;
wire net_23;
wire net_18;
wire net_12;
wire net_2;
wire net_10;
wire net_8;
wire net_9;
wire net_25;
wire net_21;
wire net_7;
wire net_20;
wire G0;
wire net_4;
wire net_17;
// Start cells
CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) );
DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) );
INV_X1 inst_12 ( .A(net_16), .ZN(G17) );
INV_X4 inst_8 ( .ZN(net_5), .A(net_1) );
NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) );
NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) );
CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) );
CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) );
NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) );
CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) );
INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) );
CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) );
CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) );
NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) );
CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) );
DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) );
DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) );
CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) );
NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) );
NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) );
INV_X4 inst_9 ( .ZN(net_9), .A(net_7) );
NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) );
INV_X2 inst_10 ( .ZN(net_4), .A(G1) );
NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) );
CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) );
INV_X2 inst_11 ( .ZN(net_15), .A(G0) );
CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) );
CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int prime = 999983; const int INF = 0x7FFFFFFF; const long long INFF = 0x7FFFFFFFFFFFFFFF; const double pi = acos(-1.0); const double inf = 1e18; const double eps = 1e-6; const long long mod = 1e9 + 7; long long qpow(long long a, long long b) { long long s = 1; while (b > 0) { if (b & 1) s = s * a % mod; a = a * a % mod; b >>= 1; } return s; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int dr[2][4] = {1, -1, 0, 0, 0, 0, -1, 1}; const int maxm = 2e7, maxn = 3e5 + 10; int a[maxn]; int num[maxm][2]; int main(void) { int n; cin >> n; long long ans = 0; num[0][0] = 1; for (int i = 1; i < n + 1; i++) { scanf( %d , &a[i]); a[i] ^= a[i - 1]; ans += num[a[i]][i % 2]; num[a[i]][i % 2]++; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const double eps = 1e-10; const float epsf = 1e-6; using namespace std; inline long long int __gcd(long long int a, long long int b) { if (a == 0 || b == 0) { return max(a, b); } long long int tempa, tempb; while (1) { if (a % b == 0) return b; else { tempa = a; tempb = b; a = tempb; b = tempa % tempb; } } } inline int compfloat(float& x, float& y) { if (fabs(x - y) < epsf) return 0; else if (x - y > 0) return 1; return -1; } inline int compdouble(double x, double y) { if (fabs(x - y) < eps) return 0; else if (x - y > 0) return 1; else return -1; } bool prime(long long int k) { for (long long int i = 2; i * i <= k; i++) if (k % i == 0) { return false; } return true; } void pdash(int n = 1) { for (int i = 0; i < n; i++) { for (int j = 0; j < 30; j++) { cout << - ; } cout << n ; } } long long int power(long long int x, long long int y) { long long int result = 1; while (y > 0) { if (y & 1) { result = (result * x); } y = y >> 1; x = (x * x); } return result; } long long int power(long long int x, long long int y, long long int z) { long long int result = 1; x = x % z; while (y > 0) { if (y & 1) { result = (result * x) % z; } y = y >> 1; x = (x * x) % z; } return result; } long long int modInverse(long long int n, long long int p) { return power(n, p - 2, p); } long long int nCrF(long long int n, long long int r, long long int p) { if (r == 0) return 1; long long int f[n + 1]; f[0] = 1; for (long long int i = 1; i <= n; i++) f[i] = f[i - 1] * i % p; return (f[n] * modInverse(f[r], p) % p * modInverse(f[n - r], p) % p) % p; } void cordinate_compression(vector<int>& v) { vector<int> p = v; sort(p.begin(), p.end()); p.erase(unique(p.begin(), p.end()), p.end()); for (int i = 0; i < (int)((v).size()); i++) v[i] = (int)(lower_bound(p.begin(), p.end(), v[i]) - p.begin()); } const int MX = 1400009; vector<int> used(MX, 0); vector<int> factor[MX]; vector<int> isprime(MX, 1); vector<bool> is_used(MX, 0); inline bool check(int index) { for (auto& j : factor[index]) { if (is_used[j]) return 0; } for (auto& j : factor[index]) { is_used[j] = 1; } return 1; } void solve() { int n; cin >> n; int a[n]; for (int i = 2; i < MX; i++) { if (isprime[i]) { for (int j = i; j < MX; j += i) { factor[j].push_back(i); isprime[j] = 0; } } } int curr = 2; bool bz = 1; for (int i = 0; i < n; i++) { cin >> a[i]; if (bz) { curr = a[i]; while (!check(curr)) curr++; if (curr != a[i]) { bz = 0; } cout << curr << ; curr = 2; } else { while (!check(curr)) curr++; cout << curr << ; } } cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); } }
|
// nios_tester_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module nios_tester_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 0,
parameter inDataWidth = 10,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 10,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [9:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [9:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_tester_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ofstream out( output.txt ); auto start = chrono::high_resolution_clock::now(); long long t = 1; for (long long test = 1; test <= t; test++) { long long n; cin >> n; vector<long long> a(n); pair<long long, long long> b[n]; for (long long i = 0; i <= n - 1; i++) cin >> a[i], b[i].first = a[i], b[i].second = i; sort(b, b + n); long long ord[n]; long long shts = 0, I = 0; for (long long i = n - 1; i >= 0; i--) { shts += (b[i].first * I + 1); ord[I] = b[i].second + 1; I++; } cout << shts << n ; for (long long i = 0; i <= n - 1; i++) cout << ord[i] << ; cout << n ; } auto stop = chrono::high_resolution_clock::now(); }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 10; int n, a, b; int main() { cin >> n >> a >> b; int table1_count = 0; int table2_count = 0; int one_two_count = 0; int ans = 0; for (int i = 0; i < n; i++) { int t; cin >> t; if (t == 1) { bool is_sit = false; if (table1_count < a) { table1_count++; is_sit = true; } if (!is_sit) { if (table2_count < b) { table2_count++; one_two_count++; is_sit = true; } } if (!is_sit) { if (one_two_count > 0) { one_two_count--; is_sit = true; } } if (!is_sit) { ans++; } } else { if (table2_count < b) { table2_count++; } else { ans += 2; } } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int F(int d); int G(int d); int n, ara[2 * 100010], dpf[2 * 100010], dpg[2 * 100010], k; bool visf[2 * 100010], visg[2 * 100010]; vector<int> vec; int add(int _a, int _b) { _a = (_a + 998244353) % 998244353; _b = (_b + 998244353) % 998244353; return (_a + _b) % 998244353; } int mul(int _a, int _b) { _a = (_a + 998244353) % 998244353; _b = (_b + 998244353) % 998244353; return ((long long int)((long long int)_a * (long long int)_b)) % 998244353; } void input() { int i, j; scanf( %d %d , &n, &k); for (i = 0; i < n; i++) { scanf( %d , &ara[i]); } } int G(int d) { int i, j; if (d == 0) { return 1; } if (visg[d]) { return dpg[d]; } visg[d] = true; int s1 = 0, s2 = 0; s1 = F(d - 1) % 998244353; s2 = mul(max(k - 2, 0), G(d - 1) % 998244353); return dpg[d] = add(s1, s2); } int F(int d) { int i, j; if (d == 0) { return 0; } if (visf[d]) { return dpf[d]; } visf[d] = true; return dpf[d] = mul(k - 1, G(d - 1) % 998244353); } int sol(int f) { int i, j, cnt, ret = 1, s; for (i = 0, vec.clear(); i < n; i++) { if (i % 2 == f) { vec.push_back(ara[i]); } } for (i = 0; i < vec.size(); i = j) { int respect = vec[i]; for (j = i + 1, cnt = 0; j < vec.size() && vec[j] == -1; j++) { cnt++; } if (j == vec.size()) { if (respect == -1) { for (j = 0; j < vec.size(); j++) { if (j == 0) { ret = mul(ret, k); } else { ret = mul(ret, k - 1); } } } else { if (cnt == 0) { ret = mul(ret, 1); } else { s = add(F(cnt - 1) % 998244353, mul(k - 1, G(cnt - 1) % 998244353)); ret = mul(ret, s); } } } else { if (respect == -1) { s = add(F(cnt) % 998244353, mul(k - 1, G(cnt) % 998244353)); ret = mul(ret, s); } else if (respect == vec[j]) { ret = mul(ret, F(cnt) % 998244353); } else { ret = mul(ret, G(cnt) % 998244353); } } } return ret; } void solve() { int i, j; int ret = mul(sol(0), sol(1)); printf( %d , ret); puts( ); } int main() { input(); solve(); }
|
`include "bch_defs.vh"
module xilinx_parallel #(
parameter T = 3,
parameter DATA_BITS = 5
) (
input clk_in,
input start,
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
input ack_done,
output done,
output ready,
output [`BCH_SIGMA_SZ(P)-1:0] sigma,
output [`BCH_ERR_SZ(P)-1:0] err_count
);
`include "bch_params.vh"
localparam P = bch_params(DATA_BITS, T);
wire [`BCH_SYNDROMES_SZ(P)-1:0] syndromes0;
wire start0;
wire ce0;
wire ready0;
wire [`BCH_SIGMA_SZ(P)-1:0] sigma0;
wire [`BCH_ERR_SZ(P)-1:0] err_count0;
wire done0;
wire ack_done0;
BUFG u_bufg (
.I(clk_in),
.O(clk)
);
pipeline #(2) u_input [`BCH_SYNDROMES_SZ(P)+2-1:0] (
.clk(clk),
.i({syndromes, start, ack_done}),
.o({syndromes0, start0, ack_done0})
);
pipeline #(2) u_output [`BCH_SIGMA_SZ(P)+`BCH_ERR_SZ(P)+2-1:0] (
.clk(clk),
.i({ready0, sigma0, done0, err_count0}),
.o({ready, sigma, done, err_count})
);
bch_sigma_bma_parallel #(P) u_bma (
.clk(clk),
.start(start0),
.ready(ready0),
.syndromes(syndromes0),
.sigma(sigma0),
.done(done0),
.ack_done(ack_done0),
.err_count(err_count0)
);
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
ColorGray2Channels
:Function
Covert Gray-scale to Channels.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module ColorGray2Channels(
gray,
channels
);
parameter color_width = 8;
parameter color_channels = 3;
input[color_width - 1 : 0] gray;
output[color_channels * color_width - 1 : 0] channels;
genvar i;
generate
`define h (i + 1) * color_width - 1
`define l i * color_width
for (i = 0; i < color_channels; i = i + 1) begin: channel
assign channels[`h : `l] = gray;
end
`undef h
`undef l
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_4_V
`define SKY130_FD_SC_HD__O2BB2AI_4_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_4_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int U[5005], V[5005]; struct emm { int a, b, x; } a[5005]; bool cmp(emm x, emm y) { return x.x < y.x; } struct Edge { int v; Edge *next; } pool[5005 << 1], *h[5005]; int fa[5005], dep[5005], ans[5005]; int tot; void addEdge(int u, int v) { Edge *p = &pool[tot++]; p->v = v; p->next = h[u]; h[u] = p; } void dfs(int u) { for (Edge *p = h[u]; p; p = p->next) { int v = p->v; if (v == fa[u]) continue; dep[v] = dep[u] + 1; fa[v] = u; dfs(v); } } int LCA(int u, int v) { if (dep[u] < dep[v]) swap(u, v); while (dep[u] > dep[v]) { u = fa[u]; } if (u == v) return u; while (fa[u] != fa[v]) { u = fa[u]; v = fa[v]; } return fa[u]; } void update(int u, int v, int x) { if (u == v) return; while (u != v) { ans[u] = x; u = fa[u]; } } int check(int u, int v) { int res = 0x3f3f3f3f; if (u == v) return res; while (u != v) { res = min(res, ans[u]); u = fa[u]; } return res; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d%d , &U[i], &V[i]); addEdge(U[i], V[i]); addEdge(V[i], U[i]); } dep[1] = 1; dfs(1); scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %d%d%d , &a[i].a, &a[i].b, &a[i].x); sort(a + 1, a + m + 1, cmp); for (int i = 1; i <= m; i++) { int t = LCA(a[i].a, a[i].b); update(a[i].a, t, a[i].x); update(a[i].b, t, a[i].x); } for (int i = 1; i <= m; i++) { int t = LCA(a[i].a, a[i].b); if (min(check(a[i].a, t), check(a[i].b, t)) != a[i].x) { printf( -1 n ); return 0; } } for (int i = 1; i < n; i++) { if (dep[U[i]] < dep[V[i]]) swap(U[i], V[i]); printf( %d , max(ans[U[i]], 1)); } printf( n ); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; int a[1005][1005]; int main() { int N, K, D, i, j; loop: while (~scanf( %d%d%d , &N, &K, &D)) { memset(a, 0, sizeof(a)); for (j = 0; j < N; ++j) { a[D - 1][j] = j; } for (i = D - 1; i > 0; --i) { for (j = 0; j < N; ++j) { a[i - 1][j] += a[i][j] / K; a[i][j] %= K; } } for (i = 0; i < D; ++i) { for (j = 0; j < N; ++j) { if (a[i][j] >= K) { puts( -1 ); goto loop; } } } for (i = 0; i < D; ++i) { for (j = 0; j < N; ++j) { printf( %d%s , a[i][j] + 1, j == N - 1 ? n : ); } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> re; int main() { cin >> n; int least[n]; for (int i = 0; i < n; i++) cin >> least[i]; sort(least, least + n); int cont = 0; for (int i = 1; i < n; i++) { if (least[i] == least[i - 1]) { re.push_back(least[i]); least[i - 1] = -1; cont++; } else { cont = 0; } if (cont >= 2) { cout << NO << endl; return 0; } } sort(re.begin(), re.end()); cout << YES << endl; cout << n - re.size() << endl; for (int i = 0; i < n; i++) { if (least[i] == -1) continue; cout << least[i] << ; } cout << endl; cout << re.size() << endl; for (int i = re.size() - 1; i >= 0; i--) cout << re[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1610; typedef int MAP[maxn][maxn]; int n, m; MAP A, B, flag, used; int total; int num[maxn * maxn], que[maxn * maxn * 2]; MAP temp; int px[] = {0, 0, 1, -1, 0}, py[] = {1, -1, 0, 0, 0}; bool isok(int x, int y) { return x >= 1 && x <= n && y >= 1 && y <= m; } void zoomin(MAP X) { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { int value = 1; for (int x = 0; x < 5; x++) if (isok(i + px[x], j + py[x]) && X[i + px[x]][j + py[x]] == 0) value = 0; temp[i][j] = value; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) X[i][j] = temp[i][j]; } void zoomout(MAP X) { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { int value = 0; for (int x = 0; x < 5; x++) if (isok(i + px[x], j + py[x]) && X[i + px[x]][j + py[x]] == 1) value = 1; temp[i][j] = value; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) X[i][j] = temp[i][j]; } void bfs(int x, int y, int& index) { index++; int start = 1, tail = 0, sum = 0; que[++tail] = x; que[++tail] = y; used[x][y] = 1; while (start <= tail) { x = que[start++]; y = que[start++]; flag[x][y] = index; sum++; for (int i = 0; i < 4; i++) if (isok(x + px[i], y + py[i]) && !used[x + px[i]][y + py[i]] && B[x + px[i]][y + py[i]] == 1) { used[x + px[i]][y + py[i]] = 1; que[++tail] = x + px[i]; que[++tail] = y + py[i]; } } if (sum < 100) index--; } void bfs(int x, int y) { int start = 1, tail = 0, sum = 0, index = 0; que[++tail] = x; que[++tail] = y; used[x][y] = 1; while (start <= tail) { x = que[start++]; y = que[start++]; sum++; for (int i = 0; i < 4; i++) if (isok(x + px[i], y + py[i]) && !used[x + px[i]][y + py[i]] && A[x + px[i]][y + py[i]] == 1) { if (!flag[x + px[i]][y + py[i]]) { used[x + px[i]][y + py[i]] = 1; que[++tail] = x + px[i]; que[++tail] = y + py[i]; } else { index = flag[x + px[i]][y + py[i]]; } } } if (sum > 2) num[index]++; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &A[i][j]); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) B[i][j] = A[i][j]; for (int i = 1; i <= 3; i++) zoomin(B); for (int i = 1; i <= 4; i++) zoomout(B); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (!used[i][j] && B[i][j]) bfs(i, j, total); memset(used, 0, sizeof(used)); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (!used[i][j] && A[i][j] && !flag[i][j]) bfs(i, j); sort(num + 1, num + 1 + total); cout << total << endl; for (int i = 1; i <= total; i++) cout << num[i] << ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_SYMBOL_V
`define SKY130_FD_SC_LP__HA_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void getint(int &v) { char ch, fu = 0; for (ch = * ; (ch < 0 || ch > 9 ) && ch != - ; ch = getchar()) ; if (ch == - ) fu = 1, ch = getchar(); for (v = 0; ch >= 0 && ch <= 9 ; ch = getchar()) v = v * 10 + ch - 0 ; if (fu) v = -v; } int n, a[500010], t, ans; int main() { cin >> n; for (int i = 1; i <= n; ++i) getint(a[i]); sort(a + 1, a + n + 1); for (int i = 1; i <= n - 1; ++i) if (a[i] == a[i + 1]) { if (t) return puts( cslnb ), 0; t = i; } if (t) { if (t == 1) { if (a[t] == 0) return puts( cslnb ), 0; --a[t]; } else { if (a[t] == a[t - 1] + 1) return puts( cslnb ), 0; --a[t]; } for (int i = 1; i <= n; ++i) (ans += a[i] - (i - 1)) %= 2; if (ans & 1) puts( cslnb ); else puts( sjfnb ); return 0; } for (int i = 1; i <= n; ++i) (ans += a[i] - (i - 1)) %= 2; if (ans % 2 == 0) puts( cslnb ); else puts( sjfnb ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5; const int mod = 1e9 + 7; int cnt; int head[MAX + 5], to[4 * MAX + 5], nex[4 * MAX + 5]; void add(int u, int v) { to[++cnt] = v; nex[cnt] = head[u]; head[u] = cnt; } int n, m; int _cnt; long long prime[MAX + 5], es[MAX + 5]; int dfs(int u, int f) { long long sub = 1; for (int i = head[u]; i; i = nex[i]) { if (to[i] != f) { long long temp = dfs(to[i], u); es[++_cnt] = temp * (n - temp); sub += temp; } } return sub; } bool cmp(long long a, long long b) { return a > b; } int main() { int T; scanf( %d , &T); while (T--) { scanf( %d , &n); cnt = 0; for (int i = 1; i <= n; i++) head[i] = 0; for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); add(u, v); add(v, u); } scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %lld , prime + i); sort(prime + 1, prime + 1 + m); if (m >= n) { for (int i = n; i <= m; i++) prime[n - 1] = prime[n - 1] * prime[i] % mod; m = n - 1; } _cnt = 0; dfs(1, 0); sort(es + 1, es + n, cmp); long long ans = 0; for (int i = 1; i < n; i++) { if (m) ans = (ans + es[i] * prime[m--] % mod) % mod; else ans = (ans + es[i]) % mod; } printf( %lld n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDLCLKP_PP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdlclkp (
GCLK,
GATE,
CLK ,
SCE ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_BLACKBOX_V
`define SKY130_FD_SC_LP__MAJ3_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__maj3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i <= n - 1; i++) cin >> arr[i]; vector<pair<int, int> > G[n]; int cnt = 0; for (int i = 0; i <= n - 1; i++) { for (int j = i + 1; j <= n - 1; j++) { if (arr[i] > arr[j]) { G[i].push_back(make_pair(arr[j], j)); cnt++; } } } cout << cnt << n ; for (int i = 0; i <= n - 1; i++) { sort(G[i].begin(), G[i].end()); int s = G[i].size(); for (int j = s - 1; j >= 0; j--) { cout << i + 1 << << G[i][j].second + 1 << n ; } } return 0; }
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.0sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_win_change (clock, reset, enable, start_event, test_expr, end_event, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input [width-1:0] test_expr;
input end_event;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_WIN_CHANGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_win_change_logic.v"
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endif
`ifdef OVL_SVA
`include "./sva05/assert_win_change_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_win_change_psl_logic.v"
`else
`endmodule // ovl_win_change
`endif
|
/*
########################################################################
ELINK CONFIGURATION REGISTER FILE
########################################################################
*/
`include "elink_regmap.v"
module erx_cfg (/*AUTOARG*/
// Outputs
mi_dout, rx_enable, mmu_enable, remap_mode, remap_base,
remap_pattern, remap_sel, timer_cfg,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, gpio_datain, rx_status
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 6; // 32 registers for now
parameter GROUP = 4'h0;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; // ecfg registers reset only by "hard reset"
input clk;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_en;
input mi_we; // single we, must write 32 bit words
input [14:0] mi_addr; // complete physical address (no shifting!)
input [31:0] mi_din;
output [31:0] mi_dout;
/*****************************/
/*CONFIG SIGNALS */
/*****************************/
//rx
output rx_enable; // enable signal for rx
output mmu_enable; // enables MMU on rx path (static)
input [8:0] gpio_datain; // frame and data inputs (static)
input [15:0] rx_status; // etx status signals
output [1:0] remap_mode; // remap mode (static)
output [31:0] remap_base; // base for dynamic remap (static)
output [11:0] remap_pattern; // patter for static remap (static)
output [11:0] remap_sel; // selects for static remap (static)
output [1:0] timer_cfg; // timeout config (00=off) (static)
/*------------------------CODE BODY---------------------------------------*/
//registers
reg [31:0] ecfg_rx_reg;
reg [31:0] ecfg_offset_reg;
reg [8:0] ecfg_gpio_reg;
reg [2:0] ecfg_rx_status_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_rx_write;
wire ecfg_base_write;
wire ecfg_remap_write;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_CFG);
assign ecfg_base_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_OFFSET);
//###########################
//# RXCFG
//###########################
always @ (posedge clk)
if(reset)
ecfg_rx_reg[31:0] <= 'b0;
else if (ecfg_rx_write)
ecfg_rx_reg[31:0] <= mi_din[31:0];
assign rx_enable = 1'b1;//is there any good reason turn RX off?
assign mmu_enable = ecfg_rx_reg[1];
assign remap_mode[1:0] = ecfg_rx_reg[3:2];
assign remap_sel[11:0] = ecfg_rx_reg[15:4];
assign remap_pattern[11:0] = ecfg_rx_reg[27:16];
assign timer_cfg[1:0] = ecfg_rx_reg[29:28];
//###########################
//# DATAIN
//###########################
always @ (posedge clk)
ecfg_gpio_reg[8:0] <= gpio_datain[8:0];
//###########################1
//# DEBUG
//###########################
always @ (posedge clk)
if(reset)
ecfg_rx_status_reg[2:0] <= 'b0;
else
ecfg_rx_status_reg[2:0] <= ecfg_rx_status_reg[2:0] | rx_status[2:0];
//###########################1
//# DYNAMIC REMAP BASE
//###########################
always @ (posedge clk)
if (ecfg_base_write)
ecfg_offset_reg[31:0] <= mi_din[31:0];
assign remap_base[31:0] = ecfg_offset_reg[31:0];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ERX_CFG: mi_dout[31:0] <= {ecfg_rx_reg[31:0]};
`ERX_GPIO: mi_dout[31:0] <= {23'b0, ecfg_gpio_reg[8:0]};
`ERX_STATUS: mi_dout[31:0] <= {16'b0, rx_status[15:3],ecfg_rx_status_reg[2:0]};
`ERX_OFFSET: mi_dout[31:0] <= {ecfg_offset_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_rx
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; void prt(long x) { cerr << x; } void prt(long long x) { cerr << x; } void prt(unsigned x) { cerr << x; } void prt(unsigned long x) { cerr << x; } void prt(unsigned long long x) { cerr << x; } void prt(float x) { cerr << x; } void prt(double x) { cerr << x; } void prt(long double x) { cerr << x; } void prt(char x) { cerr << << x << ; } void prt(const char *x) { cerr << << x << ; } void prt(const string &x) { cerr << << x << ; } void prt(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void prt(const pair<T, V> &x) { cerr << { ; prt(x.first); cerr << , ; prt(x.second); cerr << } ; } template <typename T> void prt(const T &x) { long long f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), prt(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { prt(t); if (sizeof...(v)) cerr << , ; _print(v...); } void err(istream_iterator<string> it) {} template <typename T, typename... brgs> void err(istream_iterator<string> it, T a, brgs... args) { cerr << *it << = << a << endl; err(++it, args...); } long long kadane(long long *a, long long n) { long long max_so_far = INT_MIN, max_ending_here = 0; for (__typeof(n) i = (0); i != (n); i += 1 - 2 * ((0) > (n))) { max_ending_here += a[i]; max_so_far = max(max_so_far, max_ending_here); if (max_ending_here < 0) max_ending_here = 0; } return max_so_far; } void solve() { long long n; cin >> n; double ans = 1.0 / tan(3.1415926535897932384626 / (2 * n)); cout << fixed; cout << setprecision(10) << ans << endl; return; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { solve(); } }
|
// DESCRIPTION: Example top verilog file for vpassert program
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2000-2012 by Wilson Snyder.
`timescale 1ns/1ns
module example;
pli pli (); // Put on highest level of your design
integer i;
`define ten 10
reg \escaped[10] ;
initial begin
$uinfo (0, "Welcome to a VPASSERTed file\n");
//
$uinfo (1, "Printed only at debug level %0d\n",1);
$uinfo (9, "Printed only at debug level %0d\n",9);
//
\escaped[10] = 1'b1;
$uassert (\escaped[10] , "Escaped not 1\n");
$uassert_info (\escaped[10] , "Escaped not 1\n");
//
i=0;
$uassert (1==1, "Why doesn't 1==1??\n");
$uassert (10==`ten, "Why doesn't 10==10??\n");
$uassert (/*comm
ent*/1==1,
//comment
/*com
ent*/"Why doesn't 1==1??\n"/*com
ent*/
);
//
i=3'b100; $uassert_amone(\i [2:0], "amone ok\n");
i=3'b010; $uassert_amone(i[2:0], "amone ok\n");
i=3'b001; $uassert_amone(i[2:0], "amone ok\n");
i=3'b000; $uassert_amone(i[2:0], "amone ok\n");
//i=3'b011; $uassert_amone(i[2:0], "amone error expected\n");
//i=3'b110; $uassert_amone(i[2:0], "amone error expected\n");
//
i=2'b10; $uassert_onehot(i[1:0], "onehot ok\n");
i=2'b01; $uassert_onehot(i[1:0], "onehot ok\n");
i=2'b10; $uassert_onehot(i[1],i[0], "onehot ok\n");
i=2'b10; $uassert_onehot({i[1],i[0]}, "onehot ok\n");
//i=2'b11; $uassert_onehot(i[2:0], "onehot error expected\n");
//i=2'b00; $uassert_onehot(i[2:0], "onehot error expected\n");
end
// Test assertions within case statements
initial begin
i=3'b100;
casez (i)
3'b100: ;
3'b000: $stop;
3'b010: $uerror("Why?\n");
default: $stop;
endcase
if ($time > 1000) $stop;
end
// Example of request/grant handshake
reg clk;
reg bus_req; // Request a transaction, single cycle pulse
reg bus_ack; // Acknowledged transaction, single cycle pulse
reg [31:0] bus_data;
initial begin
// Reset signals
bus_req = 1'b0;
bus_ack = 1'b0;
bus_data = 1'b0;
// Assert a request
@ (posedge clk) ;
bus_req = 1'b1;
bus_data = 32'hfeed;
// Wait for ack
@ (posedge clk) ;
bus_req = 1'b0;
// Send ack
@ (posedge clk) ;
bus_ack = 1'b1;
// Next request could be here
@ (posedge clk) ;
bus_ack = 1'b0;
end
always @ (posedge clk) begin
$uassert_req_ack (bus_req,
bus_ack /*COMMENT*/,
bus_data);
end
// Overall control loop
initial clk = 1'b0;
initial forever begin
#1;
i = i + 1;
clk = !clk;
if (i==20) $uwarn (0, "Don't know what to do next!\n");
if (i==22) $uerror (0, "Guess I'll error out!\n");
end
// Moved clock asserts
always @* begin
if (i==19) $uwarn_clk (clk,"Called at next edge (1 of 2)\n");
if (i==18) $ucover_clk (clk,"example_cover_label");
$ucover_foreach_clk(clk, "foreach_label", "27:3,1,0", (i[$ui]));
end
// Meta coverage disables
initial begin
// vp_coverage_off
if (0) begin end // cover off'ed
// vp_coverage_on
end
// Ifdef based disables
initial begin
`ifndef NEVER
`ifdef SYNTHESIS
if (1) begin end // cover on
`elsif SYNTHESIS
if (1) begin end // cover on
`else
if (1) begin end // cover off'ed
`endif
`ifndef SYNTHESIS
if (1) begin end // cover off'ed
`else
if (1) begin end // cover on
`endif
`endif
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_edb_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_edb_e.v,v 1.1 2004/04/06 10:50:54 wig Exp $
// $Date: 2004/04/06 10:50:54 $
// $Log: inst_edb_e.v,v $
// Revision 1.1 2004/04/06 10:50:54 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_edb_e
//
// No `defines in this module
module inst_edb_e
//
// Generated module inst_edb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_edb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int vis[N], parent[N]; vector<int> v[N]; void dfs(int node) { vis[node] = 1; for (auto i : v[node]) { if (!vis[i]) { parent[i] = node; dfs(i); } } } int res[N]; int main() { int n, l, r, k = 0; scanf( %d , &n); parent[n] = n; for (int i = 1; i < n; ++i) { parent[i] = i; scanf( %d %d , &l, &r); v[l].push_back(r); v[r].push_back(l); k = max(k, max((int)v[l].size(), (int)v[r].size())); } k += 1; vector<int> col(k + 1); parent[1] = 1; dfs(1); memset(vis, 0, sizeof(vis)); queue<int> q; vis[1] = true; q.push(1); res[1] = 1; col[1] = true; while (!q.empty()) { int node = q.front(); q.pop(); col[res[parent[node]]] = true; col[res[node]] = true; int j = 1, x = (int)col.size(); for (auto i : v[node]) { if (!vis[i]) { q.push(i); while (j < x and col[j] == true) ++j; res[i] = j; col[j] = true; vis[i] = 1; } } for (auto i : v[node]) col[res[i]] = false; col[res[node]] = false; } printf( %d n , k); for (int i = 1; i <= n; ++i) printf( %d , res[i]); return 0; }
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