text
stringlengths 59
71.4k
|
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
`define SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000000 + 9; long long pow(long long a, int n, long long mod) { long long res = 1; while (n) { if (n % 2) { res *= a; res %= mod; --n; } else { a *= a; a %= mod; n /= 2; } } return res; } inline long long dec(long long a, long long b) { return ((a - b) % mod + mod) % mod; } int main() { int n, m; cin >> n >> m; if (m < 26 && n > pow(2, m, mod) - 1) { cout << 0; return 0; } long long ans = dec(pow(2, m, mod), 1); int i; for (i = 1; i < n; ++i) { ans *= dec(pow(2, m, mod), i + 1); ans %= mod; } cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__XOR3_BEHAVIORAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; inline int read() { int f = 1, r = 0; char ch = getchar(); while (!isdigit(ch)) f ^= ch == - , ch = getchar(); while (isdigit(ch)) r = (r << 1) + (r << 3) + (ch ^ 48), ch = getchar(); return f ? r : -r; } const int N = 3005, M = 305; int n, m, cnt[N]; double f[M][N], g[N], d[N], sv[N], siv[N], val[N]; double ans, p[N][M]; inline void upd(int x) { memcpy(g, f[x], sizeof(g)); f[x][0] = 0; for (int i = 1; i <= n; i++) f[x][i] = f[x][i - 1] * (1 - p[i][x]) + g[i - 1] * p[i][x]; cnt[x]++, sv[x] += f[x][n]; siv[x] += f[x][n] * cnt[x]; double E = siv[x] + cnt[x] * (1 - sv[x]); d[x] = E - val[x], val[x] = E; } int main() { n = read(), m = read(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) p[i][j] = read() / 1000.; for (int i = 1; i <= m; i++) { f[i][0] = 1; for (int j = 1; j <= n; j++) f[i][j] = f[i][j - 1] * (1 - p[j][i]); sv[i] = f[i][n], upd(i); } for (int i = 1; i <= n; i++) { int k = 0; for (int j = 1; j <= m; j++) if (d[k] < d[j]) k = j; if (!k) break; ans += d[k], upd(k); } return printf( %.12lf n , ans), 0; }
|
`timescale 1ns / 1ps
/*
* Copyright 2015 Forest Crossman
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
module pwm_demo(
input CLK_100MHz,
input [2:0] ADDRESS,
input [7:0] DATA,
input SW1,
output [7:0] PWM,
output reg [7:0] LED
);
wire [2:0] address;
wire [7:0] data;
wire latch;
assign address = ADDRESS;
assign data = DATA;
assign latch = ~SW1;
reg [7:0] period [0:256-1];
pwm_generator pwm0(.clk(CLK_100MHz), .period(period[0]), .pin(PWM[0]));
pwm_generator pwm1(.clk(CLK_100MHz), .period(period[1]), .pin(PWM[1]));
pwm_generator pwm2(.clk(CLK_100MHz), .period(period[2]), .pin(PWM[2]));
pwm_generator pwm3(.clk(CLK_100MHz), .period(period[3]), .pin(PWM[3]));
pwm_generator pwm4(.clk(CLK_100MHz), .period(period[4]), .pin(PWM[4]));
pwm_generator pwm5(.clk(CLK_100MHz), .period(period[5]), .pin(PWM[5]));
pwm_generator pwm6(.clk(CLK_100MHz), .period(period[6]), .pin(PWM[6]));
pwm_generator pwm7(.clk(CLK_100MHz), .period(period[7]), .pin(PWM[7]));
always @(posedge CLK_100MHz) begin
if (latch) begin
LED <= address;
period[address] <= data;
end
end
endmodule
module pwm_generator(
input clk,
input [7:0] period,
output pin
);
reg [7:0] counter;
reg pin_out;
assign pin = pin_out;
always @(posedge clk) begin
if (counter < period)
counter <= counter + 1;
else begin
counter <= 0;
case (pin)
1'b0: pin_out <= 1;
1'b1: pin_out <= 0;
default: pin_out <= 0;
endcase
end
end
endmodule
|
//==================================================================================================
// Filename : subRecursiveKOA.v
// Created On : 2016-10-27 23:29:14
// Last Modified : 2016-10-28 00:15:22
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module subRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 8)
(
input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] Data_S_o
);
localparam integer STOP_CONT = `STOP_CONT;
generate
//assign i = Stop_I;
if (SW <= STOP_CONT) begin : GENSTOP
mult #(.SW(SW))
inst_mult (
.clk(clk),
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
end else begin : RECURSIVE
reg [2*SW-1:0] sgf_result_o;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
localparam half = SW/2;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
always @* begin : EVEN11
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
assign Data_S_o = sgf_result_o;
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
always @* begin : ODD11
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
assign Data_S_o = sgf_result_o;
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW((SW/2)+1)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW((SW/2)+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
end
endcase
end
endgenerate
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (win64) Build Wed Nov 18 09:43:45 MST 2015
// Date : Fri Mar 04 11:10:30 2016
// Host : Dries007Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_stub.v
// Design : clk_wiz_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_1(clk_in1, clk_out1)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1" */;
input clk_in1;
output clk_out1;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:26:59 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb888_to_rgb565_0_0 -prefix
// system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_stub.v
// Design : system_rgb888_to_rgb565_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_rgb565,Vivado 2016.4" *)
module system_rgb888_to_rgb565_0_0(rgb_888, rgb_565)
/* synthesis syn_black_box black_box_pad_pin="rgb_888[23:0],rgb_565[15:0]" */;
input [23:0]rgb_888;
output [15:0]rgb_565;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) scanf( %d , &a[i]); string s; cin >> s; int c1[n], c2[n]; c2[0] = a[0]; if (s[0] == 1 ) c1[0] = a[0]; else c1[0] = 0; for (int i = 1; i < n; i++) { c1[i] = c1[i - 1]; c2[i] = c2[i - 1] + a[i]; if (s[i] == 1 ) { c1[i] += a[i]; } } int last, ans = c1[n - 1]; for (int i = n - 1; i >= 0; i--) { if (s[i] == 1 ) { last = i; break; } } for (int i = 1; i <= last; i++) { if (s[i] == 1 ) { ans = max(ans, c2[i - 1] + c1[n - 1] - c1[i]); } } printf( %d , ans); }
|
// megafunction wizard: %altdll%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTDLL
// ============================================================
// File Name: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy.v
// Megafunction Name(s):
// ALTDLL
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 208 07/03/2011 SP 1.10 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altdll CBX_AUTO_BLACKBOX="ALL" DELAY_BUFFER_MODE="high" DELAY_CHAIN_LENGTH=8 DELAYCTRLOUT_WIDTH=6 device_family="Stratix IV" DLL_OFFSET_CTRL_A_STATIC_OFFSET="0" DLL_OFFSET_CTRL_A_USE_OFFSET="false" DLL_OFFSET_CTRL_B_STATIC_OFFSET="0" DLL_OFFSET_CTRL_B_USE_OFFSET="false" INPUT_FREQUENCY="1876" JITTER_REDUCTION="true" USE_DLL_OFFSET_CTRL_A="false" USE_DLL_OFFSET_CTRL_B="false" dll_clk dll_delayctrlout
//VERSION_BEGIN 11.0SP1 cbx_altdll 2011:07:03:21:10:32:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = stratixiv_dll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy_altdll_5s51
(
dll_clk,
dll_delayctrlout) ;
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] wire_dll_wys_m_delayctrlout;
stratixiv_dll dll_wys_m
(
.clk(dll_clk),
.delayctrlout(wire_dll_wys_m_delayctrlout),
.dqsupdate(),
.offsetdelayctrlclkout(),
.offsetdelayctrlout(),
.upndnout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aload(1'b0),
.upndnin(1'b1),
.upndninclkena(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b0)
// synopsys translate_on
);
defparam
dll_wys_m.delay_buffer_mode = "high",
dll_wys_m.delay_chain_length = 8,
dll_wys_m.input_frequency = "1876 ps",
dll_wys_m.jitter_reduction = "true",
dll_wys_m.static_delay_ctrl = 8,
dll_wys_m.lpm_type = "stratixiv_dll";
assign
dll_delayctrlout = wire_dll_wys_m_delayctrlout;
endmodule //ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy_altdll_5s51
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy (
dll_clk,
dll_delayctrlout);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] sub_wire0;
wire [5:0] dll_delayctrlout = sub_wire0[5:0];
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy_altdll_5s51 ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy_altdll_5s51_component (
.dll_clk (dll_clk),
.dll_delayctrlout (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: FREQUENCY_UNIT_MODE STRING "MHz"
// Retrieval info: PRIVATE: INPUT_FREQUENCY_PRIVATE_ID NUMERIC "300"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: DELAYCTRLOUT_WIDTH NUMERIC "6"
// Retrieval info: CONSTANT: DELAY_BUFFER_MODE STRING "HIGH"
// Retrieval info: CONSTANT: DELAY_CHAIN_LENGTH NUMERIC "8"
// Retrieval info: CONSTANT: DLL_OFFSET_CTRL_A_STATIC_OFFSET NUMERIC "0"
// Retrieval info: CONSTANT: DLL_OFFSET_CTRL_A_USE_OFFSET STRING "false"
// Retrieval info: CONSTANT: DLL_OFFSET_CTRL_B_STATIC_OFFSET NUMERIC "0"
// Retrieval info: CONSTANT: DLL_OFFSET_CTRL_B_USE_OFFSET STRING "false"
// Retrieval info: CONSTANT: INPUT_FREQUENCY NUMERIC "1876"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: JITTER_REDUCTION STRING "true"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altdll"
// Retrieval info: CONSTANT: USE_DLL_OFFSET_CTRL_A STRING "false"
// Retrieval info: CONSTANT: USE_DLL_OFFSET_CTRL_B STRING "false"
// Retrieval info: USED_PORT: dll_clk 0 0 1 0 INPUT NODEFVAL "dll_clk[0..0]"
// Retrieval info: CONNECT: @dll_clk 0 0 1 0 dll_clk 0 0 1 0
// Retrieval info: USED_PORT: dll_delayctrlout 0 0 6 0 OUTPUT NODEFVAL "dll_delayctrlout[5..0]"
// Retrieval info: CONNECT: dll_delayctrlout 0 0 6 0 @dll_delayctrlout 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy.cmp TRUE TRUE
|
#include <bits/stdc++.h> using namespace std; const int N = int(2e6); int n; bool used[N + 7]; int main() { cin >> n; for (int i = 2; i * i <= N; ++i) { if (!used[i]) { for (int z = i * i; z <= N; z = z + i) used[z] = true; } } int cnt = 0; for (int i = 2; i <= N; ++i) if (!used[i]) { printf( %d , i); ++cnt; if (cnt == n) return 0; } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file car.v when simulating
// the core, car. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module car(
clka,
addra,
douta
);
input clka;
input [12 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("car.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(6000),
.C_READ_DEPTH_B(6000),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(6000),
.C_WRITE_DEPTH_B(6000),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : sys_clk_gen.v
// Version : 1.7
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module sys_clk_gen (sys_clk);
output sys_clk;
reg sys_clk;
parameter offset = 0;
parameter halfcycle = 500;
initial begin
sys_clk = 0;
#(offset);
forever #(halfcycle) sys_clk = ~sys_clk;
end
endmodule // sys_clk_gen
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=25 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=ADC_PLL" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="UART_ADC_PLL_sclk_0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module ADC_PLL_altpll
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll1_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 25,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = (wire_pll1_locked & pll_lock_sync);
endmodule //ADC_PLL_altpll
//VALID FILE
|
module wiggle (osc, rstn, led, gpio, perstn, refclkp, refclkn, hdinp0, hdinn0, hdoutp0, hdoutn0);
input osc, rstn;
output [7:0] led;
output [23:0] gpio;
input perstn, refclkp, refclkn, hdinp0, hdinn0;
output hdoutp0, hdoutn0;
reg [23:0] count;
reg [7:0] sreg;
reg shift;
wire rstn;
wire clk;
wire [7:0] led;
wire [23:0] gpio;
assign rst = ~rstn;
assign clk = osc;
always @(posedge clk or posedge rst)
begin
if (rst)
count <= 0;
else
count <= count + 1;
end
always @(posedge clk or posedge rst)
begin
if (rst)
shift <= 0;
else if (count == 3)
shift <= 1;
else
shift <= 0;
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
sreg <= 8'b1111_1110;
end else if (shift == 1) begin
sreg <= sreg << 1;
sreg[0] <= sreg[7];
// end else begin
// sreg <= sreg;
end
end
assign led = sreg;
assign gpio = count;
claritycores _inst (
// Physcial Pins
.refclk_refclkp(refclkp),
.refclk_refclkn(refclkn),
.pcie_x1_hdinp0(hdinp0),
.pcie_x1_hdinn0(hdinn0),
.pcie_x1_hdoutp0(hdoutp0),
.pcie_x1_hdoutn0(hdoutn0),
.pcie_x1_rst_n(perstn),
.pcie_x1_sys_clk_125(),
// Transmit TLP Interface
.pcie_x1_tx_data_vc0(16'd0),
.pcie_x1_tx_req_vc0(1'b0),
.pcie_x1_tx_rdy_vc0(),
.pcie_x1_tx_st_vc0(1'b0),
.pcie_x1_tx_end_vc0(1'b0),
.pcie_x1_tx_nlfy_vc0(1'b0),
.pcie_x1_tx_ca_ph_vc0(),
.pcie_x1_tx_ca_nph_vc0(),
.pcie_x1_tx_ca_cplh_vc0(),
.pcie_x1_tx_ca_pd_vc0(),
.pcie_x1_tx_ca_npd_vc0(),
.pcie_x1_tx_ca_cpld_vc0(),
.pcie_x1_tx_ca_p_recheck_vc0(),
.pcie_x1_tx_ca_cpl_recheck_vc0(),
// Receive TLP Interface
.pcie_x1_rx_data_vc0(),
.pcie_x1_rx_st_vc0(),
.pcie_x1_rx_end_vc0(),
.pcie_x1_rx_us_req_vc0(),
.pcie_x1_rx_malf_tlp_vc0(),
.pcie_x1_rx_bar_hit( ),
.pcie_x1_ur_np_ext(1'b0),
.pcie_x1_ur_p_ext(1'b0),
.pcie_x1_ph_buf_status_vc0(1'b0),
.pcie_x1_pd_buf_status_vc0(1'b0),
.pcie_x1_nph_buf_status_vc0(1'b0),
.pcie_x1_npd_buf_status_vc0(1'b0),
.pcie_x1_ph_processed_vc0(1'b0),
.pcie_x1_nph_processed_vc0(1'b0),
.pcie_x1_pd_processed_vc0(1'b0),
.pcie_x1_npd_processed_vc0(1'b0),
.pcie_x1_pd_num_vc0(1'b0),
.pcie_x1_npd_num_vc0(1'b0),
// Control and Status
.pcie_x1_no_pcie_train(1'b0),
.pcie_x1_force_lsm_active(1'b0),
.pcie_x1_force_rec_ei(1'b0),
.pcie_x1_force_phy_status(1'b0),
.pcie_x1_force_disable_scr(1'b0),
.pcie_x1_hl_snd_beacon(1'b0),
.pcie_x1_hl_disable_scr(1'b0),
.pcie_x1_hl_gto_dis(1'b0),
.pcie_x1_hl_gto_det(1'b0),
.pcie_x1_hl_gto_hrst(1'b0),
.pcie_x1_hl_gto_l0stx(1'b0),
.pcie_x1_hl_gto_l0stxfts(1'b0),
.pcie_x1_hl_gto_l1(1'b0),
.pcie_x1_hl_gto_l2(1'b0),
.pcie_x1_hl_gto_lbk(4'd0),
.pcie_x1_hl_gto_rcvry(1'b0),
.pcie_x1_hl_gto_cfg(1'b0),
.pcie_x1_phy_ltssm_state(),
.pcie_x1_phy_pol_compliance(),
.pcie_x1_tx_lbk_rdy(),
.pcie_x1_tx_lbk_kcntl(2'd0),
.pcie_x1_tx_lbk_data(16'd0),
.pcie_x1_rx_lbk_kcntl(),
.pcie_x1_rx_lbk_data(),
.pcie_x1_flip_lanes(1'b0),
// Data Link Layer
.pcie_x1_dl_inactive( ),
.pcie_x1_dl_init( ),
.pcie_x1_dl_active( ),
.pcie_x1_dl_up(),
.pcie_x1_tx_dllp_val(2'd0),
.pcie_x1_tx_pmtype(3'd0),
.pcie_x1_tx_vsd_data(24'd0),
.pcie_x1_tx_dllp_sent(),
.pcie_x1_rxdp_pmd_type(),
.pcie_x1_rxdp_vsd_data(),
.pcie_x1_rxdp_dllp_val(),
// Transaction Layer
.pcie_x1_cmpln_tout(),
.pcie_x1_cmpltr_abort_np(),
.pcie_x1_cmpltr_abort_p(1'd0),
.pcie_x1_unexp_cmpln(1'd0),
.pcie_x1_np_req_pend(1'd0),
// Configuration Registers
.pcie_x1_bus_num( ),
.pcie_x1_dev_num( ),
.pcie_x1_func_num( ),
.pcie_x1_cmd_reg_out( ),
.pcie_x1_dev_cntl_out( ),
.pcie_x1_lnk_cntl_out( ),
.pcie_x1_inta_n(1'b1),
.pcie_x1_msi(8'd0),
.pcie_x1_mm_enable( ),
.pcie_x1_msi_enable( ),
.pcie_x1_pme_status(1'b0),
.pcie_x1_pme_en(),
.pcie_x1_pm_power_state( ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200100; int main() { int n = 0, u = 0, v = 0; int d[MAXN] = {0}; scanf( %d , &n); for (int i = 0; i < n - 1; i++) { scanf( %d %d , &u, &v); d[u] += 1; d[v] += 1; } for (int i = 1; i <= n; i++) { if (d[i] == 2) { printf( NO n ); return 0; } } printf( YES n ); return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( avx ) #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) using namespace std; int dx[4] = {1, 0, -1, 0}; int dy[4] = {0, 1, 0, -1}; int main() { long long A, B, C, D, E, F, N, K, M, Z, sum = 0, num = 0, flag = 0; string S, T; cin >> Z; queue<long long> que; while (Z--) { cin >> S; vector<long long> P(0, 0); num = 0; S += 0 ; for (long long int i = 0; i < S.size(); i++) { if (S[i] == 1 ) num++; else { P.push_back(num); num = 0; } } sort(P.begin(), P.end()); reverse(P.begin(), P.end()); sum = 0; for (long long int i = 0; i < P.size(); i++) { sum += P[i]; i++; } que.push(sum); } while (!que.empty()) { cout << que.front() << endl; que.pop(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n; cin >> m; cin >> k; bool done = false; int num = 0; int lanes = 0; int desks = 0; int d = 0; while (num < k) { desks = 0; done = false; num += 2 * m; lanes++; while (done == false) { if (d >= num || d >= k) { done = true; break; } d += 2; desks++; } } cout << lanes << << desks << ; if (k % 2 == 0) { cout << R << endl; } else cout << L << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) const int N = 2e5 + 3; const int MOD = 998244353; int max1 = 0, max2 = 0; void solve() { long long int a[3]; cin >> a[0] >> a[1] >> a[2]; sort(a, a + 3); cout << (a[0] + a[1] + min(a[2], 2 * (a[1] + a[0]))) / 3 << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } }
|
//**************************************************************************
// ph_reg3.v - 2 byte FIFO for 16b transfers in parasite to host direction
//
// COPYRIGHT 2019 David Banks, Richard Evans, Ed Spittles
//
// This file is part of tube - an Acorn Tube ULA compatible system.
//
// tube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// tube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with tube. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
`timescale 1ns / 1ns
module bin_gray_counter #
(
parameter N = 0, // Width of counters
parameter INIT = 0 // Initial value of binary counter
)
(
input clk,
input rst,
input inc,
output reg [N-1:0] binary,
output reg [N-1:0] gray
);
wire [N-1:0] next_binary = binary + 1'b1;
wire [N-1:0] next_gray = next_binary ^ (next_binary >> 1);
always @(posedge clk or posedge rst) begin
if (rst) begin
binary <= INIT;
gray <= INIT ^ (INIT >> 1);
end else if (inc) begin
binary <= next_binary;
gray <= next_gray;
end
end
endmodule
module async_fifo #
(
parameter D_WIDTH = 0, // FIFO data width
parameter A_WIDTH = 0, // Log(2) of the FIFO depth
parameter INIT_WADDR = 0, // Inital write address
parameter INIT_RADDR = 0 // Initial read addrtess
)
(
input rst, // asynchrous reset
input wr_clk, // write clock
input wr_en, // write enable
input [7:0] wr_data, // write data
input rd_clk, // read clock
input rd_en, // read enable
output [7:0] rd_data, // read data (value at the HEAD of the FIFO)
output rd_empty, // empty flag, synchronised to the read domain
output rd_full, // full flag, synchronised to the read domain
output wr_empty, // empty flag, synchronised to the write domain
output wr_full // full flag, synchronised to the write domain
);
// The read and write addresses are N+1 bits (where 2^N is the FIFO size)
// The purpose of the additional bit is to distingish the full/empty cases
// Write address
wire [A_WIDTH:0] waddr; // binary encoded
wire [A_WIDTH:0] waddr_g; // gray coded
reg [A_WIDTH:0] waddr_g1; // gray coded, part synchronised to read domain
reg [A_WIDTH:0] waddr_g2; // gray coded, fully synchronised to read domain
// Read address
wire [A_WIDTH:0] raddr; // binary encoded
wire [A_WIDTH:0] raddr_g; // gray coded
reg [A_WIDTH:0] raddr_g1; // gray coded, part synchronised to write domain
reg [A_WIDTH:0] raddr_g2; // gray coded, fully synchronised to write domain
// FIFO Data RAM
reg [D_WIDTH-1:0] data[0:2^A_WIDTH-1];
// Counter blocks for write address
// - binary-coded output used for RAM write address
// - gray-coded output used for flag logic
bin_gray_counter #
(
.N(A_WIDTH+1),
.INIT(INIT_WADDR)
)
waddr_counter
(
.clk(wr_clk),
.rst(rst),
.inc(wr_en && !wr_full),
.binary(waddr),
.gray(waddr_g)
);
// Counter blocks for read address
// - binary-coded output used for RAM read address
// - gray-coded output used for flag logic
bin_gray_counter #
(
.N(A_WIDTH+1),
.INIT(INIT_RADDR)
)
addr_counter
(
.clk(rd_clk),
.rst(rst),
.inc(rd_en && !rd_empty),
.binary(raddr),
.gray(raddr_g)
);
// Synchronise the gray-coded read address to the write clock domain
always @(posedge wr_clk) begin
raddr_g1 <= raddr_g;
raddr_g2 <= raddr_g1;
end
// Synchronise the gray-coded write address to the read clock domain
always @(posedge rd_clk) begin
waddr_g1 <= waddr_g;
waddr_g2 <= waddr_g1;
end
// Write logic
always @(posedge wr_clk) begin
if (wr_en && !wr_full) begin
data[waddr[A_WIDTH-1:0]] <= wr_data;
end
end
// Read logic
assign rd_data = data[raddr[A_WIDTH-1:0]];
// Full/Empty flags are generated from the gray coded addresses.
//
// The wr_ prefixed versions are valid in the write clock domain.
// The rd_ prefixed versions are valid in the read clock domain.
//
// The addresses contain one extra bit to distinguish the full and empty cases.
//
// If the pointers match exacty, then the FIFO is empty.
//
// If they match, apart from the MS two bits, then the FIFO is full. I've
// not seem this formulation used before. But by inspection it seems to be
// correct. Caveat Emptor!
assign wr_empty = (waddr_g ^ raddr_g2) == 0;
assign rd_empty = (raddr_g ^ waddr_g2) == 0;
assign wr_full = (waddr_g ^ raddr_g2) == 3 << (A_WIDTH-1);
assign rd_full = (raddr_g ^ waddr_g2) == 3 << (A_WIDTH-1);
endmodule
module ph_reg3
(
input h_rst_b,
input h_rd,
input h_selectData,
input h_phi2,
input [7:0] p_data,
input p_selectData,
input p_phi2,
input p_rdnw,
input one_byte_mode,
output [7:0] h_data,
output h_data_available,
output p_empty,
output p_full
);
// Internal flags
wire rd_empty; // empty flag, synchronised to the read domain
wire rd_full; // full flag, synchronised to the read domain
wire wr_empty; // empty flag, synchronised to the write domain
wire wr_full; // full flag, synchronised to the write domain
async_fifo #
(
.D_WIDTH(8),
.A_WIDTH(1),
.INIT_WADDR(1),
.INIT_RADDR(0)
)
ph_reg3_fifo
(
.rst(!h_rst_b),
.wr_clk(p_phi2),
.wr_en(p_selectData && !p_rdnw),
.wr_data(p_data),
.rd_clk(!h_phi2),
.rd_en(h_selectData && h_rd),
.rd_data(h_data),
.rd_empty(rd_empty),
.rd_full(rd_full),
.wr_empty(wr_empty),
.wr_full(wr_full)
);
// Register 3 is intended to enable high speed transfers of large blocks of data across the tube.
// It can operate in one or two byte mode, depending on the V flag. In one byte mode the status
// bits make each FIFO appear to be a single byte latch - after one byte is written the register
// appears to be full. In two byte mode the data available flag will only be asserted when two bytes have
// been entered, and the not full flag will only be asserted when both bytes have been removed. Thus data
// available going active means that two bytes are available, but it will remain active until both bytes
// have been removed. Not full going active means that the register is empty, but it will remain active
// until both bytes have been entered. PNMI, N and DRQ also remain active until the full two
// byte operation is completed
assign p_empty = wr_empty;
assign p_full = one_byte_mode ? wr_full : !wr_empty;
assign h_data_available = one_byte_mode ? !rd_empty : rd_full;
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, dp[100005][3], MOD = 1000000007; char s[2][100005]; long long ans = 1; int main() { scanf( %d%s%s , &N, s[0], s[1]); for (int i = 0; i < N; ++i) { if (s[0][i] == ? ) ans = (((ans * 10) % (MOD) + (MOD)) % (MOD)); if (s[1][i] == ? ) ans = (((ans * 10) % (MOD) + (MOD)) % (MOD)); for (int x = 0; x < 10; ++x) { for (int y = 0; y < 10; ++y) { if ((s[0][i] == ? || s[0][i] == x + 0 ) && (s[1][i] == ? || s[1][i] == y + 0 )) { if (x >= y) { dp[i][0] = (((dp[i][0] + (i ? dp[i - 1][0] : 1)) % (MOD) + (MOD)) % (MOD)); } if (x <= y) { dp[i][1] = (((dp[i][1] + (i ? dp[i - 1][1] : 1)) % (MOD) + (MOD)) % (MOD)); } if (x == y) { dp[i][2] = (((dp[i][2] + (i ? dp[i - 1][2] : 1)) % (MOD) + (MOD)) % (MOD)); } } } } } if (N == 1) puts( 0 ); else printf( %d n , (((ans - dp[N - 1][0] - dp[N - 1][1] + dp[N - 1][2]) % (MOD) + (MOD)) % (MOD))); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long I1 = 1e9; const long long I2 = 1e18; const int32_t M1 = 1e9 + 7; const int32_t M2 = 998244353; template <typename T, typename T1> T maxn(T &a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T minn(T &a, T1 b) { if (b < a) a = b; return a; } void solve() { long long int n; cin >> n; if (n == 1) { cout << 0 << n ; return; } long long int l = 1, r = n - 1, m1, m2, ans = 0; while (l <= r) { m1 = l + (r - l) / 3, m2 = r - (r - l) / 3; long long int c1, c2; c1 = min(2 * m1, m1 + ((n - m1) * (n - m1 - 1)) / 2); c2 = min(2 * m2, m2 + ((n - m2) * (n - m2 - 1)) / 2); ans = max({ans, c1, c2}); if (c1 > c2) r = m2 - 1; else if (c2 > c1) l = m1 + 1; else { l = m1 + 1, r = m2 - 1; } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int testcase = 1; cin >> testcase; while (testcase--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int T; priority_queue<int, vector<int>, greater<int> > q; vector<int> g[1000005]; int main() { scanf( %d , &T); int n; long long int ans; while (T--) { ans = 0; scanf( %d , &n); int x, y; for (int i = 1; i <= n; i++) { scanf( %d %d , &x, &y); g[x].push_back(y); } for (int i = n - 1; i >= 0; i--) { int sz = g[i].size(); for (int j = 0; j < sz; j++) q.push(g[i][j]); while (q.size() > n - i) { ans += q.top(), q.pop(); } } printf( %lld n , ans); for (int i = 0; i < n; ++i) { g[i].clear(); while (!q.empty()) q.pop(); } } return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_pcie_bram_7x.v
// Version : 1.11
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcieCore_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" :
((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__AND3_BEHAVIORAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (a > b) { a = b; return 1; } return 0; } template <class T> ostream &operator<<(ostream &os, const vector<T> &t) { os << [ ; for (__typeof((t).begin()) it = (t).begin(); it != (t).end(); it++) { if (it != t.begin()) os << , ; os << *it; } os << ] ; return os; } template <class T> ostream &operator<<(ostream &os, const set<T> &t) { os << { ; for (__typeof((t).begin()) it = (t).begin(); it != (t).end(); it++) { if (it != t.begin()) os << , ; os << *it; } os << } ; return os; } template <class S, class T> ostream &operator<<(ostream &os, const pair<S, T> &t) { return os << ( << t.first << , << t.second << ) ; } const int INF = 1 << 28; const double EPS = 1e-8; const int MOD = 1000000007; long long int t, a, b; long double x[2][60]; long long int dfs(int co, long long int re1, long long int re2) { if (co == 1) { if (t == a || (re1 - re2) % (t - a)) return 0; long long int i = (re1 - re2) / (t - a); return !(re1 - i * t < 0 || re2 - i * a < 0 || i < 0); } long long int ans = 0; while (re1 >= 0 && re2 >= 0) { ans += dfs(co - 1, re1, re2); re1 -= x[0][co]; re2 -= x[1][co]; } return ans; } int main() { cin >> t >> a >> b; if (t == 1 && a == 1 && b == 1) { puts( inf ); return 0; } if (t == a && a == b) { puts( 2 ); return 0; } if (t == a) { puts( 0 ); return 0; } for (long long int i = 0; i < (long long int)(60); i++) { x[0][i] = powl(t, i); x[1][i] = powl(a, i); } cout << dfs(59, a, b) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> A[7], B[100005]; int n, a[5005], f[5005][5005], ans; int main() { int i, j, u, v, w, p, q, r; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = n; i >= 1; i--) { A[a[i] % 7].push_back(i); B[a[i]].push_back(i); } ans = 2; for (i = 1; i <= n; i++) { A[a[i] % 7].pop_back(); B[a[i]].pop_back(); u = A[a[i] % 7].size() ? A[a[i] % 7][A[a[i] % 7].size() - 1] : 0; v = B[a[i] - 1].size() ? B[a[i] - 1][B[a[i] - 1].size() - 1] : 0; w = B[a[i] + 1].size() ? B[a[i] + 1][B[a[i] + 1].size() - 1] : 0; for (j = 0; j < i; j++) { f[i][j] = max(f[i][j], f[j][0] + 1); ans = max(ans, f[i][j]); if (u) f[u][j] = max(f[u][j], f[i][j] + 1); if (v) f[v][j] = max(f[v][j], f[i][j] + 1); if (w) f[w][j] = max(f[w][j], f[i][j] + 1); if (!j) continue; p = A[a[j] % 7].size() ? A[a[j] % 7][A[a[j] % 7].size() - 1] : 0; q = B[a[j] - 1].size() ? B[a[j] - 1][B[a[j] - 1].size() - 1] : 0; r = B[a[j] + 1].size() ? B[a[j] + 1][B[a[j] + 1].size() - 1] : 0; if (p) f[p][i] = max(f[p][i], f[i][j] + 1); if (q) f[q][i] = max(f[q][i], f[i][j] + 1); if (r) f[r][i] = max(f[r][i], f[i][j] + 1); } } cout << ans; return 0; }
|
#include <bits/stdc++.h> double ans, f[10][1000]; int n, k, a, v[10], p[10], g[10], ki[10], l[10]; void calc() { int b = a; for (int i = 1; i <= n; ++i) { l[i] = p[i] + g[i]; if (l[i] > 100) l[i] = 100; } f[0][0] = 1; for (int i = 1; i <= n; ++i) for (int j = 0; j <= (1 << i - 1) - 1; ++j) { f[i][j] = f[i - 1][j] * (100 - l[i]) / 100; f[i][j + (1 << i - 1)] = f[i - 1][j] * l[i] / 100; } double res = 0; for (int i = 0; i <= (1 << n) - 1; ++i) { int tot = 0, b = a; for (int j = 1; j <= n; ++j) if (i & (1 << j - 1)) ++tot; else b += v[j]; if (tot * 2 > n) res += f[n][i]; else res += f[n][i] * a / b; } if (res > ans) ans = res; } void dfs(int now, int left) { if (now == n + 1) { calc(); return; } if (left == 0) dfs(now + 1, 0); else { for (int i = 0; i <= left; ++i) { if (p[now] + i * 10 >= 110) break; g[now] = i * 10; dfs(now + 1, left - i); g[now] = 0; } } } int main() { scanf( %d%d%d , &n, &k, &a); for (int i = 1; i <= n; ++i) scanf( %d%d , &v[i], &p[i]); dfs(1, k); printf( %.6lf n , ans); return 0; }
|
/*
File: ewrapper_io_rx_slow.v
This file is part of the Parallella Project .
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_io_rx_slow (/*AUTOARG*/
// Outputs
CLK_DIV_OUT, DATA_IN_TO_DEVICE,
// Inputs
CLK_IN_P, CLK_IN_N, CLK_RESET, IO_RESET, DATA_IN_FROM_PINS_P,
DATA_IN_FROM_PINS_N, BITSLIP
);
//###########
//# INPUTS
//###########
input CLK_IN_P; // Differential clock from IOB
input CLK_IN_N;
input CLK_RESET;
input IO_RESET;
input [8:0] DATA_IN_FROM_PINS_P;
input [8:0] DATA_IN_FROM_PINS_N;
input BITSLIP;
//#############
//# OUTPUTS
//#############
output CLK_DIV_OUT; // Slow clock output
output [71:0] DATA_IN_TO_DEVICE;
//############
//# REGS
//############
reg [3:0] clk_edge;
reg rx_pedge_first;
reg [8:0] clk_even_reg;
reg [8:0] clk_odd_reg;
reg [8:0] clk0_even;
reg [8:0] clk1_even;
reg [8:0] clk2_even;
reg [8:0] clk3_even;
reg [8:0] clk0_odd;
reg [8:0] clk1_odd;
reg [8:0] clk2_odd;
reg [8:0] clk3_odd;
reg [71:0] rx_out_sync_pos;
reg rx_outclock_del_45;
reg rx_outclock_del_135;
reg [71:0] rx_out;
//############
//# WIRES
//############
wire reset;
wire rx_outclock;
wire rxi_lclk;
wire [71:0] rx_out_int;
wire [8:0] rx_in_t;
wire [8:0] rx_in;
wire [8:0] clk_even;
wire [8:0] clk_odd;
wire [8:0] iddr_q1;
wire [8:0] iddr_q2;
// Inversions for E16/E64 migration
`ifdef TARGET_E16
assign rx_in = rx_in_t;
assign clk_even = iddr_q1;
assign clk_odd = iddr_q2;
`define CLKEDGE_DDR "SAME_EDGE_PIPELINED"
`elsif TARGET_E64
assign rx_in = ~rx_in_t;
assign clk_even = iddr_q2;
assign clk_odd = iddr_q1;
`define CLKEDGE_DDR "SAME_EDGE"
`endif
/*AUTOINPUT*/
/*AUTOWIRE*/
assign reset = IO_RESET;
assign DATA_IN_TO_DEVICE[71:0] = rx_out[71:0];
assign CLK_DIV_OUT = rx_outclock;
//################################
//# Input Buffers Instantiation
//################################
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (`IOSTD_ELINK))
ibufds_inst[0:8]
(.I (DATA_IN_FROM_PINS_P),
.IB (DATA_IN_FROM_PINS_N),
.O (rx_in_t));
//#####################
//# Clock Buffers
//#####################
IBUFGDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (`IOSTD_ELINK))
ibufds_clk_inst
(.I (CLK_IN_P),
.IB (CLK_IN_N),
.O (rxi_lclk));
// BUFR generates the slow clock
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("4"))
clkout_buf_inst
(.O (rx_outclock),
.CE(1'b1),
.CLR(CLK_RESET),
.I (rxi_lclk));
//#################################
//# De-serialization Cycle Counter
//#################################
always @ (posedge rxi_lclk) begin
if(rx_pedge_first)
clk_edge <= 4'b1000;
else
clk_edge <= {clk_edge[2:0], clk_edge[3]};
end
//################################################################
//# Posedge Detection of the Slow Clock in the Fast Clock Domain
//################################################################
always @ (negedge rxi_lclk) begin
rx_outclock_del_45 <= rx_outclock;
rx_outclock_del_135 <= rx_outclock_del_45;
rx_pedge_first <= ~rx_outclock_del_45 & ~rx_outclock_del_135;
end
//#############################
//# De-serialization Output
//#############################
// Synchronizing the clocks (fast to slow)
always @ (posedge rxi_lclk or posedge reset)
if(reset)
rx_out_sync_pos <= 72'd0;
else
rx_out_sync_pos <= rx_out_int;
always @ (posedge rx_outclock or posedge reset)
if(reset)
rx_out <= 72'd0;
else
rx_out <= rx_out_sync_pos;
//#############################
//# IDDR instantiation
//#############################
IDDR #(
.DDR_CLK_EDGE (`CLKEDGE_DDR),
.SRTYPE ("ASYNC"))
iddr_inst[0:8] (
.Q1 (iddr_q1),
.Q2 (iddr_q2),
.C (rxi_lclk),
.CE (1'b1),
.D (rx_in),
.R (1'b0),
.S (1'b0));
//#############################
//# De-serialization Registers
//#############################
always @ (posedge rxi_lclk or posedge reset) begin
if(reset) begin
clk_even_reg <= 9'd0;
clk_odd_reg <= 9'd0;
clk0_even <= 9'd0;
clk0_odd <= 9'd0;
clk1_even <= 9'd0;
clk1_odd <= 9'd0;
clk2_even <= 9'd0;
clk2_odd <= 9'd0;
clk3_even <= 9'd0;
clk3_odd <= 9'd0;
end else begin
clk_even_reg <= clk_even;
clk_odd_reg <= clk_odd;
if(clk_edge[0]) begin
clk0_even <= clk_even_reg;
clk0_odd <= clk_odd_reg;
end
if(clk_edge[1]) begin
clk1_even <= clk_even_reg;
clk1_odd <= clk_odd_reg;
end
if(clk_edge[2]) begin
clk2_even <= clk_even_reg;
clk2_odd <= clk_odd_reg;
end
if(clk_edge[3]) begin
clk3_even <= clk_even_reg;
clk3_odd <= clk_odd_reg;
end
end // else: !if(reset)
end // always @ (posedge rxi_lclk or posedge reset)
//#####################################
//# De-serialization Data Construction
//#####################################
assign rx_out_int[71:64]={clk0_even[8],clk0_odd[8],clk1_even[8],clk1_odd[8],
clk2_even[8],clk2_odd[8],clk3_even[8],clk3_odd[8]};
assign rx_out_int[63:56]={clk0_even[7],clk0_odd[7],clk1_even[7],clk1_odd[7],
clk2_even[7],clk2_odd[7],clk3_even[7],clk3_odd[7]};
assign rx_out_int[55:48]={clk0_even[6],clk0_odd[6],clk1_even[6],clk1_odd[6],
clk2_even[6],clk2_odd[6],clk3_even[6],clk3_odd[6]};
assign rx_out_int[47:40]={clk0_even[5],clk0_odd[5],clk1_even[5],clk1_odd[5],
clk2_even[5],clk2_odd[5],clk3_even[5],clk3_odd[5]};
assign rx_out_int[39:32]={clk0_even[4],clk0_odd[4],clk1_even[4],clk1_odd[4],
clk2_even[4],clk2_odd[4],clk3_even[4],clk3_odd[4]};
assign rx_out_int[31:24]={clk0_even[3],clk0_odd[3],clk1_even[3],clk1_odd[3],
clk2_even[3],clk2_odd[3],clk3_even[3],clk3_odd[3]};
assign rx_out_int[23:16]={clk0_even[2],clk0_odd[2],clk1_even[2],clk1_odd[2],
clk2_even[2],clk2_odd[2],clk3_even[2],clk3_odd[2]};
assign rx_out_int[15:8] ={clk0_even[1],clk0_odd[1],clk1_even[1],clk1_odd[1],
clk2_even[1],clk2_odd[1],clk3_even[1],clk3_odd[1]};
assign rx_out_int[7:0] ={clk0_even[0],clk0_odd[0],clk1_even[0],clk1_odd[0],
clk2_even[0],clk2_odd[0],clk3_even[0],clk3_odd[0]};
endmodule // dv_io_rx
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:44:11 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_stub.v
// Design : system_xadc_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xadc_wiz_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, vauxp0, vauxn0, vauxp1,
vauxn1, vauxp2, vauxn2, vauxp4, vauxn4, vauxp5, vauxn5, vauxp6, vauxn6, vauxp7, vauxn7, vauxp9, vauxn9,
vauxp10, vauxn10, vauxp12, vauxn12, vauxp13, vauxn13, vauxp14, vauxn14, vauxp15, vauxn15, busy_out,
channel_out, eoc_out, eos_out, vccaux_alarm_out, vccint_alarm_out, user_temp_alarm_out,
alarm_out, temp_out, vp_in, vn_in)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[10:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[10:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,vauxp0,vauxn0,vauxp1,vauxn1,vauxp2,vauxn2,vauxp4,vauxn4,vauxp5,vauxn5,vauxp6,vauxn6,vauxp7,vauxn7,vauxp9,vauxn9,vauxp10,vauxn10,vauxp12,vauxn12,vauxp13,vauxn13,vauxp14,vauxn14,vauxp15,vauxn15,busy_out,channel_out[4:0],eoc_out,eos_out,vccaux_alarm_out,vccint_alarm_out,user_temp_alarm_out,alarm_out,temp_out[11:0],vp_in,vn_in" */;
input s_axi_aclk;
input s_axi_aresetn;
input [10:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [10:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output ip2intc_irpt;
input vauxp0;
input vauxn0;
input vauxp1;
input vauxn1;
input vauxp2;
input vauxn2;
input vauxp4;
input vauxn4;
input vauxp5;
input vauxn5;
input vauxp6;
input vauxn6;
input vauxp7;
input vauxn7;
input vauxp9;
input vauxn9;
input vauxp10;
input vauxn10;
input vauxp12;
input vauxn12;
input vauxp13;
input vauxn13;
input vauxp14;
input vauxn14;
input vauxp15;
input vauxn15;
output busy_out;
output [4:0]channel_out;
output eoc_out;
output eos_out;
output vccaux_alarm_out;
output vccint_alarm_out;
output user_temp_alarm_out;
output alarm_out;
output [11:0]temp_out;
input vp_in;
input vn_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int res = -1; for (int i = 1; i < s.size(); i++) { for (int j = 1; i + j < s.size(); j++) { int p1; string P1 = s.substr(0, i); if (P1.size() > 1 && P1[0] == 0 ) p1 = -1; else if (P1.size() >= 7 && P1 != 1000000 ) p1 = -1; else istringstream(P1) >> p1; int p2; string P2 = s.substr(i, j); if (P2.size() > 1 && P2[0] == 0 ) p2 = -1; else if (P2.size() >= 7 && P2 != 1000000 ) p2 = -1; else istringstream(P2) >> p2; int p3; string P3 = s.substr(i + j, s.size()); if (P3.size() > 1 && P3[0] == 0 ) p3 = -1; else if (P3.size() >= 7 && P3 != 1000000 ) p3 = -1; else istringstream(P3) >> p3; if (p1 == -1 || p2 == -1 || p3 == -1) continue; res = max(res, p1 + p2 + p3); } } cout << res << endl; return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_6_3,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_6_3,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=32,DIN_FROM=30,DIN_TO=7}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_6_3 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(30),
.DIN_TO(7)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9643_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input [13:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
// internal registers
reg adc_valid_in = 'd0;
reg [27:0] adc_pn_data_in = 'd0;
reg [29:0] adc_pn_data_pn = 'd0;
// internal signals
wire [27:0] adc_pn_data_in_s;
wire [29:0] adc_pn_data_pn_s;
// PN23 function
function [29:0] pn23;
input [29:0] din;
reg [29:0] dout;
begin
dout[29] = din[22] ^ din[17];
dout[28] = din[21] ^ din[16];
dout[27] = din[20] ^ din[15];
dout[26] = din[19] ^ din[14];
dout[25] = din[18] ^ din[13];
dout[24] = din[17] ^ din[12];
dout[23] = din[16] ^ din[11];
dout[22] = din[15] ^ din[10];
dout[21] = din[14] ^ din[ 9];
dout[20] = din[13] ^ din[ 8];
dout[19] = din[12] ^ din[ 7];
dout[18] = din[11] ^ din[ 6];
dout[17] = din[10] ^ din[ 5];
dout[16] = din[ 9] ^ din[ 4];
dout[15] = din[ 8] ^ din[ 3];
dout[14] = din[ 7] ^ din[ 2];
dout[13] = din[ 6] ^ din[ 1];
dout[12] = din[ 5] ^ din[ 0];
dout[11] = din[ 4] ^ din[22] ^ din[17];
dout[10] = din[ 3] ^ din[21] ^ din[16];
dout[ 9] = din[ 2] ^ din[20] ^ din[15];
dout[ 8] = din[ 1] ^ din[19] ^ din[14];
dout[ 7] = din[ 0] ^ din[18] ^ din[13];
dout[ 6] = din[22] ^ din[12];
dout[ 5] = din[21] ^ din[11];
dout[ 4] = din[20] ^ din[10];
dout[ 3] = din[19] ^ din[ 9];
dout[ 2] = din[18] ^ din[ 8];
dout[ 1] = din[17] ^ din[ 7];
dout[ 0] = din[16] ^ din[ 6];
pn23 = dout;
end
endfunction
// PN9 function
function [29:0] pn9;
input [29:0] din;
reg [29:0] dout;
begin
dout[29] = din[ 8] ^ din[ 4];
dout[28] = din[ 7] ^ din[ 3];
dout[27] = din[ 6] ^ din[ 2];
dout[26] = din[ 5] ^ din[ 1];
dout[25] = din[ 4] ^ din[ 0];
dout[24] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[23] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[22] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[21] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[20] = din[ 8] ^ din[ 0];
dout[19] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[18] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[17] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[16] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[15] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[13] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[12] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[11] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[10] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 9] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 8] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 7] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 6] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 5] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 4] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 3] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 2] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 1] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 0] = din[ 6] ^ din[ 8] ^ din[ 0];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_in_s = {adc_pn_data_in[13:0], ~adc_data[13], adc_data[12:0]};
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b0) ? adc_pn_data_pn :
{ adc_pn_data_pn[29], adc_pn_data_in[27:14],
adc_pn_data_pn[14], adc_pn_data_in[13: 0]};
always @(posedge adc_clk) begin
adc_valid_in <= ~adc_valid_in;
adc_pn_data_in <= adc_pn_data_in_s;
if (adc_valid_in == 1'b1) begin
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(30)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_valid_in),
.adc_data_in ({ adc_pn_data_pn[29], adc_pn_data_in[27:14],
adc_pn_data_pn[14], adc_pn_data_in[13: 0]}),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:09:45 05/22/2014
// Design Name:
// Module Name: pipeemreg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pipeemreg(i_wreg,i_m2reg,i_wmem,i_alu,i_b,i_rn,clk,rst,o_wreg,o_m2reg,o_wmem,o_alu,o_b,o_rn);
input wire clk, rst,i_wreg,i_m2reg,i_wmem;
input wire [31:0] i_b,i_alu;
input wire [4:0] i_rn;
output reg o_wreg,o_m2reg,o_wmem;
output reg [31:0] o_b,o_alu;
output reg [4:0] o_rn;
always @(posedge clk) begin
if (rst) begin
o_wreg<=0;
o_m2reg<=0;
o_wmem<=0;
o_alu<=0;
o_b<=0;
o_rn<=0;
end
//if reset signal is given, turn to the first instruction
else begin
o_wreg<=i_wreg;
o_m2reg<=i_m2reg;
o_wmem<=i_wmem;
o_alu<=i_alu;
o_b<=i_b;
o_rn<=i_rn;
end
//PC count change (how to change is determined by i_pc)
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string a, b; int rs, p; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> a >> b; if (a.size() != b.size()) return cout << NO , 0; for (int i = 0; i < a.size(); i++) if (a[i] != b[i]) rs++, p = i; if (rs != 2) return cout << NO , 0; for (int i = 0; i < a.size(); i++) if (a[i] != b[i] && a[i] == b[p] && a[p] == b[i]) return cout << YES , 0; else if (a[i] != b[i]) return cout << NO , 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 12, INF = 1e9 + 7; int a[N]; int main() { int n, m, i, j, k; scanf( %d , &(n)); ; vector<int> dp; dp.push_back(-100001); for (i = 0; i < (n); ++i) { dp.push_back(100001); scanf( %d , &(a[i])); ; } for (i = 0; i < n; ++i) { int j = int(upper_bound(dp.begin(), dp.end(), a[i]) - dp.begin()); if (dp[j - 1] < a[i] && a[i] < dp[j]) dp[j] = a[i]; } for (i = 1; i <= n; ++i) { if (dp[i] == 100001) break; } cout << i - 1; }
|
#include <bits/stdc++.h> using namespace std; int N, Q; vector<vector<int> > ad; vector<int> val, par; void fun(int c, int p) { par[c] = p; int i; for (i = 0; i < ad[c].size(); i++) { if (ad[c][i] != p) fun(ad[c][i], c); } } int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int query(int c, int v) { if (c == -1) return c; if (gcd(val[c], v) > 1) return c + 1; return query(par[c], v); } int main() { int i, j, k; cin >> N >> Q; ad.resize(N); val.resize(N); par.resize(N); for (i = 0; i < N; i++) cin >> val[i]; for (i = 1; i < N; i++) { cin >> j >> k; ad[j - 1].push_back(k - 1); ad[k - 1].push_back(j - 1); } fun(0, -1); while (Q) { Q--; cin >> k; if (k == 2) { cin >> j >> k; val[j - 1] = k; } else { cin >> j; cout << query(par[j - 1], val[j - 1]) << endl; } } return 0; }
|
module emesh_mux (/*AUTOARG*/
// Outputs
ready_out, access_out, packet_out,
// Inputs
access_in, packet_in, ready_in
);
//#####################################################################
//# PARAMETERS
//#####################################################################
parameter AW = 32;
parameter PW = 2 * AW + 40;
parameter N = 99;
parameter CFG = "STATIC"; //Arbitration configuration
//"STATIC" fixed priority
//"DYNAMIC" round robin priority
//#####################################################################
//# INTERFACE
//#####################################################################
//Incoming transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] ready_out;
//Outgoing transaction
output access_out;
output [PW-1:0] packet_out;
input ready_in;
//#####################################################################
//# BODY
//#####################################################################
//local variables
wire [N-1:0] grants;
reg [PW-1:0] packet_out;
integer i;
//arbiter
generate
if(CFG=="STATIC")
begin : arbiter_static
oh_arbiter #(.N(N))
arbiter(// Outputs
.grants (grants[N-1:0]),
// Inputs
.requests (access_in[N-1:0])
);
end
else if (CFG=="DYNAMIC")
begin : arbiter_dynamic
`ifdef TARGET_SIM
initial
$display("ROUND ROBIN ARBITER NOT IMPLEMENTED\n");
`endif
end
endgenerate
//access signal
assign access_out = |(access_in[N-1:0]);
//raise ready signals
assign ready_out[N-1:0] = ~(access_in[N-1:0] & ~grants[N-1:0]) & {(N){ready_in}});
//parametrized mux
always @*
begin
packet_out[PW-1:0] = 'b0;
for(i=0;i<N;i=i+1)
packet_out[PW-1:0] = packet_out[PW-1:0] | {(PW){grants[i]}} & packet_in[((i+1)*PW-1)-:PW];
end
endmodule // mesh_mux
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
#include<bits/stdc++.h> using namespace std; #define show(x) cout<< #x << = << x << n ; #define mod 998244353 #define INF 1000000000000000000 #define pie 3.14159265358979323846 #define ll long long int #define pb push_back #define popcnt __builtin_popcount #define mp make_pair #define pii pair<ll,ll> #define prod(a,b) ((a*b)%mod) #define set0(x) memset(x,0,sizeof(x)) #define setm1(x) memset(x,-1,sizeof(x)) #define printlist(arr) for(auto lstelem :arr) cout<< lstelem << ;cout<< n #define all(a) a.begin(),a.end() #define sqre(a) ((a)*(a)) //maths stuff ll powr(ll a,ll b){ ll res=1; while(b){ if(b%2) res=(a*res)%mod; a=(a*a)%mod; b/=2; } return res; } void extentded_eucledian(ll a,ll b,ll &ex,ll &ey){ if(b==0){ ex=1; ey=0; return; } extentded_eucledian(b,a%b,ex,ey); swap(ex,ey); ey-= (a/b)*ex;//gcd= x*a+y*b } ll dp[1002][1002][2]; int main(){ #ifdef ONLINE_JUDGE //onlinesubmission #else freopen( input.txt , r ,stdin); #endif ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); string x,y; cin>> x >> y ; ll n=x.size(),m=y.size(); set0(dp); ll ans=0; for(ll i=0;i<=n;++i){ for(ll j=0;j<=m;++j){ if(i>0) dp[i][j][0]=(dp[i][j][0]+1)%mod; if(j>0) dp[i][j][1]=(dp[i][j][1]+1)%mod; if(i>1){ if(x[i-1]!=x[i-2]) dp[i][j][0]=(dp[i][j][0]+dp[i-1][j][0])%mod; } if(i>0 && j>0){ if(x[i-1]!=y[j-1]){ dp[i][j][0]=(dp[i][j][0]+dp[i-1][j][1])%mod; dp[i][j][1]=(dp[i][j][1]+dp[i][j-1][0])%mod; } } if(j>1){ if(y[j-1]!=y[j-2]) dp[i][j][1]=(dp[i][j][1]+dp[i][j-1][1])%mod; } ans=(ans+dp[i][j][0]+dp[i][j][1])%mod; } } for(ll i=0;i<n;++i){ ll j=i; while(j+1<n) if(x[j]!=x[j+1]) ++j; else break; ll l=(j-i+1),v=(( ((l+1)*l/2)%mod )*(m+1))%mod; ans=(ans-v+mod)%mod; i=j; } for(ll i=0;i<m;++i){ ll j=i; while(j+1<m) if(y[j]!=y[j+1]) ++j; else break; ll l=(j-i+1),v=((((l+1)*l/2)%mod)*(n+1))%mod; ans=(ans-v+mod)%mod; i=j; } cout<< ans ; return 0; } //might1331 pratapSingh: Try Kr raha hu mai bc, timer laga rakha h
|
#include <bits/stdc++.h> using namespace std; int INF = 1000 * 1000 * 1000; vector<vector<pair<int, int>>> adj; int mem[80][80][80][80]; int dp(int cur, int closestLeft, int closestRight, int remainingMoves) { if (remainingMoves == 0) return 0; if (mem[cur][closestLeft][closestRight][remainingMoves] != -1) { return mem[cur][closestLeft][closestRight][remainingMoves]; } int res = INF; for (auto& nxt : adj[cur]) if (nxt.first != cur) { if (nxt.first >= closestLeft && nxt.first <= closestRight) { int newClosestLeft = closestLeft; if (nxt.first > cur) newClosestLeft = cur + 1; int newClosestRight = closestRight; if (nxt.first < cur) newClosestRight = cur - 1; res = min(res, nxt.second + dp(nxt.first, newClosestLeft, newClosestRight, remainingMoves - 1)); } } return mem[cur][closestLeft][closestRight][remainingMoves] = res; } int main() { int n, k, m; cin >> n >> k >> m; memset(mem, -1, sizeof(mem)); adj.resize(n); for (int i = 0; i < m; i++) { int u; cin >> u; u--; int v; cin >> v; v--; int c; cin >> c; adj[u].push_back(make_pair(v, c)); } int res = INF; for (int start = 0; start < n; start++) { int temp = dp(start, 0, n - 1, k - 1); res = min(res, temp); } if (res >= INF) cout << -1 << endl; else cout << res << endl; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Thu Oct 13 08:24:14 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.2 2006/01/19 09:18:57 wig Exp $
// $Date: 2006/01/19 09:18:57 $
// $Log: ent_a.v,v $
// Revision 1.2 2006/01/19 09:18:57 wig
// Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
//
// Generator: mix_0.pl Revision: 1.37 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No `defines in this module
`define const_17_c 8'b00000000 // __I_ConvConstant: 0x0
module ent_a
//
// Generated module inst_a
//
(
const_p_19, // Constant on inst_a
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Module parameters:
parameter generic_15 = 4660;
// Generated Module Inputs:
input [15:0] const_p_19;
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire [15:0] const_p_19;
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [7:0] const_17;
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign const_17 = `const_17_c;
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment ...
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.const_p_17(const_17), // Constant
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment ...
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/30 16:32:25
// Design Name:
// Module Name: uart_rx
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_rx(
clk,
rst_n,
bps_start,
clk_bps,
RS232_rx,
rx_data,
rx_int,
data_out
);
input clk; //ʱÖÓ
input rst_n; //¸´Î»
input RS232_rx; //½ÓÊÕÊý¾ÝÐźÅ
input clk_bps; //¸ßµçƽʱΪ½ÓÊÕÐźÅÖмä²ÉÑùµã
output bps_start; //½ÓÊÕÐźÅʱ,²¨ÌØÂÊʱÖÓÐźÅÖÃλ
output [7:0] rx_data;//½ÓÊÕÊý¾Ý¼Ä´æÆ÷
output rx_int; //½ÓÊÕÊý¾ÝÖжÏÐźÅ,½ÓÊÕ¹ý³ÌÖÐΪ¸ß
output reg [7:0]data_out;
reg RS232_rx0,RS232_rx1,RS232_rx2,RS232_rx3;//½ÓÊÕÊý¾Ý¼Ä´æÆ÷
wire neg_RS232_rx;//±íʾÊý¾ÝÏß½ÓÊÕµ½ÏÂÑØ
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
RS232_rx0 <= 1'b0;
RS232_rx1 <= 1'b0;
RS232_rx2 <= 1'b0;
RS232_rx3 <= 1'b0;
end
else begin
RS232_rx0 <= RS232_rx;
RS232_rx1 <= RS232_rx0;
RS232_rx2 <= RS232_rx1;
RS232_rx3 <= RS232_rx2;
end
end
assign neg_RS232_rx = RS232_rx3 & RS232_rx2 & ~RS232_rx1 & ~RS232_rx0;//´®¿Ú´«ÊäÏßµÄÏÂÑرêÖ¾
reg bps_start_r;
reg [3:0] num;//ÒÆλ´ÎÊý
reg rx_int; //½ÓÊÕÖжÏÐźÅ
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
bps_start_r <=1'bz;
rx_int <= 1'b0;
end
else if(neg_RS232_rx) begin//
bps_start_r <= 1'b1; //Æô¶¯´®¿Ú,×¼±¸½ÓÊÕÊý¾Ý
rx_int <= 1'b1; //½ÓÊÕÊý¾ÝÖжÏʹÄÜ
end
else if(num==4'd12) begin //½ÓÊÕÍêÓÐÓõÄÐźÅ,
bps_start_r <=1'b0; //½ÓÊÕÍê±Ï,¸Ä±ä²¨ÌØÂÊÖÃλ,·½±ãÏ´νÓÊÕ
rx_int <= 1'b0; //½ÓÊÕÐźŹرÕ
end
assign bps_start = bps_start_r;
reg [7:0] rx_data_r;//´®¿ÚÊý¾Ý¼Ä´æÆ÷
reg [7:0] rx_temp_data;//µ±Ç°Êý¾Ý¼Ä´æÆ÷
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
rx_temp_data <= 8'd0;
num <= 4'd0;
rx_data_r <= 8'd0;
end
else if(rx_int) begin //½ÓÊÕÊý¾Ý´¦Àí
if(clk_bps) begin
num <= num+1'b1;
case(num)
4'd1: rx_temp_data[0] <= RS232_rx;
4'd2: rx_temp_data[1] <= RS232_rx;
4'd3: rx_temp_data[2] <= RS232_rx;
4'd4: rx_temp_data[3] <= RS232_rx;
4'd5: rx_temp_data[4] <= RS232_rx;
4'd6: rx_temp_data[5] <= RS232_rx;
4'd7: rx_temp_data[6] <= RS232_rx;
4'd8: rx_temp_data[7] <= RS232_rx;
default: ;
endcase
data_out <= rx_temp_data;
end
else if(num==4'd12) begin
num <= 4'd0; //Êý¾Ý½ÓÊÕÍê±Ï
rx_data_r <= rx_temp_data;
end
end
assign rx_data = rx_data_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const int inf = 0x3f3f3f3f; int b[maxn]; int a[maxn]; int ma[maxn]; int pre[maxn * 10]; int _find(int x) { return x == pre[x] ? x : pre[x] = _find(pre[x]); } void _union(int x, int y) { x = _find(x), y = _find(y); if (x < y) pre[x] = y; else pre[y] = x; } int main() { int n; scanf( %d , &n); for (int i = 0; i < maxn * 10; ++i) pre[i] = i; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); ma[i] = max(ma[i - 1], a[i]); } bool flag = true; int x = 0; for (int i = n; i > 0; --i) { if (a[i] > ma[i - 1]) b[i] = ma[i - 1]; else b[i] = a[i] + 1; b[i] = _find(b[i]); _union(b[i], b[i] + 1); _union(a[i], a[i] + 1); x = max(x, a[i]); } if (!flag) puts( -1 ); else { for (int i = 1; i <= n; ++i) printf( %d%c , b[i], i == n ? n : ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T, size_t... Is> struct arr_helper; template <class T, size_t... Is> using arr = typename arr_helper<T, Is...>::type; template <class T> struct arr_helper<T> { using type = T; }; template <class T, size_t I, size_t... Is> struct arr_helper<T, I, Is...> { using type = array<arr<T, Is...>, I>; }; using ll = long long; using u64 = uint64_t; using u32 = uint32_t; using vi = vector<int>; using vl = vector<ll>; using vvi = vector<vi>; using pi = pair<int, int>; using pl = pair<ll, ll>; using vpi = vector<pi>; [[maybe_unused]] const int INF = (int)1e9; [[maybe_unused]] const ll INFL = (ll)1e18; ll M = 998244353; int mod_pow(ll b, ll e) { ll res = 1; for (; e; b = b * b % M, e /= 2) if (e % 2) res = res * b % M; return (int)res; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, m, k; cin >> n >> m >> k; vi f(k + 1), fi(k + 1), fn(k + 1); f[0] = 1; for (int i = (1); i < (k + 1); ++i) f[i] = (ll)f[i - 1] * i % M; for (int i = 0; i < (k + 1); ++i) fi[i] = mod_pow(f[i], M - 2); fn[0] = 1; for (int i = (1); i < (k + 1); ++i) fn[i] = fn[i - 1] * (ll)(n - i + 1) % M; auto choose = [&](int n, int k) { if (k > n) return 0ll; return (ll)f[n] * fi[n - k] % M * (ll)fi[k] % M; }; auto choose_n = [&](int k) { return fn[k] * (ll)fi[k] % M; }; ll sum = 0; auto p = mod_pow(m, M - 2); auto q = (ll)(m - 1) * p % M; vi nmkitok(k + 1); for (int i = 0; i < (k + 1); ++i) nmkitok[i] = mod_pow(n - i, k); for (int j = 0; j < (k + 1); ++j) { ll si = 0; for (int ki = 0; ki < (j + 1); ++ki) { si += (ll)(ki % 2 ? M - 1 : 1) * choose(j, ki) % M * nmkitok[ki] % M; si %= M; } sum += mod_pow(M - q, j) * (ll)choose_n(j) % M * si % M; sum %= M; } cout << sum << n ; return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file police.v when simulating
// the core, police. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module police(
clka,
addra,
douta
);
input clka;
input [12 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("police.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(6400),
.C_READ_DEPTH_B(6400),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(6400),
.C_WRITE_DEPTH_B(6400),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> int main() { int t; scanf( %d , &t); int a, b, c, d, k, x, y; while (t--) { scanf( %d %d %d %d %d , &a, &b, &c, &d, &k); if (a % c == 0) { x = a / c; } else { x = a / c + 1; } if (b % d == 0) { y = b / d; } else { y = b / d + 1; } if (x + y > k) { printf( -1 n ); } else printf( %d %d n , k - y, y); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> const int mod = 1000000007; const int gmod = 3; const int inf = 1039074182; const double eps = 1e-9; const long long llinf = 2LL * inf * inf; template <typename T1, typename T2> inline void chmin(T1 &x, T2 b) { if (b < x) x = b; } template <typename T1, typename T2> inline void chmax(T1 &x, T2 b) { if (b > x) x = b; } inline void chadd(int &x, int b) { x += b - mod; x += (x >> 31 & mod); } template <typename T1, typename T2> inline void chadd(T1 &x, T2 b) { x += b; if (x >= mod) x -= mod; } template <typename T1, typename T2> inline void chmul(T1 &x, T2 b) { x = 1LL * x * b % mod; } template <typename T1, typename T2> inline void chmod(T1 &x, T2 b) { x %= b, x += b; if (x >= b) x -= b; } template <typename T> inline T mabs(T x) { return (x < 0 ? -x : x); } using namespace std; using namespace std; template <typename T> ostream &operator<<(ostream &cout, vector<T> vec) { cout << { ; for (int i = 0; i < (int)vec.size(); i++) { cout << vec[i]; if (i != (int)vec.size() - 1) cout << , ; } cout << } ; return cout; } template <typename T> void operator*=(vector<T> &vec, int k) { for (auto &x : vec) x *= k; } template <typename T> void operator-=(vector<T> &a, const vector<T> &b) { assert(a.size() == b.size()); for (size_t it = 0; it < a.size(); it++) { a[it] -= b[it]; } } template <typename T> vector<T> operator*(const vector<T> &vec, int k) { vector<T> res(vec); res *= k; return res; } template <typename T1, typename T2> ostream &operator<<(ostream &cout, pair<T1, T2> p) { cout << ( << p.first << , << p.second << ) ; return cout; } template <typename T, typename T2> ostream &operator<<(ostream &cout, set<T, T2> s) { vector<T> t; for (auto x : s) t.push_back(x); cout << t; return cout; } template <typename T, typename T2> ostream &operator<<(ostream &cout, multiset<T, T2> s) { vector<T> t; for (auto x : s) t.push_back(x); cout << t; return cout; } template <typename T> ostream &operator<<(ostream &cout, queue<T> q) { vector<T> t; while (q.size()) { t.push_back(q.front()); q.pop(); } cout << t; return cout; } template <typename T1, typename T2, typename T3> ostream &operator<<(ostream &cout, map<T1, T2, T3> m) { for (auto &x : m) { cout << Key: << x.first << << Value: << x.second << endl; } return cout; } template <typename T> T operator*(vector<T> v1, vector<T> v2) { assert(v1.size() == v2.size()); int n = v1.size(); T res = 0; for (int i = 0; i < n; i++) { res += v1[i] * v2[i]; } return res; } template <typename T1, typename T2> void operator+=(pair<T1, T2> &x, const pair<T1, T2> y) { x.first += y.first; x.second += y.second; } template <typename T1, typename T2> pair<T1, T2> operator+(const pair<T1, T2> &x, const pair<T1, T2> &y) { return make_pair(x.first + y.first, x.second + y.second); } template <typename T1, typename T2> pair<T1, T2> operator-(const pair<T1, T2> &x, const pair<T1, T2> &y) { return make_pair(x.first - y.first, x.second - y.second); } template <typename T1, typename T2> pair<T1, T2> operator-(pair<T1, T2> x) { return make_pair(-x.first, -x.second); } template <typename T> vector<vector<T>> operator~(vector<vector<T>> vec) { vector<vector<T>> v; int n = vec.size(), m = vec[0].size(); v.resize(m); for (int i = 0; i < m; i++) { v[i].resize(n); } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { v[i][j] = vec[j][i]; } } return v; } void print0x(int x) { std::vector<int> vec; while (x) { vec.push_back(x & 1); x >>= 1; } std::reverse(vec.begin(), vec.end()); for (int i = 0; i < (int)vec.size(); i++) { std::cout << vec[i]; } std::cout << ; } template <typename T> void print0x(T x, int len) { std::vector<int> vec; while (x) { vec.push_back(x & 1); x >>= 1; } reverse(vec.begin(), vec.end()); for (int i = (int)vec.size(); i < len; i++) { putchar( 0 ); } for (size_t i = 0; i < vec.size(); i++) { std::cout << vec[i]; } std::cout << ; } template <int mod> struct ModInt { int x; ModInt() { x = 0; } ModInt(int _x) { x = _x % mod; if (x < 0) x += mod; } ModInt(long long _x) { x = _x % mod; if (x < 0) x += mod; } ModInt<mod> &operator++() { ++x; if (x == mod) x = 0; return *this; } ModInt<mod> operator++(int) { int t = x; x++; if (x == mod) x = 0; return t; } ModInt<mod> &operator--() { --x; if (x == -1) x += mod; return *this; } ModInt<mod> operator--(int) { int t = x; x--; if (x == -1) x += mod; return t; } }; template <int mod> inline int mabs(const ModInt<mod> &a) { return a.x; } template <int mod> bool operator==(const ModInt<mod> &a, const ModInt<mod> &b) { return a.x == b.x; } template <int mod> bool operator==(ModInt<mod> a, int x) { return (a.x == x); } template <int mod> bool operator!=(const ModInt<mod> &a, const ModInt<mod> &b) { return (a.x != b.x); } template <int mod> bool operator!=(ModInt<mod> a, int x) { return (a.x != x); } template <int mod> ModInt<mod> operator+(ModInt<mod> a, int b) { a.x += b; if (a.x >= mod) a.x -= mod; return a; } template <int mod> ModInt<mod> operator+(ModInt<mod> a, ModInt<mod> b) { int tmp = a.x + b.x; if (tmp >= mod) tmp -= mod; return tmp; } template <int mod> ModInt<mod> operator-(ModInt<mod> a, ModInt<mod> b) { int tmp = a.x - b.x; if (tmp < 0) tmp += mod; return tmp; } template <int mod> ModInt<mod> operator-(ModInt<mod> a, int b) { return a - (ModInt<mod>)b; } template <int mod> void operator-=(ModInt<mod> &a, ModInt<mod> b) { a.x -= b.x; a.x += (a.x >> 31 & mod); } template <int mod, typename T> void operator-=(ModInt<mod> &a, const T &b) { a.x -= b; a.x += (a.x >> 31 & mod); } template <int mod> ModInt<mod> operator*(ModInt<mod> a, ModInt<mod> b) { return 1LL * a.x * b.x % mod; } template <int mod> ModInt<mod> operator*(ModInt<mod> a, int b) { return 1LL * a.x * b % mod; } template <int mod> void operator*=(ModInt<mod> &a, ModInt<mod> b) { a = a * b; } template <int mod, typename T> void operator*=(ModInt<mod> &a, const T &b) { a = a * b; } template <int mod> void operator+=(ModInt<mod> &a, ModInt<mod> b) { a.x += b.x; if (a.x >= mod) a.x -= mod; } template <int mod, typename T> void operator+=(ModInt<mod> &a, const T &b) { a.x += b; if (a.x >= mod) a.x -= mod; } template <int mod> inline ModInt<mod> inv(ModInt<mod> x) { int m = mod - 2; ModInt<mod> basic = x; x = 1; while (m) { if (m & 1) x *= basic; m >>= 1; basic *= basic; } return x; } template <int mod> ModInt<mod> operator/(ModInt<mod> a, ModInt<mod> b) { return a * inv(b); } template <int mod> ModInt<mod> operator/(ModInt<mod> a, int b) { return a * inv((ModInt<mod>)b); } template <int mod> void operator/=(ModInt<mod> &a, int b) { a *= inv(ModInt<mod>(b)); } template <int mod> void operator/=(ModInt<mod> &a, ModInt<mod> b) { a = a / b; } template <int mod> ModInt<mod> operator^(ModInt<mod> basic, int x) { ModInt<mod> res = 1; while (x) { if (x & 1) res *= basic; basic *= basic; x >>= 1; } return res; } template <int mod> istream &operator>>(istream &cin, ModInt<mod> &x) { cin >> x.x; x.x %= mod; if (x.x < 0) x.x += mod; return cin; } template <int mod> ostream &operator<<(ostream &cout, ModInt<mod> x) { cout << x.x; return cout; } namespace combinatorics { int *fac; int *ifac; int __Tmod; inline int add(int a, int b) { return (a + b) % __Tmod; } inline int sub(int a, int b) { return (a - b + __Tmod) % __Tmod; } inline int mult(int a, int b) { return (1LL * a * b) % __Tmod; } inline int fastpow(int basic, int x) { chmod(x, __Tmod - 1); if (x == 0) return 1; int res = 1; while (x) { if (x & 1) res = mult(res, basic); basic = mult(basic, basic); x >>= 1; } return res; } inline int inv(int x) { return fastpow(x, __Tmod - 2); } inline int div(int a, int b) { return mult(a, inv(b)); } void init(int n, int tmod) { __Tmod = tmod; fac = new int[n + 5]; ifac = new int[n + 5]; fac[0] = 1; for (int i = 1; i <= n; i++) { fac[i] = mult(fac[i - 1], i); } ifac[n] = inv(fac[n]); for (int i = n - 1; i >= 0; i--) { ifac[i] = mult(ifac[i + 1], i + 1); } } inline int C(int n, int m) { if (n < m || n < 0 || m < 0) return 0; return mult(mult(fac[n], ifac[m]), ifac[n - m]); } inline int Cat(int x) { return mult(C(x * 2, x), inv(x + 1)); } } // namespace combinatorics using namespace std; using Int = ModInt<mod>; int n, k; char c[100005]; Int sum[100005]; Int a[100005]; int main() { scanf( %d%d , &n, &k); scanf( %s , c); for (int i = 0; i < n; i++) c[i] -= 0 ; combinatorics::init(n, mod); for (int i = 0; i < n; i++) { a[i] = c[i]; sum[i] = a[i] + (i ? sum[i - 1] : 0); } Int res = 0; for (int j = 0; j <= n - 2; j++) { Int b = Int(combinatorics::C(n - j - 2, k - 1)) * (Int(10) ^ j); res += b * sum[n - j - 2]; } for (int i = 0; i < n; i++) { res += a[i] * combinatorics::C(i, k) * (Int(10) ^ (n - 1 - i)); } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int ans = 1000000000000, n, m, i, d, j, a, fo = 0; vector<long long int> v; set<long long int> mset; cin >> n >> m >> d; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> a; mset.insert(a); v.emplace_back(a); } } sort(v.begin(), v.end()); for (auto x : mset) { long long int counter = 0; for (j = 0; j < v.size(); j++) { a = abs(x - v[j]); if (a % d != 0 || counter >= ans) { counter = 1000000000000; break; } counter += (a / d); } if (ans > counter) { ans = counter; } } if (ans == 1000000000000) cout << -1 << endl; else cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int matrix[101][101]; struct HATE { int t, r, c, x; HATE(int t, int r, int c, int x) { this->t = t; this->r = r; this->c = c; this->x = x; } }; HATE* hates[10001]; int main() { int n, m, q; cin >> n >> m >> q; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { matrix[i][j] = 1e9 + 1; } } for (int heh = 0; heh < q; heh++) { int t; cin >> t; if (t == 1) { int r; cin >> r; hates[heh] = new HATE(t, r, 0, 0); } else if (t == 2) { int c; cin >> c; hates[heh] = new HATE(t, 0, c, 0); } else { int r, c, x; cin >> r >> c >> x; hates[heh] = new HATE(t, r, c, x); } } for (int heh = q - 1; heh >= 0; heh--) { int t = hates[heh]->t; int r = hates[heh]->r; int c = hates[heh]->c; int x = hates[heh]->x; if (t == 1) { r--; int temp = matrix[r][m - 1]; for (int i = m - 1; i >= 1; i--) { matrix[r][i] = matrix[r][i - 1]; } matrix[r][0] = temp; } else if (t == 2) { c--; int temp = matrix[n - 1][c]; for (int i = n - 1; i >= 1; i--) { matrix[i][c] = matrix[i - 1][c]; } matrix[0][c] = temp; } else { r--; c--; matrix[r][c] = x; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (matrix[i][j] == 1e9 + 1) { cout << 1488 << ; } else { cout << matrix[i][j] << ; } } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; const int mod = 1e9 + 7; vector<int> G[maxn]; char s[maxn]; int vis[maxn]; map<string, int> mp; long long a[maxn], n, L, R, t; void solve1() { L = 0, R = n; for (int i = 0; i <= n - 2; i++) { if (s[i] == < ) L++; else { for (int i = R - L; i <= R; i++) printf( %d , i); R = R - L - 1, L = 0; } } for (int i = R - L; i <= R && i >= 1; i++) printf( %d , i); printf( n ); } void solve2() { L = 0, R = 1; for (int i = 0; i <= n - 2; i++) { if (s[i] == > ) L++; else { for (int i = R + L; i >= R; i--) printf( %d , i); R = R + L + 1, L = 0; } } for (int i = R + L; i >= R && i <= n; i--) printf( %d , i); printf( n ); } int main() { cin >> t; while (t--) { scanf( %lld%s , &n, s); solve1(); solve2(); } }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 300000; long long n, x[Maxn], w[Maxn], Index[Maxn], nx[Maxn]; set<pair<long long, long long> > poi, xx; set<pair<long long, long long> > u; void input() { cin >> n; for (int i = 0; i < n; i++) { cin >> x[i] >> w[i]; xx.insert(make_pair(x[i], i)); poi.insert(make_pair(x[i] - w[i], i)); } } void solve() { long long k = 0; for (auto c : poi) { Index[c.second] = k; k++; } for (auto c : xx) { long long ind = c.second; poi.erase(make_pair(x[ind] - w[ind], ind)); long long sum = x[ind] + w[ind]; auto limIt = poi.lower_bound(make_pair(sum, 0)); if (limIt != poi.end()) { auto lim = *limIt; nx[Index[ind]] = Index[lim.second]; u.insert(make_pair(Index[lim.second], Index[ind])); } else nx[Index[ind]] = -1; } int ans = 1, last = 0; while (((int)u.size())) { auto c = (*u.begin()).first; ans++; for (; last < c; last++) if (nx[last] >= 0) u.erase(make_pair(nx[last], last)); } cout << ans << endl; } int main() { ios::sync_with_stdio(0); cin.tie(); input(); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_4_V
`define SKY130_FD_SC_LP__MUX2I_4_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[105]; for (int i = 0; i < n; i++) { cin >> a[i]; } a[n] = a[0]; int k; int minn = 10005; for (int i = 1; i <= n; i++) { if (abs(a[i] - a[i - 1]) < minn) { minn = abs(a[i] - a[i - 1]); k = i; } } if (k >= n) { cout << 1 << << k << endl; } else { cout << k + 1 << << k << endl; } }
|
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; using ll = long long; using vll = int64_t; const int N = 1e6 + 1; vector<int> adj[N]; vector<bool> vis(N, false); vector<short> col(N, -1); inline bool bfs(int src) { queue<pair<int, int>> q; q.push({src, 0}); vis[src] = true; col[src] = 0; while (!q.empty()) { auto p = q.front(); q.pop(); for (int i : adj[p.first]) { if (vis[i]) { if (col[i] == col[p.first]) { return false; } continue; } vis[i] = true; col[i] = (p.second == 1 ? 0 : 1); q.push({i, col[i]}); } } return true; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int m; cin >> m; unordered_set<int> hs; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; adj[a].push_back(b); adj[b].push_back(a); hs.insert(a); hs.insert(b); } for (int i = 0; i < n; i++) { if (!vis[i] && hs.find(i) != hs.end()) { bool ok = bfs(i); if (!ok) { cout << -1 n ; return 0; } } } int red = 0, black = 0; for (int i = 0; i < n; i++) { if (col[i] == 1) black++; else if (col[i] == 0) red++; } cout << red << n ; for (int i = 0; i < n; i++) { if (col[i] == 0) cout << 1 + i << ; } cout << n ; cout << black << n ; for (int i = 0; i < n; i++) { if (col[i] == 1) cout << i + 1 << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int x[1005], y[1005], r[1005], level[1005]; long long sum[1005]; vector<pair<int, int> > X[1005]; void dfs(int node, int l) { level[node] = l; int i; for (i = 0; i < X[node].size(); i++) { if (level[X[node][i].second] <= level[node]) dfs(X[node][i].second, l + 1); } } bool check(int ind1, int ind2) { if (r[ind1] < r[ind2]) return false; long double dist = (long long)(x[ind1] - x[ind2]) * (x[ind1] - x[ind2]) + (long long)(y[ind1] - y[ind2]) * (y[ind1] - y[ind2]); dist = sqrtl(dist); if (dist + r[ind2] > (long double)r[ind1]) return false; return true; } int main() { int n; scanf( %d , &n); int i; for (i = 1; i <= n; i++) { scanf( %d%d%d , x + i, y + i, r + i); } for (i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if (check(i, j)) X[i].push_back(make_pair(r[j], j)); if (check(j, i)) X[j].push_back(make_pair(r[i], i)); } } for (i = 1; i <= n; i++) { sort(X[i].begin(), X[i].end()); reverse(X[i].begin(), X[i].end()); } for (i = 1; i <= n; i++) { if (!level[i]) dfs(i, 1); } for (i = 1; i <= n; i++) { sum[level[i]] += (long long)r[i] * r[i]; } int cnt = 0; long long ans = 0; for (i = 1; i <= 1000; i++) { if (i <= 2) { ans += sum[i]; continue; } if (i % 2) ans -= sum[i]; else ans += sum[i]; } long double p = (long double)(3.14159265359) * ans; cout.precision(9); cout << fixed << p; }
|
#include <bits/stdc++.h> using namespace std; template <class T> long long ToInt(const T &x) { stringstream s; s << x; long long r; s >> r; return r; } template <class T> string ToString(const T &x) { stringstream s; s << x; return s.str(); } int main() { string str, str2; cin >> str; if (str.length() == 1) return cout << 1 << endl, 0; long long N = str[0] - 0 ; N++; for (int i = 1; i < str.length(); i++) str2 += 0 ; string temp = ToString(N); str2 = temp + str2; printf( %lld n , ToInt(str2) - ToInt(str)); }
|
module RAMB16_S1_S1(
input WEA,
input ENA,
input SSRA,
input CLKA,
input [13:0] ADDRA,
input [0:0] DIA,
// input DIPA,
// output [3:0] DOPA,
output [0:0] DOA,
input WEB,
input ENB,
input SSRB,
input CLKB,
input [13:0] ADDRB,
input [0:0] DIB,
// input DIPB,
// output [3:0] DOPB,
output [0:0] DOB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
RAMB16_RIGEL #(.WRITE_MODE_A(WRITE_MODE_A),.WRITE_MODE_B(WRITE_MODE_B),.BITS(1),.INIT_00(INIT_00),.INIT_01(INIT_01),.INIT_02(INIT_02),.INIT_03(INIT_03),.INIT_04(INIT_04),.INIT_05(INIT_05),.INIT_06(INIT_06),.INIT_07(INIT_07),.INIT_08(INIT_08),.INIT_09(INIT_09),.INIT_0A(INIT_0A),.INIT_0B(INIT_0B),.INIT_0C(INIT_0C),.INIT_0D(INIT_0D),.INIT_0E(INIT_0E),.INIT_0F(INIT_0F),.INIT_10(INIT_10),.INIT_11(INIT_11),.INIT_12(INIT_12),.INIT_13(INIT_13),.INIT_14(INIT_14),.INIT_15(INIT_15),.INIT_16(INIT_16),.INIT_17(INIT_17),.INIT_18(INIT_18),.INIT_19(INIT_19),.INIT_1A(INIT_1A),.INIT_1B(INIT_1B),.INIT_1C(INIT_1C),.INIT_1D(INIT_1D),.INIT_1E(INIT_1E),.INIT_1F(INIT_1F),.INIT_20(INIT_20),.INIT_21(INIT_21),.INIT_22(INIT_22),.INIT_23(INIT_23),.INIT_24(INIT_24),.INIT_25(INIT_25),.INIT_26(INIT_26),.INIT_27(INIT_27),.INIT_28(INIT_28),.INIT_29(INIT_29),.INIT_2A(INIT_2A),.INIT_2B(INIT_2B),.INIT_2C(INIT_2C),.INIT_2D(INIT_2D),.INIT_2E(INIT_2E),.INIT_2F(INIT_2F),.INIT_30(INIT_30),.INIT_31(INIT_31),.INIT_32(INIT_32),.INIT_33(INIT_33),.INIT_34(INIT_34),.INIT_35(INIT_35),.INIT_36(INIT_36),.INIT_37(INIT_37),.INIT_38(INIT_38),.INIT_39(INIT_39),.INIT_3A(INIT_3A),.INIT_3B(INIT_3B),.INIT_3C(INIT_3C),.INIT_3D(INIT_3D),.INIT_3E(INIT_3E),.INIT_3F(INIT_3F)) inner_ram(.WEA(WEA),.ENA(ENA),.SSRA(SSRA),.CLKA(CLKA),.ADDRA(ADDRA),.DIA(DIA),.DIPA(1'b0),.DOA(DOA),.WEB(WEB),.ENB(ENB),.SSRB(SSRB),.CLKB(CLKB),.ADDRB(ADDRB),.DIB(DIB),.DIPB(1'b0),.DOB(DOB));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, dir[200005]; long long cnt, le; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &dir[i]); if (dir[i] == 0) le++; } for (int i = 0; i < n; i++) { if (dir[i] == 1) cnt += le; else le--; } printf( %I64d , cnt); return 0; }
|
#include <bits/stdc++.h> const int mod = 998244353; using namespace std; int a[200010], b[200010]; void solve() { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; int x; for (int i = 1; i <= n; i++) cin >> x, b[i] = a[i] - x; sort(b + 1, b + n + 1); long long ans = 0; for (int i = 1; i <= n - 1; i++) { if (b[i] > 0) ans += n - i; else { int j = upper_bound(b + 1, b + n + 1, -b[i]) - b; ans += max(0, n - j + 1); } } cout << ans << n ; } int main() { ios::sync_with_stdio(false), cin.tie(nullptr); int t = 1; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKBUF_PP_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_PP_BLACKBOX_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file msu_databuf.v when simulating
// the core, msu_databuf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module msu_databuf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [7 : 0] dina;
input clkb;
input [13 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_SYMBOL_V
`define SKY130_FD_SC_LS__DFRBP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_SYMBOL_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The module for debug RAM program
//
// ====================================================================
module sirv_debug_ram(
input clk,
input rst_n,
input ram_cs,
input ram_rd,
input [ 3-1:0] ram_addr,
input [32-1:0] ram_wdat,
output [32-1:0] ram_dout
);
wire [31:0] debug_ram_r [0:6];
wire [6:0] ram_wen;
assign ram_dout = debug_ram_r[ram_addr];
genvar i;
generate //{
for (i=0; i<7; i=i+1) begin:debug_ram_gen//{
assign ram_wen[i] = ram_cs & (~ram_rd) & (ram_addr == i) ;
sirv_gnrl_dfflr #(32) ram_dfflr (ram_wen[i], ram_wdat, debug_ram_r[i], clk, rst_n);
end//}
endgenerate//}
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_V
|
#include <bits/stdc++.h> const int N_MAX = 600007; std::map<std::pair<int, int>, int> ext; long long ans[N_MAX], now; int fa[N_MAX], siz[N_MAX][2], top; std::pair<int, int> stk[N_MAX]; int find(int x) { while (fa[x] != x) x = fa[x]; return x; } void merge(std::pair<int, int> v) { int x = find(v.first), y = find(v.second); if (x != y) { if (siz[x][0] + siz[x][1] < siz[y][0] + siz[y][1]) std::swap(x, y); now -= 1ll * siz[x][0] * siz[x][1] + 1ll * siz[y][0] * siz[y][1]; siz[x][0] += siz[y][0], siz[x][1] += siz[y][1]; now += 1ll * siz[x][0] * siz[x][1]; fa[y] = x, stk[++top] = std::make_pair(x, y); } } void undoMerge() { int x = stk[top].first, y = stk[top].second; now -= 1ll * siz[x][0] * siz[x][1]; siz[x][0] -= siz[y][0], siz[x][1] -= siz[y][1]; now += 1ll * siz[x][0] * siz[x][1] + 1ll * siz[y][0] * siz[y][1]; fa[y] = y, --top; } static const int T_MAX = 1200007; std::vector<std::pair<int, int> > op[T_MAX]; void modify(int k, int l, int r, int x, int y, std::pair<int, int> v) { if (x <= l && r <= y) { op[k].push_back(v); return; } if (x <= ((l + r) >> 1)) modify((k << 1), l, ((l + r) >> 1), x, y, v); if (((l + r) >> 1) < y) modify((k << 1 | 1), ((l + r) >> 1) + 1, r, x, y, v); } void dfs(int k, int l, int r) { int temp = top; for (auto v : op[k]) merge(v); if (l == r) ans[l] = now; else dfs((k << 1), l, ((l + r) >> 1)), dfs((k << 1 | 1), ((l + r) >> 1) + 1, r); while (top > temp) undoMerge(); } int main() { const int n = 3e5; int Q; scanf( %d , &Q); for (int i = 1; i <= Q; ++i) { std::pair<int, int> temp; scanf( %d%d , &temp.first, &temp.second), temp.second += n; if (ext.find(temp) == ext.end()) ext[temp] = i; else modify(1, 1, Q, ext[temp], i - 1, temp), ext.erase(temp); } for (auto i : ext) modify(1, 1, Q, i.second, Q, i.first); for (int i = 1; i <= n; ++i) fa[i] = i, siz[i][0] = 1; for (int i = n + 1; i <= n + n; ++i) fa[i] = i, siz[i][1] = 1; dfs(1, 1, Q); for (int i = 1; i <= Q; ++i) printf( %lld , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T, class L> bool smax(T& x, L y) { return x < y ? (x = y, 1) : 0; } template <class T, class L> bool smin(T& x, L y) { return x > y ? (x = y, 1) : 0; } const int maxn = 2e5 + 17; int n, m, gp[maxn], rate[maxn], cnt, sz[maxn]; unordered_map<int, pair<int, int> > p; set<int> s[maxn]; vector<int> ag[maxn]; void dfs(int v, int rt = 0) { if (gp[v]) return; gp[v] = cnt, rate[v] = rt; s[cnt].insert(rt); sz[cnt]++; dfs((v + m) % n, rt + 1); } int main() { long long ans = 0; p.max_load_factor(0.25), p.reserve(512); scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) if (!gp[i]) cnt++, dfs(i); int q; cin >> q; for (int id, h; q--;) { char c; scanf( %c %d , &c, &id); if (c == + ) { scanf( %d , &h); int g = gp[h], r = rate[h]; auto it = s[g].lower_bound(r); if (it == s[g].end()) it = s[g].begin(), ans += sz[g]; ans += *it - r; p[id] = {g, *it}; s[g].erase(it); } else { auto tmp = p[id]; s[tmp.first].insert(tmp.second); } } printf( %lld , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mn = 200005; const int mod = 1e9 + 7; int n, m; unordered_set<int> h[mn]; priority_queue<pair<int, int> > q; int sum = 0; int maxi, mini; vector<tuple<int, int, int> > ans; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { int u; scanf( %d , &u); for (int j = 1; j <= u; j++) { int v; scanf( %d , &v); h[i].insert(v); } sum += u; } mini = sum / n; maxi = mini + (sum % n != 0); for (int i = 1; i <= n; i++) { if ((int)h[i].size() >= maxi) { q.push({(int)h[i].size(), i}); } } for (int i = 1; i <= n; i++) { while ((int)h[i].size() < mini) { pair<int, int> u = q.top(); q.pop(); for (auto it = h[u.second].begin(); it != h[u.second].end(); it++) { if (!h[i].count(*it)) { h[i].insert(*it); ans.push_back({u.second, i, *it}); h[u.second].erase(it++); if ((int)h[i].size() == mini || (int)h[u.second].size() <= maxi) break; } } if ((int)h[u.second].size() >= maxi) q.push({(int)h[u.second].size(), u.second}); } } for (int i = 1; i <= n; i++) { if (q.top().first == maxi) break; while ((int)h[i].size() == mini) { pair<int, int> u = q.top(); q.pop(); for (auto it = h[u.second].begin(); it != h[u.second].end(); it++) { if (!h[i].count(*it)) { h[i].insert(*it); ans.push_back({u.second, i, *it}); h[u.second].erase(it++); break; } } if ((int)h[u.second].size() >= maxi) q.push({(int)h[u.second].size(), u.second}); } } printf( %d n , (int)ans.size()); for (auto &i : ans) { printf( %d %d %d n , get<0>(i), get<1>(i), get<2>(i)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y, z; cin >> x >> y >> z; if (abs(x - y) > z) { if (x > y) { cout << + n ; } else { cout << - n ; } } else { if (abs(x - y) == 0 && z == 0) { cout << 0 n ; } else { cout << ? n ; } } return 0; }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_gmii_rx
*/
module test_axis_gmii_rx;
// Parameters
parameter DATA_WIDTH = 8;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
reg clk_enable = 1;
reg mii_select = 0;
// Outputs
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire start_packet;
wire error_bad_frame;
wire error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
ptp_ts,
clk_enable,
mii_select
);
$to_myhdl(
m_axis_tdata,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
start_packet,
error_bad_frame,
error_bad_fcs
);
// dump file
$dumpfile("test_axis_gmii_rx.lxt");
$dumpvars(0, test_axis_gmii_rx);
end
axis_gmii_rx #(
.DATA_WIDTH(DATA_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.ptp_ts(ptp_ts),
.clk_enable(clk_enable),
.mii_select(mii_select),
.start_packet(start_packet),
.error_bad_frame(error_bad_frame),
.error_bad_fcs(error_bad_fcs)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A21BOI_BEHAVIORAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; inline int sn() { int n = 0; int ch = getchar(); while (ch < 48) ch = getchar(); while (ch > 47) n = (n << 3) + (n << 1) + ch - 0 , ch = getchar(); return n; } double dp[2005][2005]; int main() { int i, j, n, t; double p; scanf( %d %lf %d , &n, &p, &t); dp[0][0] = 1; for (i = 1; i <= t; i++) { dp[i][0] = pow(1 - p, i); dp[i][n] = dp[i - 1][n] + dp[i - 1][n - 1] * p; for (j = 1; j <= n - 1; j++) { dp[i][j] = dp[i - 1][j] * (1 - p) + dp[i - 1][j - 1] * p; } } double ans = 0; for (i = 1; i <= n; i++) { ans = ans + i * dp[t][i]; } printf( %0.6lf , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool debug = 0; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; string direc = RDLU ; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? YES : NO ); exit(0); } void addmod(int& x, int y, int mod = 1000000007) { x += y; if (x >= mod) x -= mod; assert(x >= 0 && x < mod); } void et() { puts( -1 ); exit(0); } struct Point { long double x, y; Point() {} Point(long double x, long double y) : x(x), y(y) {} Point operator*(double o) const { return Point(x * o, y * o); } Point operator+(const Point& o) const { return Point(x + o.x, y + o.y); } Point operator-(const Point& o) const { return Point(x - o.x, y - o.y); } bool operator<(const Point& o) const { return x < o.x || (x == o.x && y < o.y); } friend bool operator==(const Point& r1, const Point& r2) { return r1.x == r2.x && r1.y == r2.y; } long double cross(Point b) const { return x * b.y - b.x * y; } long double dot(Point b) const { return x * b.x + y * b.y; } }; set<Point> ss; void add(long double x, long double y) { Point p = Point(x, y); auto it = ss.lower_bound({x, 0}); auto pre = it; pre--; if (it != ss.end() && (p - *pre).cross(*it - *pre) <= 0) return; ss.insert(p); pre = ss.lower_bound(p); pre--; if (pre == ss.begin()) return; auto pp = pre; pp--; while (pre != ss.begin() && (*pre - *pp).cross(p - *pre) <= 0) { ss.erase(pre); pre = pp; if (pp == ss.begin()) return; pp--; } } inline int dcmp(long double x) { return fabsl(x) < 1e-9 ? 0 : (x > 0 ? 1 : -1); } bool ck(long double dam, long double mana) { auto cur = ss.lower_bound(Point(dam, 0)); if (cur == ss.end()) return 0; auto pre = cur; pre--; long double x = dam - (*pre).x, y = mana - (*pre).y; Point z = *cur - *pre; if (dcmp(x * z.y - y * z.x) <= 0) return 1; return 0; } void fmain(int tid) { scanf( %d%lld , &n, &lm); int ans = 0, M = 1e6; ss.insert(Point(0, 0)); for (int(i) = 1; (i) <= (int)(n); (i)++) { int t, x, y; scanf( %d%d%d , &t, &x, &y); x = (x + ans) % M + 1; y = (y + ans) % M + 1; if (t == 1) add(x, y); else { bool ok = ck((long double)y / x, (long double)lm / x); puts(ok ? YES : NO ); if (ok) ans = i; } } } int main() { int t = 1; for (int(i) = 1; (i) <= (int)(t); (i)++) { fmain(i); } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: CHARMAP.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module CHARMAP (
address,
clock,
q);
input [8:0] address;
input clock;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] q = sub_wire0[17:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({18{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "../charmap/charmap.rif"
`else
altsyncram_component.init_file = "../charmap/charmap.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 18,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../charmap/charmap.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "18"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../charmap/charmap.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CHARMAP_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__AND3_BEHAVIORAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5005; int a[N]; int main() { int n, m; scanf( %d%d , &n, &m); int tot = 0; for (int i = 1; i <= n; i++) { if (m < (i - 1) / 2) break; a[++tot] = i; m -= (i - 1) / 2; } if (!m) { int cnt = 1e8; for (int i = tot + 1; i <= n; i++) a[i] = cnt, cnt += 10000; for (int i = 1; i <= n; i++) cout << a[i] << ; } else { if (tot == n) puts( -1 ); else { a[tot + 1] = a[tot] + a[tot] - m * 2 + 1; int cnt = 1e8; for (int i = tot + 2; i <= n; i++) a[i] = cnt, cnt += 10000; for (int i = 1; i <= n; i++) cout << a[i] << ; } } }
|
#include <bits/stdc++.h> using namespace std; bool F = true; long long sum = 0; void DFS(int v, int par, vector<vector<int>> &g, vector<long long> &s, vector<long long> &a) { if (s[v] == -1) { if (g[v].size() == 0) return; long long m = 2e9; for (int u : g[v]) m = min(s[u], m); a[v] = m - s[par]; if (a[v] < 0) { F = false; } for (int u : g[v]) a[u] = s[u] - m; } sum += a[v]; for (int u : g[v]) DFS(u, v, g, s, a); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<vector<int>> g(n); vector<long long> s(n), a(n); for (int i = 1; i < n; ++i) { int p; cin >> p; g[p - 1].push_back(i); } for (int i = 0; i < n; ++i) { cin >> s[i]; } a[0] = s[0]; DFS(0, 0, g, s, a); if (!F) { cout << -1 << n ; } else { cout << sum << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long b, d, s, res = 0; cin >> b; cin >> d; cin >> s; long long val = max(b, max(d, s)) - 1; if (val > b) res += val - b; if (val > d) res += val - d; if (val > s) res += val - s; cout << res; }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> s[100010]; int a[100010], b[100010]; int main() { int N, P, i, x; scanf( %d n , &N); for (i = 0; i < N; i++) { scanf( %d , &x); s[i] = make_pair(x, i); } sort(s, s + N); P = N / 3; for (i = 0; i < P; i++) { a[s[i].second] = s[i].first; b[s[i].second] = 0; } P = (2 * N) / 3; for (; i < P; i++) { a[s[i].second] = 0; b[s[i].second] = s[i].first; } for (; i < N; i++) { a[s[i].second] = s[i].first - (N - i - 1); b[s[i].second] = N - i - 1; } printf( YES n ); for (i = 0; i < N; i++) printf( %d , a[i]); printf( n ); for (i = 0; i < N; i++) printf( %d , b[i]); printf( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND4BB_PP_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 55; int n, m, dp[MAX_N][MAX_N][MAX_N][MAX_N]; char a[MAX_N][MAX_N]; int dfs(int x1, int y1, int x2, int y2) { if (dp[x1][y1][x2][y2] >= 0) { return dp[x1][y1][x2][y2]; } if (x1 == x2 && y1 == y2) { return dp[x1][y1][x2][y2] = a[x1][y1] == # ; } int &ans = dp[x1][y1][x2][y2]; ans = max(x2 - x1 + 1, y2 - y1 + 1); for (int i = x1; i < x2; ++i) { ans = min(ans, dfs(x1, y1, i, y2) + dfs(i + 1, y1, x2, y2)); } for (int j = y1; j < y2; ++j) { ans = min(ans, dfs(x1, y1, x2, j) + dfs(x1, j + 1, x2, y2)); } return ans; } int main() { scanf( %d , &n); memset(dp, -1, sizeof dp); for (int i = 1; i <= n; ++i) { scanf( %s , a[i] + 1); } printf( %d n , dfs(1, 1, n, n)); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood$l_pp$PG (
UDP_OUT,
UDP_IN ,
VPWR ,
VGND
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_BLACKBOX_V
|
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Title : PCI Express LTSSM monitor
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcietb_pipe_phy.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This function interconnects two PIPE MAC interfaces for a single lane.
// For now this uses a common PCLK for both interfaces, an enhancement woudl be
// to support separate PCLK's for each interface with the requisite elastic
// buffer.
//-----------------------------------------------------------------------------
// Copyright (c) 2005 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcietb_ltssm_mon (
rp_clk,
rstn,
rp_ltssm,
ep_ltssm,
dummy_out
);
`include "altpcietb_bfm_constants.v"
`include "altpcietb_bfm_log.v"
`include "altpcietb_bfm_shmem.v"
`include "altpcietb_bfm_rdwr.v"
input rp_clk;
input rstn;
input [4:0] rp_ltssm;
input [4:0] ep_ltssm;
output dummy_out;
reg [4:0] rp_ltssm_r;
reg [4:0] ep_ltssm_r;
task conv_ltssm;
input device;
input detect_timout;
input [4:0] ltssm;
reg[(23)*8:1] ltssm_str;
reg dummy, dummy2 ;
begin
case (ltssm)
5'b00000: ltssm_str = "DETECT.QUIET ";
5'b00001: ltssm_str = "DETECT.ACTIVE ";
5'b00010: ltssm_str = "POLLING.ACTIVE ";
5'b00011: ltssm_str = "POLLING.COMPLIANCE ";
5'b00100: ltssm_str = "POLLING.CONFIG ";
5'b00110: ltssm_str = "CONFIG.LINKWIDTH.START ";
5'b00111: ltssm_str = "CONFIG.LINKWIDTH.ACCEPT";
5'b01000: ltssm_str = "CONFIG.LANENUM.ACCEPT ";
5'b01001: ltssm_str = "CONFIG.LANENUM.WAIT ";
5'b01010: ltssm_str = "CONFIG.COMPLETE ";
5'b01011: ltssm_str = "CONFIG.IDLE ";
5'b01100: ltssm_str = "RECOVERY.RCVRLOCK ";
5'b01101: ltssm_str = "RECOVERY.RCVRCFG ";
5'b01110: ltssm_str = "RECOVERY.IDLE ";
5'b01111: ltssm_str = "L0 ";
5'b10000: ltssm_str = "DISABLE ";
5'b10001: ltssm_str = "LOOPBACK.ENTRY ";
5'b10010: ltssm_str = "LOOPBACK.ACTIVE ";
5'b10011: ltssm_str = "LOOPBACK.EXIT ";
5'b10100: ltssm_str = "HOT RESET ";
5'b10101: ltssm_str = "L0s ";
5'b10110: ltssm_str = "L1.ENTRY ";
5'b10111: ltssm_str = "L1.IDLE ";
5'b11000: ltssm_str = "L2.IDLE ";
5'b11001: ltssm_str = "L2.TRANSMITWAKE ";
5'b11010: ltssm_str = "RECOVERY.SPEED ";
default: ltssm_str = "UNKNOWN ";
endcase
if (detect_timout==1)
dummy = ebfm_display(EBFM_MSG_ERROR_FATAL, { " LTSSM does not change from DETECT.QUIET"});
else if (device == 0)
dummy = ebfm_display(EBFM_MSG_INFO, { " RP LTSSM State: ", ltssm_str});
else
dummy = ebfm_display(EBFM_MSG_INFO, { " EP LTSSM State: ", ltssm_str});
end
endtask
reg [3:0] detect_cnt;
always @(posedge rp_clk)
begin
rp_ltssm_r <= rp_ltssm;
ep_ltssm_r <= ep_ltssm;
if (rp_ltssm_r != rp_ltssm)
conv_ltssm(0,0,rp_ltssm);
if (ep_ltssm_r != ep_ltssm)
conv_ltssm(1,0,ep_ltssm);
end
always @ (posedge rp_clk or negedge rstn) begin
if (rstn==1'b0) begin
detect_cnt <= 4'h0;
end
else begin
if (rp_ltssm_r != rp_ltssm) begin
if (detect_cnt == 4'b1000) begin
conv_ltssm(1,1,rp_ltssm);
end
else if (rp_ltssm==5'b01111) begin
detect_cnt <= 4'h0;
end
else if (rp_ltssm==5'b00000) begin
detect_cnt <= detect_cnt + 4'h1;
end
end
end
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module converts video streams between RGB color formats. *
* *
******************************************************************************/
module video_sys_Pixel_RGB_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15;
parameter ODW = 29;
parameter IEW = 0;
parameter OEW = 1;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[15:11], stream_in_data[15:11]};
assign g = {stream_in_data[10: 5], stream_in_data[10: 7]};
assign b = {stream_in_data[ 4: 0], stream_in_data[ 4: 0]};
assign a = ALPHA;
assign converted_data[29:20] = r[ 9: 0];
assign converted_data[19:10] = g[ 9: 0];
assign converted_data[ 9: 0] = b[ 9: 0];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int a[n]; long long int sum = 0; for (int i = 0; i < n; i++) { cin >> a[i]; sum += 1ll * a[i]; } long long int m = ceil(sum / 2); long long int temp = 0; for (int i = 0; i < n; i++) { temp += 1ll * a[i]; if (2 * temp >= sum) { cout << i + 1 << n ; break; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long num[30], pre[100010], cnt; int main() { int n, l, lr, ll; char s[100010]; cin >> n; for (int i = 0; i < n; i++) { cin >> s + 1; l = strlen(s + 1); for (int j = 0; j < 26; j++) if (num[j] && j + a != s[1] && j + a != s[l]) num[j] = 1; lr = 1; while (s[lr + 1] == s[lr]) lr++; ll = l; while (lr != l && s[ll] == s[ll - 1]) ll--; ll = l - ll + 1; if (s[1] == s[l]) if (lr == l) num[s[1] - a ] = (l + 1) * num[s[1] - a ] + l; else num[s[1] - a ] = lr + ll + 1; else { num[s[1] - a ] = num[s[1] - a ] > 0 ? lr + 1 : lr; num[s[l] - a ] = num[s[l] - a ] > 0 ? ll + 1 : ll; } for (int j = lr + 1; j <= l - ll + 1; j++) if (s[j] == s[j - 1]) pre[j] = pre[j - 1] + 1; else { pre[j] = 1; num[s[j - 1] - a ] = max(num[s[j - 1] - a ], pre[j - 1]); } } cnt = 0; for (int j = 0; j < 26; j++) cnt = max(cnt, num[j]); cout << cnt; }
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char **argv) { int n, h; cin >> n >> h; bool flag; for (int k = 0; k < n; k++) { flag = false; for (int j = 0; j < n; j++) { if (flag) cout << ; flag = true; if (j == k) cout << h; else cout << 0 ; } cout << endl; } return 0; }
|
module CPU(reset, clk);
input reset, clk;
// PC.
reg [31:0] PC;
wire [31:0] PC_next;
always @(posedge reset or posedge clk)
if (reset)
PC <= 32'h00000000;
else
PC <= PC_next;
wire [31:0] PC_plus_4;
assign PC_plus_4 = PC + 32'd4;
// Read instruction.
wire [31:0] Instruction;
InstructionMemory instruction_memory1(.Address(PC), .Instruction(Instruction));
// Generate control signals.
wire [1:0] RegDst;
wire [1:0] PCSrc;
wire Branch;
wire MemRead;
wire [1:0] MemtoReg;
wire [3:0] ALUOp;
wire ExtOp;
wire LuOp;
wire MemWrite;
wire ALUSrc1;
wire ALUSrc2;
wire RegWrite;
Control control1(
.OpCode(Instruction[31:26]), .Funct(Instruction[5:0]),
.PCSrc(PCSrc), .Branch(Branch), .RegWrite(RegWrite), .RegDst(RegDst),
.MemRead(MemRead), .MemWrite(MemWrite), .MemtoReg(MemtoReg),
.ALUSrc1(ALUSrc1), .ALUSrc2(ALUSrc2), .ExtOp(ExtOp), .LuOp(LuOp), .ALUOp(ALUOp));
// Register file.
wire [31:0] Databus1, Databus2, Databus3;
wire [4:0] Write_register;
assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: (RegDst == 2'b01)? Instruction[15:11]: 5'b11111;
RegisterFile register_file1(.reset(reset), .clk(clk), .RegWrite(RegWrite),
.Read_register1(Instruction[25:21]), .Read_register2(Instruction[20:16]), .Write_register(Write_register),
.Write_data(Databus3), .Read_data1(Databus1), .Read_data2(Databus2));
// Immediate.
wire [31:0] Ext_out;
assign Ext_out = {ExtOp? {16{Instruction[15]}}: 16'h0000, Instruction[15:0]};
wire [31:0] LU_out;
assign LU_out = LuOp? {Instruction[15:0], 16'h0000}: Ext_out;
// ALU Control.
wire [4:0] ALUCtl;
wire Sign;
ALUControl alu_control1(.ALUOp(ALUOp), .Funct(Instruction[5:0]), .ALUCtl(ALUCtl), .Sign(Sign));
// ALU.
wire [31:0] ALU_in1;
wire [31:0] ALU_in2;
wire [31:0] ALU_out;
wire Zero;
assign ALU_in1 = ALUSrc1? {17'h00000, Instruction[10:6]}: Databus1;
assign ALU_in2 = ALUSrc2? LU_out: Databus2;
ALU alu1(.in1(ALU_in1), .in2(ALU_in2), .ALUCtl(ALUCtl), .Sign(Sign), .out(ALU_out), .zero(Zero));
// Memory.
wire [31:0] Read_data;
DataMemory data_memory1(.reset(reset), .clk(clk), .Address(ALU_out), .Write_data(Databus2), .Read_data(Read_data), .MemRead(MemRead), .MemWrite(MemWrite));
assign Databus3 = (MemtoReg == 2'b00)? ALU_out: (MemtoReg == 2'b01)? Read_data: PC_plus_4;
// Jump.
wire [31:0] Jump_target;
assign Jump_target = {PC_plus_4[31:28], Instruction[25:0], 2'b00};
// Branch.
wire [31:0] Branch_target;
assign Branch_target = (Branch & Zero)? PC_plus_4 + {LU_out[29:0], 2'b00}: PC_plus_4;
// Branch or PC + 4 / j / jr.
assign PC_next = (PCSrc == 2'b00)? Branch_target: (PCSrc == 2'b01)? Jump_target: Databus1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, t; cin >> n >> k >> t; if (t <= k) cout << t << endl; else if (t > k && t <= n) cout << k << endl; else cout << k - (t - n) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, cc = 0, cn = 0, ic = 0, in1 = 0; int pr; cin >> n; for (int i = 1; i <= n; i++) { cin >> pr; if (pr % 2 == 1) { cn++; in1 = i; } else { cc++; ic = i; } } int answer = cn > cc ? ic : in1; cout << answer; return 0; }
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt12_kon(
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input [3:0] keyon_op,
input [2:0] keyon_ch,
input [1:0] next_op,
input [2:0] next_ch,
input up_keyon,
input csm,
// input flag_A,
input overflow_A,
output reg keyon_I
);
parameter num_ch=6;
wire csr_out;
generate
if(num_ch==6) begin
// capture overflow signal so it lasts long enough
reg overflow2;
reg [4:0] overflow_cycle;
always @(posedge clk) if( clk_en ) begin
if(overflow_A) begin
overflow2 <= 1'b1;
overflow_cycle <= { next_op, next_ch };
end else begin
if(overflow_cycle == {next_op, next_ch}) overflow2<=1'b0;
end
end
always @(posedge clk) if( clk_en )
keyon_I <= (csm&&next_ch==3'd2&&overflow2) || csr_out;
reg up_keyon_reg;
reg [3:0] tkeyon_op;
reg [2:0] tkeyon_ch;
wire key_upnow;
assign key_upnow = up_keyon_reg && (tkeyon_ch==next_ch) && (next_op == 2'd3);
always @(posedge clk) if( clk_en ) begin
if (rst)
up_keyon_reg <= 1'b0;
if (up_keyon) begin
up_keyon_reg <= 1'b1;
tkeyon_op <= keyon_op;
tkeyon_ch <= keyon_ch; end
else if (key_upnow)
up_keyon_reg <= 1'b0;
end
wire middle1;
wire middle2;
wire middle3;
wire din = key_upnow ? tkeyon_op[3] : csr_out;
wire mid_din2 = key_upnow ? tkeyon_op[1] : middle1;
wire mid_din3 = key_upnow ? tkeyon_op[2] : middle2;
wire mid_din4 = key_upnow ? tkeyon_op[0] : middle3;
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch0(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( din ),
.drop ( middle1 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch1(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din2 ),
.drop ( middle2 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch2(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din3 ),
.drop ( middle3 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch3(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din4 ),
.drop ( csr_out )
);
end
else begin // 3 channels
reg din;
reg [3:0] next_op_hot;
always @(*) begin
case( next_op )
2'd0: next_op_hot = 4'b0001; // S1
2'd1: next_op_hot = 4'b0100; // S3
2'd2: next_op_hot = 4'b0010; // S2
2'd3: next_op_hot = 4'b1000; // S4
endcase
din = keyon_ch[1:0]==next_ch[1:0] && up_keyon ? |(keyon_op&next_op_hot) : csr_out;
end
always @(posedge clk) if( clk_en )
keyon_I <= csr_out; // No CSM for YM2203
jt12_sh_rst #(.width(1),.stages(12),.rstval(1'b0)) u_konch1(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( din ),
.drop ( csr_out )
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000005; int T, n, m, las = 1, ndnum = 1, ans; char s[maxn]; struct node { int ch[26], len, fa; } d[maxn << 1]; int siz[maxn << 1], vis[maxn << 1], timer; int head[maxn << 1], tot; struct edge { int nxt, to; } e[maxn << 1]; void Addedge(int x, int y) { e[++tot] = (edge){head[x], y}; head[x] = tot; } void Insert(int x) { int p = las, np = las = ++ndnum; siz[np] = 1; d[np].len = d[p].len + 1; while (p && !d[p].ch[x]) { d[p].ch[x] = np; p = d[p].fa; } if (!p) { d[np].fa = 1; } else { int q = d[p].ch[x]; if (d[q].len == d[p].len + 1) { d[np].fa = q; } else { int nq = ++ndnum; d[nq] = d[q]; d[nq].len = d[p].len + 1; d[q].fa = d[np].fa = nq; while (p && d[p].ch[x] == q) { d[p].ch[x] = nq; p = d[p].fa; } } } } void dfs(int x) { int id; for (int i = head[x]; i; i = e[i].nxt) { id = e[i].to; dfs(id); siz[x] += siz[id]; } } void go(int &x, int y, int &len) { if (d[x].ch[y]) { ++len; x = d[x].ch[y]; } else { while (x && !d[x].ch[y]) x = d[x].fa; if (!x) { x = 1; len = 0; } else { len = d[x].len + 1; x = d[x].ch[y]; } } } void del(int &x, int &len) { if (len != m) return; --len; if (len == d[d[x].fa].len) x = d[x].fa; } void work(int x, int y) { if (y < m || vis[x] == timer) return; ans += siz[x]; vis[x] = timer; } int main() { scanf( %s , s + 1); n = strlen(s + 1); for (int i = 1; i <= n; ++i) Insert(s[i] - a ); for (int i = 2; i <= ndnum; ++i) Addedge(d[i].fa, i); dfs(1); scanf( %d , &T); int now, len; while (T--) { scanf( %s , s + 1); m = strlen(s + 1); now = 1; len = 0; for (int i = 1; i <= m; ++i) go(now, s[i] - a , len); ++timer; ans = 0; work(now, len); for (int i = 1; i < m; ++i) { del(now, len); go(now, s[i] - a , len); work(now, len); } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main(void) { double d, l, v1, v2; cin >> d >> l >> v1 >> v2; printf( %.10lf , double((l - d) / (v1 + v2))); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, c, l, r, cp, cm; string s; int main() { cin >> n >> s; for (int i = 0; i < n; i++) { l = i - 1; r = i; cp = 1; cm = 1; while (l >= 0 && s[l] != L ) { cp += (s[l] == R ); l--; } while (r < n - 1 && s[r] != R ) { cm += (s[r] == L ); r++; } cout << max(cp, cm) << endl; } }
|
#include <bits/stdc++.h> using namespace std; #define inf 1e15 #define mod 1000000007 #define N 100001 #define ll long long int #define vint vector<int> #define vll vector<ll> #define vstr vector<string> #define vvint vector<vector<int> > #define vvll vector<vector<ll> > #define vint_pair vector<pair<int,int> > #define input(arr) for(auto &x:arr) cin>>x; #define all(x) (x).begin(), (x).end() #define rall(x) (x).rbegin(), (x).rend() int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t=1; cin>>t; while(t--){ int n; cin>>n; set<int>num; vint arr(n); for(int i=0;i<n;++i){ cin>>arr[i]; num.insert(arr[i]); } int vis[n+1]; memset(vis, 0, sizeof(vis)); int l = 1; for(int i=0;i<n;++i){ if(vis[arr[i]]){ cout<<l<< ; vis[l] = 1; } else{ cout<<arr[i]<< ; vis[arr[i]] = 1; } while(vis[l]){ ++l; } } cout<< n ; set<int>st; memset(vis, 0, sizeof(vis)); for(int i=1;i<=n;++i){ if(num.find(i)==num.end()){ st.insert(i); } } for(int i=0;i<n;++i){ if(!vis[arr[i]]){ cout<<arr[i]<< ; vis[arr[i]] = 1; } else{ auto it = st.lower_bound(arr[i]); --it; int tmp = *it; cout<<tmp<< ; vis[tmp] = 1; st.erase(tmp); } } cout<< n ; } }
|
#include <bits/stdc++.h> int main() { int n, i, a = 0; scanf( %d , &n); for (i = n; i > a; i--) { if (n % i == 0) { printf( %d , i); n = i; } } return 0; }
|
// nios_tester_jtagdebug.v
// This file was auto-generated from altera_msgdma_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module nios_tester_jtagdebug (
output wire [25:0] mm_write_address, // mm_write.address
output wire mm_write_write, // .write
output wire [7:0] mm_write_writedata, // .writedata
input wire mm_write_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_n_reset_n, // reset_n.reset_n
input wire [31:0] csr_writedata, // csr.writedata
input wire csr_write, // .write
input wire [3:0] csr_byteenable, // .byteenable
output wire [31:0] csr_readdata, // .readdata
input wire csr_read, // .read
input wire [2:0] csr_address, // .address
input wire descriptor_slave_write, // descriptor_slave.write
output wire descriptor_slave_waitrequest, // .waitrequest
input wire [127:0] descriptor_slave_writedata, // .writedata
input wire [15:0] descriptor_slave_byteenable, // .byteenable
output wire csr_irq_irq, // csr_irq.irq
input wire [7:0] st_sink_data, // st_sink.data
input wire st_sink_valid, // .valid
output wire st_sink_ready // .ready
);
wire dispatcher_internal_write_command_source_valid; // dispatcher_internal:src_write_master_valid -> write_mstr_internal:snk_command_valid
wire [255:0] dispatcher_internal_write_command_source_data; // dispatcher_internal:src_write_master_data -> write_mstr_internal:snk_command_data
wire dispatcher_internal_write_command_source_ready; // write_mstr_internal:snk_command_ready -> dispatcher_internal:src_write_master_ready
wire write_mstr_internal_response_source_valid; // write_mstr_internal:src_response_valid -> dispatcher_internal:snk_write_master_valid
wire [255:0] write_mstr_internal_response_source_data; // write_mstr_internal:src_response_data -> dispatcher_internal:snk_write_master_data
wire write_mstr_internal_response_source_ready; // dispatcher_internal:snk_write_master_ready -> write_mstr_internal:src_response_ready
dispatcher #(
.MODE (2),
.RESPONSE_PORT (2),
.DESCRIPTOR_INTERFACE (0),
.DESCRIPTOR_FIFO_DEPTH (8),
.ENHANCED_FEATURES (0),
.DESCRIPTOR_WIDTH (128),
.DESCRIPTOR_BYTEENABLE_WIDTH (16)
) dispatcher_internal (
.clk (clock_clk), // clock.clk
.reset (~reset_n_reset_n), // clock_reset.reset
.csr_writedata (csr_writedata), // CSR.writedata
.csr_write (csr_write), // .write
.csr_byteenable (csr_byteenable), // .byteenable
.csr_readdata (csr_readdata), // .readdata
.csr_read (csr_read), // .read
.csr_address (csr_address), // .address
.descriptor_write (descriptor_slave_write), // Descriptor_Slave.write
.descriptor_waitrequest (descriptor_slave_waitrequest), // .waitrequest
.descriptor_writedata (descriptor_slave_writedata), // .writedata
.descriptor_byteenable (descriptor_slave_byteenable), // .byteenable
.src_write_master_data (dispatcher_internal_write_command_source_data), // Write_Command_Source.data
.src_write_master_valid (dispatcher_internal_write_command_source_valid), // .valid
.src_write_master_ready (dispatcher_internal_write_command_source_ready), // .ready
.snk_write_master_data (write_mstr_internal_response_source_data), // Write_Response_Sink.data
.snk_write_master_valid (write_mstr_internal_response_source_valid), // .valid
.snk_write_master_ready (write_mstr_internal_response_source_ready), // .ready
.csr_irq (csr_irq_irq), // csr_irq.irq
.src_response_data (), // (terminated)
.src_response_valid (), // (terminated)
.src_response_ready (1'b0), // (terminated)
.snk_descriptor_data (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.snk_descriptor_valid (1'b0), // (terminated)
.snk_descriptor_ready (), // (terminated)
.mm_response_waitrequest (), // (terminated)
.mm_response_byteenable (4'b0000), // (terminated)
.mm_response_address (1'b0), // (terminated)
.mm_response_readdata (), // (terminated)
.mm_response_read (1'b0), // (terminated)
.src_read_master_data (), // (terminated)
.src_read_master_valid (), // (terminated)
.src_read_master_ready (1'b0), // (terminated)
.snk_read_master_data (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.snk_read_master_valid (1'b0), // (terminated)
.snk_read_master_ready () // (terminated)
);
write_master #(
.DATA_WIDTH (8),
.LENGTH_WIDTH (24),
.FIFO_DEPTH (256),
.STRIDE_ENABLE (0),
.BURST_ENABLE (0),
.PACKET_ENABLE (0),
.ERROR_ENABLE (0),
.ERROR_WIDTH (8),
.BYTE_ENABLE_WIDTH (1),
.BYTE_ENABLE_WIDTH_LOG2 (1),
.ADDRESS_WIDTH (26),
.FIFO_DEPTH_LOG2 (8),
.SYMBOL_WIDTH (8),
.NUMBER_OF_SYMBOLS (1),
.NUMBER_OF_SYMBOLS_LOG2 (1),
.MAX_BURST_COUNT_WIDTH (1),
.UNALIGNED_ACCESSES_ENABLE (0),
.ONLY_FULL_ACCESS_ENABLE (1),
.BURST_WRAPPING_SUPPORT (0),
.PROGRAMMABLE_BURST_ENABLE (0),
.MAX_BURST_COUNT (1),
.FIFO_SPEED_OPTIMIZATION (1),
.STRIDE_WIDTH (1),
.ACTUAL_BYTES_TRANSFERRED_WIDTH (32)
) write_mstr_internal (
.clk (clock_clk), // Clock.clk
.reset (~reset_n_reset_n), // Clock_reset.reset
.master_address (mm_write_address), // Data_Write_Master.address
.master_write (mm_write_write), // .write
.master_writedata (mm_write_writedata), // .writedata
.master_waitrequest (mm_write_waitrequest), // .waitrequest
.snk_data (st_sink_data), // Data_Sink.data
.snk_valid (st_sink_valid), // .valid
.snk_ready (st_sink_ready), // .ready
.snk_command_data (dispatcher_internal_write_command_source_data), // Command_Sink.data
.snk_command_valid (dispatcher_internal_write_command_source_valid), // .valid
.snk_command_ready (dispatcher_internal_write_command_source_ready), // .ready
.src_response_data (write_mstr_internal_response_source_data), // Response_Source.data
.src_response_valid (write_mstr_internal_response_source_valid), // .valid
.src_response_ready (write_mstr_internal_response_source_ready), // .ready
.master_byteenable (), // (terminated)
.master_burstcount (), // (terminated)
.snk_sop (1'b0), // (terminated)
.snk_eop (1'b0), // (terminated)
.snk_empty (1'b0), // (terminated)
.snk_error (8'b00000000) // (terminated)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug420
typedef logic [7-1:0] wb_ind_t;
typedef logic [7-1:0] id_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
wire [6:0] out = line_wb_ind( in[6:0] );
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc918fa0aa882a206
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function wb_ind_t line_wb_ind( id_t id );
if( id[$bits(id_t)-1] == 0 )
return {2'b00, id[$bits(wb_ind_t)-3:0]};
else
return {2'b01, id[$bits(wb_ind_t)-3:0]};
endfunction // line_wb_ind
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_FUNCTIONAL_V
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.