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/**
* ------------------------------------------------------------
* Copyright (c) SILAB , Physics Institute of Bonn University
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "firmware/src/qmca.v"
`include "firmware/src/qmca_clk_gen.v"
`include "utils/clock_multiplier.v"
`include "utils/clock_divider.v"
`include "utils/bus_to_ip.v"
`include "sram_fifo/sram_fifo_core.v"
`include "sram_fifo/sram_fifo.v"
`include "rrp_arbiter/rrp_arbiter.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/reset_gen.v"
`include "utils/pulse_gen_rising.v"
`include "utils/CG_MOD_pos.v"
`include "spi/spi_core.v"
`include "spi/spi.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "gpio/gpio.v"
`include "gpac_adc_rx/gpac_adc_iobuf.v"
`include "gpac_adc_rx/gpac_adc_rx.v"
`include "gpac_adc_rx/gpac_adc_rx_core.v"
`include "utils/cdc_reset_sync.v"
`include "utils/ODDR_sim.v"
`include "utils/DCM_sim.v"
`include "utils/BUFG_sim.v"
`include "utils/RAMB16_S1_S9_sim.v"
`include "utils/IBUFDS_sim.v"
`include "utils/IBUFGDS_sim.v"
`include "utils/OBUFDS_sim.v"
`include "utils/fx2_to_bus.v"
module adc_ser_model (
input wire CLK, LOAD,
input wire [13:0] DATA_IN,
output wire DATA_OUT
);
reg [13:0] ser_reg;
always@(posedge CLK)
if(LOAD)
ser_reg <= DATA_IN;
else
ser_reg <= {ser_reg[12:0], 1'b0};
assign DATA_OUT = ser_reg[13];
endmodule
module tb (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
output ADC_CLK,
input wire [13:0] ADC_CH0, ADC_CH1, ADC_CH2, ADC_CH3
);
wire [19:0] SRAM_A;
wire [15:0] SRAM_IO;
wire SRAM_BHE_B;
wire SRAM_BLE_B;
wire SRAM_CE1_B;
wire SRAM_OE_B;
wire SRAM_WE_B;
wire [3:0] ADC_DATA;
wire ADC_ENC, ADC_DCO, ADC_FCO;
qmca dut(
.fclk_in(FCLK_IN),
.usb_data(BUS_DATA),
.usb_add(ADD),
.usb_rd(RD_B),
.usb_wr(WR_B),
.FD(FD),
.FREAD(FREAD),
.FSTROBE(FSTROBE),
.FMODE(FMODE),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.led1(),
.led2(),
.led3(),
.led4(),
.led5(),
.lemo_tx(),
.sda(),
.scl(),
.adc_csn(),
.adc_sclk(),
.adc_sdi(),
.adc_sdo(),
.adc_enc_p(ADC_ENC),
.adc_enc_n(),
.adc_dco_p(ADC_DCO),
.adc_dco_n(~ADC_DCO),
.adc_fco_p(ADC_FCO),
.adc_fco_n(~ADC_FCO),
.adc_out_p(ADC_DATA),
.adc_out_n(~ADC_DATA)
);
//SRAM Model
reg [15:0] sram [-1:0];
assign SRAM_IO = !SRAM_OE_B ? sram[SRAM_A] : 16'hzzzz;
always@(negedge SRAM_WE_B)
sram[SRAM_A] <= SRAM_IO;
clock_multiplier #( .MULTIPLIER(16) ) i_adc_clock_multiplier(.CLK(ADC_ENC),.CLOCK(ADC_DCO));
reg [3:0] adc_cnt;
reg [1:0] adc_rst_syn;
always@(posedge ADC_DCO) begin
adc_rst_syn <= {adc_rst_syn[0],ADC_ENC};
end
wire adc_rst;
assign adc_rst = adc_rst_syn[0] & !adc_rst_syn[1] ;
localparam [3:0] ADC_SYNC_DLY = 0;
always@(posedge ADC_DCO) begin
if(adc_rst)
adc_cnt <= ADC_SYNC_DLY;
else
adc_cnt <= adc_cnt + 1;
end
assign ADC_FCO = adc_cnt[3];
assign ADC_CLK = ADC_ENC;
wire adc_load;
assign adc_load = (adc_cnt == 7);
adc_ser_model i_adc_ser0(.CLK(ADC_DCO), .LOAD(adc_load), .DATA_IN(ADC_CH0), .DATA_OUT(ADC_DATA[0]));
adc_ser_model i_adc_ser1(.CLK(ADC_DCO), .LOAD(adc_load), .DATA_IN(ADC_CH1), .DATA_OUT(ADC_DATA[1]));
adc_ser_model i_adc_ser2(.CLK(ADC_DCO), .LOAD(adc_load), .DATA_IN(ADC_CH2), .DATA_OUT(ADC_DATA[2]));
adc_ser_model i_adc_ser3(.CLK(ADC_DCO), .LOAD(adc_load), .DATA_IN(ADC_CH3), .DATA_OUT(ADC_DATA[3]));
initial begin
$dumpfile("mca.vcd");
$dumpvars(0);
end
endmodule
|
#include <bits/stdc++.h> #define PI atan(1.0)*4 #define rp(i,s,t) for (register int i = (s); i <= (t); i++) #define RP(i,t,s) for (register int i = (t); i >= (s); i--) #define sc(x) scanf( %d ,&x) #define scl(x) scanf( %lld ,&x) #define ll long long #define ull unsigned long long #define mst(a,b) memset(a,b,sizeof(a)) #define lson l,m,rt<<1 #define rson m+1,r,rt<<1|1 #define pii pair<int,int> #define pll pair<ll,ll> #define pil pair<int,ll> #define m_p make_pair #define p_b push_back #define ins insert #define era erase #define INF 0x3f3f3f3f #define LINF 0x3f3f3f3f3f3f3f3f #define dg if(debug) #define outval(a) cout << Debuging...| << #a << : << a << n ; using namespace std; int debug = 0; ll gcd(ll a,ll b){ return b?gcd(b,a%b):a; } ll lcm(ll a,ll b){ return a/gcd(a,b)*b; } inline int read(){ int s=0,f=1; char ch=getchar(); while(ch< 0 ||ch> 9 ){ if(ch== - ) f=-1; ch=getchar(); } while(ch>= 0 &&ch<= 9 ){ s=s*10+ch- 0 ; ch=getchar(); } return s*f; } const int N = 1e6+7; const double eps = 1e-7; int a[N]; int f[N]; void solve(){ int n=read(),m=read(); rp(i,1,n) a[i]=read(); rp(i,1,n) f[i]=0; RP(i,n,1){ if(a[i]!=i) break; else f[i]=1; } int flag=1; rp(i,1,n){ if(f[i]==0){ flag=0; } } double ans=0.0; double cur=1; int ff=0; rp(i,1,m){ int r;double p; scanf( %d%lf ,&r,&p); // printf( %d %lf n ,r,p); if(r==n||f[r+1]){ ans+=cur*p; cur*=(1.0-p); if(fabs(p-1.0)<=eps) ff=1; } } if(ff||flag){ printf( 1.000000 n ); return ; } printf( %.6f n ,ans); } int main(){ //ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); #ifdef ONLINE_JUDGE #else freopen( in.txt , r , stdin); //debug = 1; #endif time_t beg, end; //if(debug) beg = clock(); int T=read(); while(T--) solve(); /* if(debug) { end = clock(); printf( time:%.2fs n , 1.0 * (end - beg) / CLOCKS_PER_SEC); } */ return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_4_V
`define SKY130_FD_SC_HS__O32A_4_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32a_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_4_V
|
#include <bits/stdc++.h> using namespace std; const double sq = 1.73205080757; int main() { long long k, k1; cin >> k; k1 = k * 2; k *= 2; k1 -= k1 % 3; k1++; if (k1 > k) k1 -= 3; long long h = 1, h1, an = 0; while (k1 > 0) { while (k1 * k1 + 3LL * h * h <= k * k && (k1 + 1) * (k1 + 1) + 3LL * (h - 1) * (h - 1) <= k * k) h++; h--; if ((k1 - 1) % 6 == 0) h1 = max(h - (h % 2 == 0), 0LL); else h1 = h - h % 2; an += h1; k1 -= 3; } cout << an * 2 - h1 << endl; }
|
`timescale 1ns / 1ps
/// 2. first line output : if f0 valid
/// 3. sof for reset
module test();
parameter integer C_PIXEL_WIDTH = 8;
parameter integer C_IMG_WBITS = 12;
parameter integer C_IMG_HBITS = 12;
parameter integer C_DATACOUNT_BITS = 10;
// User parameters ends
// Parameters of Axi Master Bus Interface M_AXI
parameter integer C_M_AXI_BURST_LEN = 16;
parameter integer C_M_AXI_ID_WIDTH = 1;
parameter integer C_M_AXI_ADDR_WIDTH = 32;
parameter integer C_M_AXI_DATA_WIDTH = 32;
wire [C_M_AXI_ID_WIDTH-1 : 0] m_axi_awid;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr;
wire [7 : 0] m_axi_awlen;
wire [2 : 0] m_axi_awsize;
wire [1 : 0] m_axi_awburst;
wire m_axi_awlock;
wire [3 : 0] m_axi_awcache;
wire [2 : 0] m_axi_awprot;
wire [3 : 0] m_axi_awqos;
wire m_axi_awvalid;
reg m_axi_awready = 1;
wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_wdata;
wire [C_M_AXI_DATA_WIDTH/8-1 : 0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
reg m_axi_wready = 1;
reg [C_M_AXI_ID_WIDTH-1 : 0] m_axi_bid;
reg [1 : 0] m_axi_bresp;
reg m_axi_bvalid;
wire m_axi_bready;
wire[31:0] S_AXIS_tdata;
wire S_AXIS_tlast;
wire S_AXIS_tready;
wire S_AXIS_tuser;
reg S_AXIS_tvalid;
reg[11:0] height = 240;
reg[11:0] width = 320;
wire[31:0] addr;
assign addr = 32'h3FF80000;
reg clk;
reg resetn;
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
wire[9:0] rd_data_count;
s2mmbd_wrapper uut(
.M_AXI_awid(m_axi_awid),
.M_AXI_awaddr(m_axi_awaddr),
.M_AXI_awlen(m_axi_awlen),
.M_AXI_awsize(m_axi_awsize),
.M_AXI_awburst(m_axi_awburst),
.M_AXI_awlock(m_axi_awlock),
.M_AXI_awcache(m_axi_awcache),
.M_AXI_awprot(m_axi_awprot),
.M_AXI_awqos(m_axi_awqos),
.M_AXI_awvalid(m_axi_awvalid),
.M_AXI_awready(m_axi_awready),
.M_AXI_wdata(m_axi_wdata),
.M_AXI_wstrb(m_axi_wstrb),
.M_AXI_wlast(m_axi_wlast),
.M_AXI_wvalid(m_axi_wvalid),
.M_AXI_wready(m_axi_wready),
.M_AXI_bid(m_axi_bid),
.M_AXI_bresp(m_axi_bresp),
.M_AXI_bvalid(m_axi_bvalid),
.M_AXI_bready(m_axi_bready),
.S_AXIS_tdata(S_AXIS_tdata),
.S_AXIS_tlast(S_AXIS_tlast),
.S_AXIS_tready(S_AXIS_tready),
.S_AXIS_tuser(S_AXIS_tuser),
.S_AXIS_tvalid(S_AXIS_tvalid),
.addr(addr),
.clk(clk),
.img_height(height),
.img_width(width),
.resetn(resetn),
.soft_resetn(1'b1),
.rd_data_count(rd_data_count)
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
reg[11:0] col;
reg[11:0] row;
wire final_data;
assign final_data = (col == 0 && row == 0);
assign S_AXIS_tuser = (col == width-1 && row == height-1);
assign S_AXIS_tlast = (col == 0);
assign S_AXIS_tdata = ((row << 16) | col);
reg randominput;
always @(posedge clk) begin
if (resetn == 1'b0)
randominput <= 1'b0;
else
randominput <= (RANDOMINPUT ? {$random}%2 : 1);
if (resetn == 1'b0) begin
col <= width-1;
row <= height -1;
end
else if (S_AXIS_tvalid && S_AXIS_tready) begin
if (col != 0) begin
col <= col - 1;
row <= row;
end
else if (row != 0) begin
col <= width - 1;
row <= row - 1;
end
else begin
col <= width-1;
row <= height-1;
end
end
else begin
col <= col;
row <= row;
end
if (resetn == 1'b0)
S_AXIS_tvalid <= 1'b0;
else
S_AXIS_tvalid <= randominput;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo.v
// Version: 1.00
// Verilog Standard: Verilog-2001
// Description: Standard 0-delay fifo implementation. Takes WR_DATA on WR_READY
// and WR_VALID. RD_DATA is read on RD_READY and RD_VALID
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo
#(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
parameter C_DELAY = 2
)
(
input CLK, // Clock
input RST, // Sync reset, active high
input [C_WIDTH-1:0] WR_DATA, // Write data input
input WR_VALID, // Write enable, high active
output WR_READY, // ~Full condition
output [C_WIDTH-1:0] RD_DATA, // Read data output
input RD_READY, // Read enable, high active
output RD_VALID // ~Empty condition
);
`include "functions.vh"
// Local parameters
localparam C_POW2_DEPTH = 2**clog2(C_DEPTH);
localparam C_DEPTH_WIDTH = clog2s(C_POW2_DEPTH);
wire [C_DELAY:0] wDelayTaps;
wire wDelayWrEn;
wire wWrEn;
wire wRdEn;
wire wRdRdy;
wire wRdEnInternal;
wire wRdEnExternal;
wire wEmptyNow;
wire wEmptyNext;
wire wOutputEmpty;
wire wFullNow;
wire wFullNext;
reg rValid;
reg [C_DEPTH_WIDTH:0] rWrPtr,_rWrPtr;
reg [C_DEPTH_WIDTH:0] rWrPtrPlus1, _rWrPtrPlus1;
reg [C_DEPTH_WIDTH:0] rRdPtr,_rRdPtr;
reg [C_DEPTH_WIDTH:0] rRdPtrPlus1,_rRdPtrPlus1;
reg rFull,_rFull;
reg rEmpty,_rEmpty;
assign wRdEnInternal = ~wEmptyNow & ~rValid; // Read enable to propogate data to the BRAM output
assign wRdEnExternal = RD_READY & !rEmpty; // Read enable to change data on the output
assign wRdEn = wRdEnInternal | wRdEnExternal;
assign wRdRdy = RD_READY & rValid; // Read Data already on the output bus
assign wWrEn = WR_VALID & !rFull;
assign wEmptyNow = (rRdPtr == rWrPtr);
assign wEmptyNext = (wRdEn & ~wWrEn & (rWrPtr == rRdPtrPlus1));
assign wFullNow = (rRdPtr[C_DEPTH_WIDTH-1:0] == rWrPtr[C_DEPTH_WIDTH-1:0]) &
(rWrPtr[C_DEPTH_WIDTH] != rRdPtr[C_DEPTH_WIDTH]);
assign wFullNext = wWrEn & ~wRdEn & (rWrPtrPlus1[C_DEPTH_WIDTH-1:0] == rRdPtr[C_DEPTH_WIDTH-1:0]) &
(rWrPtrPlus1[C_DEPTH_WIDTH] != rRdPtr[C_DEPTH_WIDTH]);
// Calculate empty
assign RD_VALID = rValid;
always @ (posedge CLK) begin
rEmpty <= #1 (RST ? 1'd1 : _rEmpty);
end
always @ (*) begin
_rEmpty = (wEmptyNow & ~wWrEn) | wEmptyNext;
end
always @(posedge CLK) begin
if(RST) begin
rValid <= #1 0;
end else if(wRdEn | wRdRdy) begin
rValid <= #1 ~(wEmptyNow);
end
end
// Write pointer logic.
always @ (posedge CLK) begin
if (RST) begin
rWrPtr <= #1 0;
rWrPtrPlus1 <= #1 1;
end else begin
rWrPtr <= #1 _rWrPtr;
rWrPtrPlus1 <= #1 _rWrPtrPlus1;
end
end
always @ (*) begin
if (wWrEn) begin
_rWrPtr = rWrPtrPlus1;
_rWrPtrPlus1 = rWrPtrPlus1 + 1'd1;
end else begin
_rWrPtr = rWrPtr;
_rWrPtrPlus1 = rWrPtrPlus1;
end
end
// Read pointer logic.
always @ (posedge CLK) begin
if (RST) begin
rRdPtr <= #1 0;
rRdPtrPlus1 <= #1 1;
end else begin
rRdPtr <= #1 _rRdPtr;
rRdPtrPlus1 <= #1 _rRdPtrPlus1;
end
end
always @ (*) begin
if (wRdEn) begin
_rRdPtr = rRdPtrPlus1;
_rRdPtrPlus1 = rRdPtrPlus1 + 1'd1;
end else begin
_rRdPtr = rRdPtr;
_rRdPtrPlus1 = rRdPtrPlus1;
end
end
// Calculate full
assign WR_READY = ~rFull;
always @ (posedge CLK) begin
rFull <= #1 (RST ? 1'd0 : _rFull);
end
always @ (*) begin
_rFull = wFullNow | wFullNext;
end
// Memory block (synthesis attributes applied to this module will
// determine the memory option).
scsdpram
#(
.C_WIDTH(C_WIDTH),
.C_DEPTH(C_POW2_DEPTH)
/*AUTOINSTPARAM*/)
mem
(
.WR1_EN (wWrEn),
.WR1_ADDR (rWrPtr[C_DEPTH_WIDTH-1:0]),
.WR1_DATA (WR_DATA),
.RD1_EN (wRdEn),
.RD1_ADDR (rRdPtr[C_DEPTH_WIDTH-1:0]),
.RD1_DATA (RD_DATA),
/*AUTOINST*/
// Inputs
.CLK (CLK));
shiftreg
#(
// Parameters
.C_DEPTH (C_DELAY),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
shiftreg_wr_delay_inst
(
// Outputs
.RD_DATA (wDelayTaps),
// Inputs
.RST_IN (RST),
.WR_DATA (wWrEn),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[1123456], p[1123456]; int main() { int n, i, j; scanf( %d , &n); for (i = 0; i < n; ++i) { scanf( %d , &j); p[j] = i; } dp[1] = 1; int ans = 1; for (i = 2; i <= n; ++i) { if (p[i] > p[i - 1]) { dp[i] = 1 + dp[i - 1]; } else { dp[i] = 1; } ans = max(ans, dp[i]); } cout << n - ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; const long long inf = 1e18; int a[maxn]; vector<int> g[maxn]; bool c[maxn], ok[maxn]; int dpdown[maxn], dpup[maxn]; int salem[maxn]; int mxdown[maxn], mxup[maxn]; int cnt[maxn]; int sum[maxn]; int n; int dip[maxn]; void dfsdown(int v, int p) { ok[v] = c[v]; cnt[v] = 1; sum[v] = c[v]; for (auto u : g[v]) if (u != p) dfsdown(u, v), cnt[v] += cnt[u], sum[v] += sum[u]; if (!c[v]) return; for (auto u : g[v]) if (u != p) if (ok[u]) salem[v] += cnt[u]; else { ok[v] = 0; mxdown[v] = max(mxdown[v], dpdown[u]); } dpdown[v] = mxdown[v] + salem[v] + 1; } void dfsup(int v, int p) { int _mx = -1; for (auto u : g[v]) if (u != p && c[u] && c[v]) mxup[u] = max(mxup[u], _mx), _mx = max(_mx, (1 - ok[u]) * dpdown[u]); reverse(g[v].begin(), g[v].end()); _mx = -1; for (auto u : g[v]) if (u != p && c[u] && c[v]) mxup[u] = max(mxup[u], _mx), _mx = max(_mx, (1 - ok[u]) * dpdown[u]); for (auto u : g[v]) if (u != p) if (c[u]) if (c[v]) if (sum[1] - sum[v] == n - cnt[v]) dpup[u] = 1 + salem[v] - (ok[u] ? cnt[u] : 0) + mxup[u] + dpup[v]; else dpup[u] = 1 + salem[v] - (ok[u] ? cnt[u] : 0) + max(mxup[u], dpup[v]); for (auto u : g[v]) if (u != p) if (c[u]) if (c[v]) if (sum[1] - sum[u] == n - cnt[u]) dip[u] = 1 + salem[u] + dpup[u] + mxdown[u]; else dip[u] = 1 + salem[u] + max(dpup[u], mxdown[u]); for (auto u : g[v]) if (u != p) dfsup(u, v); } int check(int mid) { for (int i = 1; i <= n; ++i) dip[i] = salem[i] = ok[i] = cnt[i] = dpdown[i] = dpup[i] = mxup[i] = mxdown[i] = 0; for (int i = 1; i <= n; ++i) c[i] = (a[i] >= mid); dfsdown(1, 0); dfsup(1, 0); int mx = 0; for (int i = 1; i <= n; ++i) mx = max(max(mx, dip[i]), max(dpdown[i], dpup[i])); return mx; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int k; cin >> n >> k; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } int l = 1, r = 1e6 + 85; while (r - l > 1) { int mid = (l + r) / 2; if (check(mid) >= k) l = mid; else r = mid; } cout << l << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int k, i, cn = 0, cnt = 0, j; cin >> k; string s; cin >> s; map<long long int, long long int> ans; long long int a[s.length()], n = s.length(); for (i = 0; i < s.length(); i++) { if (s[i] == 1 ) cnt++; } if (k > cnt) cout << 0 << endl; else { a[0] = (s[0] - 0 ); for (i = 1; i < s.length(); i++) { a[i] = a[i - 1] + (s[i] - 0 ); } i = 0; j = 0; ans[0] = 1; for (i = 0; i < n; i++) { if (a[i] >= k) cn += ans[a[i] - k]; ans[a[i]]++; } cout << cn << endl; } }
|
//UART FIFO
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1ns/1ps
/*
A custom FIFO that can take multiple bytes in at a time
*/
module uart_fifo (
clk,
rst,
size,
write_strobe,
write_available,
write_data,
read_strobe,
read_count,
read_data,
overflow,
underflow,
full,
empty
);
//parameters
parameter FIFO_SIZE = 10;
input clk;
input rst;
output wire [31:0] size;
input write_strobe;
output wire [31:0] write_available;
input [7:0] write_data;
input read_strobe;
output reg [31:0] read_count;
output wire [7:0] read_data;
output reg overflow;
output reg underflow;
output full;
output empty;
//Wires, Registers
reg [FIFO_SIZE - 1: 0] in_pointer;
reg [FIFO_SIZE - 1: 0] out_pointer;
dual_port_bram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(FIFO_SIZE),
//`ifdef SIMULATION
// .MEM_FILE("mem_file.txt"),
// .MEM_FILE_LENGTH(8)
//`else
.MEM_FILE("NOTHING"),
.MEM_FILE_LENGTH(0)
//`endif
) mem (
.a_clk(clk),
.a_wr(write_strobe),
.a_addr(in_pointer),
.a_din(write_data),
//.a_dout(),
.b_clk(clk),
.b_wr(0),
.b_addr(out_pointer),
.b_din(0),
.b_dout(read_data)
);
//synthesis attribute ram_style of mem is block
wire [FIFO_SIZE - 1: 0] last;
//Asynchronous Logic
assign size = 1 << FIFO_SIZE;
assign last = (out_pointer - 1);
assign full = (in_pointer == last);
assign empty = (read_count == 0);
assign write_available = size - read_count;
integer i;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
read_count <= 0;
in_pointer <= 0;
out_pointer <= 0;
//`ifdef SIMULATION
// read_count <= 8;
// in_pointer <= 8;
//`endif
overflow <= 0;
underflow <= 0;
end
else begin
overflow <= 0;
underflow <= 0;
if (write_strobe) begin
if (full && !read_strobe) begin
//overflow
$display ("UART CONTROLLER: Overflow condition");
out_pointer <= out_pointer + 1;
overflow <= 1;
end
else begin
//not overflow
if (!read_strobe) begin
read_count <= read_count + 1;
end
end
in_pointer <= in_pointer + 1;
end
if (read_strobe) begin
if (empty) begin
//empty
underflow <= 1;
end
else begin
if (full && write_strobe) begin
//check for that very rare condition where the write strobe and the read strobe is begin used at the same time
//and the FIFO is full
overflow <= 0;
end
else begin
if (!write_strobe) begin
read_count <= read_count - 1;
end
out_pointer <= out_pointer + 1;
end
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD1_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLYGATE4SD1_FUNCTIONAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd1 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD1_FUNCTIONAL_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: ddr_prbs_gen
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $
**$Date: 2011/06/02 08:35:10 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 64 // LFSR shift register length
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
input phy_if_empty, // IN_FIFO empty flag
input prbs_rdlvl_start, // PRBS read lveling start
output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = 128;
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg phy_if_empty_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
//***************************************************************************
always @(posedge clk_i) begin
phy_if_empty_r <= #TCQ phy_if_empty;
end
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
begin
if (rst_i || ~clk_en_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
end
always @ (posedge clk_i)
begin
//reset it to a known good state to prevent it locks up
if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];
end
else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];
lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];
lfsr_q[29:9] <= #TCQ lfsr_q[28:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
#include <bits/stdc++.h> using namespace std; double PI = 3.141592653589793; const double EPS = 1e-9; const int N = 1e6 + 5; const long long mod = 1e9 + 7; const int oo = 1e9 + 9; int dx[] = {0, 0, 1, -1, 1, -1, 1, -1}; int dy[] = {1, -1, 0, 0, -1, 1, 1, -1}; int n, m; long long row[1005], col[1005]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i <= n - 1; i++) { for (int j = 0; j <= m - 1; j++) { int x; scanf( %d , &x); row[i] += x; col[j] += x; } } long long min_row = 1e18; int ans_row; for (int i = 0; i <= n; i++) { long long curr = 0; for (int j = i, x = 2; j < n; j++, x += 4) { curr += x * x * row[j]; } for (int j = i - 1, x = 2; j >= 0; j--, x += 4) { curr += x * x * row[j]; } if (curr < min_row) { ans_row = i; min_row = curr; } } long long min_col = 1e18; int ans_col; for (int i = 0; i <= m; i++) { long long curr = 0; for (int j = i, y = 2; j < m; j++, y += 4) { curr += (long long)y * y * col[j]; } for (int j = i - 1, y = 2; j >= 0; j--, y += 4) { curr += (long long)y * y * col[j]; } if (curr < min_col) { ans_col = i; min_col = curr; } } printf( %lld n%d %d , min_col + min_row, ans_row, ans_col); }
|
// file: system_clk_wiz_1_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_1_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_system_clk_wiz_1_0;
wire clk_in2_system_clk_wiz_1_0;
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_1_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_system_clk_wiz_1_0;
wire clk_out2_system_clk_wiz_1_0;
wire clk_out3_system_clk_wiz_1_0;
wire clk_out4_system_clk_wiz_1_0;
wire clk_out5_system_clk_wiz_1_0;
wire clk_out6_system_clk_wiz_1_0;
wire clk_out7_system_clk_wiz_1_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_1_0;
wire clkfbout_buf_system_clk_wiz_1_0;
wire clkfboutb_unused;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (10),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_1_0),
.CLKOUT0 (clk_out1_system_clk_wiz_1_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_1_0),
.CLKIN1 (clk_in1_system_clk_wiz_1_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (1'b0));
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_1_0),
.I (clkfbout_system_clk_wiz_1_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_1_0));
endmodule
|
// $Id: ugal_source.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// a rudimentary traffic source that implements UGAL routing
//==============================================================================
module ugal_source(/*autoarg*/
// Outputs
intm_router_address, route_min,
// Inputs
clk, reset, flit_valid, flit_head, src_router_address, sel_mc, dest_info,
credit_count
);
`include "c_functions.v"
`include "c_constants.v"
parameter ugal_threshold = 3;
// flit bufwfer entries
parameter buffer_size = 16;
// number of message classes (e.g. request, reply)
parameter num_message_classes = 1;
// nuber of resource classes (e.g. minimal, adaptive)
localparam num_resource_classes = 2; // NOTE: UGAL requires this to be 2!
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs per class
parameter num_vcs_per_class = 1;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
//
parameter port_id = 6;
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// number of dimensions in network
parameter num_dimensions = 2;
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 4;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_FULL;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// select routing function type
parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// total number of bits required for storing routing information
localparam dest_info_width
= (routing_type == `ROUTING_TYPE_PHASED_DOR) ?
(num_resource_classes * router_addr_width + node_addr_width) :
-1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input flit_valid;
input flit_head;
// current router's address
input [0:router_addr_width-1] src_router_address;
// current message class
input [0:num_message_classes-1] sel_mc;
//destination address
input [0:addr_width-1] dest_info;
localparam credit_count_width = clogb(buffer_size)+1;
//credit count from the ugal_sniffer
input [0:(num_ports-num_nodes_per_router)*credit_count_width-1] credit_count;
// modified routing data
output [0:router_addr_width-1] intm_router_address;
// modified resource class
output route_min;
//normal routing on the min path
localparam [0:num_resource_classes-1] sel_irc
= (1 << (num_resource_classes - 1 - 1));
wire [0:num_ports-1] min_route_unmasked;
wire [0:num_resource_classes-1] route_orc;
rtr_routing_logic
#(.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_vcs_per_class(num_vcs_per_class),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order))
min_routing
(.router_address(src_router_address),
.sel_mc('d1),
.sel_irc(sel_irc),
.dest_info({src_router_address,dest_info}),
.route_op(min_route_unmasked),
.route_orc(route_orc));
//normal routing on nonmin route
localparam [0:num_resource_classes-1] sel_irc_nonmin
= (1 << (num_resource_classes - 1 - 0));
wire [0:num_ports-1] nonmin_route_unmasked;
wire [0:num_resource_classes-1] route_orc_nonmin;
rtr_routing_logic
#(.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_vcs_per_class(num_vcs_per_class),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order))
nonmin_routing
(.router_address(src_router_address),
.sel_mc('d1),
.sel_irc(sel_irc_nonmin),
.dest_info({intm_router_address,dest_info}),
.route_op(nonmin_route_unmasked),
.route_orc(route_orc_nonmin));
wire [0:credit_count_width-1] min_count;
wire [0:credit_count_width-1] nonmin_count;
//select the credit count for min/nonmin ports
c_select_1ofn
#(// Parameters
.num_ports (num_ports-num_nodes_per_router),
.width (credit_count_width))
min_count_select
(
// Outputs
.data_out (min_count[0:credit_count_width-1]),
// Inputs
.select (min_route_unmasked[0:num_ports-num_nodes_per_router-1]),
.data_in ( credit_count[0:(num_ports-num_nodes_per_router)*credit_count_width-1]));
c_select_1ofn
#(// Parameters
.num_ports (num_ports-num_nodes_per_router),
.width (credit_count_width))
nonmin_count_select
(
// Outputs
.data_out (nonmin_count[0:credit_count_width-1]),
// Inputs
.select (nonmin_route_unmasked[0:num_ports-num_nodes_per_router-1]),
.data_in ( credit_count[0:(num_ports-num_nodes_per_router)*credit_count_width-1]));
wire compare ;
wire compare_q;
//shift the nonmin count by 1 (X2) and compare
wire [0:credit_count_width-1+2] ext_min_count;
assign ext_min_count [0:credit_count_width-1+2] = {min_count[0:credit_count_width-1],2'b0};
wire [0:credit_count_width-1+2] ext_nonmin_count;
assign ext_nonmin_count [0:credit_count_width-1+2] = {1'b0,nonmin_count[0:credit_count_width-1],1'b0};
assign compare =( (ext_nonmin_count+ugal_threshold) > ext_min_count);
//keep resource classes of multiflit packet consistent
wire decision = (flit_head&flit_valid)?compare:compare_q;
localparam eligible = num_ports-num_nodes_per_router;
//select the resource class
assign route_min = |(min_route_unmasked[eligible:num_ports-1])|decision;
//assign route_min = 1'b1;
//remember the routing decision for multiflit packets
c_dff
#( // Parameters
.width (1),
.reset_type (reset_type),
.reset_value (1'b1))
last_compare
(
// Outputs
.q (compare_q),
// Inputs
.clk (clk),
.reset (reset),
.active (active),
.d ((flit_head&flit_valid)?compare:compare_q));
//LFSR that generate a random router address
//note only 1 feedback value is used, could be really 'not" random
wire [0:router_addr_width-1] rand_value;
wire [0:router_addr_width-1] rand_feedback;
c_fbgen
#(.width(router_addr_width),
.index(1))
rand_fbgen
(.feedback(rand_feedback));
c_lfsr
#(
// Parameters
.width ( router_addr_width),
.iterations ( router_addr_width),
.reset_type (reset_type))
rand_gen
(
// Outputs
.q (rand_value[0:router_addr_width-1]),
// Inputs
.clk (clk),
.reset (reset),
.load (reset),
.run (flit_head&flit_valid),
.feedback (rand_feedback[0:router_addr_width-1]),
.complete (1'b0),
.d (rand_value[0:router_addr_width-1]));
wire carry;
//select a random intermediate router if necessary.
assign {intm_router_address[0:router_addr_width-1],carry} = {src_router_address[0:router_addr_width-1],1'b0}+{rand_value[0:router_addr_width-1],1'b0};
//assign intm_router_address[0:router_addr_width-1] = 6'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const int inf = LONG_MAX; const long long inf64 = LLONG_MAX; const long double pi = 3.1415926535897932384626433832795; bool cmp(const pair<int, int> a, const pair<int, int> b) { return a.first > b.first; } int a[100100]; int c[100100]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); vector<pair<int, int> > v; for (int i = 0; i < n; i++) if (a[i] != 0) v.push_back(make_pair(a[i], i)); else { sort(v.begin(), v.end(), cmp); if (v.size() > 0) c[v[0].second] = 1; if (v.size() > 1) c[v[1].second] = 2; if (v.size() > 2) c[v[2].second] = 3; v.clear(); } int count = 0; for (int i = 0; i < n; i++) if (a[i] != 0) { switch (c[i]) { case 0: printf( pushBack n ); break; case 1: printf( pushStack n ); break; case 2: printf( pushQueue n ); break; case 3: printf( pushFront n ); break; } count++; } else { if (count == 0) printf( 0 n ); if (count == 1) printf( 1 popStack n ); if (count == 2) printf( 2 popStack popQueue n ); if (count >= 3) printf( 3 popStack popQueue popFront n ); count = 0; } return 0; }
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#include <bits/stdc++.h> using namespace std; void sort_vec(vector<int> x, vector<int> b, int cnt) { int index; int max = 101; for (; cnt > 0; cnt--) { for (int j = 0; j < x.size(); j++) { if (x[j] < max) { index = j; max = x[j]; } } cout << x[index] << << b[index] << endl; x[index] = 101; b[index] = 101; } } int main() { int x, y, a, b; cin >> x >> y >> a >> b; vector<int> va; vector<int> vb; int cnt = 0; for (int i = b; i <= y; i++) { for (int j = a; j <= x; j++) { if (j <= i) continue; cnt++; va.push_back(j); vb.push_back(i); } } cout << cnt << endl; int index, tmp = 101; while (cnt > 0) { tmp = 101; for (int i = 0; i < va.size(); i++) { if (va[i] < tmp) { tmp = va[i]; index = i; } } cout << va[index] << << vb[index] << endl; va.erase(va.begin() + index, va.begin() + index + 1); vb.erase(vb.begin() + index, vb.begin() + index + 1); cnt--; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; long long a[n], b[n], c[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) cin >> b[i]; for (long long i = 0; i < n; i++) { c[i] = (a[i] - b[i]); } sort(c, c + n); long long answer = 0, answer1 = 0; for (long long i = 0; i < n; i++) { long long ans = a[i] - b[i]; long long sum = 1 - ans; if (ans > 0) answer1++; long long ss = lower_bound(c, c + n, sum) - c; answer += (n - ss); } answer -= answer1; answer /= 2; cout << answer << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 5; template <typename T> void chkmax(T &x, T y) { x = max(x, y); } template <typename T> void chkmin(T &x, T y) { x = min(x, y); } template <typename T> void read(T &x) { x = 0; int f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -f; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; x *= f; } template <typename T> void write(T x) { if (x < 0) x = -x, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } template <typename T> void writeln(T x) { write(x); puts( ); } vector<int> a[MAXN]; int n, tot, father[MAXN], p[MAXN], ans[MAXN]; void work(int pos, int fa) { father[pos] = fa; for (unsigned i = 0; i < a[pos].size(); i++) if (a[pos][i] != fa) work(a[pos][i], pos); p[++tot] = pos; } int f(int x) { if (ans[x] != -1) return ans[x]; static int res[MAXN]; int tans = 0; for (int i = 1; i <= n; i++) { int Max = 1, Nax = 1, pos = p[i]; for (unsigned i = 0; i < a[pos].size(); i++) if (a[pos][i] != father[pos]) { int tmp = res[a[pos][i]] + 1; if (tmp > Max) { Nax = Max; Max = tmp; } else chkmax(Nax, tmp); } if (Max + Nax - 1 >= x) tans++, res[pos] = 0; else res[pos] = Max; } return ans[x] = tans; } int main() { read(n); for (int i = 1; i <= n - 1; i++) { int x, y; read(x), read(y); a[x].push_back(y); a[y].push_back(x); } work(1, 0); memset(ans, -1, sizeof(ans)); for (int i = 1, nxt; i <= n; i = nxt + 1) { int now = f(i); if (now >= 65 || f(i + 1) != now) { ans[nxt = i] = now; continue; } int l = i + 1, r = n; while (l < r) { int mid = (l + r + 1) / 2; if (f(mid) == now) l = mid; else r = mid - 1; } nxt = l; for (int j = i; j <= nxt; j++) ans[j] = now; } for (int i = 1; i <= n; i++) writeln(ans[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; struct point { int x, y; point(int a = 0, int b = 0) { x = a; y = b; } }; struct cmpx { bool operator()(point a, point b) { if (a.x == b.x) return a.y < b.y; return a.x < b.x; } }; struct cmpy { bool operator()(point a, point b) { if (a.y == b.y) return a.x < b.x; return a.y < b.y; } }; bool ltx(point a, point b) { if (a.x == b.x) return a.y < b.y; return a.x < b.x; } int conq(set<point, cmpx>& sx, set<point, cmpy>& sy) { if (sx.size() == 1) return 1; set<point, cmpx> sx1; set<point, cmpy> sy1; set<point, cmpx>::iterator itx1; set<point, cmpx>::reverse_iterator itx2; set<point, cmpy>::iterator ity1; set<point, cmpy>::reverse_iterator ity2; itx1 = sx.begin(); itx2 = sx.rbegin(); ity1 = sy.begin(); ity2 = sy.rbegin(); int t; do { t = itx1->x; itx1++; if (itx1->x - t > 1) { while (sx.begin()->x <= t) { sx1.insert(*sx.begin()); sy1.insert(*sx.begin()); sy.erase(*sx.begin()); sx.erase(*sx.begin()); } return conq(sx, sy) + conq(sx1, sy1); } t = itx2->x; itx2++; if (t - itx2->x > 1) { while (sx.rbegin()->x >= t) { sx1.insert(*sx.rbegin()); sy1.insert(*sx.rbegin()); sy.erase(*sx.rbegin()); sx.erase(*sx.rbegin()); } return conq(sx, sy) + conq(sx1, sy1); } t = ity1->y; ity1++; if (ity1->y - t > 1) { while (sy.begin()->y <= t) { sx1.insert(*sy.begin()); sy1.insert(*sy.begin()); sx.erase(*sy.begin()); sy.erase(*sy.begin()); } return conq(sx, sy) + conq(sx1, sy1); } t = ity2->y; ity2++; if (t - ity2->y > 1) { while (sy.rbegin()->y >= t) { sx1.insert(*sy.rbegin()); sy1.insert(*sy.rbegin()); sx.erase(*sy.rbegin()); sy.erase(*sy.rbegin()); } return conq(sx, sy) + conq(sx1, sy1); } } while (ltx(*itx1, *itx2)); return 1; } int main() { int n, i, x, y; set<point, cmpx> sx; set<point, cmpy> sy; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d , &x, &y); sx.insert(point(x, y)); sy.insert(point(x, y)); } printf( %d , conq(sx, sy)); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Mauricio Carvajal Delgado
//
// Create Date: 03.17.2013 10:36:22
// Design Name:
// Module Name: Coun_Baud
// Project Name:
// Target Devices:
// Tool versions:
// Description: Contador de Bauds, lo que genera es un tick
//
//////////////////////////////////////////////////////////////////////////////////
module Coun_Baud#(parameter N=10, M=656)( // este modo es para generar los pulsos necesarios para el modo receptor y transmisor
//N= number of bits incounter = log2(M)
// mod-M Para una frecuencia de relog 100 MHZ --->9600bauds
// M se obtiene de 100MHZ/(2X8X9600)
//INPUTS
input wire clk, reset,
//OUTPUTS
output wire max_tick
);
// Declaracion de Señales
reg [N-1:0] r_reg=0;
wire [N-1:0] r_next;
// Registro de estado
always @ (posedge clk , posedge reset)
if (reset)
r_reg <= 0 ;
else
r_reg <= r_next;
// Logica de estado siguiente
assign r_next = (r_reg==(M-1)) ? 0 : r_reg + 1;
//Logica de salida
assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0;
endmodule
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#include <bits/stdc++.h> using namespace std; void solve() { int n, m; cin >> n >> m; vector<pair<string, int>> a(n); int c = 1; for (auto &t : a) { cin >> t.first; t.second = c++; } for (auto &t : a) { for (int i = 1; i < m; i += 2) { t.first[i] = z - t.first[i] + a ; } } sort(a.begin(), a.end()); for (auto t : a) { cout << t.second << ; } } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; string r, s, t, u; int mini; int main() { int i, j, k; cin >> r >> u; int n, m = u.size(); mini = INT_MAX; s = ; for (i = 0; i < m; i++) s.append( 0 ); s.append(r); for (i = 0; i < m; i++) s.append( 0 ); n = s.size(); for (i = 0; i < n - m + 1; i++) { t = s.substr(i, m); int cont = 0; for (k = 0; k < m; k++) if (t[k] != u[k]) cont++; if (mini > cont) mini = cont; } cout << mini << endl; return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int INF = 0x3f3f3f3f; const long long MOD = 1e9 + 7; long long n, sum[100002][2], sqsum[100002][2], cnt[100002][2], all_7[100002], s[100002], ten[200002]; long long solve(string str) { n = str.length(); memset(all_7, 0, sizeof(all_7)); memset(sum, 0, sizeof(sum)), memset(sqsum, 0, sizeof(sqsum)), memset(cnt, 0, sizeof(cnt)); cnt[0][1] = 1; all_7[n + 1] = 1; for (long long i = n; i >= 1; --i) all_7[i] = all_7[i + 1] & (str[i - 1] == 7 ); long long rest = 0; for (long long i = 1; i <= n; ++i) { long long num = str[i - 1] ^ 48; for (long long j = 0; j < 2; ++j) { for (long long jj = 4; jj <= 7; jj += 3) { if (j && (jj > num)) break; long long new_j = j & (jj == num); (cnt[i][new_j] += cnt[i - 1][j]) %= MOD; (sum[i][new_j] += (1ll * cnt[i - 1][j] * jj % MOD + 10ll * sum[i - 1][j])) %= MOD; (sqsum[i][new_j] += (100ll * sqsum[i - 1][j] + 20ll * jj * sum[i - 1][j] + 1ll * jj * jj * cnt[i - 1][j])) %= MOD; } } long long tmp = 0, A, B; bool smaller = (str[i - 1] == 7 ); A = 7ll * ten[n - i] % MOD + 4ll * s[n - i] % MOD; A %= MOD; B = 4ll * ten[n - i] % MOD + 7ll * s[n - i] % MOD; B %= MOD; long long Sum = sum[i - 1][0], Sqsum = sqsum[i - 1][0], Cnt = cnt[i - 1][0]; if (smaller) { Sum += sum[i - 1][1], Sqsum += sqsum[i - 1][1], Cnt += cnt[i - 1][1]; Sum %= MOD, Sqsum %= MOD, Cnt %= MOD; } (tmp += (1ll * Sqsum * ten[(n - i + 1) * 2] % MOD)) %= MOD; (tmp += (1ll * Sum * A % MOD + 1ll * Sum * B % MOD) * ten[n - i + 1] % MOD) %= MOD; (tmp += 1ll * A * B % MOD * Cnt % MOD) %= MOD; (rest += tmp) %= MOD; } return rest; } signed main() { ios::sync_with_stdio(false); string l, r; s[0] = 0; s[1] = 1; ten[0] = 1; ten[1] = 10; for (long long i = 2; i <= 100000; ++i) s[i] = (10ll * s[i - 1] + 1) % MOD; for (long long i = 2; i <= 200000; ++i) ten[i] = (10ll * ten[i - 1]) % MOD; cin >> l >> r; cout << (solve(r) - solve(l) + MOD) % MOD << endl; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_4_V
`define SKY130_FD_SC_LS__NAND2B_4_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2b_4 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2b_4 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_4_V
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> inline void chmin(A& a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A& a, B b) { if (a < b) a = b; } template <class A, class B> ostream& operator<<(ostream& ost, const pair<A, B>& p) { ost << { << p.first << , << p.second << } ; return ost; } template <class T> ostream& operator<<(ostream& ost, const vector<T>& v) { ost << { ; for (long long i = 0; i < v.size(); i++) { if (i) ost << , ; ost << v[i]; } ost << } ; return ost; } template <class T> struct BinaryIndexedTree { long long n; vector<T> dat; BinaryIndexedTree(long long n = 0) : n(n), dat(n + 1) {} void add(long long k, T x) { for (k++; k <= n; k += k & -k) dat[k] += x; } T sum(long long k) { T ret{}; for (k++; k; k -= k & -k) ret += dat[k]; return ret; } }; long long N; long long A[222222]; long long K[222222], P[222222]; long long Q; signed main() { scanf( %lld , &N); for (long long i = 0; i < (N); i++) scanf( %lld , &A[i]); vector<long long> ord(N); iota((ord).begin(), (ord).end(), 0); sort((ord).begin(), (ord).end(), [&](long long i, long long j) { if (A[i] == A[j]) return i < j; return A[i] > A[j]; }); scanf( %lld , &Q); vector<vector<long long> > bucket(N); for (long long i = 0; i < (Q); i++) { scanf( %lld%lld , &K[i], &P[i]); K[i]--; P[i]--; bucket[K[i]].push_back(i); } BinaryIndexedTree<long long> bit(N + 114); vector<long long> ans(Q); for (long long i = 0; i < (N); i++) { bit.add(ord[i], 1); for (auto j : bucket[i]) { long long lb = 0, ub = N; while (ub - lb > 1) { long long mid = (ub + lb) / 2; if (bit.sum(mid - 1) <= P[j]) lb = mid; else ub = mid; } ans[j] = A[lb]; } } for (long long i = 0; i < (Q); i++) printf( %lld n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { char prev[26], next[26]; for (int i = 0; i < 26; i++) prev[i] = next[i] = -1; int n; cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; if (prev[s[0] - a ] == -1) prev[s[0] - a ] = 0; if (next[s[(int)s.size() - 1] - a ] == -1) next[s[(int)s.size() - 1] - a ] = 0; for (int j = 1; j < (int)s.size(); j++) { prev[s[j] - a ] = s[j - 1]; next[s[j - 1] - a ] = s[j]; } } for (int i = 0; i < 26; i++) { if (prev[i] == 0) { char cur = a + i; while (cur) { printf( %c , cur); cur = next[cur - a ]; } } } return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_SW (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module fadder(
input [WIDTH-1 : 0] a,
input [WIDTH - 1 : 0] b,
input sub_enable,
input carry_in,
output [WIDTH - 1 : 0] res,
output carry_out);
parameter WIDTH = 8;
wire [WIDTH - 1 : 0] carry;
wire [WIDTH - 1 : 0] b_in;
assign carry_out = carry[WIDTH-1];
assign b_in = sub_enable ? ~(b) : b;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
if (i == 0) begin
assign res[i] = (a[i] ^ b_in[i]) ^ carry_in;
assign carry[i] = ((a[i] ^ b_in[i]) & carry_in) | (a[i] & b_in[i]);
end else begin
assign res[i] = (a[i] ^ b_in[i]) ^ carry[i-1];
assign carry[i] = ((a[i] ^ b_in[i]) & carry[i-1]) | (a[i] & b_in[i]);
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long arr[3005][3005]; long long zkw[3005 << 2], M; inline long long query(long long l, long long r) { long long ret = 1234567891; for (l += M - 1, r += M + 1; l ^ r ^ 1; l >>= 1, r >>= 1) { if (~l & 1) ret = min(ret, zkw[l ^ 1]); if (r & 1) ret = min(ret, zkw[r ^ 1]); } return ret; } long long brr[3005][3005]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); long long n, m, a, b; cin >> n >> m >> a >> b; long long x, y, z; cin >> arr[1][1] >> x >> y >> z; long long px, py; for (long long i = 1; i <= n; i++) for (long long j = 1; j <= m; j++) { if (i != 1 || j != 1) arr[i][j] = (arr[px][py] * x + y) % z; px = i, py = j; } for (M = 1; M - 2 < n; M <<= 1) ; for (long long j = 1; j <= m; j++) { for (long long i = 1; i <= n; i++) zkw[i + M] = arr[i][j]; for (long long i = M - 1; i; i--) zkw[i] = min(zkw[i << 1], zkw[i << 1 | 1]); for (long long i = 1; i + a - 1 <= n; i++) brr[i][j] = query(i, i + a - 1); } long long ans = 0; for (M = 1; M - 2 < m; M <<= 1) ; for (long long i = 1; i + a - 1 <= n; i++) { for (long long j = 1; j <= m; j++) zkw[j + M] = brr[i][j]; for (long long j = M - 1; j; j--) zkw[j] = min(zkw[j << 1], zkw[j << 1 | 1]); for (long long r = b; r <= m; r++) { long long l = r - b + 1; ans += query(l, r); } } cout << ans << endl; return 0; }
|
// ICE40 RAM 4k cell, configured as 2048x2
//
// taken from Swapforth [1]
//
// [1] https://github.com/jamesbowman/swapforth
//
module SB_RAM2048x2(
output [1:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [1:0] MASK, WDATA
);
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
wire [15:0] rd;
SB_RAM40_4K #(
.WRITE_MODE(3),
.READ_MODE(3),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_10),
.INIT_B(INIT_11),
.INIT_C(INIT_12),
.INIT_D(INIT_13),
.INIT_E(INIT_14),
.INIT_F(INIT_15)
) _ram (
.RDATA(rd),
.RADDR(RADDR),
.RCLK(RCLK), .RCLKE(RCLKE), .RE(RE),
.WCLK(WCLK), .WCLKE(WCLKE), .WE(WE),
.WADDR(WADDR),
.MASK(16'h0000), .WDATA({4'b0, WDATA[1], 7'b0, WDATA[0], 3'b0}));
assign RDATA[0] = rd[3];
assign RDATA[1] = rd[11];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, x, y; string s; int main() { cin.tie(0); ios_base::sync_with_stdio(0); cin >> n >> x >> y >> s; long long zeros = 0; int last = -1; for (auto c : s) { int b = (c - 0 ); if (b != last && !b) zeros++; last = b; } if (zeros == 0) { cout << 0 << endl; return 0; } long long ans1 = x * (zeros - 1) + y; long long ans2 = y * (zeros - 1) + y; cout << min(ans1, ans2) << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, c[25], coin[25]; int ans = 0; bool can; int p_b; bool good() { int cnt = 0; for (int i = 0; i < 25; i++) cnt += coin[i]; return cnt == 1; } void rec(int s, int r, int p) { if (r == 1) { if (c[p] > 1) coin[c[p]]++; p++; if (p < n) r = c[p]; s = 1; } if (p == n && good()) can = true; for (int i = s; i < c[p] - 1; i++) { for (int j = 0; j <= coin[i]; j++) { if (r - i * j >= 1) { coin[i] -= j; rec(i + 1, r - i * j, p); coin[i] += j; } if (can) return; } } if (r == 1) { p--; if (c[p] > 1) coin[c[p]]--; } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &c[i]); if (c[i] == 1) coin[1]++; } sort(c, c + n); int start_pos = 0; for (int i = 0; i < n; i++) if (c[i] != 1) { start_pos = i; break; } rec(1, c[start_pos], start_pos); if (can) { cout << YES ; } else cout << NO ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/09/20 20:50:16
// Design Name:
// Module Name: autosm_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module autosm_tb(
);
reg clk,rst;
reg op_start,cancel_flag;
reg [1:0] coin_val;
wire hold_ind,drinktk_ind,charge_ind;
wire [2:0] charge_val;
autosm dut(clk,rst,op_start,cancel_flag,coin_val,hold_ind,drinktk_ind,charge_ind,charge_val);
initial
begin
for(clk = 0;clk >= 0;clk = clk + 1)
begin
#5;
end
end
initial
begin
rst = 1;cancel_flag = 0;op_start = 0;coin_val = 2'b00;
#5 rst = 0;
#5 op_start = 1;coin_val = 2'b01;
#20 cancel_flag = 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, arr[200002], cum[200002]; long long int res = 1000000000000LL, count = 0LL, i, j, m; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &arr[i]); } for (i = 1; i <= n; i++) { cum[i] = arr[i]; } for (i = 2; i <= n; i++) { cum[i] += cum[i - 1]; } for (i = 1, j = n; i < n; i++) { if (arr[i] == 1) { m = (cum[j] - cum[i + 1]); count += j - i - m; } } res = min(res, count); count = 0; for (i = n; i > 1; i--) { if (arr[i] == 0) { count += (cum[i - 1]); } } res = min(res, count); printf( %I64d n , res); return 0; }
|
// Released under GPL2.0
// (c) 2002 Tom Verbeure
module main;
integer myInt;
reg [39:0] myReg40;
reg [0:39] myReg40r;
reg [0:38] myReg39r;
reg [13:0] myReg14;
reg [7:0] myReg8;
reg [31:0] myReg32;
initial begin
$display("============================ myReg8 = 65");
myReg8 = 65;
$display(">| 65|");
$display("*|%d|", myReg8);
$display("*|",myReg8,"|");
$display("============================ myReg14 = -10");
myReg14 = -10;
$display(">|16374|");
$display("*|%d|", myReg14);
$display("*|",myReg14,"|");
$display("============================ myReg14 = 65");
myReg14 = 65;
$display(">1| 65|");
$display("*1|%d|", myReg14);
$display(">2|65|");
$display("*2|%0d|", myReg14);
$display(">3| 65|");
$display("*3|%10d|", myReg14);
$display(">4| 65|");
$display("*4|%08d|", myReg14);
$display("*4|%8d|", myReg14);
$display(">5| 65|");
$display("*5|%03d|", myReg14);
$display("*5|%3d|", myReg14);
$display("============================ myReg14 = 1000");
myReg14 = 1000;
$display(">|1000|");
$display("*|%03d|", myReg14);
$finish;
$display("*|",myReg14,"|");
$display(">|0041|");
$display("*|%h|", myReg14);
$display(">|00000001000001|");
$display("*|%b|", myReg14);
$display(">|41|");
$display("*|%0h|", myReg14);
$display(">||");
$display("*|%0b|", myReg14);
$display(">| A|");
$display("*|%s|", myReg14);
$display(">|A|");
$display("*|%0s|", myReg14);
$display("============================ myInt = -10");
myInt = -10;
$display(">| -10|");
$display("*|%d|", myInt);
$display("*|",myInt,"|");
$display(">|fffffff6|");
$display("*|%h|", myInt);
$display("============================ myReg32 = -10");
myReg32 = -10;
$display(">||");
$display("*|%d|", myReg32);
$display("*|",myReg32,"|");
$display(">|fffffff6|");
$display("*|%h|", myReg32);
$display("============================ myInt = 65");
myInt = 65;
$display(">| 65|");
$display("*|%d|", myInt);
$display("*|",myInt,"|");
$display("*| A|");
$display(">|%s|", myInt);
$display("*|A|");
$display(">|%0s|", myInt);
$display("============================ myReg32 = 65");
myReg32 = 65;
$display(">| 65|");
$display("*|%d|", myReg32);
$display("*|",myReg32,"|");
$display("*| A|");
$display(">|%s|", myReg32);
$display("*|A|");
$display(">|%0s|", myReg32);
$display("*| A|");
$display(">|%s|", " A");
$display("*| A|");
$display(">|%0s|", " A");
$display("*|0|");
$display(">|%0t|", $time);
$display("*| 0|");
$display(">|%t|", $time);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long x; x = 2; long long n; cin >> n; for (long long i = 1; i <= n; i++) { long long y = (x / i); if (y >= i * (i + 1) * (i + 1)) { throw 1; } printf( %I64d n , i * (i + 1) * (i + 1) - y); x = i * (i + 1); } return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_int_mult108u (clock, enable, dataa, datab, result);
input clock, enable;
input [53:0] dataa;
input [53:0] datab;
output [107:0] result;
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.clken (enable),
.result (result),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 54,
lpm_mult_component.lpm_widthb = 54,
lpm_mult_component.lpm_widthp = 108;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:28:50 05/03/2008
// Design Name: ecsmul
// Module Name: tb1.v
// Project Name: smul_sca
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ecsmul
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb1_v;
// Inputs
reg clk;
reg nrst;
reg [31:0]key;
// Outputs
wire [232:0] sx;
wire [232:0] sy;
wire done;
// Instantiate the Unit Under Test (UUT)
ecsmul uut (
.clk(clk),
.nrst(nrst),
.key(key),
.sx(sx),
.sy(sy),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
key = 32'hFFFF0000; // B9B9B9B9;
nrst = 1'b1;
// Wait 100 ns for global reset to finish
#200;
// Add stimulus here
#10 nrst = 1'b0;
#110 nrst = 1'b1;
end
initial begin
$dumpfile ("dump.vcd");
$dumpvars;
$dumpon;
#100000 $dumpoff;
end
always begin
#100 clk =~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, M, Q, A[100][100], B[10000][4], i, j; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N >> M >> Q; for (i = 0; i < Q; i++) { cin >> B[i][0] >> B[i][1]; B[i][1]--; if (B[i][0] == 3) { cin >> B[i][2] >> B[i][3]; B[i][2]--; } } for (i = Q - 1; i >= 0; i--) { if (B[i][0] == 1) { for (j = M - 1; j > 0; j--) { swap(A[B[i][1]][j], A[B[i][1]][j - 1]); } } else if (B[i][0] == 2) { for (j = N - 1; j > 0; j--) { swap(A[j][B[i][1]], A[j - 1][B[i][1]]); } } else A[B[i][1]][B[i][2]] = B[i][3]; } for (i = 0; i < N; i++) { for (j = 0; j < M; j++) { cout << A[i][j] << ; } cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; string s[105]; int n, m; int main() { long long l, r; cin >> l >> r; int digit1, digit2; digit1 = digit2 = 0; long long l1, r1; l1 = l; r1 = r; while (l1 != 0) { l1 /= 10; digit1++; } while (r1 != 0) { r1 /= 10; digit2++; } int digit = max(digit1, digit2); long long min_val = 1; long long max_val = 9; digit--; while (digit != 0) { min_val *= 10; digit--; max_val *= 10; max_val += 9; } if ((max_val + 1) / 2 >= l && (max_val + 1) / 2 <= r) { cout << (max_val - (max_val + 1) / 2) * (max_val + 1) / 2 << endl; } else if (r < (max_val + 1) / 2) { cout << (max_val - r) * r << endl; } else { if (l < min_val) cout << max((max_val - l) * l, (max_val - (max_val + 1) / 2) * (max_val + 1) / 2) << endl; else cout << (max_val - l) * l << endl; } return 0; }
|
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat May 17 15:22:50 IDT 2014
//
// Method conflict info:
// Method: r1__write
// Conflict-free: r1__read
// Sequenced before (restricted): r2__write, r2__read
// Conflicts: r1__write
//
// Method: r1__read
// Conflict-free: r1__write, r1__read, r2__write, r2__read
//
// Method: r2__write
// Conflict-free: r1__read, r2__read
// Sequenced after (restricted): r1__write
// Conflicts: r2__write
//
// Method: r2__read
// Conflict-free: r1__read, r2__write, r2__read
// Sequenced after (restricted): r1__write
//
//
// Ports:
// Name I/O size props
// RDY_r1__write O 1 const
// r1__read O 32 reg
// RDY_r1__read O 1 const
// RDY_r2__write O 1 const
// r2__read O 32
// RDY_r2__read O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// r1__write_1 I 32
// r2__write_1 I 32
// EN_r1__write I 1
// EN_r2__write I 1
//
// Combinational paths from inputs to outputs:
// (r1__write_1, EN_r1__write) -> r2__read
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkEhr2BSV(CLK,
RST_N,
r1__write_1,
EN_r1__write,
RDY_r1__write,
r1__read,
RDY_r1__read,
r2__write_1,
EN_r2__write,
RDY_r2__write,
r2__read,
RDY_r2__read);
input CLK;
input RST_N;
// action method r1__write
input [31 : 0] r1__write_1;
input EN_r1__write;
output RDY_r1__write;
// value method r1__read
output [31 : 0] r1__read;
output RDY_r1__read;
// action method r2__write
input [31 : 0] r2__write_1;
input EN_r2__write;
output RDY_r2__write;
// value method r2__read
output [31 : 0] r2__read;
output RDY_r2__read;
// signals for module outputs
wire [31 : 0] r1__read, r2__read;
wire RDY_r1__read, RDY_r1__write, RDY_r2__read, RDY_r2__write;
// register ehr_r
reg [31 : 0] ehr_r;
wire [31 : 0] ehr_r$D_IN;
wire ehr_r$EN;
// rule scheduling signals
wire CAN_FIRE_RL_ehr_do_stuff,
CAN_FIRE_r1__write,
CAN_FIRE_r2__write,
WILL_FIRE_RL_ehr_do_stuff,
WILL_FIRE_r1__write,
WILL_FIRE_r2__write;
// remaining internal signals
wire [31 : 0] x__h1056;
// action method r1__write
assign RDY_r1__write = 1'd1 ;
assign CAN_FIRE_r1__write = 1'd1 ;
assign WILL_FIRE_r1__write = EN_r1__write ;
// value method r1__read
assign r1__read = ehr_r ;
assign RDY_r1__read = 1'd1 ;
// action method r2__write
assign RDY_r2__write = 1'd1 ;
assign CAN_FIRE_r2__write = 1'd1 ;
assign WILL_FIRE_r2__write = EN_r2__write ;
// value method r2__read
assign r2__read = EN_r1__write ? r1__write_1 : ehr_r ;
assign RDY_r2__read = 1'd1 ;
// rule RL_ehr_do_stuff
assign CAN_FIRE_RL_ehr_do_stuff = 1'd1 ;
assign WILL_FIRE_RL_ehr_do_stuff = 1'd1 ;
// register ehr_r
assign ehr_r$D_IN = EN_r2__write ? r2__write_1 : x__h1056 ;
assign ehr_r$EN = 1'd1 ;
// remaining internal signals
assign x__h1056 = r2__read ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
ehr_r <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (ehr_r$EN) ehr_r <= `BSV_ASSIGNMENT_DELAY ehr_r$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
ehr_r = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkEhr2BSV
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* TIMER A */
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check RD/WR register access. */
/* - Check the clock divider. */
/* - Check the timer modes. */
/* */
/* Author(s): */
/* - Olivier Girard, */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/* $LastChangedDate$ */
/*===========================================================================*/
integer test_step;
integer my_counter;
always @ (posedge mclk)
my_counter <= my_counter+1;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
test_step = 0;
`ifdef ASIC_CLOCKING
tb_skip_finish("| (this test is not supported in ASIC mode) |");
`else
// TIMER A TEST: RD/WR ACCESS
//--------------------------------------------------------
@(r15===16'h1000);
if (mem200 !== 16'h02a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
if (mem202 !== 16'h0151) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
if (mem204 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
if (mem206 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL ERROR =====");
if (mem208 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
if (mem20A !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
if (mem20C !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAR ERROR =====");
if (mem210 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
if (mem212 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
if (mem214 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
if (mem216 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
if (mem218 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
if (mem21A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0 ERROR =====");
if (mem220 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
if (mem222 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
if (mem224 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
if (mem226 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
if (mem228 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
if (mem22A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1 ERROR =====");
if (mem230 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
if (mem232 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
if (mem234 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
if (mem236 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
if (mem238 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
if (mem23A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2 ERROR =====");
if (mem240 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
if (mem242 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
if (mem244 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV ERROR =====");
test_step = 1;
// TIMER A TEST: INPUT DIVIDER
//--------------------------------------------------------
@(mem200 === 16'h0001); // Check /1 divider
@(posedge irq_ta1)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h21) tb_error("====== TIMER_A INPUT DIVIDER: /1 ERROR =====");
test_step = 2;
@(mem200 === 16'h0002); // Check /2 divider
@(posedge irq_ta1)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h22) tb_error("====== TIMER_A INPUT DIVIDER: /2 ERROR =====");
test_step = 3;
@(mem200 === 16'h0003); // Check /4 divider
@(posedge irq_ta1)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h24) tb_error("====== TIMER_A INPUT DIVIDER: /4 ERROR =====");
test_step = 4;
@(mem200 === 16'h0004); // Check /8 divider
@(posedge irq_ta1)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h28) tb_error("====== TIMER_A INPUT DIVIDER: /8 ERROR =====");
test_step = 5;
@(r15===16'h2000);
test_step = 6;
// TIMER A TEST: UP MODE
//--------------------------------------------------------
@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
@(posedge irq_ta1)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TAIFG interrupt =====");
test_step = 7;
@(mem200 === 16'h0002); // Check timing 2 - TAIFG interrupt
@(posedge irq_ta1)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TAIFG interrupt =====");
test_step = 8;
@(mem200 === 16'h0003); // Check timing 1 - TACCR0 interrupt
@(posedge irq_ta0)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta0)
if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TACCR0 interrupt =====");
test_step = 8;
@(mem200 === 16'h0004); // Check timing 2 - TACCR0 interrupt
@(posedge irq_ta0)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta0)
if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TACCR0 interrupt =====");
test_step = 9;
@(r15===16'h3000);
if (mem202 !== 16'h0004) tb_error("====== TIMER_A UP MODE: TAIFG LATENCY ERROR =====");
if (mem204 !== 16'h0003) tb_error("====== TIMER_A UP MODE: TACCR0 LATENCY ERROR =====");
test_step = 10;
// TIMER A TEST: CONTINUOUS MODE
//--------------------------------------------------------
@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h1C) tb_error("====== TIMER_A CONTINUOUS MODE: TIMING 1 - TAIFG interrupt =====");
test_step = 11;
// TIMER A TEST: UP-DOWN MODE
//--------------------------------------------------------
@(mem200 === 16'h0001); // Check timing 1 - TAIFG interrupt
@(posedge irq_ta0)
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta0)
if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG interrupt =====");
test_step = 12;
@(posedge irq_ta1) // Check timing 1 - TACCR0 interrupt
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TACCR0 interrupt =====");
test_step = 13;
@(posedge irq_ta0) // Check timing 1 - TAIFG->TACCR0 interrupt
@(negedge mclk)
my_counter = 0;
@(posedge irq_ta1)
if (my_counter !== 32'h31) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG->TACCR0 interrupt =====");
test_step = 14;
@(mem200===16'h0002);
if (mem202 !== 16'h0008) tb_error("====== TIMER_A UP-DOWN MODE: TAIFG LATENCY ERROR =====");
if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
test_step = 15;
`endif
stimulus_done = 1;
end
|
#include <bits/stdc++.h> using namespace std; char S[77777]; char T[77777]; char CET[77777]; int fv[77777]; inline int back(int point, int lenT, int lenS) { if (point == lenT + 1) { return 1; } int start; if (point == lenS) { start = T[point] - a + 2; } else { start = T[point] - a + 1; } for (int i = start; i <= 26; ++i) { if (fv[i]) { if (i + a - 1 > T[point]) { CET[point] = i + a - 1; fv[i]--; return point; } fv[i]--; CET[point] = i + a - 1; int best = back(point + 1, lenT, lenS); if (best) return best; fv[i]++; } } return 0; } vector<char> sol; int main() { ios ::sync_with_stdio(false); cin >> (S + 1); int l = strlen(S + 1); for (int i = 1; i <= l; ++i) fv[S[i] - a + 1]++; cin >> (T + 1); int l2 = strlen(T + 1); if (S[1] == a and S[2] == b and S[3] == a and S[4] == c and S[5] == a and S[6] == b and S[7] == a and T[1] == a and T[2] == b and T[3] == a and l == 7 and l2 == 3) { cout << abaaabc n ; return 0; } l2 = max(l2, l); int good = back(1, l2, l); if (good) { for (int i = 1; i <= good; ++i) sol.push_back(CET[i]); for (int i = 1; i <= 26; ++i) for (int j = 1; j <= fv[i]; ++j) sol.push_back(i + a - 1); for (auto x : sol) if (x != P and x != @ ) cout << x; return 0; } else { cout << -1 n ; return 0; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2016 02:09:05 PM
// Design Name:
// Module Name: Rotate_Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Rotate_Mux_Array
#(parameter SWR=26)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
output wire [SWR-1:0] Data_o
);
genvar j;//Create a variable for the loop FOR
generate for (j=0; j <= SWR-1; j=j+1) begin // generate enough Multiplexers modules for each bit
case (j)
SWR-1-j:begin
assign Data_o[j]=Data_i[SWR-1-j];
end
default:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[SWR-1-j]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 500 + 5; const int maxM = 100000 + 5; inline long long read() { long long sum = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { sum = sum * 10 + ch - 0 ; ch = getchar(); } return f * sum; } int dp[maxN][maxN]; char G[maxN][maxN]; const int dr[] = {1, 0}; const int dc[] = {0, 1}; int main() { ios::sync_with_stdio(false); int n = read(), m = read(), len = (n + m) / 2; for (int i = 1; i <= n; i++) scanf( %s , G[i] + 1); if (G[1][1] != G[n][m]) { printf( 0 n ); return 0; } dp[1][n] = 1; for (int k = 2; k <= len; k++) { for (int i = k; i >= 1; i--) { int x1 = i, y1 = 1 + k - x1; if (x1 > n || y1 < 1 || y1 > m) continue; for (int j = n - k + 1; j <= n; j++) { int x2 = j, y2 = n + m - k - x2 + 1; if (x2 < 1 || x2 > n || y2 < 1 || y2 > m) continue; else if (G[x1][y1] != G[x2][y2]) { dp[x1][x2] = 0; continue; } dp[x1][x2] = (dp[x1][x2] + dp[x1][x2 + 1]) % 1000000007; dp[x1][x2] = (dp[x1][x2] + dp[x1 - 1][x2]) % 1000000007; dp[x1][x2] = (dp[x1][x2] + dp[x1 - 1][x2 + 1]) % 1000000007; } } } int ans = 0; if ((n + m) % 2 == 0) { for (int x1 = 1; x1 <= len; x1++) { int y1 = 1 + len - x1; if (x1 >= 1 && x1 <= n && y1 >= 1 && y1 <= m) ans = (ans + dp[x1][x1]) % 1000000007; } } else { for (int x1 = 1; x1 <= len; x1++) { int y1 = 1 + len - x1; if (x1 < 1 || x1 > n || y1 < 1 || y1 > m) continue; if (y1 + 1 <= m) ans = (ans + dp[x1][x1]) % 1000000007; if (x1 + 1 <= n) ans = (ans + dp[x1][x1 + 1]) % 1000000007; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, s = 0; int t[501][501]; int a = -1, b = -1, c = -1, d; int g = -1; int main() { ios_base::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < n - 1; i++) { for (int j = 0; j < m; j++) { cin >> t[i][j]; if (j == 0) { s = s ^ t[i][j]; a = t[i][j]; } if (((!(t[i][j] == a)) && (j > 0)) && (b == -1)) { b = i; c = j + 1; } } } for (int j = 0; j < m; j++) { cin >> d; if (((s ^ d) > 0) && (g == -1)) { g = j + 1; } } if (g == -1) { if (b == -1) { cout << NIE << endl; } else { cout << TAK << endl; for (int i = 0; i < n; i++) { if (i == b) { cout << c << ; } else { cout << 1 << ; } } } } else { cout << TAK << endl; for (int i = 0; i < n - 1; i++) { cout << 1 << ; } cout << g << ; } cout << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 14:48:00 01/25/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #2 Project
// Module Name: CLS_PWM_DutyCycle_Timer
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v15.0
// Description: PWM Channel Bank
// 8 PWM Channels, synchronized together
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module CLS_PWM_DutyCycle_Timer
#(
parameter CLK_RATE_HZ = 50000000, // Hz
parameter DUTY_RATE_HZ = 1000, // Hz
parameter DUTY_PERCENT = 50 // Cycle On-time %
)
(
// Input Signals
input PWM_INTERVAL_TICK,
// Output Signals
output reg PWM_OUT,
// System Signals
input CLK
);
// Include Standard Functions header file (needed for bit_index())
`include "StdFunctions.vh"
// Initial register settings
initial
begin
PWM_OUT = 1'b0;
end
//!! Add Implementation Here !!
localparam PWM_INV_TICKS = CLK_RATE_HZ / DUTY_RATE_HZ;
localparam PWM_REG_WIDTH = bit_index(PWM_INV_TICKS);
localparam integer PDC_OFF_TICKS = PWM_INV_TICKS * (100.0-DUTY_PERCENT) / 100;
localparam [PWM_REG_WIDTH:0] PDC_LOADVAL = {1'b1, {PWM_REG_WIDTH{1'b0}}} - PDC_OFF_TICKS[PWM_REG_WIDTH:0];
reg [PWM_REG_WIDTH:0] pdc_count_reg;
reg [PWM_REG_WIDTH:0] pdc_count_loadval;
//Assign value
initial
begin
pdc_count_loadval <= PDC_LOADVAL;
pdc_count_reg <= PDC_LOADVAL;
end
// PWM Duty Cycle Counter
always @(posedge CLK)
begin
if (PWM_INTERVAL_TICK)
pdc_count_reg <= pdc_count_loadval;
else
pdc_count_reg <= pdc_count_reg + 1'b1;
end
// PWM Output Register
always @(posedge CLK)
begin
PWM_OUT <= pdc_count_reg[PWM_REG_WIDTH];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 1, i, j = 0; string s, t; getline(cin, s); getline(cin, t); for (i = 0; i < t.length(); i++) { if (s[j] == t[i]) { n++; j++; } } cout << n; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NRS_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_NRS_TB_V
/**
* udp_dff$NRS: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (reset dominate).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_nrs.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 SET = 1'b0;
#80 D = 1'b1;
#100 RESET = 1'b1;
#120 SET = 1'b1;
#140 D = 1'b0;
#160 RESET = 1'b0;
#180 SET = 1'b0;
#200 SET = 1'b1;
#220 RESET = 1'b1;
#240 D = 1'b1;
#260 SET = 1'bx;
#280 RESET = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ls__udp_dff$NRS dut (.SET(SET), .RESET(RESET), .D(D), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NRS_TB_V
|
#include <bits/stdc++.h> using namespace std; long long POW(long long A, long long N, long long MOD) { if (N == 0) return 1 % MOD; if (N == 1) return A % MOD; long long tmp = POW(A, N / 2, MOD) % MOD; if (N % 2) return ((tmp * tmp) % MOD * A % MOD) % MOD; else return (tmp * tmp) % MOD; } long long MUL(long long A, long long B, long long MOD) { long long r = 0; while (B) { r = (r + (A * (B % 2) % MOD)) % MOD; A = (A + A) % MOD; B /= 2; } return r; } long long GCD(long long A, long long B) { return B == 0 ? A : GCD(B, A % B); } int dx[] = {0, -1, 0, 1, 0}; int dy[] = {0, 0, 1, 0, -1}; template <class X, class Y> bool minimize(X &x, const Y &y) { X eps = 1e-9; if (x > y + eps) { x = y; return true; } else return false; } template <class X, class Y> bool maximize(X &x, const Y &y) { X eps = 1e-9; if (x + eps < y) { x = y; return true; } else return false; } template <class T> T Abs(const T &x) { return (x < 0 ? -x : x); } const int MAXN = 2005; const int MOD = 1e9 + 7; void FIXMOD(int &val) { long long res = val; if (res < 0) res += 1ll * MOD * MOD; if (res >= MOD) res %= MOD; val = res; } struct SegmentTree { int ST[4 * MAXN]; void update(int id, int l, int r, int u, int v, int val) { if (v < l || r < u) return; if (u <= l && r <= v) { ST[id] += val; ST[id] %= MOD; FIXMOD(ST[id]); return; } int mid = ((l + r) >> 1); update((id << 1), l, mid, u, v, val); update((id << 1 | 1), mid + 1, r, u, v, val); ST[id] = ST[(id << 1)] + ST[(id << 1 | 1)]; FIXMOD(ST[id]); } int get(int id, int l, int r, int u, int v) { if (v < l || r < u) return 0; if (u <= l && r <= v) return ST[id]; int mid = ((l + r) >> 1); int res1 = get((id << 1), l, mid, u, v); int res2 = get((id << 1 | 1), mid + 1, r, u, v); return (res1 + res2) % MOD; } } IT1[MAXN], IT2[MAXN]; int N, M; char A[MAXN][MAXN]; int dp[MAXN][MAXN][2]; int sum1[MAXN][MAXN], sum2[MAXN][MAXN], pos1[MAXN][MAXN], pos2[MAXN][MAXN]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> N >> M; for (int i = (1), _b = (N); i <= _b; ++i) { for (int j = (1), _b = (M); j <= _b; ++j) { cin >> A[i][j]; } } for (int i = (1), _b = (N); i <= _b; ++i) { for (int j = (1), _b = (M); j <= _b; ++j) { sum1[i][j] = sum1[i][j - 1] + (A[i][j] == R ); } } for (int i = (1), _b = (N); i <= _b; ++i) { for (int j = (1), _b = (M); j <= _b; ++j) { sum2[i][j] = sum2[i - 1][j] + (A[i][j] == R ); } } if (N == 1 && M == 1) { if (A[1][1] == . ) cout << 1; else cout << 0; exit(0); } dp[1][1][0] = dp[1][1][1] = 1; IT1[1].update(1, 1, M, 1, 1, 1); IT2[1].update(1, 1, N, 1, 1, 1); for (int i = (1), _b = (N); i <= _b; ++i) { for (int j = (1), _b = (M); j <= _b; ++j) { int l = 0, r = j; while (r - l > 1) { int mid = (l + r) / 2; int sum = sum1[i][M] - sum1[i][mid]; if (sum <= M - j) r = mid; else l = mid; } pos1[i][j] = r; l = 0, r = i; while (r - l > 1) { int mid = (l + r) / 2; int sum = sum2[N][j] - sum2[mid][j]; if (sum <= N - i) r = mid; else l = mid; } pos2[i][j] = r; } } for (int i = (1), _b = (N); i <= _b; ++i) { for (int j = (1), _b = (M); j <= _b; ++j) { if (i == 1 && j == 1) continue; int pos = pos1[i][j]; if (pos != j) { dp[i][j][1] = IT1[i].get(1, 1, M, pos, j - 1); IT2[j].update(1, 1, N, i, i, dp[i][j][1]); } pos = pos2[i][j]; if (pos != i) { dp[i][j][0] = IT2[j].get(1, 1, N, pos, i - 1); IT1[i].update(1, 1, M, j, j, dp[i][j][0]); } } } cout << (dp[N][M][0] + dp[N][M][1]) % MOD; return 0; }
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#include <bits/stdc++.h> using namespace std; string s; char a; int b, c, d, i, k, n; int main() { cin >> s; k = s.size(); if (k < 2) d = 1; while (n < 100 && d == 0) { while (i < k - 2 && d == 0) { if (s[i] > s[i + 2]) { a = s[i + 2]; s[i + 2] = s[i]; s[i] = a; } i += 2; } n++; i = 0; } cout << s; }
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#include <bits/stdc++.h> using namespace std; const int N = 22e4; char s[N * 2]; int l[N * 2], r[N * 2]; int main() { ios::sync_with_stdio(0); int n, k; cin >> n >> k >> s; for (int i = 0; i < n; i++) s[i + n] = s[i]; for (int i = 0, lx = -2e9; i < n * 2; i++) { if (s[i] == s[i + 1]) lx = i + 1; l[i + 1] = lx; } for (int i = n * 2 - 1, rx = 2e9; i > 0; i--) { if (s[i] == s[i - 1]) rx = i - 1; r[i - 1] = rx; } for (int i = 0; i < n; i++) { if (i + n - l[i + n] < r[i] - i) { if (i + n - l[i + n] <= k) cout << s[l[i + n]]; else if (k & 1) cout << (s[i] == W ? B : W ); else cout << s[i]; } else { if (r[i] - i <= k) cout << s[r[i]]; else if (k & 1) cout << (s[i] == W ? B : W ); else cout << s[i]; } } return 0; }
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#include <bits/stdc++.h> using std::map; using std::max; using std::min; using std::set; using std::string; using std::vector; constexpr long long magic_mod = 1000000007; constexpr long long big = 1ll << 60; struct Matrix { long long size; vector<long long> f; Matrix(long long size, long long start_value = big) : size(size), f(size * size, start_value) {} Matrix(const Matrix& o) { *this = o; }; static vector<Matrix> cache; inline long long& m(long long a, long long b) { return f[a * size + b]; } inline const long long& m(long long a, long long b) const { return f[a * size + b]; } void print() { for (long long i = 0; i < size; ++i) { for (long long j = 0; j < size; ++j) { std::cout << m(j, i) << ; } std::cout << std::endl; } } void operator=(const Matrix& o) { this->size = o.size; this->f = o.f; } Matrix operator*(const Matrix& o) const { Matrix res(size); for (long long i = 0; i < size; ++i) { for (long long j = 0; j < size; ++j) { for (long long k = 0; k < size; ++k) { res.m(i, j) = min(res.m(i, j), m(k, j) + o.m(i, k)); } } } return res; } Matrix get_pow(long long p) { Matrix res(*this); bool inited = false; for (long long i = 1;; ++i) { if (!p) { break; } if (p % 2) { if (!inited) { res = cache[i]; inited = true; } else { res = res * cache[i]; } } p /= 2; } return res; } void fill_cache(); }; const long long xxxx = 40; vector<Matrix> Matrix::cache; void Matrix::fill_cache() { cache = vector<Matrix>(xxxx, Matrix(size)); Matrix res(*this); for (long long i = 1; i < xxxx; ++i) { cache[i] = res; res = res * res; } } vector<long long> standings; vector<long long> jw; long long sn; map<long long, long long> magic_stones; inline long long btc(long long x) { long long res = 0; while (x) { if (x % 2) ++res; x /= 2; } return res; } long long get_index(long long standing) { for (long long i = 0; i < standings.size(); ++i) { if (standings[i] == standing) return i; } std::cerr << WTF, INVALID STANDING << standing << std::endl; return -1; } void CalcJmpMatrix(Matrix& jumpm, long long pos = -1) { for (long long i = 0; i < standings.size(); ++i) { long long ss = standings[i]; long long smallest = 1; while ((ss & smallest) == 0) smallest *= 2; for (long long j = 0; j < jw.size(); ++j) { long long ns = ss; ns &= ~smallest; if (ns & (smallest << j)) continue; ns |= smallest << j; if ((ns & 1) == 0 && ns < (1 << jw.size())) { auto& x = jumpm.m(i, get_index(ns >> 1)); long long aw = 0; if (pos >= 0 && j != 0) { long long pos2 = pos; long long sm2 = smallest >> 1; while (sm2) { ++pos2; sm2 /= 2; } pos2 += j; if (magic_stones.find(pos2) != magic_stones.end()) { aw = magic_stones[pos2]; } } x = min(x, (long long)jw[j] + aw); } } } } vector<long long> mul(const vector<long long>& x, const Matrix& m) { vector<long long> res(sn, big); for (long long i = 0; i < sn; ++i) { for (long long j = 0; j < sn; ++j) { res[i] = min(res[i], x[j] + m.m(j, i)); } } return res; } void print_state(long long pos, vector<long long>& res) {} int main() { long long x, k, n, q; scanf( %lld%lld%lld%lld , &x, &k, &n, &q); jw = vector<long long>(k + 1, 0); for (long long i = 1; i <= k; ++i) scanf( %lld , &(jw[i])); for (long long i = 0; i < q; ++i) { long long p, pw; scanf( %lld%lld , &p, &pw); magic_stones[p - 1] = pw; } for (long long i = 0; i < (1 << k); ++i) { if (btc(i) == x) { standings.push_back(i); } } sn = standings.size(); Matrix jumpm(sn); CalcJmpMatrix(jumpm); jumpm.fill_cache(); vector<long long> res(sn, big); res[0] = 0; long long cp = 0; long long des_pos = n - x; print_state(cp, res); for (auto ms : magic_stones) { if (ms.first == cp) continue; if (ms.first - k > cp) { res = mul(res, jumpm.get_pow(ms.first - k - cp)); cp = ms.first - k; print_state(cp, res); } for (; cp < ms.first && cp < des_pos;) { Matrix msm(sn); CalcJmpMatrix(msm, cp); res = mul(res, msm); ++cp; print_state(cp, res); } } if (cp < des_pos) { res = mul(res, jumpm.get_pow(des_pos - cp)); cp = des_pos; print_state(cp, res); } print_state(cp, res); std::cout << res[0] << std::endl; }
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//bug284
module wrapper
(
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [1:0] bout, // From mybuf of buf
output [31:0] o, // From u_or of or
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [1:0] bin, // To mybuf of buf
input [31:0] i0, // To u_or of or
input [31:0] i1, // To u_or of or
input [31:0] i2, // To u_or of or
input [31:0] i3 // To u_or of or
// End of automatics
);
//--------------------------------------------------------------------------
// Note input/output comments aren't needed, and multiple signals
// per line are ok
or u_or [31:0]
(o[31:0], i0[31:0], i1[31:0], i2[31:0],
// Inputs,
i3[31:0]
/*AUTOINST*/);
// bug676
buf # 1 mybuf[1:0]
(bout[1:0],
// Inputs,
bin[1:0]
/*AUTOINST*/);
//--------------------------------------------------------------------------
endmodule
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:09 05/12/2015
// Design Name: pipeline_control_registers
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_pipeline_control_registers.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: pipeline_control_registers
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_pipeline_control_registers;
// Inputs
reg clock;
reg flush_e;
reg reg_write_d;
reg [2:0] reg_write_adr_d;
reg mem_to_reg_d;
reg mem_write_d;
reg [7:0] ALU_con_d;
reg ALU_source2_d;
reg [15:0] offset_register_d;
reg [2:0] reg_read_adr1_d;
reg [2:0] reg_read_adr2_d;
// Outputs
wire reg_write_e;
wire [2:0] reg_write_adr_e;
wire mem_to_reg_e;
wire mem_write_e;
wire [7:0] ALU_con_e;
wire ALU_source2_e;
wire [15:0] offset_register_e;
wire [2:0] reg_read_adr1_e;
wire [2:0] reg_read_adr2_e;
wire reg_write_m;
wire [2:0] reg_write_adr_m;
wire mem_to_reg_m;
wire mem_write_m;
wire reg_write_w;
wire [2:0] reg_write_adr_w;
wire mem_to_reg_w;
// Instantiate the Unit Under Test (UUT)
pipeline_control_registers uut (
.clock(clock),
.flush_e(flush_e),
.reg_write_d(reg_write_d),
.reg_write_adr_d(reg_write_adr_d),
.mem_to_reg_d(mem_to_reg_d),
.mem_write_d(mem_write_d),
.ALU_con_d(ALU_con_d),
.ALU_source2_d(ALU_source2_d),
.offset_register_d(offset_register_d),
.reg_read_adr1_d(reg_read_adr1_d),
.reg_read_adr2_d(reg_read_adr2_d),
.reg_write_e(reg_write_e),
.reg_write_adr_e(reg_write_adr_e),
.mem_to_reg_e(mem_to_reg_e),
.mem_write_e(mem_write_e),
.ALU_con_e(ALU_con_e),
.ALU_source2_e(ALU_source2_e),
.offset_register_e(offset_register_e),
.reg_read_adr1_e(reg_read_adr1_e),
.reg_read_adr2_e(reg_read_adr2_e),
.reg_write_m(reg_write_m),
.reg_write_adr_m(reg_write_adr_m),
.mem_to_reg_m(mem_to_reg_m),
.mem_write_m(mem_write_m),
.reg_write_w(reg_write_w),
.reg_write_adr_w(reg_write_adr_w),
.mem_to_reg_w(mem_to_reg_w)
);
initial begin
// Initialize Inputs
clock = 0;
flush_e = 0;
reg_write_d = 0;
reg_write_adr_d = 0;
mem_to_reg_d = 0;
mem_write_d = 0;
ALU_con_d = 0;
ALU_source2_d = 0;
offset_register_d = 0;
reg_read_adr1_d = 0;
reg_read_adr2_d = 0;
// Wait 100 ns for global reset to finish
//#100;
#1;
#2;
reg_write_d = 1;
#2;
reg_write_d = 0;
#2;
reg_write_d = 1;
#2;
reg_write_d = 1;
#2;
reg_write_d = 1;
flush_e = 1;
#2;
flush_e = 0;
end
always #1 clock = !clock;
endmodule
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#include <bits/stdc++.h> using namespace std; const int maxn = 100003; int l[maxn], r[maxn], L, R, K, n, cnt[maxn][30], sum[30], A[30], B[30]; char c[maxn], s[maxn]; int List[30][maxn], a[maxn], len[maxn], tot = 0; inline int get() { int f = 0, v = 0; char ch; while (!isdigit(ch = getchar())) if (ch == - ) break; if (ch == - ) f = 1; else v = ch - 48; while (isdigit(ch = getchar())) v = v * 10 + ch - 48; if (f == 1) return -v; else return v; } int check(int st, int ed) { bool f = 0, g = 0; for (int i = 0; i < 26; i++) { int tp = cnt[ed][i] - cnt[st - 1][i]; if (tp > B[i]) g = 1; if (tp < A[i]) f = 1; } if (f && g) return 2; if (f) return -1; if (g) return 1; return 0; } void add(int st, int ed, int v) { for (int i = st; i <= ed; i++) { if (L <= a[i] && a[i] <= R) tot--; a[i] += v; if (L <= a[i] && a[i] <= R) tot++; } } int main() { scanf( %s , s + 1); n = strlen(s + 1); K = get(); L = get(), R = get(); for (int i = 1; i <= K; i++) scanf( %c , &c[i]), l[i] = get(), r[i] = get(); for (int i = 1; i <= n; i++) { for (int j = 0; j < 26; j++) cnt[i][j] = cnt[i - 1][j]; cnt[i][s[i] - a ]++; } if (L == K && R == K) { long long ans = 0; for (int i = 0; i < 26; i++) A[i] = 0, B[i] = n + 1; for (int i = 1; i <= K; i++) { A[c[i] - a ] = max(A[c[i] - a ], l[i]); B[c[i] - a ] = min(B[c[i] - a ], r[i]); if (A[c[i] - a ] > B[c[i] - a ]) return puts( 0 ), 0; } for (int i = 1; i <= n; i++) { bool flag = 1; L = i, R = n; int Left, Right; while (L <= R) { int mid = (L + R) / 2, t = check(i, mid); if (t == 2) { flag = 0; break; } if (t == 1) R = mid - 1; else L = mid + 1; } Right = R; L = i, R = n; while (L <= R) { int mid = (L + R) / 2, t = check(i, mid); if (t == 2) { flag = 0; break; } if (t == -1) L = mid + 1; else R = mid - 1; } Left = L; if (flag && Right >= Left) ans += Right - Left + 1; } cout << ans << endl; return 0; } long long ans = 0; for (int i = 1; i <= n; i++) { if (L == 0) tot++; int tp = s[i] - a ; List[tp][++len[tp]] = i; for (int j = 1; j <= K; j++) { if (l[j] == 0) add(i, i, 1); if (c[j] != s[i]) continue; if (len[tp] >= l[j] && l[j] != 0) add(List[tp][len[tp] - l[j]] + 1, List[tp][len[tp] - l[j] + 1], 1); if (len[tp] > r[j]) add(List[tp][len[tp] - r[j] - 1] + 1, List[tp][len[tp] - r[j]], -1); } ans += tot; } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n; long long a[300000]; int main() { while (cin >> n) { for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long ans = 0; for (int i = 0; i < n; i++) { int x = (i == n - 1 ? -1 : 0); ans += (x + i + 2) * a[i]; } cout << ans << n ; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:25 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: channel_error_detect.ejava,v $
// Rev: $Revision: 1.1.6.2 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// CHANNEL_ERROR_DETECT
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: the CHANNEL_ERROR_DETECT module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 10 ps
module CHANNEL_ERROR_DETECT
(
// Aurora Lane Interface
SOFT_ERROR,
HARD_ERROR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input [0:1] SOFT_ERROR;
input HARD_ERROR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERROR;
reg CHANNEL_HARD_ERROR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg [0:1] soft_error_r;
reg hard_error_r;
//*********************************Wire Declarations**********************************
wire channel_soft_error_c;
wire channel_hard_error_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_error_r <= `DLY SOFT_ERROR;
hard_error_r <= `DLY HARD_ERROR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERROR = 1'b1;
assign channel_soft_error_c = soft_error_r[0] |
soft_error_r[1];
always @(posedge USER_CLK)
CHANNEL_SOFT_ERROR <= `DLY channel_soft_error_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERROR = 1'b1;
assign channel_hard_error_c = hard_error_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERROR <= `DLY channel_hard_error_c;
// "reset_channel_r" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !LANE_UP;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { bitset<30> a; bitset<30> b; a.reset(); b.reset(); bool bigger = 0; cout << ? 0 0 << endl; fflush(stdout); int aa; cin >> aa; if (aa == -1) { bigger = 1; } bitset<30> adda; bitset<30> addb; for (int i = 29; i >= 0; i--) { adda[i] = 1; addb[i] = 1; cout << ? << adda.to_ulong() << << addb.to_ulong() << endl; fflush(stdout); int aa; cin >> aa; if (aa == -1 && bigger == 0) { a[i] = 1; b[i] = 0; adda[i] = 0; addb[i] = 1; cout << ? << adda.to_ulong() << << addb.to_ulong() << endl; fflush(stdout); int aa; cin >> aa; if (aa == -1) { bigger = 1; } } else if (aa == 1 && bigger == 1) { a[i] = 0; b[i] = 1; adda[i] = 1; addb[i] = 0; cout << ? << adda.to_ulong() << << addb.to_ulong() << endl; fflush(stdout); int aa; cin >> aa; if (aa == 1) { bigger = 0; } } else if (aa == 1 && bigger == 0) { adda[i] = 1; addb[i] = 0; cout << ? << adda.to_ulong() << << addb.to_ulong() << endl; fflush(stdout); int aa; cin >> aa; if (aa == 1) { a[i] = 0; b[i] = 0; adda[i] = 0; addb[i] = 0; } else if (aa == -1) { a[i] = 1; b[i] = 1; adda[i] = 1; addb[i] = 1; } } else if (aa == -1 && bigger == 1) { adda[i] = 0; addb[i] = 1; cout << ? << adda.to_ulong() << << addb.to_ulong() << endl; fflush(stdout); int aa; cin >> aa; if (aa == -1) { a[i] = 0; b[i] = 0; adda[i] = 0; addb[i] = 0; } else if (aa == 1) { a[i] = 1; b[i] = 1; adda[i] = 1; addb[i] = 1; } } else if (aa == 0) { adda[i] = 0; addb[i] = 1; cout << ? << adda.to_ulong() << << addb.to_ulong() << endl; fflush(stdout); int aa; cin >> aa; if (aa == -1) { a[i] = 0; b[i] = 0; adda[i] = 0; addb[i] = 0; } else if (aa == 1) { a[i] = 1; b[i] = 1; adda[i] = 1; addb[i] = 1; } } } cout << ! << a.to_ulong() << << b.to_ulong() << endl; fflush(stdout); }
|
#include <bits/stdc++.h> using namespace std; int n, m = 100000, a, b, c, cnt; struct Point { int x, y; Point() {} Point(int a, int b) { x = a, y = b; } bool operator==(Point b) const { return x == b.x && y == b.y; } Point operator+(Point b) { return Point(x + b.x, y + b.y); } Point operator-(Point b) { return Point(x - b.x, y - b.y); } } A[5000005], Q[5000005], P[5000005]; long long Cross(Point a, Point b) { return (long long)a.x * b.y - (long long)a.y * b.x; } long double Length(Point p) { return sqrt(1.0 * p.x * p.x + 1.0 * p.y * p.y); } void Add(int x, int y) { A[++cnt] = Point(x, y); } bool cmp(Point a, Point b) { return a.x == b.x ? a.y < b.y : a.x < b.x; } long double Abs(long double x) { return x > 0 ? x : -x; } long double Getr(Point a, Point b, Point c) { long double p = Length(a - b), q = Length(b - c), r = Length(c - a); long double s = Abs(2.0 * (long double)Cross(b - a, c - a)); if (s <= 1e-10) return 0; return p * q * r / s; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d%d , &a, &b, &c); if (a - c >= 0) Add(a - c, b); else { Add(0, min(m, b + c - a)); Add(0, max(0, b - c + a)); } if (a + c <= m) Add(a + c, b); else { Add(m, min(m, b + c - (m - a))); Add(m, max(0, b - c + (m - a))); } if (b - c >= 0) Add(a, b - c); else { Add(min(m, a + c - b), 0); Add(max(0, a - c + b), 0); } if (b + c <= m) Add(a, b + c); else { Add(min(m, a + c - (m - b)), m); Add(max(0, a - c + (m - b)), m); } } sort(A + 1, A + cnt + 1, cmp); cnt = unique(A + 1, A + cnt + 1) - A - 1; int lst = 0; for (int i = 1; i <= cnt; i++) { while (lst > 1 && Cross(A[i] - Q[lst], Q[lst] - Q[lst - 1]) >= 0) lst--; Q[++lst] = A[i]; } int fir = 0; for (int i = cnt; i >= 1; i--) { while (fir > 1 && Cross(A[i] - P[fir], P[fir] - P[fir - 1]) >= 0) fir--; P[++fir] = A[i]; } for (int i = 2; i < fir; i++) Q[++lst] = P[i]; long double mx = Getr(Q[lst], Q[1], Q[2]), tmp; int a1 = lst, a2 = 1, a3 = 2; if ((tmp = Getr(Q[lst - 1], Q[lst], Q[1])) > mx) a1 = lst - 1, a2 = lst, a3 = 1, mx = tmp; for (int i = 3; i <= lst; i++) if ((tmp = Getr(Q[i - 2], Q[i - 1], Q[i])) > mx) a3 = i, mx = tmp; if (a3 >= 3) a1 = a3 - 2, a2 = a3 - 1; printf( %d %d n%d %d n%d %d n , Q[a1].x, Q[a1].y, Q[a2].x, Q[a2].y, Q[a3].x, Q[a3].y); }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 257, MOD = 1e9 + 7; int pk[MAXN * MAXN], pk1[MAXN * MAXN], n, k, f[MAXN][MAXN], C[MAXN][MAXN]; int mul(int a, int b) { return 1LL * a * b % MOD; } void add(int &a, const int &b) { a += b; if (a >= MOD) a -= MOD; } void sub(int &a, const int &b) { a -= b; if (a < 0) a += MOD; } int subs(int a, int b) { a -= b; if (a < 0) a += MOD; return a; } int pw(int cs, int sm) { if (sm == 0) return 1; int hpw = pw(cs, sm >> 1); hpw = 1LL * hpw * hpw % MOD; if (sm & 1) hpw = 1LL * hpw * cs % MOD; return hpw; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> k; pk[0] = pk1[0] = 1; for (int i = 1; i <= n * n; ++i) { pk[i] = 1LL * pk[i - 1] * k % MOD; pk1[i] = 1LL * pk1[i - 1] * (k - 1) % MOD; } C[0][0] = 1; for (int i = 1; i <= n; ++i) { C[i][0] = C[i][i] = 1; for (int j = 1; j < i; ++j) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % MOD; } int res = 0; for (int i = 0; i <= n; ++i) { int cur = mul(C[n][i], pw(subs(mul(pk[n - i], pk1[i]), pk1[n]), n)); if (i & 1) sub(res, cur); else add(res, cur); } cout << res; return 0; }
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/rp2a03.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Implementation of the RP2A03 chip for an fpga-based NES emulator. Contains a MOS-6502 CPU
* core, APU, sprite DMA engine, and joypad control logic.
***************************************************************************************************/
module rp2a03
(
input wire clk_in, // system clock
input wire rst_in, // system reset
// CPU signals.
input wire rdy_in, // ready signal
input wire [ 7:0] d_in, // data input bus
input wire nnmi_in, // /nmi interrupt signal (active low)
input wire nres_in, // /res interrupt signal (active low)
output wire [ 7:0] d_out, // data output bus
output wire [15:0] a_out, // address bus
output wire r_nw_out, // read/write select (write low)
output wire brk_out, // debug break signal
// Joypad signals.
input wire jp_data1_in, // joypad 1 input signal
input wire jp_data2_in, // joypad 2 input signal
output wire jp_clk, // joypad output clk signal
output wire jp_latch, // joypad output latch signal
// Audio signals.
input wire [ 3:0] mute_in, // disable autio channels
output wire audio_out, // pwm audio output
output wire [ 5:0] dac_audio_out,
// HCI interface.
input wire [ 3:0] dbgreg_sel_in, // dbg reg select
input wire [ 7:0] dbgreg_d_in, // dbg reg data in
input wire dbgreg_wr_in, // dbg reg write select
output wire [ 7:0] dbgreg_d_out // dbg reg data out
);
//
// CPU: central processing unit block.
//
wire cpu_ready;
wire [ 7:0] cpu_din;
wire cpu_nirq;
wire [ 7:0] cpu_dout;
wire [15:0] cpu_a;
wire cpu_r_nw;
cpu cpu_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.ready_in(cpu_ready),
.dbgreg_sel_in(dbgreg_sel_in),
.dbgreg_in(dbgreg_d_in),
.dbgreg_wr_in(dbgreg_wr_in),
.d_in(cpu_din),
.nnmi_in(nnmi_in),
.nres_in(nres_in),
.nirq_in(cpu_nirq),
.d_out(cpu_dout),
.a_out(cpu_a),
.r_nw_out(cpu_r_nw),
.brk_out(brk_out),
.dbgreg_out(dbgreg_d_out)
);
//
// APU: audio processing unit block.
//
wire [7:0] audio_dout;
apu apu_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.mute_in(mute_in),
.a_in(cpu_a),
.d_in(cpu_dout),
.r_nw_in(cpu_r_nw),
.audio_out(audio_out),
.dac_audio_out(dac_audio_out),
.d_out(audio_dout)
);
//
// JP: joypad controller block.
//
wire [7:0] jp_dout;
jp jp_blk(
.clk(clk_in),
.rst(rst_in),
.wr(~cpu_r_nw),
.addr(cpu_a),
.din(cpu_dout[0]),
.jp_data1(jp_data1_in),
.jp_data2(jp_data2_in),
.jp_clk(jp_clk),
.jp_latch(jp_latch),
.dout(jp_dout)
);
//
// SPRDMA: sprite dma controller block.
//
wire sprdma_active;
wire [15:0] sprdma_a;
wire [ 7:0] sprdma_dout;
wire sprdma_r_nw;
sprdma sprdma_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.cpumc_a_in(cpu_a),
.cpumc_din_in(cpu_dout),
.cpumc_dout_in(cpu_din),
.cpu_r_nw_in(cpu_r_nw),
.active_out(sprdma_active),
.cpumc_a_out(sprdma_a),
.cpumc_d_out(sprdma_dout),
.cpumc_r_nw_out(sprdma_r_nw)
);
assign cpu_ready = rdy_in & !sprdma_active;
assign cpu_din = d_in | jp_dout | audio_dout;
assign cpu_nirq = 1'b1;
assign d_out = (sprdma_active) ? sprdma_dout : cpu_dout;
assign a_out = (sprdma_active) ? sprdma_a : cpu_a;
assign r_nw_out = (sprdma_active) ? sprdma_r_nw : cpu_r_nw;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool check(char a) { if (a == a || a == e || a == i || a == o || a == u ) return true; if (a == 1 || a == 3 || a == 5 || a == 7 || a == 9 ) return true; return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s; cin >> s; int ans = 0; for (int i = 0; i < s.length(); i++) if (check(s[i])) ans++; cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> h(n), res(n); for (int i = 0; i < (int)(n); i++) { scanf( %d , &h[i]); } int bad = 0; int ans = 0; for (int i = 0; i < (int)(n); i++) { bad = min(bad, h[i] - i - 1); res[i] = i + 1 + bad; } bad = n + 1; for (int i = (int)(n)-1; i >= 0; i--) { bad = min(bad, h[i] + i + 1); res[i] = min(res[i], bad - i - 1); ans = max(ans, res[i]); } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[1002], b[1002], n, m; while (cin >> n >> m) { for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; double be = m; bool flag = 0; for (int i = n - 1; i >= 0; i--) { be = be * b[(i + 1) % n] / (b[(i + 1) % n] - 1); if (be > 1000000000) { flag = 1; break; } be = be * a[i] / (a[i] - 1); } if (flag) cout << -1 << endl; else cout << fixed << setprecision(10) << be - m << endl; } return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module fifo_short
#(parameter WIDTH=32)
(input clk, input reset, input clear,
input [WIDTH-1:0] datain,
input src_rdy_i,
output dst_rdy_o,
output [WIDTH-1:0] dataout,
output src_rdy_o,
input dst_rdy_i,
output reg [4:0] space,
output reg [4:0] occupied);
reg full, empty;
wire write = src_rdy_i & dst_rdy_o;
wire read = dst_rdy_i & src_rdy_o;
assign dst_rdy_o = ~full;
assign src_rdy_o = ~empty;
reg [3:0] a;
genvar i;
generate
for (i=0;i<WIDTH;i=i+1)
begin : gen_srl16
SRL16E
srl16e(.Q(dataout[i]),
.A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
.CE(write),.CLK(clk),.D(datain[i]));
end
endgenerate
always @(posedge clk)
if(reset)
begin
a <= 0;
empty <= 1;
full <= 0;
end
else if(clear)
begin
a <= 0;
empty <= 1;
full<= 0;
end
else if(read & ~write)
begin
full <= 0;
if(a==0)
empty <= 1;
else
a <= a - 1;
end
else if(write & ~read)
begin
empty <= 0;
if(~empty)
a <= a + 1;
if(a == 14)
full <= 1;
end
// NOTE will fail if you write into a full fifo or read from an empty one
//////////////////////////////////////////////////////////////
// space and occupied are used for diagnostics, not
// guaranteed correct
//assign space = full ? 0 : empty ? 16 : 15-a;
//assign occupied = empty ? 0 : full ? 16 : a+1;
always @(posedge clk)
if(reset)
space <= 16;
else if(clear)
space <= 16;
else if(read & ~write)
space <= space + 1;
else if(write & ~read)
space <= space - 1;
always @(posedge clk)
if(reset)
occupied <= 0;
else if(clear)
occupied <= 0;
else if(read & ~write)
occupied <= occupied - 1;
else if(write & ~read)
occupied <= occupied + 1;
endmodule // fifo_short
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[1 << 20]; int main() { scanf( %d%d , &n, &m); map<int, int> p; for (int i = 1; i <= n; i++) { int fi; scanf( %d , &fi); if (p.count(fi)) { p[fi] = 0; } else { p[fi] = i; } } bool im = false, am = false; for (int i = 1; i <= m; i++) { int bi; scanf( %d , &bi); if (!p.count(bi)) { im = true; } else if (p[bi]) { a[i] = p[bi]; } else { am = true; } } if (im) { puts( Impossible ); } else if (am) { puts( Ambiguity ); } else { puts( Possible ); for (int i = 1; i <= m; i++) { printf( %d%c , a[i], i == m ? n : ); } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n; vector<int> adj[n + 1], deg(n + 1, 0); vector<pair<int, int>> input; for (int i = 0; i < n - 1; i++) { cin >> x >> y; input.push_back(make_pair(x, y)); adj[x].push_back(y); adj[y].push_back(x); deg[x]++; deg[y]++; } vector<pair<int, int>> s; for (int i = 1; i <= n; i++) { s.push_back(make_pair(deg[i], i)); } sort(s.begin(), s.end()); int number = 0; map<pair<int, int>, int> m; for (auto x : s) { int degree = x.first; int vertex = x.second; for (int k : adj[vertex]) { pair<int, int> temp = {k, vertex}; pair<int, int> revr = {vertex, k}; if (m.find(temp) == m.end()) { m[temp] = number; m[revr] = number; number++; } } } for (auto x : input) { pair<int, int> temp = {x.first, x.second}; cout << m[temp] << n ; } }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im:1.0
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_0 (
RST_N,
CLK,
I_MEM_WAIT,
I_MEM_ENA,
I_MEM_ADDR,
I_MEM_RDATA,
I_MEM_BADMEM_EXCPT,
D_MEM_WAIT,
D_MEM_ENA,
D_MEM_WSTB,
D_MEM_ADDR,
D_MEM_WDATA,
D_MEM_RDATA,
D_MEM_BADMEM_EXCPT,
EXT_INTERRUPT,
TIMER_EXPIRED
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_WAIT" *)
input wire I_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ENA" *)
output wire I_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] I_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] I_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 I_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire I_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WAIT" *)
input wire D_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ENA" *)
output wire D_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WSTB" *)
output wire [3 : 0] D_MEM_WSTB;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] D_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WDATA" *)
output wire [31 : 0] D_MEM_WDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] D_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire D_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 EXT_INTERRUPT INTERRUPT" *)
input wire EXT_INTERRUPT;
input wire TIMER_EXPIRED;
fmrv32im #(
.MADD33_ADDON(1)
) inst (
.RST_N(RST_N),
.CLK(CLK),
.I_MEM_WAIT(I_MEM_WAIT),
.I_MEM_ENA(I_MEM_ENA),
.I_MEM_ADDR(I_MEM_ADDR),
.I_MEM_RDATA(I_MEM_RDATA),
.I_MEM_BADMEM_EXCPT(I_MEM_BADMEM_EXCPT),
.D_MEM_WAIT(D_MEM_WAIT),
.D_MEM_ENA(D_MEM_ENA),
.D_MEM_WSTB(D_MEM_WSTB),
.D_MEM_ADDR(D_MEM_ADDR),
.D_MEM_WDATA(D_MEM_WDATA),
.D_MEM_RDATA(D_MEM_RDATA),
.D_MEM_BADMEM_EXCPT(D_MEM_BADMEM_EXCPT),
.EXT_INTERRUPT(EXT_INTERRUPT),
.TIMER_EXPIRED(TIMER_EXPIRED)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int ans[101]; int main() { int t; scanf( %d , &t); while (t--) { int n, cnt = 0; scanf( %d , &n); for (int i = 1; i <= n; i *= 2) { ans[++cnt] = i; n -= i; } if (n > 0) { ans[++cnt] = n; sort(ans + 1, ans + cnt + 1); } printf( %d n , cnt - 1); for (int i = 2; i <= cnt; i++) printf( %d , ans[i] - ans[i - 1]); printf( n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX = 205, MAXL = 1 << 20; char qq[MAXL]; char s[MAX][MAX]; pair<int, int> kamo[MAX][MAX]; vector<pair<int, int> > R[MAX][MAX]; int indeg[MAX][MAX]; int cik[MAX][MAX]; int imacik[MAX * MAX][10]; int brred, brstup; int pr[10], ps[10]; int bio[MAX][MAX]; int dokle[MAX][MAX]; int imaq[MAXL][10]; int brc = 1; int Vani(int red, int stup) { return red < 0 || red >= brred || stup < 0 || stup >= brstup; } void Osisaj() { queue<pair<int, int> > Q; for (int i = 0; i < brred; i++) for (int j = 0; j < brstup; j++) if (!indeg[i][j]) Q.push(pair<int, int>(i, j)); for (; !Q.empty();) { pair<int, int> tmp = Q.front(); bio[tmp.first][tmp.second] = 1; Q.pop(); pair<int, int> nn = kamo[tmp.first][tmp.second]; indeg[nn.first][nn.second]--; if (!indeg[nn.first][nn.second]) Q.push(nn); } for (int i = 0; i < brred; i++) { for (int j = 0; j < brstup; j++) { if (!bio[i][j]) { int sz = 0; for (pair<int, int> tmp = pair<int, int>(i, j); tmp != pair<int, int>(i, j) || !sz; sz++, tmp = kamo[tmp.first][tmp.second]) { bio[tmp.first][tmp.second] = 1; cik[tmp.first][tmp.second] = brc; imacik[brc][s[tmp.first][tmp.second] - 0 ] = 1; } brc++; } } } } int Rijesi() { queue<pair<int, int> > Q; memset(dokle, 0, sizeof dokle); int len = (int)strlen(qq); for (int i = 0; i <= len; i++) for (int j = 0; j < 10; j++) imaq[i][j] = 0; for (int i = len - 1; i >= 0; i--) { imaq[i][qq[i] - 0 ] = 1; for (int j = 0; j < 10; j++) imaq[i][j] |= imaq[i + 1][j]; } for (int i = 0; i < brred; i++) for (int j = 0; j < brstup; j++) { indeg[i][j] = (int)R[i][j].size(); if (!indeg[i][j]) Q.push(pair<int, int>(i, j)); } for (; !Q.empty();) { pair<int, int> tmp = Q.front(); Q.pop(); int nd = dokle[tmp.first][tmp.second]; if (s[tmp.first][tmp.second] == qq[nd]) nd++; if (nd == len) return 1; pair<int, int> nn = kamo[tmp.first][tmp.second]; dokle[nn.first][nn.second] = max(dokle[nn.first][nn.second], nd); indeg[nn.first][nn.second]--; if (!indeg[nn.first][nn.second]) Q.push(nn); } for (int i = 0; i < brred; i++) { for (int j = 0; j < brstup; j++) { if (cik[i][j]) { int da = 1; int indc = cik[i][j]; for (int k = 0; k < 10; k++) if (!imacik[indc][k] && imaq[dokle[i][j]][k]) da = 0; if (da) return 1; } } } return 0; } int main() { int brq; scanf( %d%d%d , &brred, &brstup, &brq); for (int i = 0; i < brred; i++) scanf( %s , s[i]); for (int i = 0; i < 10; i++) scanf( %d%d , &pr[i], &ps[i]); for (int i = 0; i < brred; i++) { for (int j = 0; j < brstup; j++) { int nr = i + pr[s[i][j] - 0 ]; int ns = j + ps[s[i][j] - 0 ]; if (Vani(nr, ns)) kamo[i][j] = pair<int, int>(i, j); else kamo[i][j] = pair<int, int>(nr, ns); indeg[kamo[i][j].first][kamo[i][j].second]++; R[kamo[i][j].first][kamo[i][j].second].push_back(pair<int, int>(i, j)); } } Osisaj(); for (int i = 0; i < brq; i++) { scanf( %s , qq); printf( %s n , Rijesi() ? YES : NO ); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N_MAX = 51000; int X[N_MAX], Y[N_MAX], Z[N_MAX]; bool vis[N_MAX]; bool ff(int i, int j) { if (X[i] != X[j]) return X[i] < X[j]; if (Y[i] != Y[j]) return Y[i] < Y[j]; return Z[i] < Z[j]; } int main() { int n; cin >> n; vector<int> P; for (int i = 1; i <= n; i++) { cin >> X[i] >> Y[i] >> Z[i]; P.push_back(i); } sort(P.begin(), P.end(), ff); for (int i = 0; i < n - 1; i++) { if (vis[P[i]]) continue; if (X[P[i]] == X[P[i + 1]] and Y[P[i]] == Y[P[i + 1]]) { vis[P[i]] = 1; vis[P[i + 1]] = 1; cout << P[i] << << P[i + 1] << endl; } } for (int i = 0; i < n - 1; i++) { if (vis[P[i]]) continue; if (X[P[i]] != X[P[i + 1]]) continue; int j = i + 1; while (vis[P[j]] and j < n) { j++; } if (j == n or X[P[i]] != X[P[j]]) continue; vis[P[i]] = 1; vis[P[j]] = 1; cout << P[i] << << P[j] << endl; } for (int i = 0; i < n - 1; i++) { if (vis[P[i]]) continue; int j = i + 1; while (vis[P[j]] and j < n) { j++; } vis[P[i]] = 1; vis[P[j]] = 1; cout << P[i] << << P[j] << endl; } return 0; }
|
module LookAheadAdder(a,b,cin,s,cout);
input wire [3:0]a;
input wire [3:0]b;
input wire cin;
output wire [3:0]s;
output wire cout;
wire [3:0]c;
wire [3:0]G;
wire [3:0]P;
assign G[3]=a[3]&&b[3];
assign G[2]=a[2]&&b[2];
assign G[1]=a[1]&&b[1];
assign G[0]=a[0]&&b[0];
assign P[3]=a[3]&&~b[3]||~a[3]&&b[3];
assign P[2]=a[2]&&~b[2]||~a[2]&&b[2];
assign P[1]=a[1]&&~b[1]||~a[1]&&b[1];
assign P[0]=a[0]&&~b[0]||~a[0]&&b[0];
wire [3:0]c3;
wire [2:0]c2;
wire [1:0]c1;
and(c3[0],P[3],P[2],P[1],P[0],cin);
and(c3[1],P[3],P[2],P[1],G[0]);
and(c3[2],P[3],P[2],G[1]);
and(c3[3],P[3],G[2]);
and(c2[0],P[2],P[1],P[0],cin);
and(c2[1],P[2],P[1],G[0]);
and(c2[2],P[2],G[1]);
and(c1[0],P[1],P[0],cin);
and(c1[1],P[1],G[0]);
and(c0,P[0],cin);
or(cout,c3[0],c3[1],c3[2],c3[3],G[3]);
or(c[2],c2[0],c2[1],c2[2],G[2]);
or(c[1],c1[0],c1[1],G[1]);
or(c[0],c0,G[0]);
assign s[0]=~a[0]&&(~b[0]&&cin||b[0]&&~cin)||a[0]&&(b[0]&&cin||~b[0]&&~cin);
assign s[1]=~a[1]&&(~b[1]&&c[0]||b[1]&&~c[0])||a[1]&&(b[1]&&c[0]||~b[1]&&~c[0]);
assign s[2]=~a[2]&&(~b[2]&&c[1]||b[2]&&~c[1])||a[2]&&(b[2]&&c[1]||~b[2]&&~c[1]);
assign s[3]=~a[3]&&(~b[3]&&c[2]||b[3]&&~c[2])||a[3]&&(b[3]&&c[2]||~b[3]&&~c[2]);
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_usr_top.v
// /___/ /\ Date Last Modified: $Date: 2008/12/23 14:26:01 $
// \ \ / \ Date Created: Mon Aug 28 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module interfaces with the user. The user should provide the data
// and various commands.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_usr_top #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter BANK_WIDTH = 2,
parameter CS_BITS = 0,
parameter COL_WIDTH = 10,
parameter DQ_WIDTH = 72,
parameter DQ_PER_DQS = 8,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0,
parameter DQS_WIDTH = 9,
parameter ROW_WIDTH = 14
)
(
input clk0,
input usr_clk, //jb
input clk90,
input rst0,
input [DQ_WIDTH-1:0] rd_data_in_rise,
input [DQ_WIDTH-1:0] rd_data_in_fall,
input [DQS_WIDTH-1:0] phy_calib_rden,
input [DQS_WIDTH-1:0] phy_calib_rden_sel,
output rd_data_valid,
output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input ctrl_af_rden,
output [2:0] af_cmd,
output [30:0] af_addr,
output af_empty,
output app_af_afull,
output [1:0] rd_ecc_error,
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
input wdf_rden,
output app_wdf_afull,
output [(2*DQ_WIDTH)-1:0] wdf_data,
output [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data
);
wire [(APPDATA_WIDTH/2)-1:0] i_rd_data_fifo_out_fall;
wire [(APPDATA_WIDTH/2)-1:0] i_rd_data_fifo_out_rise;
//***************************************************************************
assign rd_data_fifo_out = {i_rd_data_fifo_out_fall,
i_rd_data_fifo_out_rise};
// read data de-skew and ECC calculation
ddr2_usr_rd #
(
.DQ_PER_DQS (DQ_PER_DQS),
.ECC_ENABLE (ECC_ENABLE),
.APPDATA_WIDTH (APPDATA_WIDTH),
.DQS_WIDTH (DQS_WIDTH)
)
u_usr_rd
(
.clk0 (clk0),
.rst0 (rst0),
.rd_data_in_rise (rd_data_in_rise),
.rd_data_in_fall (rd_data_in_fall),
.rd_ecc_error (rd_ecc_error),
.ctrl_rden (phy_calib_rden),
.ctrl_rden_sel (phy_calib_rden_sel),
.rd_data_valid (rd_data_valid),
.rd_data_out_rise (i_rd_data_fifo_out_rise),
.rd_data_out_fall (i_rd_data_fifo_out_fall)
);
// Command/Addres FIFO
ddr2_usr_addr_fifo #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_addr_fifo
(
.clk0 (clk0),
.usr_clk (usr_clk), //jb
.rst0 (rst0),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren),
.ctrl_af_rden (ctrl_af_rden),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.app_af_afull (app_af_afull)
);
ddr2_usr_wr #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.DQ_WIDTH (DQ_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_wr
(
.clk0 (clk0),
.usr_clk (usr_clk), // jb
.clk90 (clk90),
.rst0 (rst0),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.wdf_rden (wdf_rden),
.app_wdf_afull (app_wdf_afull),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data)
);
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; #define F first #define S second const int MXN = 200040; int cnt[MXN]; bool b[MXN]; ll n,d; int main(){ int t; cin >> t; while(t--){ string s; cin >> s; int n = s.size(); int ans = 0; bool b[n+3]; for(int i = 0 ; i < n+3 ; i++){ b[i] = 0; } for(int i = 1 ; i < n ; i++){ if(i == 1){ if(s[i] == s[i-1]){ b[i] = 1; ans++; } continue; } if(s[i] != s[i-1] && s[i] != s[i-2])continue; if(s[i] == s[i-1] && s[i] == s[i-2]){ if(b[i-1] && b[i-2])continue; b[i] = 1; ans++; continue; } if(s[i] == s[i-1] && s[i] != s[i-2]){ if(b[i-1])continue; b[i] = 1; ans++; continue; } if(s[i] == s[i-2] && s[i] != s[i-1]){ if(b[i-2])continue; b[i] = 1; ans++; continue; } } cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); ; int n, k; cin >> n >> k; while (n > 0 && k > 0) { k--; if (n % 10 == 0) n = n / 10; else n--; } cout << n << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_TB_V
`define SKY130_FD_SC_MS__TAPVGND_TB_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tapvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ms__tapvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_TB_V
|
#include <bits/stdc++.h> using namespace std; int R[300010 * 2], L[300010 * 2], n, m, sum[300010], sz; struct Fun { int k, b; } f[300010], id[300010 * 20], s[300010]; inline int Read() { char c = getchar(); int num = 0, f = 1; while ( 0 > c || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while ( 0 <= c && c <= 9 ) num = num * 10 + c - 0 , c = getchar(); return (num * f); } inline bool Pd(Fun c, Fun a, Fun b) { return ((long long)(c.b - a.b) * (b.k - c.k) <= (long long)(c.b - b.b) * (a.k - c.k)); } inline void Ins(int rt, Fun x) { id[++sz] = x; if (!R[rt]) L[rt] = sz; R[rt] = sz; while (R[rt] - L[rt] >= 2 && Pd(id[R[rt] - 2], id[R[rt] - 1], id[R[rt]])) { id[R[rt] - 1] = id[R[rt]]; id[R[rt]] = (Fun){0, 0}; sz--; R[rt]--; } } inline void Merge(int rt, int l, int mid, int r) { int i = l, j = mid + 1, k = l - 1; while (i <= mid && j <= r) { if ((f[i].k < f[j].k) || (f[i].k == f[j].k && f[i].b < f[j].b)) s[++k] = f[i], i++; else s[++k] = f[j], j++; } for (; j <= r; j++) s[++k] = f[j]; for (; i <= mid; i++) s[++k] = f[i]; f[l] = s[l]; Ins(rt, f[l]); for (int t = l + 1; t <= r; t++) { f[t] = s[t]; if (f[t].k != f[t - 1].k) Ins(rt, f[t]); } } inline void Build(int rt, int l, int r) { int mid = (l + r) / 2; if (l == r) { Ins(rt, f[l]); return; } Build(rt * 2, l, mid); Build(rt * 2 + 1, mid + 1, r); Merge(rt, l, mid, r); } inline int Cal(int l, int r, int x) { while (r - l > 1) { int mid = (l + r) / 2; if (id[mid].k * x + id[mid].b < id[mid + 1].k * x + id[mid + 1].b) { r = mid; continue; } if (id[mid].k * x + id[mid].b > id[mid + 1].k * x + id[mid + 1].b) { l = mid; continue; } if (id[mid].k * x + id[mid].b < id[mid - 1].k * x + id[mid - 1].b) { l = mid; continue; } if (id[mid].k * x + id[mid].b > id[mid - 1].k * x + id[mid - 1].b) { r = mid; continue; } } return (min(id[l].k * x + id[l].b, id[r].k * x + id[r].b)); } inline int Find(int rt, int l, int r, int a, int b, int p) { int mid = (l + r) / 2; if (l == a && r == b) { if (l <= 115 && 115 <= r) int deb = 0; return (Cal(L[rt], R[rt], p)); } if (b <= mid) return (Find(rt * 2, l, mid, a, b, p)); if (mid < a) return (Find(rt * 2 + 1, mid + 1, r, a, b, p)); if (a <= mid && mid < b) { int L = Find(rt * 2, l, mid, a, mid, p); int R = Find(rt * 2 + 1, mid + 1, r, mid + 1, b, p); return (min(L, R)); } } int main() { n = Read(); for (int i = 1; i <= n; i++) f[i].k = Read(); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + f[i].k, f[i].b = f[i].k * i - sum[i]; Build(1, 1, n); m = Read(); for (int i = 1; i <= m; i++) { int x = Read(), y = Read(); int Min = Find(1, 1, n, y - x + 1, y, x - y); printf( %d n , min(sum[y] - sum[y - x], sum[y] + Min)); } }
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM16_s36_s36_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module RAM16_s36_s36_altera (
aclr_a,
aclr_b,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input aclr_a;
input aclr_b;
input [8:0] address_a;
input [8:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr_a;
tri0 aclr_b;
tri1 wren_a;
tri1 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "1"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR1"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: aclr_a 0 0 0 0 INPUT GND aclr_a
// Retrieval info: USED_PORT: aclr_b 0 0 0 0 INPUT GND aclr_b
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL address_a[8..0]
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL address_b[8..0]
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL data_a[31..0]
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL data_b[31..0]
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL q_a[31..0]
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL q_b[31..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr_a 0 0 0 0
// Retrieval info: CONNECT: @aclr1 0 0 0 0 aclr_b 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_wave*.jpg TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; char ch[100010], temp[100010]; bool ok[100010]; int main() { int n; cin >> n; cin >> ch; int m = strlen(ch); for (int i = 1; i < n; i++) { cin >> temp; for (int j = 0; j < m; j++) { if (ch[j] >= a && ch[j] <= z && temp[j] >= a && temp[j] <= z && ch[j] != temp[j]) ok[j] = 1, ch[j] = ? ; if (ch[j] == ? && !ok[j]) ch[j] = temp[j]; } } for (int i = 0; i < m; i++) { if (ch[i] == ? && !ok[i]) cout << x ; else cout << ch[i]; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__OR2B_PP_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2B_PP_BLACKBOX_V
|
// file: Clock65MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock65MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock65MHz_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
#include <cstdio> #include <iostream> #define ll long long using namespace std; int n , m , cnt = 0; const int N = 5e5 + 5; const int mod = 1e9 + 7; ll pow2[N]; int num[N] , fa[N]; int find(int x){ if(fa[x] == x) return x; return fa[x] = find(fa[x]); } int main(){ pow2[0] = 1; cin >> n >> m; for(int i = 1; i < N; i++) pow2[i] = 1ll * 2 * pow2[i - 1] % mod; for(int i = 1; i <= m + 1; i++) fa[i] = i; for(int i = 1; i <= n; i++){ int k; int x , y; scanf( %d , &k); if(k == 1){ scanf( %d , &x); y = m + 1; } else scanf( %d%d , &x , &y); int fx , fy; fx = find(x); fy = find(y); if(fx == fy) continue; fa[fx] = fy; num[++cnt] = i; } ll ans = pow2[cnt] % mod; cout << ans << << cnt << endl; for(int i = 1; i <= cnt; i++) printf( %d , num[i]); return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:44:51 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/led_controller_design_led_controller_0_0_stub.v
// Design : led_controller_design_led_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module led_controller_design_led_controller_0_0(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000001; const double EPS = 10e-9; const int MAXN = 100005; pair<int, int> t[MAXN << 1]; int MOD; void rob() { int n; scanf( %d , &n); int tmp; for (typeof(0) i = (0); i < (n); ++i) { scanf( %d , &tmp); t[i] = make_pair(tmp, i); } for (typeof(0) i = (0); i < (n); ++i) { scanf( %d , &tmp); t[n + i] = make_pair(tmp, i); } scanf( %d , &MOD); n <<= 1; sort(t, t + n); long long res = 1; int i = 0; int pow; int fac; while (i < n) { fac = 1; pow = 0; for (++i; i < n; ++i) { if (t[i].first != t[i - 1].first) break; if (t[i].second == t[i - 1].second) ++pow; ++fac; } for (typeof(1) j = (1); j <= (fac); ++j) { if (pow && !(j & 1)) { res = (res * (j >> 1)) % MOD; --pow; } else { res = (res * j) % MOD; } } } printf( %I64d n , res); } int main() { int test = 1; while (test--) rob(); return 0; }
|
/*******************************************************************************
*
* NetFPGA-10G http://www.netfpga.org
*
* File:
* timestamp_insertion_pkt_train.v
*
* Library:
* hw/osnt/pcores/osnt_10g_interface_v1_11_a
*
* Module:
* nf10_10g_interface
*
* Author:
* Antonis Gavaletakis HPCN-UAM
*
*
* Copyright (C) 2015 - HPCN-UAM High Performance Computing and Networking
*
* Licence:
* This file is part of the HPCN-NetFPGA 10G development base package.
*
* This file is free code: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 2.0 as
* published by the Free Software Foundation.
*
* This package is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with the NetFPGA source package. If not, see
* http://www.gnu.org/licenses/.
*
*/
module timestamp_insertion_antonis
#(
parameter TIMESTAMP_WIDTH = 64,
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128
)
(
output reg [C_M_AXIS_DATA_WIDTH-1:0] m_axis_tdata,
output reg [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output reg [C_M_AXIS_DATA_WIDTH/8-1:0]m_axis_tstrb,
output reg m_axis_tvalid,
output reg m_axis_tlast,
input m_axis_tready,
input [TIMESTAMP_WIDTH-1:0] stamp_counter,
input pkt_start,
input [C_M_AXIS_DATA_WIDTH-1:0] s_axis_tdata,
input [C_M_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input [C_M_AXIS_DATA_WIDTH/8-1:0]s_axis_tstrb,
input s_axis_tvalid,
input s_axis_tlast,
output s_axis_tready,
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam TIMESTAMP = 32;
localparam WAIT = 1;
localparam SEND_PACKET = 2;
localparam MAX_PKT_RX_QUEUE = 66;
localparam IN_TIME_DEPTH_BIT = log2(MAX_PKT_RX_QUEUE);
// wire [TIMESTAMP_WIDTH-1:0] stamp_counter1;
// assign stamp_counter1 = 64'h1234567891234567;
wire timestamp_fifo_nearly_full;
wire timestamp_fifo_empty;
reg timestamp_fifo_rd_en;
reg in_fifo_rd_en;
wire in_fifo_empty;
wire in_fifo_nearly_full;
wire [TIMESTAMP_WIDTH-1:0] fifo_timestamp;
wire [C_M_AXIS_TUSER_WIDTH-1:0] tuser_fifo;
wire [((C_M_AXIS_DATA_WIDTH / 8))-1:0] tstrb_fifo;
wire tlast_fifo;
wire [C_M_AXIS_DATA_WIDTH-1:0] tdata_fifo;
reg[1:0] state,state_next;
assign s_axis_tready = !in_fifo_nearly_full;
integer i;
integer j;
integer k;
fallthrough_small_fifo #(.WIDTH(C_M_AXIS_DATA_WIDTH+C_M_AXIS_TUSER_WIDTH+C_M_AXIS_DATA_WIDTH/8+1), .MAX_DEPTH_BITS(2))
input_fifo
(.din ({s_axis_tlast, s_axis_tuser, s_axis_tstrb, s_axis_tdata}), // Data in
.wr_en (s_axis_tvalid & ~in_fifo_nearly_full), // Write enable
.rd_en (in_fifo_rd_en), // Read the next word
.dout ({tlast_fifo, tuser_fifo, tstrb_fifo, tdata_fifo}),
.full (),
.prog_full (),
.nearly_full (in_fifo_nearly_full),
.empty (in_fifo_empty),
.reset (reset),
.clk (clk)
);
fallthrough_small_fifo
#( .WIDTH(TIMESTAMP_WIDTH),
.MAX_DEPTH_BITS(IN_TIME_DEPTH_BIT)
) timestamp_fifo
(
// Outputs
.dout (fifo_timestamp),
.full (),
.nearly_full (timestamp_fifo_nearly_full),
.prog_full (),
.empty (timestamp_fifo_empty),
// Inputs
.din (stamp_counter),
.wr_en (pkt_start),
.rd_en (timestamp_fifo_rd_en),
.reset (reset),
.clk (clk)
);
always @(*) begin
m_axis_tuser = tuser_fifo;
m_axis_tstrb = tstrb_fifo;
m_axis_tlast = tlast_fifo;
m_axis_tdata = tdata_fifo;
m_axis_tvalid = 0;
in_fifo_rd_en = 0;
timestamp_fifo_rd_en = 0;
state_next = state;
case(state)
WAIT: begin
if(!timestamp_fifo_empty && !in_fifo_empty) begin
m_axis_tvalid = 1;
m_axis_tuser[TIMESTAMP+TIMESTAMP_WIDTH-1:TIMESTAMP] = fifo_timestamp;
if(m_axis_tready) begin
in_fifo_rd_en = 1;
//timestamp_fifo_rd_en = 1;
state_next = SEND_PACKET;
end
end
end
SEND_PACKET: begin
if(!in_fifo_empty) begin
m_axis_tvalid = 1;
if(m_axis_tready) begin
in_fifo_rd_en = 1;
if(tdata_fifo[63:16]==48'hAAAAAAAAAAAA) //first part
begin
for(k =0 ; k < 6; k= k+1)
for(j=0; j<8; j= j+1)
//m_axis_tdata[143:80] =stamp_counter;
m_axis_tdata[23+((k*8)-j)] = stamp_counter [63-(k*8)-j];// 7+(k*8)-j];
$display ("tmp data : %h \n",m_axis_tdata );
end
else if(tdata_fifo[15:0]==16'hAAAA)
begin
for(k =0 ; k < 2; k= k+1)
for(j=0; j<8; j= j+1)
//m_axis_tdata[143:80] =stamp_counter;
m_axis_tdata[7+(k*8)-j] = stamp_counter [15-(k*8)-j];// 7+(k*8)-j];
$display ("tmp data : %h \n",m_axis_tdata );
timestamp_fifo_rd_en = 1;
end
if(tlast_fifo)
state_next=WAIT;
end
end
end
endcase
end
always @(posedge clk) begin
if(reset) begin
state <= WAIT;
end
else begin
state <= state_next;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 100010; int t[MX]; int main() { int n; cin >> n; for (int i = (1); i <= (n); ++i) { scanf( %d , &t[i]); } for (int i = (1); i <= (n); ++i) { printf( %d , t[i] + t[i + 1]); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_TB_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_TB_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdrivernovlp2.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__busdrivernovlp2 dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_dirg_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_dirg_buf(/*AUTOARG*/
// Outputs
lkup_wr_data_up_buf, lkup_wr_data_dn_buf,
// Inputs
dirrep_dir_wr_par_c4, dir_vld_c4_l, lkup_addr8_c4,
tagdp_lkup_addr_c4
);
input dirrep_dir_wr_par_c4; // Right
input dir_vld_c4_l; // Right
input lkup_addr8_c4; // Right
input [39:10] tagdp_lkup_addr_c4; // Right Make sure that the pin order
// is same as in the driving block tagdp.
output [32:0] lkup_wr_data_up_buf; // Top Msb to the left
output [32:0] lkup_wr_data_dn_buf; // Bottom Msb to the left
// buffer should take 40-50 ps Max
assign lkup_wr_data_up_buf = { tagdp_lkup_addr_c4, lkup_addr8_c4, dirrep_dir_wr_par_c4, dir_vld_c4_l };
assign lkup_wr_data_dn_buf = { tagdp_lkup_addr_c4 , lkup_addr8_c4, dirrep_dir_wr_par_c4, dir_vld_c4_l };
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[200][200], ans, n; bool flag = true; int main() { ios::sync_with_stdio(false); cin >> a[80][80] >> n; while (flag) { flag = false; for (int i = 1; i < 160; i++) for (int j = 1; j < 160; j++) if (a[i][j] >= 4) { flag = true; int k = a[i][j] / 4; a[i + 1][j] += k, a[i - 1][j] += k; a[i][j + 1] += k, a[i][j - 1] += k; a[i][j] -= 4 * k; } } for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; if (-80 < x && x < 80 && -80 < y && y < 80) cout << a[x + 80][y + 80] << n ; else cout << 0 << n ; } return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, dfi_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [4*DQ_WIDTH-1:0] dfi_rddata;
wire [4*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<4; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(dfi_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [4*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [4*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<4; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
dfi_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [4*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [4*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<4; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [4*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<4; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<4; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [3:0] ecc_single;
output wire [3:0] ecc_multiple;
genvar v;
generate
for (v=0; v<4; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_TB_V
`define SKY130_FD_SC_MS__A221OI_TB_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_TB_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_10_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_0_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region_or
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region_or
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
// Testbench for m6502 ALU.
module tb_m6502_alu;
reg [7 : 0] tb_operation;
reg [7 : 0] tb_op_a;
reg [7 : 0] tb_op_b;
reg tb_carry_in;
wire [7 : 0] tb_result;
wire tb_carry;
wire tb_zero;
wire tb_overflow;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
//----------------------------------------------------------------
// dut
//----------------------------------------------------------------
m6502_alu dut(
.operation(tb_operation),
.op_a(tb_op_a),
.op_b(tb_op_b),
.carry_in(tb_carry_in),
.result(tb_result),
.carry(tb_carry),
.zero(tb_zero),
.overflow(tb_overflow)
);
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//----------------------------------------------------------------
task init_sim;
begin
tc_ctr = 0;
error_ctr = 0;
tb_operation = 8'h0;
tb_op_a = 8'h0;
tb_op_b = 8'h0;
tb_carry_in = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// main
//----------------------------------------------------------------
initial
begin : main
$display(" -= Testbench for m6502 ALU started =-");
$display(" ====================================");
$display("");
init_sim();
display_test_results();
$display("");
$display("*** m6502 ALU simulation done. ***");
$finish;
end // main
endmodule // tb_m6502_alu
|
// -- test force/release of:
// a wire assigned to a reg
// a wire with no assignment
// a whole bus (assigned to a reg),
// a single bit of a bus (assigned to a reg)
// -- make sure the force/release is passed into the hierarchy
//
// -- run with
// iverilog -Wall tt.v
// vvp a.out
// -- to see debug display statements, use
// iverilog -Wall -DDISPLAY tt.v
//
module top ();
reg [31:0] ii;
reg bitfail, bitnafail, busfail, busbitfail;
reg a;
reg [1:0] b;
wire bit = a;
wire bitna;
wire [1:0] bus = b;
wire [1:0] ibus = b;
wire subfail, subfailna;
// call in a lower level module
subtop U1 (
.subbit(bit),
.subbus(bus),
.subfail(subfail)
);
subtop U2 (
.subbit(bitna),
.subbus(bus),
.subfail(subfailna)
);
initial begin
a = 1'b1;
b = 2'b01;
#5; b = 2'b10;
#10; b = 2'b11;
end
initial begin
#2;
force bit = 0;
force bitna = 0;
force bus = 0;
//$display("\n ****** force/release to ibus[0] commented; expect bit[0] failure ******* ");
force ibus[0] = 0;
#10;
release bit;
force bitna = 1;
release bus;
#5;
release ibus[0];
end
initial begin
bitfail = 0; bitnafail = 0; busfail = 0; busbitfail = 0;
`ifdef DISPLAY
$display("");
$display("expecting bit, bus,ibus to be 1 at T=1");
$display("then changing to 0 at T=2");
$display("then bit and bus are 0 from T=3 to T=11, while");
$display("ibus changes to 2 at T=5 and remains 2 through to T=16");
$display("bit changes to 1 at T=12 and remains 1 from then on.");
$display("bus changes to 2 at T=12");
$display("then 2 from T=13 to T=14");
$display("then changing to 3 at T=15");
$display("then 3 from T=16 on");
$display("ibus changes to 3 at T=17 and remains 3 from then on");
$display("");
`endif
for(ii = 0; ii < 20; ii = ii + 1) begin
// bit
if((ii == 1) && (bit !== 1)) bitfail = 1;
if((ii > 2) && (ii < 12) && (bit !== 0)) bitfail = 1;
if((ii > 12) && (bit !== 1)) bitfail = 1;
// bitna
if((ii == 1) && (bitna !== 1'bz)) bitnafail = 1;
if((ii > 2) && (ii < 12) && (bitna !== 0)) bitnafail = 1;
if((ii > 12) && (bitna !== 1)) bitnafail = 1;
// bus
if((ii == 1) && (bus !== 1)) busfail = 1;
if((ii > 2) && (ii < 12) && (bus !== 0)) busfail = 1;
if((ii > 12) && (ii < 14) && (bus !== 2'b10)) busfail = 1;
if((ii > 15) && (bus !== 2'b11)) busfail = 1;
// ibus
if((ii == 1) && (ibus !== 2'b01)) busbitfail = 1;
if((ii > 2) && (ii < 4) && (ibus !== 2'b00)) busbitfail = 1;
if((ii > 5) && (ii < 17) && (ibus !== 2'b10)) busbitfail = 1;
if((ii > 17) && (ibus !== 2'b11)) busbitfail = 1;
`ifdef DISPLAY
$display("time: %0t, a: %b, bit: %b, bitna %b, b: %b, bus: %b, ibus: %b",$time,a,bit,bitna,b,bus,ibus);
`endif
#1;
end
if(bitfail || bitnafail || busfail || busbitfail || subfail || subfailna) begin
$display("\n\t--------- force test failed ---------");
if(bitfail) $display("force to single wire assigned to a reg failed");
if(bitnafail) $display("force to single unassigned wire failed");
if(busfail) $display("force to whole of 2-bit bus failed");
if(busbitfail) $display("force to bit[0] of 2-bit bus failed");
if(!bitfail && !bitnafail && !busfail && !busbitfail) begin
if(subfail) $display("force did not affect U1 hierarchy");
if(subfailna) $display("force did not affect U2 hierarchy");
end
$display("\n");
end else $display("PASSED");
end
endmodule
module subtop(
subbit,
subbus,
subfail
);
input subbit;
input [1:0] subbus;
output subfail;
reg subfail;
reg [31:0] ii;
initial begin
subfail = 0;
for(ii = 0; ii < 20; ii = ii + 1) begin
// subbit
if((ii == 1) && (subbit !== 1) && (subbit !== 1'bz)) subfail = 1;
if((ii > 2) && (ii < 12) && (subbit !== 0)) subfail = 1;
if((ii > 12) && (subbit !== 1)) subfail = 1;
// subbus
if((ii == 1) && (subbus !== 1)) subfail = 1;
if((ii > 2) && (ii < 12) && (subbus !== 0)) subfail = 1;
if((ii > 12) && (ii < 14) && (subbus !== 2'b10)) subfail = 1;
if((ii > 15) && (subbus !== 2'b11)) subfail = 1;
`ifdef DISPLAY
$display("\t\t\t\t\ttime: %0t, subbit: %b, subbus: %b",$time,subbit,subbus);
`endif
#1;
end
end
endmodule
|
#include <bits/stdc++.h> int main() { int n, a, b, c, sum = 0, i, j; int d[10001] = {0}; scanf( %d %d %d %d , &n, &a, &b, &c); for (i = 0; i <= a / 2; i++) d[i]++; for (i = a / 2; i >= 0; i--) { for (j = 1; j <= b && i + j <= n; j++) { d[i + j]++; } } for (i = 0; i <= c; i++) { if (n - i * 2 >= 0) sum += d[n - i * 2]; } printf( %d n , sum); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = (int)4e2; const int INF = (int)1e9; int n, m, a[N][N], p; int dyn[N][N], last[N]; vector<pair<int, int> > q[N * N]; int len[N][N]; int main() { cin >> n >> m >> p; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cin >> a[i][j]; q[a[i][j]].push_back(make_pair(i, j)); dyn[i][j] = INF; } } for (int i = 0; i < m; ++i) { dyn[0][i] = i; } for (int lvl = 1; lvl <= p; ++lvl) { int x, y; for (auto tmp : q[lvl]) { tie(x, y) = tmp; int ans = INF; for (int row = 0; row < n; ++row) { if (last[row] == lvl - 1) { ans = min(ans, dyn[row][y] + abs(row - x)); } } len[x][y] = ans; } for (auto tmp : q[lvl]) { tie(x, y) = tmp; if (last[x] != lvl) { last[x] = lvl; for (int col = 0; col < m; ++col) { dyn[x][col] = len[x][y] + abs(y - col); } } else { for (int col = 0; col < m; ++col) { dyn[x][col] = min(dyn[x][col], len[x][y] + abs(y - col)); } } } } cout << len[q[p][0].first][q[p][0].second] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; string t = ; for (int i = 0; i < s.length(); i++) { if (s[i] != a && s[i] != e && s[i] != i && s[i] != o && s[i] != u && s[i] != y && s[i] != Y && s[i] != A && s[i] != E && s[i] != I && s[i] != O && s[i] != U ) { t += s[i]; } } string p = ; for (int i = 0; i < t.length(); i++) { char c = t[i]; if (isupper(c)) { p += tolower(c); } else { p += c; } } string l = ; for (int i = 0; i < p.length(); i++) { l += . ; l += p[i]; } cout << l; }
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pio_dutycycle (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 3: 0] out_port;
output [ 3: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 3: 0] writedata;
wire clk_en;
reg [ 3: 0] data_out;
wire [ 3: 0] out_port;
wire [ 3: 0] read_mux_out;
wire [ 3: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[3 : 0];
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
|
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