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//=======================================================================
// Filename :cloz.v
// Author :(RDC)
// Created On :2014-04-28 09:31
// Last Modified :
// Update Count :2014-04-28 09:31
// Description :To Count the number of leading ones/zero in a word
//
//
//=======================================================================
module cloz(/*AUTOARG*/
//Inputs
data_in, io,
//Outputs
data_out);
input [31:0] data_in;
input io;
output [31:0] data_out;
/*
reg [31:0] v, c, data_out;
always @* begin
if (io == 1)
v = ~(data_in ^ (data_in - 1));
else
v = data_in ^ (data_in - 1);
for (c=0; v; c=c+1)
v = v>>1;
data_out = c;
end
*/
wire [31:0] result = 32'b0;
wire [31:0] value;
wire [15:0] val16;
wire [7:0] val8;
wire [3:0] val4;
assign value = io ? ~data_in : data_in;
assign result[4] = (value[31:16] == 16'b0);
assign val16 = result[4] ? value[15:0] : value[31:16];
assign result[3] = (val16[15:8] == 8'b0);
assign val8 = result[3] ? val16[7:0] : val16[15:8];
assign result[2] = (val8[7:4] == 4'b0);
assign val4 = result[2] ? val8[3:0] : val8[7:4];
assign result[1] = (val4[3:2] == 2'b0);
assign result[0] = result[1] ? ~val4[1] : ~val4[3];
assign data_out = result;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100; const int maxm = 100; const int maxlen = maxn + maxm - 1; struct point { int ind, p; bool operator<(const point& b) const { return p < b.p; } } cell[maxlen]; char state[maxlen]; int n, m; long long k; int p; long long dp[maxlen][maxlen]; long long Cnt() { memset(dp, 0, sizeof(dp)); if (state[0] == ) ) return 0; dp[0][1] = 1; for (int i = 1; i <= (n - 1) + (m - 1); ++i) { for (int j = 0; j <= (n - 1) + (m - 1); ++j) { if (state[i] == 0) { if (j > 0) dp[i][j] = dp[i - 1][j - 1]; dp[i][j] += dp[i - 1][j + 1]; } else if (state[i] == ( ) { if (j > 0) dp[i][j] = dp[i - 1][j - 1]; } else dp[i][j] = dp[i - 1][j + 1]; if (dp[i][j] > k) dp[i][j] = k + 1; } } return dp[(n - 1) + (m - 1)][0]; } int main() { ios_base::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 0; i <= (n - 1) + (m - 1); ++i) cell[i].ind = i, cell[i].p = n * m + 1; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) { cin >> p; cell[i + j].p = min(cell[i + j].p, p); } sort(cell, cell + n + m - 1); for (int i = 0; i <= (n - 1) + (m - 1); ++i) { state[cell[i].ind] = ( ; long long num = Cnt(); if (num < k) { k -= num; state[cell[i].ind] = ) ; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) cout << state[i + j]; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a = 1, b, c = 0, d = 0, e = 0, f, i = 0, k = 0, j = 0, n = 0, t = 0, l = 0, m = 0, h[3000] = {0}; string s, x; cin >> t; n = 1000000; for (i = 0; i < t; i++) { cin >> b; j = max(j, min(b - 1, 1000000 - b)); } cout << j; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3006; struct arr { int x, y, i; } a[maxn]; int r, c, n, K; int pos[maxn], L[maxn], R[maxn]; long long ans; bool cmpx(arr x, arr y) { if (x.x == y.x) return x.y < y.y; return x.x < y.x; } bool cmpy(arr x, arr y) { if (x.y == y.y) return x.x < y.x; return x.y < y.y; } int main() { scanf( %d%d%d%d , &r, &c, &n, &K); for (int i = 1; i <= n; i++) scanf( %d%d , &a[i].x, &a[i].y); sort(a + 1, a + n + 1, cmpy); for (int i = 1; i <= n; i++) a[i].i = i; sort(a + 1, a + n + 1, cmpx); for (int i = 1; i <= n; i++) L[i] = i - 1; for (int i = 1; i <= n; i++) R[i] = i + 1; for (int i = 1; i <= n; i++) pos[a[i].i] = i; R[0] = 1; L[n + 1] = n; pos[n + 1] = n + 1; a[n + 1].x = r + 1; a[n + 1].y = c + 1; int nn = n; for (int i = r; i >= 1; i--) { int t = 0; long long tmp = 0; for (int j = 1; j <= n && a[j].x <= i; t = j++) R[L[a[j].i]] = R[a[j].i], L[R[a[j].i]] = L[a[j].i]; for (int j = i, k = t; j >= 1; ans += tmp, j--) { for (; a[k].x == j; k--) { R[L[a[k].i]] = a[k].i; L[R[a[k].i]] = a[k].i; int val = 1, lp = a[k].i, rp = a[k].i; for (; L[lp] && val < K; lp = L[lp], val++) ; for (; lp <= a[k].i; lp = R[lp], val--) { for (; R[rp] <= n && val < K; rp = R[rp], val++) ; if (val < K) break; long long tmp_1 = a[pos[lp]].y - a[pos[L[lp]]].y; long long tmp_2 = a[pos[R[rp]]].y - a[pos[rp]].y; tmp += tmp_1 * tmp_2; } } } while (a[nn].x == i) { R[L[a[nn].i]] = R[a[nn].i]; L[R[a[nn].i]] = L[a[nn].i]; nn--; } } printf( %lld n , ans); return 0; }
|
`timescale 1ns / 1ps
module uart_tx(
input CLK,
input RST,
input EN,
input [DATAWIDTH - 1 : 0] DATA,
input DATARDY,
output READ,
output TX
);
parameter DATAWIDTH = 8;
parameter IDLE = 4'h0;
parameter START = 4'h1;
parameter BIT_TX = 4'h2;
parameter STOP = 4'h3;
reg read_reg;
reg tx_reg;
reg [1:0] curr_state;
reg [1:0] next_state;
reg [2:0] bit_cnt;
always @ (posedge CLK) begin
if(RST == 1) begin
tx_reg <= 1;
next_state <= IDLE;
curr_state <= IDLE;
bit_cnt <= 3'h0;
end
else begin
case(curr_state)
IDLE: begin
tx_reg <= 1'b1;
if((EN == 1'b1) && (DATARDY == 1'b1)) begin
read_reg <= 1;
next_state <= START;
end
else begin
read_reg <= 0;
next_state <= IDLE;
end
end
START: begin
tx_reg <= 1'b0;
read_reg <= 1'b0;
next_state <= BIT_TX;
end
BIT_TX: begin
tx_reg <= DATA[bit_cnt];
if(bit_cnt == 3'h7) begin
bit_cnt <= 3'h0;
next_state <= STOP;
end
else begin
bit_cnt <= bit_cnt + 1'b1;
next_state <= BIT_TX;
end
end
STOP: begin
tx_reg <= 1'b1;
if(DATARDY == 1'b1) begin
read_reg <= 1'b1;
next_state <= START;
end
else begin
next_state <= IDLE;
end
end
default: begin
tx_reg <= 1'b1;
next_state <= IDLE;
end
endcase
curr_state <= next_state;
end
end
assign READ = read_reg;
assign TX = tx_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; int m, n, h; int t[maxn]; int first[maxn * 2], nxt[maxn * 2], des[maxn * 2], tot; int dfn[maxn], low[maxn], dft; bool d[maxn]; int flag[maxn], cnt[maxn], scc; stack<int> stk; inline void add(int x, int y) { tot++; des[tot] = y; nxt[tot] = first[x]; first[x] = tot; } void tar(int node) { dfn[node] = low[node] = ++dft; stk.push(node); for (int t = first[node]; t; t = nxt[t]) { int v = des[t]; if (!dfn[v]) tar(v); low[node] = min(low[node], low[v]); } if (dfn[node] == low[node]) { scc++; while (true) { int temp = stk.top(); flag[temp] = scc; cnt[scc]++; stk.pop(); if (temp == node) break; } } } int main() { scanf( %d%d%d , &n, &m, &h); for (int i = 1; i <= n; i++) { scanf( %d , t + i); } for (int i = 0; i < m; i++) { int u1, u2; scanf( %d%d , &u1, &u2); if (t[u1] == (t[u2] + 1) % h) add(u2, u1); if (t[u2] == (t[u1] + 1) % h) add(u1, u2); } for (int i = 1; i <= n; i++) { if (!dfn[i]) tar(i); } for (int i = 1; i <= n; i++) { for (int t = first[i]; t; t = nxt[t]) { if (flag[i] == flag[des[t]]) continue; else { d[flag[i]]++; } } } cnt[0] = n + 1; int ans = 0; for (int i = 1; i <= scc; i++) { if (d[i] == 0 && cnt[i] < cnt[ans]) { ans = i; } } cout << cnt[ans] << endl; for (int i = 1; i <= n; i++) { if (flag[i] == ans) { cout << i << ; } } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, x, ans, kiri, kanan, sum, i, pos; long long a[300007], dua[300007]; int main() { scanf( %lld , &n); dua[0] = 1; for (i = 1; i <= 300000; i++) dua[i] = (dua[i - 1] * 2) % 1000000007; x = 1; scanf( %lld , &a[0]); pos = -1; for (i = 1; i < n; i++) { scanf( %lld , &a[i]); sum = (sum + x) % 1000000007; x = (x * 2) % 1000000007; pos++; } sort(a, a + n); kiri = 0; kanan = n - 1; x = 1; while (kiri <= kanan) { ans = (ans + sum * (a[kanan] - a[kiri])) % 1000000007; kiri++; kanan--; sum = ((sum - x) % 1000000007 + 1000000007) % 1000000007; sum = ((sum - dua[pos]) % 1000000007 + 1000000007) % 1000000007; pos--; x = (x * 2) % 1000000007; } printf( %lld n , ans); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a, b, sum = 0, sum1 = 0; cin >> n >> m >> a >> b; sum = n / m; sum1 = n - (sum * m); if (sum * b < n * a) { cout << min((sum * b + sum1 * a), ((sum + 1) * b)); } if (sum * b >= n * a) { cout << n * a; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; if (k < 25) { cout << -1 << endl; } else { int r = 0, c = 0; for (int i = 5; i <= sqrt(k); i++) { if (k % i == 0) { r = i; c = k / i; break; } } if (r == 0 or c == 0) { cout << -1 << endl; } else { char ch[] = { a , e , i , o , u }; string fr = ; for (int j = 0; j < r; j++) { for (int i = 0; i < c; i++) { fr += ch[(j + i) % 5]; } } cout << fr << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); for (int tt = 0; tt < t; tt++) { vector<vector<int> > A(9, vector<int>(9)); for (int i = 0; i < 9; i++) { int q; scanf( %d , &q); for (int j = 0; j < 9; j++) { A[i][8 - j] = q % 10; q /= 10; } } A[0][0] = A[0][1]; A[1][3] = A[0][3]; A[2][6] = A[0][6]; A[3][1] = A[3][0]; A[4][4] = A[3][4]; A[5][7] = A[4][7]; A[6][2] = A[6][1]; A[7][5] = A[8][5]; A[8][8] = A[7][7]; for (int i = 0; i < 9; i++) { for (int j = 0; j < 9; j++) printf( %d , A[i][j]); printf( n ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_LP_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_LP_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog wrapper for inputisolatch with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputisolatch.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inputisolatch_lp (
Q ,
D ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inputisolatch base (
.Q(Q),
.D(D),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inputisolatch_lp (
Q ,
D ,
SLEEP_B
);
output Q ;
input D ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inputisolatch base (
.Q(Q),
.D(D),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_LP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; int n, a[N], pre[N], suf[N]; char ans[N]; struct Fenwick { int n, c[N]; void init(int _n) { n = _n; memset(c, 0, sizeof(c[0]) * (n + 1)); } void upd(int i, int v) { while (i <= n) { c[i] = max(c[i], v); i += i & -i; } } int qry(int i) { int r = 0; while (i > 0) { r = max(r, c[i]); i -= i & -i; } return r; } } fw; void solve(int f[]) { fw.init(*max_element(a, a + n)); for (int i = (0); i < (n); ++i) { f[i] = fw.qry(a[i] - 1) + 1; fw.upd(a[i], f[i]); } } map<pair<int, int>, int> R; int main() { scanf( %d , &n); for (int i = (0); i < (n); ++i) scanf( %d , a + i); solve(pre); reverse(a, a + n); int L = *max_element(a, a + n); for (int i = (0); i < (n); ++i) a[i] = L - a[i] + 1; solve(suf); reverse(suf, suf + n); L = *max_element(pre, pre + n); for (int i = (0); i < (n); ++i) if (pre[i] + suf[i] - 1 == L) { ++R[make_pair(pre[i], suf[i])]; } else { ans[i] = 1 ; } for (int i = (0); i < (n); ++i) if (pre[i] + suf[i] - 1 == L) ans[i] = 2 + (R[make_pair(pre[i], suf[i])] == 1); ans[n] = 0 ; puts(ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool isprime(long long n) { if (n == 2) return true; if (n < 2 || n % 2 == 0) return false; for (long long i = 3; i * i <= n; i += 2) { if (n % i == 0) return false; } return true; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; int n; cin >> n; if (isprime(n)) cout << 1 << endl; else if (n % 2 == 0) cout << 2 << endl; else if (isprime(n - 2)) cout << 2 << endl; else cout << 3 << endl; return 0; }
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module vgachar(
input wire clk,
input wire clr,
input wire cBlink,
/* char data input */
input wire [6:0] char,
input wire [7:0] fontcolor,
input wire [7:0] backcolor,
input wire Blink,
/* Pipeline VGA sync */
input wire xsync,
input wire ysync,
input wire [11:0] xpos,
input wire [11:0] ypos,
input wire valid,
/* VGA output */
output reg [2:0] vgaRed,
output reg [2:0] vgaGreen,
output reg [2:1] vgaBlue,
output reg hsync,
output reg vsync
);
wire [10:0] addra;
wire [7:0] douta;
wire pixel;
asciifont fontmap (
.a(addra), // input [10 : 0] addra
.spo({douta[0], douta[1], douta[2], douta[3],
douta[4], douta[5], douta[6], douta[7]}) // output [7 : 0] douta
);
assign addra = {char, ypos[3:0]};
assign pixel = douta[xpos[2:0]];
always @(posedge clk or posedge clr)
if(clr == 1) begin
vgaRed <= 3'b000;
vgaGreen <= 3'b000;
vgaBlue[2:1] <= 2'b00;
hsync <= 0;
vsync <= 0;
end else begin
hsync <= xsync;
vsync <= ysync;
if(valid == 0) begin
vgaRed <= 3'b000;
vgaGreen <= 3'b000;
vgaBlue[2:1] <= 2'b00;
end else if(pixel && ~(Blink && cBlink)) begin
vgaRed <= fontcolor[7:5];
vgaGreen <= fontcolor[4:2];
vgaBlue[2:1] <= fontcolor[1:0];
end else begin
vgaRed <= backcolor[7:5];
vgaGreen <= backcolor[4:2];
vgaBlue[2:1] <= backcolor[1:0];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[105][105][12]; int main() { int n, C, q; scanf( %d%d%d , &n, &q, &C); for (int i = 1; i <= n; i++) { int a, b, c; scanf( %d%d%d , &a, &b, &c); dp[a][b][c]++; } for (int i = 1; i <= 100; i++) for (int j = 1; j <= 100; j++) for (int k = 0; k <= 10; k++) dp[i][j][k] += dp[i - 1][j][k] + dp[i][j - 1][k] - dp[i - 1][j - 1][k]; while (q--) { int t, x1, x2, y1, y2; scanf( %d%d%d%d%d , &t, &x1, &y1, &x2, &y2); long long ans = 0; for (int i = 0; i <= C; i++) { int l = (i + t) % (C + 1); ans += l * (dp[x2][y2][i] - dp[x2][y1 - 1][i] - dp[x1 - 1][y2][i] + dp[x1 - 1][y1 - 1][i]); } printf( %lld n , ans); } return 0; }
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
//`define ENABLE_HPS
module DE0_NANO_SOC_Default(
//////////// ADC //////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
`ifdef ENABLE_HPS
//////////// HPS //////////
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CKE,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout HPS_GSENSOR_INT,
inout HPS_I2C0_SCLK,
inout HPS_I2C0_SDAT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif /*ENABLE_HPS*/
//////////// KEY //////////
input [1:0] KEY,
//////////// LED //////////
output [7:0] LED,
//////////// SW //////////
input [3:0] SW,
//////////// GPIO_0, GPIO connect to GPIO Default //////////
inout [35:0] GPIO_0,
//////////// GPIO_1, GPIO connect to GPIO Default //////////
inout [35:0] GPIO_1
);
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [31:0] Cont;
//=======================================================
// Structural coding
//=======================================================
assign GPIO_0 = 36'hzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzz;
always@(posedge FPGA_CLK1_50 or negedge KEY[0])
begin
if(!KEY[0])
Cont <= 0;
else
Cont <= Cont+1;
end
assign LED = KEY[0]? {Cont[25:24],Cont[25:24],Cont[25:24],
Cont[25:24],Cont[25:24]}:10'h3ff;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFBBN_PP_SYMBOL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK,
D ,
DE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_V
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2010-2011
//
// mix up border and pixels, add palette and blanks
//
module video_palframe(
input wire clk, // 28MHz clock
input wire hpix,
input wire vpix,
input wire hblank,
input wire vblank,
input wire [ 3:0] pixels,
input wire [ 3:0] border,
input wire atm_palwr,
input wire [ 5:0] atm_paldata,
output reg [ 5:0] palcolor, // just for palette readback
output wire [ 5:0] color
);
wire [ 3:0] zxcolor;
reg win;
reg [3:0] border_r;
// always @(posedge clk)
// win <= hpix & vpix;
//
// always @(posedge clk)
// border_r <= border;
//
// assign zxcolor = win ? pixels : border_r;
assign zxcolor = (hpix&vpix) ? pixels : border;
// palette
reg [5:0] palette [0:15]; // let quartus instantiate it as RAM if needed
always @(posedge clk)
begin
if( atm_palwr )
palette[zxcolor] <= atm_paldata;
palcolor <= palette[zxcolor];
end
assign color = (hblank | vblank) ? 6'd0 : palcolor;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:01:05 04/13/2015
// Design Name:
// Module Name: Sieve
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sieve(input clk, output reg [8:0] primeNumber, output reg loop
);
reg [255:0] nextNumberArray;
reg [255:0] numberArray;
reg [9:0] nextIndex;
reg [9:0] index;
reg nextLoop;
reg [8:0] nextPrimeNumber;
initial begin
nextNumberArray = 256'b0;
nextNumberArray = ~nextNumberArray;
numberArray = 256'b0;
numberArray = ~numberArray;
index = 10'd4;
nextIndex = 10'd4;
nextPrimeNumber = 9'd2;
primeNumber = 9'd2;
loop = 0;
nextLoop = 0;
end
always @ (posedge clk) begin
numberArray <= nextNumberArray;
index <= nextIndex;
primeNumber <= nextPrimeNumber;
loop <= nextLoop;
end
always @ (*) begin
if (index < 256) begin
nextNumberArray[index] = 0;
nextIndex = index + primeNumber;
nextPrimeNumber = primeNumber;
nextLoop = 0;
end
else begin
nextNumberArray = numberArray;
if (loop) begin
if (numberArray[primeNumber] == 0) begin
nextPrimeNumber = primeNumber + 1;
nextLoop = 1;
nextIndex = index;
end
else begin
nextPrimeNumber = primeNumber;
nextIndex = primeNumber + primeNumber;
nextLoop = 0;
end
end
else begin
nextPrimeNumber = primeNumber + 1;
nextLoop = 1;
nextIndex = index;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout << setprecision(20) << fixed; long long t; cin >> t; while (t--) { long long n; cin >> n; long long a[n]; vector<long long> b, c; long long s = 0, z = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; if (a[i] > 0) { b.push_back(a[i]); s += a[i]; } else if (a[i] == 0) z++; else c.push_back(a[i]); } long long f = 0; for (long long i = 0; i < c.size(); i++) { if (s + c[i] != 0) { s += c[i]; b.push_back(c[i]); } else { f = 1; b.push_back(c[i]); s += c[i]; } } if (f == 1) reverse(b.begin(), b.end()); for (long long i = 0; i < z; i++) b.push_back(0); if (s == 0) cout << NO << endl; else { cout << YES << endl; for (long long i = 0; i < n; i++) cout << b[i] << ; cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace sat { const int MAX = 200010; bool vis[MAX]; vector<int> ed[MAX], rev[MAX]; int n, m; vector<int> order; int comp[MAX]; inline int inv(int x) { return ((x) <= n ? (x + n) : (x - n)); } void init(int vars) { n = vars, m = vars << 1; for (int i = 1; i <= m; i++) { ed[i].clear(); rev[i].clear(); } } inline void add(int a, int b) { ed[a].push_back(b); rev[b].push_back(a); } inline void OR(int a, int b) { add(inv(a), b); add(inv(b), a); } inline void AND(int a, int b) { add(a, b); add(b, a); } void XOR(int a, int b) { add(inv(b), a); add(a, inv(b)); add(inv(a), b); add(b, inv(a)); } inline void XNOR(int a, int b) { add(a, b); add(b, a); add(inv(a), inv(b)); add(inv(b), inv(a)); } inline void force_true(int x) { add(inv(x), x); } void dfs(int s) { vis[s] = true; for (int x : ed[s]) { if (vis[x]) continue; dfs(x); } order.push_back(s); } void mark(int s, int c) { comp[s] = c; vis[s] = true; for (int x : rev[s]) { if (vis[x]) continue; mark(x, c); } } bool satisfy(vector<int> &res) { memset(vis, 0, sizeof(vis)); for (int i = 1; i <= m; i++) { if (vis[i]) continue; dfs(i); } memset(vis, 0, sizeof(vis)); reverse(order.begin(), order.end()); int it = 0; for (int s : order) { if (vis[s]) continue; mark(s, ++it); } res.clear(); for (int i = 1; i <= n; i++) { if (comp[i] == comp[inv(i)]) return false; if (comp[i] > comp[inv(i)]) res.push_back(i); } return true; } } // namespace sat int main() { int n, m, a, b, c; scanf( %d %d , &n, &m); sat::init(n); for (int i = 1; i <= m; i++) { scanf( %d %d %d , &a, &b, &c); if (c == 0) sat::XOR(a, b); else sat::XNOR(a, b); } vector<int> V; if (sat::satisfy(V)) { cout << V.size() << endl; for (int i = 0; i < V.size(); i++) cout << V[i] << ; puts( ); } else puts( Impossible ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_1_V
`define SKY130_FD_SC_LP__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_1_V
|
#include <bits/stdc++.h> using namespace std; struct node { int data; long int sum; struct node *left, *right; struct node* next; }; struct node* newNode(int data) { struct node* Node = new (struct node); Node->data = data; Node->left = Node->right = Node->next = NULL; return (Node); } long long ans[110][110][2]; void solveTestCase() { int n1, n2, k1, k2; scanf( %d , &n1); ; scanf( %d , &n2); ; scanf( %d , &k1); ; scanf( %d , &k2); ; k1 = min(k1, n1); k2 = min(k2, n2); ans[0][0][0] = 1; ans[0][0][1] = 1; for (int i = 0; i < n1 + 1; i++) { for (int j = 0; j < n2 + 1; j++) { if (i == 0 && j == 0) { continue; } for (int k = 1; k < k1 + 1; k++) { if (i - k < 0) { break; } ans[i][j][0] = (ans[i][j][0] + ans[i - k][j][1]) % 100000000; } for (int k = 1; k < k2 + 1; k++) { if (j - k < 0) { break; } ans[i][j][1] = (ans[i][j][1] + ans[i][j - k][0]) % 100000000; } } } long long ans_final = (ans[n1][n2][0] + ans[n1][n2][1]) % 100000000; printf( %I64d n , ans_final); ; } int main() { solveTestCase(); return 0; }
|
`timescale 1ns/1ps
module key_gen(
clk,
reset,
p2k_valid,
p2k_ingress,
p2k_rloc_src,
p2k_eid_dst,
p2k_metadata,
mode, //1 ceng die wang ;
k2m_metadata_valid,
k2m_metadata
);
input clk;
input reset;
input p2k_valid;
input [7:0] p2k_ingress;
input [127:0] p2k_rloc_src;
input [127:0] p2k_eid_dst;
input [7:0] p2k_metadata;//useless
input mode;
output k2m_metadata_valid;
output [107:0] k2m_metadata;
reg k2m_metadata_valid;
reg [107:0] k2m_metadata;
//reg [127:0] rloc_src;
//reg [127:0] eid_dst;
//--state--//
//reg [3:0] key_state;
//-------------------key_gen_state-------------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
k2m_metadata_valid <= 1'b0;
k2m_metadata <= 108'b0;
end
else
begin
if(p2k_valid == 1'b1)
begin
if(mode == 1'b1)//ceng die wang
begin
if(p2k_ingress == 8'b0) k2m_metadata <= {mode,p2k_ingress,p2k_rloc_src[17:0],81'b0};
else k2m_metadata <= {mode,p2k_ingress,18'b0,81'b0};
k2m_metadata_valid <= 1'b1;
end
else//shi wang
begin
k2m_metadata_valid <= 1'b1;
k2m_metadata <= {mode,p2k_ingress,p2k_eid_dst[127:56],56'b0};
end
end
else k2m_metadata_valid <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_SYMBOL_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s15kapwr (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 1e6 + 7; long long t, n, k, temp; int main(int argc, char* argv[]) { cin >> t; while (t--) { cin >> n >> k; long long cnt = 0; while (n > 0) { if (n % k != 0) { cnt += n % k; n -= n % k; } else { cnt++; n /= k; } } cout << cnt << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1; cin >> t; while (t--) { long long int i, j, k, n, m = 1e10, f = 1; cin >> n; vector<long long int> a(n), b(n), in, val; for (i = 0; i < n; i++) { cin >> a[i], b[i] = a[i]; m = min(a[i], m); } sort(b.begin(), b.end()); for (i = 0; i < n; i++) if (a[i] % m == 0) in.emplace_back(i), val.emplace_back(a[i]); sort(val.begin(), val.end()); for (i = 0; i < in.size(); i++) a[in[i]] = val[i]; for (i = 0; i < n; i++) if (a[i] != b[i]) { f = 0; break; } if (f) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 10; int n, m, k; string l[maxn]; int t[maxn], T; int w[5][3]; vector<pair<int, int> > v; pair<pair<int, int>, pair<int, int> > a[maxn]; int vis[24 * 30 * 60 + 10]; int cor[24 * 30 * 60 + 10]; int dp[maxn][24 * 30 * 60 + 10]; int par[maxn][24 * 30 * 60 + 10]; inline bool cmp(pair<pair<int, int>, pair<int, int> > fi, pair<pair<int, int>, pair<int, int> > se) { return fi.first.second < se.first.second; } inline int solve(int work, int time) { time++; int &ret = dp[work][time]; if (ret > -1) return ret; if (work == 0) return ret = 0; int need = t[a[work].first.first]; if (need <= time) { int Max = solve(work - 1, min(time - 1 - need, a[work - 1].first.second)) + a[work].second.first; int Max_ = solve(work - 1, min(time - 1, a[work - 1].first.second)); if (Max > Max_) par[work][time] = 1; return ret = max(Max, Max_); } else return ret = solve(work - 1, min(time - 1, a[work - 1].first.second)); } inline void Out_(int Time) { int t = cor[Time]; cout << t / 1440 + 1 << ; int p, q; t %= 1440; p = t / 60; q = t % 60; if (p < 10) cout << 0 << p << : ; else cout << p << : ; if (q < 10) cout << 0 << q; else cout << q; } int main() { ios_base::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 1; i <= n; ++i) cin >> l[i]; for (int i = 1; i <= n; ++i) cin >> t[i]; for (int i = 1; i <= 4; ++i) { int p, q; int p_, q_; char g, g_; cin >> p >> g >> q >> g_ >> p_ >> g >> q_; w[i][1] = p * 60 + q; w[i][2] = p_ * 60 + q_; } for (int i = 1; i <= k; ++i) for (int j = 1; j <= 4; ++j) v.push_back(pair<int, int>(24 * 60 * (i - 1) + w[j][1], 24 * 60 * (i - 1) + w[j][2])); for (int i = 0; i < v.size(); ++i) for (int j = v[i].first; j <= v[i].second; ++j) vis[j] = 1; int cp = m; for (int i = 1, cur = 1; i <= m; ++i, cur++) { string hlp; cin >> hlp; for (int j = 1; j <= n; ++j) if (hlp == l[j]) a[i].first.first = j; int day; cin >> day; int p, q; char g; cin >> p >> g >> q; a[i].first.second = (day - 1) * 24 * 60 + p * 60 + q; cin >> a[i].second.first; a[i].second.second = cur; if (a[i].first.first == 0) { a[m] = a[i]; i--; m--; } } for (int i = 1; i <= m; ++i) { int q = 0; bool flag = false; for (int j = 0; j < v.size(); ++j) if (a[i].first.second >= v[j].first) if (a[i].first.second > v[j].second) q += v[j].second - v[j].first + 1; else { q += a[i].first.second - v[j].first + 1; flag = true; } a[i].first.second -= q; if (flag == false) a[i].first.second--; } sort(a + 1, a + 1 + m, cmp); int cur = 0; for (int i = 0; i < k * 24 * 60; ++i) if (vis[i] == 0) { cor[cur++] = i; T++; } T--; memset(dp, -1, sizeof dp); cout << solve(m, min(a[m].first.second, T)) << endl; vector<int> ans; int ind, time; time = min(a[m].first.second, T); ind = m; for (; ind > 0;) { time++; int need = t[a[ind].first.first]; int nex = par[ind][time]; if (nex == 1) { ans.push_back(ind); time = min(time - 1 - need, a[ind - 1].first.second); ind--; } else { time = min(time - 1, a[ind - 1].first.second); ind--; } } cout << ans.size() << endl; int Min = 0; for (int i = ans.size() - 1; i >= 0; --i) { cout << a[ans[i]].second.second << ; Out_(Min); cout << ; Out_(Min + t[a[ans[i]].first.first] - 1); cout << endl; Min += t[a[ans[i]].first.first]; } return 0; }
|
//
// Paul Gao 08/2019
//
//
`include "bsg_noc_links.vh"
module bsg_fifo_1r1w_small_hardened_test_node
#(parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,parameter is_client_node_p = 0
,localparam width_lp = num_channels_p * channel_width_p
,localparam bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(width_lp)
)
(// Node side
input node_clk_i
,input node_reset_i
,input node_en_i
,output logic error_o
,output [31:0] sent_o
,output [31:0] received_o
// Link side
,input clk_i
,input reset_i
,input [bsg_ready_and_link_sif_width_lp-1:0] link_i
,output [bsg_ready_and_link_sif_width_lp-1:0] link_o
);
localparam lg_fifo_depth_lp = 3;
genvar i;
// Async fifo signals
logic node_async_fifo_valid_li, node_async_fifo_yumi_lo;
logic node_async_fifo_valid_lo, node_async_fifo_ready_li;
logic [width_lp-1:0] node_async_fifo_data_li;
logic [width_lp-1:0] node_async_fifo_data_lo;
if (is_client_node_p == 0)
begin: master
/********************* Master node *********************/
logic resp_in_v;
logic [width_lp-1:0] resp_in_data;
logic resp_in_yumi;
logic req_out_ready;
logic [width_lp-1:0] req_out_data;
logic req_out_v;
bsg_two_fifo
#(.width_p(width_lp)
) resp_in_fifo
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.ready_o(node_async_fifo_ready_li)
,.v_i (node_async_fifo_valid_lo)
,.data_i (node_async_fifo_data_lo)
,.v_o (resp_in_v)
,.data_o (resp_in_data)
,.yumi_i (resp_in_yumi)
);
bsg_two_fifo
#(.width_p(width_lp)
) req_out_fifo
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.ready_o(req_out_ready)
,.v_i (req_out_v)
,.data_i (req_out_data)
,.v_o (node_async_fifo_valid_li)
,.data_o (node_async_fifo_data_li)
,.yumi_i (node_async_fifo_yumi_lo)
);
logic [width_lp-1:0] data_gen, data_check;
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p(num_channels_p)
) gen_out
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (req_out_v & req_out_ready)
,.o (data_gen)
);
assign req_out_v = node_en_i;
assign req_out_data = data_gen;
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p(num_channels_p)
) gen_in
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (resp_in_v)
,.o (data_check)
);
assign resp_in_yumi = resp_in_v;
// Count sent and received packets
bsg_counter_clear_up
#(.max_val_p(1<<32-1)
,.init_val_p(0)
) sent_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (req_out_v & req_out_ready)
,.count_o(sent_o)
);
bsg_counter_clear_up
#(.max_val_p(1<<32-1)
,.init_val_p(0)
) received_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (resp_in_v)
,.count_o(received_o)
);
// Check errors
always_ff @(posedge node_clk_i)
if (node_reset_i)
error_o <= 0;
else
if (resp_in_v && data_check != resp_in_data)
begin
$error("%m mismatched resp data %x %x",data_check, resp_in_data);
error_o <= 1;
end
end
else
begin: client
/********************* Client node *********************/
logic req_in_v;
logic [width_lp-1:0] req_in_data;
logic req_in_yumi;
logic resp_out_ready;
logic [width_lp-1:0] resp_out_data;
logic resp_out_v;
bsg_two_fifo
#(.width_p(width_lp)
) req_in_fifo
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.ready_o(node_async_fifo_ready_li)
,.v_i (node_async_fifo_valid_lo)
,.data_i (node_async_fifo_data_lo)
,.v_o (req_in_v)
,.data_o (req_in_data)
,.yumi_i (req_in_yumi)
);
// loopback any data received
assign resp_out_data = req_in_data;
assign resp_out_v = req_in_v;
assign req_in_yumi = resp_out_v & resp_out_ready;
bsg_two_fifo
#(.width_p(width_lp)
) resp_out_fifo
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.ready_o(resp_out_ready)
,.v_i (resp_out_v)
,.data_i (resp_out_data)
,.v_o (node_async_fifo_valid_li)
,.data_o (node_async_fifo_data_li)
,.yumi_i (node_async_fifo_yumi_lo)
);
end
/********************* Interfacing bsg_noc link *********************/
`declare_bsg_ready_and_link_sif_s(width_lp, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_i_cast, link_o_cast;
assign link_i_cast = link_i;
assign link_o = link_o_cast;
/********************* Async fifo to link *********************/
// Node side async fifo input
logic node_async_fifo_full_lo;
assign node_async_fifo_yumi_lo = ~node_async_fifo_full_lo & node_async_fifo_valid_li;
// Node side async fifo output
logic node_async_fifo_deq_li;
assign node_async_fifo_deq_li = node_async_fifo_ready_li & node_async_fifo_valid_lo;
// Link side async fifo input
logic link_async_fifo_full_lo;
assign link_o_cast.ready_and_rev = ~link_async_fifo_full_lo;
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) wh_to_mc
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_enq_i (link_i_cast.v & link_o_cast.ready_and_rev)
,.w_data_i (link_i_cast.data)
,.w_full_o (link_async_fifo_full_lo)
,.r_clk_i (node_clk_i)
,.r_reset_i(node_reset_i)
,.r_deq_i (node_async_fifo_deq_li)
,.r_data_o (node_async_fifo_data_lo)
,.r_valid_o(node_async_fifo_valid_lo)
);
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) mc_to_wh
(.w_clk_i (node_clk_i)
,.w_reset_i(node_reset_i)
,.w_enq_i (node_async_fifo_yumi_lo)
,.w_data_i (node_async_fifo_data_li)
,.w_full_o (node_async_fifo_full_lo)
,.r_clk_i (clk_i)
,.r_reset_i(reset_i)
,.r_deq_i (link_o_cast.v & link_i_cast.ready_and_rev)
,.r_data_o (link_o_cast.data)
,.r_valid_o(link_o_cast.v)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_small_hardened_test_node)
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$lcu" *)
module _80_xilinx_lcu (P, G, CI, CO);
parameter WIDTH = 2;
input [WIDTH-1:0] P, G;
input CI;
output [WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = WIDTH <= 2;
wire [WIDTH-1:0] C = {CO, CI};
wire [WIDTH-1:0] S = P & ~G;
genvar i;
generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(G[i]),
.S(S[i]),
.O(CO[i])
);
end endgenerate
endmodule
(* techmap_celltype = "$alu" *)
module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH-1:0] P = AA ^ BB;
wire [Y_WIDTH-1:0] G = AA & BB;
wire [Y_WIDTH-1:0] C = {CO, CI};
wire [Y_WIDTH-1:0] S = P & ~G;
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(G[i]),
.S(S[i]),
.O(CO[i])
);
XORCY xorcy (
.CI(C[i]),
.LI(S[i]),
.O(Y[i])
);
end endgenerate
assign X = P;
endmodule
|
#include <bits/stdc++.h> using namespace std; unsigned long long int dp[1001], sum[1001]; unsigned long long int nCrModp(unsigned long long int n, unsigned long long int r) { unsigned long long int p = 1000000007; n = n + r - 1; r = r - 1; unsigned long long int C[r + 1]; memset(C, 0, sizeof(C)); C[0] = 1; for (unsigned long long int i = 1; i <= n; i++) { for (unsigned long long int j = min(i, r); j > 0; j--) C[j] = (C[j] + C[j - 1]) % p; } return C[r]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); unsigned long long int n, t, i, j, k, ans = 0; cin >> n; unsigned long long int ar[n]; for (i = 0; i < n; i++) { cin >> ar[i]; if (i != 0) sum[i] = sum[i - 1] + ar[i]; else sum[i] = ar[i]; } unsigned long long int prod = 1; dp[0] = 1; for (i = 1; i < n; i++) { dp[i] = nCrModp(sum[i - 1], ar[i]) % 1000000007; prod *= dp[i]; prod %= 1000000007; } cout << prod; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DynamicDelay_Start.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DynamicDelay_Start (
address,
clock,
q);
input [0:0] address;
input clock;
output [127:0] q;
wire [127:0] sub_wire0;
wire [127:0] q = sub_wire0[127:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({128{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "DynamicDelay_Start.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 1,
altsyncram_component.width_a = 128,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "DynamicDelay_Start.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "1"
// Retrieval info: PRIVATE: WidthData NUMERIC "128"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "DynamicDelay_Start.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; struct node { int x, y; } arr[104]; vector<int> graph[105]; int visited[105] = {0}; void dfs(int i) { visited[i] = 1; int j = 0; while (j < graph[i].size()) { if (visited[graph[i][j]] == 0) { dfs(graph[i][j]); } j++; } } int main() { int n; scanf( %d , &n); int x, y; for (int i = 0; i < n; i++) { scanf( %d%d , &x, &y); arr[i].x = x; arr[i].y = y; } int hash[102] = {0}; int ct = 0; for (int i = 0; i < n; i++) { int flag = 0; for (int j = 0; j < n; j++) { if (i == j) continue; if (arr[j].x == arr[i].x || arr[j].y == arr[i].y) { graph[i].push_back(j); graph[j].push_back(i); flag = 1; } } if (flag == 0) visited[i] = 1; } for (int i = 0; i < n; i++) { if (visited[i] == 0) { dfs(i); ct++; } } int c = 0; for (int i = 0; i < n; i++) { if (!graph[i].size()) c++; } printf( %d n , c - 1 + ct); return 0; }
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; const long double ep = 1e-10; struct pnt { long double x, y; pnt() { x = y = 0; } pnt(long double xx, long double yy) { x = xx, y = yy; } pnt operator+(pnt a) { return pnt(x + a.x, y + a.y); } void in() { int xx, yy; cin >> xx >> yy; x = xx, y = yy; } long double operator^(const pnt &a) const { return x * a.y - y * a.x; } bool operator<(const pnt &a) const { return x != a.x ? x < a.x : y < a.y; } bool int_pnt(pnt &a) { int xx = x + (x > 0 ? 0.5 : -0.5), yy = y + (y > 0 ? 0.5 : -0.5); if (abs(x - xx) < ep && abs(y - yy) < ep) { a = pnt(xx, yy); return 1; } return 0; } } p[N], M, MM; vector<pnt> P; int n; map<pnt, int> h; bool opp[N]; int main() { cin >> n; for (int i = 1; i <= n; i++) { p[i].in(); M = M + p[i]; h[p[i]] = i; } M.x /= n, M.y /= n; MM.x = M.x * 2, MM.y = M.y * 2; for (int i = 1; i <= n; i++) if (!opp[i]) { pnt pp = pnt(MM.x - p[i].x, MM.y - p[i].y), qq; if (pp.int_pnt(qq) && h.count(qq)) { int t = h[qq]; opp[t] = 1; opp[i] = 1; } } for (int i = 1; i <= n; i++) if (!opp[i]) P.push_back(p[i]); if (P.empty()) puts( -1 ); else { pnt A = P[0]; int ans = 0; vector<pnt> D; for (auto x : P) { pnt AM = A + x; AM.x /= 2, AM.y /= 2; pnt d = pnt(M.x - AM.x, M.y - AM.y); vector<long double> pos, neg; for (auto y : P) { long double l = d ^ pnt(y.x - AM.x, y.y - AM.y); if (abs(l) < ep) continue; if (l < 0) neg.push_back(-l); else pos.push_back(l); } if (neg.size() != pos.size()) continue; sort(neg.begin(), neg.end()); sort(pos.begin(), pos.end()); bool flag = 0; for (int i = 0; i < pos.size(); i++) if (abs(pos[i] - neg[i]) > ep) flag = 1; if (!flag) D.push_back(d); } for (auto &x : D) { if (x.y < 0) x.y = -x.y, x.x = -x.x; if (x.y == 0 && x.x < 0) x.x = -x.x; } sort(D.begin(), D.end(), [](const pnt &x, const pnt &y) { return (x ^ y) > 0; }); int sz = D.size(); for (int i = 0, j; i < sz; i = j) { for (j = i; j < sz && (D[i] ^ D[j]) == 0; j++) ; ans++; } printf( %d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_4_V
`define SKY130_FD_SC_HS__O2BB2AI_4_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_4_V
|
#include <bits/stdc++.h> using namespace std; long long mul(long long a, long long b) { if (!b) return 1; long long k = mul(a, b / 2); if (b & 1) return k * k % 998244353 * a % 998244353; return k * k % 998244353; } int n, k, N; long long A[200010], B[200010], C[200010], a, b, c, sum; long long f[200010], g[200010], h[200010]; void FWT(long long *v, int dir) { long long inv2 = mul(2, 998244353 - 2); for (int i = 1; i < N; i <<= 1) for (int j = 0; j < N; j += 2 * i) for (int k = 0; k < i; k++) { long long x = v[j + k], y = v[j + k + i]; v[j + k] = (x + y) * (dir == -1 ? inv2 : 1) % 998244353; v[j + k + i] = (x - y + 998244353) * (dir == -1 ? inv2 : 1) % 998244353; } } int main() { ios::sync_with_stdio(false); cin >> n >> k >> a >> b >> c; N = (1 << k); for (int i = 0; i < n; i++) { cin >> A[i] >> B[i] >> C[i]; f[B[i] ^ A[i]]++, g[C[i] ^ A[i]]++, h[B[i] ^ C[i]]++; sum ^= A[i]; } FWT(f, 1), FWT(g, 1), FWT(h, 1); long long ans = 1; long long X = (a + b + c) % 998244353, Y = (a + b - c + 998244353) % 998244353, Z = (a - b + c + 998244353) % 998244353, W = (a - b - c + 2 * 998244353) % 998244353; long long inv2 = mul(2, 998244353 - 2); for (int i = 0; i < N; i++) { long long x = (n + f[i] + g[i] + h[i]) % 998244353 * inv2 % 998244353 * inv2 % 998244353, y = ((n + f[i]) % 998244353 * inv2 % 998244353 - x + 998244353) % 998244353, z = ((n + g[i]) % 998244353 * inv2 % 998244353 - x + 998244353) % 998244353, w = ((n + h[i]) % 998244353 * inv2 % 998244353 - x + 998244353) % 998244353; f[i] = mul(X, x) * mul(Y, y) % 998244353 * mul(Z, z) % 998244353 * mul(W, w) % 998244353; } FWT(f, -1); for (int i = 0; i < N; i++) cout << f[sum ^ i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, i; int oma = 0, omi = 0, ma, mi; int a[101]; string s; int main() { cin >> n >> k; for (i = 1; i <= n; i++) { cin >> s; a[s.size()]++; } cin >> s; for (i = 1; i < s.size(); i++) omi = omi + a[i]; mi = omi; ma = oma; omi = 5 * (omi / k) + 1 + omi; oma = a[s.size()] + ((a[s.size()] - 1 + mi) / k) * 5 + mi; cout << omi << << oma << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005, S = 100; int L[N], R[N], bel[N], to[N]; long long a[N], b[N], taga[N], tagb[N]; long double slope(int x, int y) { if (a[x] == a[y]) { if (b[x] == b[y]) return 1; return b[x] < b[y] ? 1e18 : -1e18; } return (long double)(b[y] - b[x]) / (a[y] - a[x]); } vector<int> s[N / S + 5]; int pos[N / S + 5]; void build(int x) { for (int i = L[x]; i <= R[x]; i++) b[to[i]] += a[to[i]] * taga[x] + tagb[x]; taga[x] = tagb[x] = 0; s[x].clear(); int top = 0; for (int i = L[x]; i <= R[x]; i++) { while (top > 1 && slope(s[x][top - 2], s[x][top - 1]) <= slope(s[x][top - 1], to[i])) --top, s[x].pop_back(); ++top, s[x].push_back(to[i]); } pos[x] = 0; } inline long long calc(int x) { return a[x] * taga[bel[x]] + b[x] + tagb[bel[x]]; } long long querymax(int x) { while (pos[x] < s[x].size() - 1) { if (calc(s[x][pos[x]]) > calc(s[x][pos[x] + 1])) break; pos[x]++; } return calc(s[x][pos[x]]); } bool cmp(const int& x, const int& y) { return a[x] < a[y]; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]), b[i] = a[i], to[i] = i; for (int i = 1; i <= n; i++) bel[i] = (i - 1) / S + 1; for (int i = 1; i <= bel[n]; i++) L[i] = S * (i - 1) + 1, R[i] = min(S * i, n), sort(to + L[i], to + R[i] + 1, cmp); for (int i = 1; i <= bel[n]; i++) build(i); long long ans = 0; for (int i = 1; i <= n; i++) { long long mx = -1ll << 60ll; int p; for (int j = 1; j <= bel[n]; j++) if (querymax(j) > mx) mx = querymax(j), p = s[j][pos[j]]; if (mx > 0 && p != 0) ans += mx; else break; b[p] = -1ll << 60ll; for (int j = 1; j < bel[p]; j++) tagb[j] += a[p]; for (int j = bel[p] + 1; j <= bel[n]; j++) taga[j]++; for (int j = L[bel[p]]; j < p; j++) b[j] += a[p]; for (int j = p + 1; j <= R[bel[p]]; j++) b[j] += a[j]; build(bel[p]); } printf( %lld , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_BEHAVIORAL_PP_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_2_V
`define SKY130_FD_SC_LP__NAND3B_2_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_2 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_2 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__BUF_BEHAVIORAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
/*
-- Module Name: output_control_unit
-- Description: Unida de control para el bloque de salida de la interfaz
de red. Este bloque se encarga de organizar la salida
de paquetes desde el nodo de procesamiento en direccion
al router de la NoC.
El control de creditos para el control de flujo de
paquetes reeside en este modulo.
-- Dependencies: -- system.vh
-- Parameters: -- BUFFER_DEPTH: Numero de flits que es capaz de
almacenar la cola de
almacenamiento de la NiC.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 18 de Junio 2015: Creacion
*/
`include "system.vh"
module output_control_unit
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire credit_in_din,
input wire done_strobe_din,
// -- outputs ------------------------------------------------ >>>>>
output wire zero_credits_dout,
output wire [2:0] output_selector_dout
);
// -- Parametros locales ----------------------------------------- >>>>>
// -- FSM ---------------------------------------------------- >>>>>
localparam IDLE = 2'b00;
localparam REQUEST = 2'b01;
localparam ACTIVE = 2'b10;
// -- Flit Counter ------------------------------------------- >>>>>
localparam LOAD = 1'b1;
localparam DEC = 1'b0;
// -- Credit Counter ----------------------------------------- >>>>>
localparam CREDITS = `BUFFER_DEPTH/5;
localparam CRT_WIDTH = clog2(CREDITS);
/*
-- Contador de creditos.
-- Descripcion: Registro de control de creditos disponibles en el
router. La señal 'zero_credits' se conecta con el bloque
de entrada de la interfaz de red para el control de
flujo de paquetes.
El numero de creditos esta definido por el router de la
NoC, no por la interfaz.
La llegada de la señal 'credit_in_din' incrementa en 1
el numero de creditos disponibles.
*/
// -- Elemento de Memoria :: Contador de Creditos ------------ >>>>>
reg [CRT_WIDTH-1:0] credit_reg;
reg [CRT_WIDTH-1:0] credit_next;
always @(posedge clk)
if (reset)
credit_reg <= CREDITS;
else
credit_reg <= credit_next;
always @(*)
begin
credit_next = credit_reg;
case ({credit_in_din, credit_sub})
2'b01: credit_next = credit_reg - 1'b1;
2'b10: credit_next = credit_reg + 1'b1;
endcase //{credit_in_din, credit_sub}
end
// -- Logica de Estado Siguiente :: Contador de Creditos ----- >>>>>
assign credit_sub = (state_reg == REQUEST & state_next == ACTIVE) ? 1'b1 : 1'b0;
// -- Logica de salidas -------------------------------------- >>>>>
assign zero_credits = ~(|credit_reg);
assign zero_credits_dout = zero_credits;
/*
-- Contador de transferencia de flits.
-- Descripcion: Contador para el control de numero de flits que se han
liberado de la salida de la interfaz de red en direccion
al router.
Este contador maneja la salida 'output_selector_dout',
la cual es una señal selectora del registro de salida
que se expondra para la captura de dato por parte del
router de la red.
El valor por defecto de la señal 'output_selector_dout'
es 0.
*/
// -- Elementos de memoria ----------------------------------- >>>>>
reg [2:0] flit_counter_reg;
reg [2:0] flit_counter_next;
wire flit_counter_load;
wire flit_counter_sub;
always @(posedge clk)
if (reset)
flit_counter_reg <= 3'b000;
else
flit_counter_reg <= flit_counter_next;
// -- Logica del estado siguiente ---------------------------- >>>>>
always @(*)
begin
flit_counter_next <= flit_counter_reg;
case ({flit_counter_load, flit_counter_sub})
2'b10:
flit_counter_next <= `DATA_FLITS + 1;
2'b01:
flit_counter_next <= flit_counter_reg - 1'b1;
endcase
end
// -- Logica de salidas -------------------------------------- >>>>>
assign output_selector_dout = (state_next == ACTIVE || state_reg == ACTIVE) ? flit_counter_reg : 3'b000;
/*
-- Maquina de estados
-- Descripcion: FSM para el control de la salida de la interfaz de red.
La FSM inicia en un estado de reposo (IDLE), en este
estado espera por la señal 'done_strobe_din' desde el
nodo de procesamiento. Este evento indica a la FSM que
el nodo a terminado su tarea y que el resultado correcto
se encuentra disponible.
Con la recepcion 'done_strobe_din' la FSM transita al
estado 'REQUEST'. eL ESTADO 'REQUEST' es un estado
intermedio donde se valida la disponiblidad de creditos
para la transferencia de datos al router. Este estado
es necesario ya que la señal 'done_strobe_din' es un
pulso transitorio.
Si se cuenta con creditos necesarios para la
tranferencia de un paquete de datos, la FSM pasa al
estado 'ACTIVE'.
La FSM permanece en estado 'ACTIVE' un numero de ciclos
igual al numero de flits que forman un paquete. Cada
ciclo en 'ACTIVE' substrae una unidad al contador de
flits de este modulo. Con la salida de todos los flits,
indicada por:
flit_counter_reg == 3'b000
La FSM transita nuevamente al estado de reposo en espera
al siguiente paquete para ser transferido a la red.
La finalizacion de una transferencia de paquete
decrementa el contador de creditos, ya que un espacio de
buffer en el router a sido tomado por el paquete recien
liberado.
*/
// -- FSM -------------------------------------------------------- >>>>>
// -- Elementos de memoria ----------------------------------- >>>>>
reg [1:0] state_reg;
reg [1:0] state_next;
always @(posedge clk)
if (reset)
state_reg <= IDLE;
else
state_reg <= state_next;
// -- Logica del estado siguiente ---------------------------- >>>>>
always @(*)
begin
state_next <= state_reg;
case (state_reg)
IDLE:
if (done_strobe_din)
state_next <= REQUEST;
REQUEST:
if (~zero_credits)
state_next <= ACTIVE;
ACTIVE:
if (flit_counter_reg == {3{1'b0}})
state_next <= IDLE;
endcase // state_reg
end
// -- logica de salida --------------------------------------- >>>>>
assign flit_counter_load = (state_reg == IDLE & state_next == REQUEST) ? 1'b1 : 1'b0;
assign flit_counter_sub = (state_next == ACTIVE) ? 1'b1 : 1'b0;
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
// -- Simbolos de depuracion --------------------------------- >>>>>
reg [8*7:0] state_reg_dbg;
always @(*)
case (state_reg)
IDLE : state_reg_dbg = " IDLE ";
REQUEST : state_reg_dbg = "REQUEST";
ACTIVE : state_reg_dbg = " ACTIVE";
default : state_reg_dbg = "ERROR";
endcase
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
output_control_unit output_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.done_strobe_din (done_strobe_din),
// -- outputs ------------------------------------------------ >>>>>
.zero_credits_dout (zero_credits_dout),
.output_selector_dout (output_selector_dout)
);
*/
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; int base = sqrt(n); if (base * base == n) { cout << base << << 1 << endl; return; } n = n - base * base; if (n <= base + 1) { cout << n << << base + 1 << endl; } else cout << base + 1 << << (2 * (base + 1) - n) << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { solve(); } }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
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#include <bits/stdc++.h> using namespace std; struct abc { int p, q, idx; }; bool compareTwoStudents(abc a, abc b) { if (a.p != b.p) return a.p < b.p; return (a.q < b.q); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int i, j, k, m, n, t, u, v, w, p = 0, q, flag = 0; long long int x, y, z; string s, s1, s2; vector<int> abc; vector<int>::iterator it; priority_queue<int> pq; map<int, int> make_pair; cin >> t; while (t--) { std::cin >> n; std::cout << n << n ; } return 0; }
|
#include <bits/stdc++.h> int main() { int n, m; int sum = 0; int a, b; int i = 0; int x[1010] = {0}, y[1010] = {0}; scanf( %d %d , &n, &m); while (m-- > 0) { scanf( %d %d , &a, &b); y[a] = 1; x[b] = 1; } for (i = 2; i <= n - 1; i++) { if (x[i] == 0) sum++; if (y[i] == 0) sum++; } if (n % 2 == 1 && x[n / 2 + 1] == 0 && y[n / 2 + 1] == 0) sum--; printf( %d n , sum); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1000 + 10; char ch[N]; int a[N][N]; int h[N], l[N]; int n, m; int main() { cin >> n >> m; int tot = 0; for (int i = 1; i <= n; i++) { scanf( %s , ch + 1); for (int j = 1; j <= m; j++) { a[i][j] = ch[j] == * ? 1 : 0; h[i] += a[i][j]; l[j] += a[i][j]; tot += a[i][j]; } } int x = -1, y = -1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (h[i] + l[j] - a[i][j] == tot) { x = i; y = j; break; } if (x == -1) { puts( NO ); } else { puts( YES ); cout << x << << y << endl; } return 0; }
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// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_256_134.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_256_134 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [133:0] data;
input rdreq;
input wrreq;
output empty;
output [133:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [133:0] sub_wire1;
wire [7:0] sub_wire2;
wire empty = sub_wire0;
wire [133:0] q = sub_wire1[133:0];
wire [7:0] usedw = sub_wire2[7:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.usedw (sub_wire2),
.almost_empty (),
.almost_full (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 134,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "134"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "134"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "134"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 134 0 INPUT NODEFVAL "data[133..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 134 0 OUTPUT NODEFVAL "q[133..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 134 0 data 0 0 134 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 134 0 @q 0 0 134 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main(int argc, const char* argv[]) { int n; cin >> n; int a[n]; int b[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; } long long mx = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { long long an = 0; long long bn = 0; for (int t = i; t <= j; t++) { an = an | a[t]; bn = bn | b[t]; } if (an + bn > mx) { mx = an + bn; } } } cout << mx; }
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#include<bits/stdc++.h> using namespace std; #define ll long long template <typename Arg1> //print with endl void pn(Arg1&& arg1) { cout<<arg1<< n ;} template <typename Arg1, typename... Args> void pn(Arg1&& arg1, Args&&... args) { cout<<arg1<< n ; pn(args...); } //print with space template <typename Arg1> void ps(Arg1&& arg1) { cout<<arg1<< ;} template <typename Arg1, typename... Args> void ps(Arg1&& arg1, Args&&... args) { cout<<arg1<< ; ps(args...); } template <typename Arg1> void pvs(Arg1&& arg1, ll n) { for(ll i=0;i<n;i++)ps(arg1[i]); } template <typename Arg1> void pvn(Arg1&& arg1, ll n) { for(ll i=0;i<n;i++)pn(arg1[i]); } ll sum(ll n){ ll v=0; while(n!=0){ v+=(n%10); n/=10; } return v; } ll log(ll n, ll b) { ll c=0; while(n>(b-1)) { c++; n/=b; } return c; } #define fast ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); #define mod 1000000007 //10^9+7 #define st string #define ull unsigned long long #define pb push_back #define mp make_pair #define vi vector <int> #define vll vector <long long> #define f0(i,a) for(i=0;i<a;i++) #define f1(i,a) for(i=1;i<=n;i++) #define all(a) a.begin(),a.end() #define sz(a) a.size() #define lb lower_bound #define ub upper_bound #define pl pair<ll,ll> #define vpl vector<pl> #define ff first #define ss second #define um unordered_map #define dsort(v) sort(v); reverse(v); #define maxall(v) *max_element(all(v)) #define minall(v) *min_element(all(v)) #define gcd(a,b) __gcd(a,b) #define lcm(a,b) a/__gcd(a,b)*b #define Y YES #define N NO #define endl n #define debug(x) cout << #x << : << x << nl; const ll MOD = 998244353; const ll inf = 1e18; const ll MAX = 2e5 + 1; ll GCD(ll a,ll b){ if(b==0) return a; else return GCD(b,a%b); } ll mulmod(ll x,ll n,ll M) { ll result=1; while(n>0) { if(n% 2 ==1) result=(result * x)%M; x=(x*x)%M; n=n/2; } return result; } ///////////////////////// bool isPowerOfTwo(ll n) { if (n == 0) return 0; while (n != 1) { if (n%2 != 0) return 0; n = n/2; } return 1; } void solve(){ ll i; ll n; cin>>n; vll v(n); f0(i,n) cin>>v[i]; f0(i,n){ if(v[i]&1) cout<<v[i]<< ; } f0(i,n){ if(!(v[i]&1)) cout<<v[i]<< ; } cout<<endl; } int main(){ fast; #ifdef Local freopen( inp.txt , r , stdin); // freopen( out.txt , w , stdin); #endif // solve();/* ll t; cin>>t; for(ll tt=1;tt<=t;tt++) { // cout<< Case # <<tt<< : ; solve(); } //*/ }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: playback_fifo.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module playback_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
wrempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output rdempty;
output rdfull;
output wrempty;
output wrfull;
output [4:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire [4:0] sub_wire5;
wire [63:0] q = sub_wire0[63:0];
wire rdempty = sub_wire1;
wire rdfull = sub_wire2;
wire wrempty = sub_wire3;
wire wrfull = sub_wire4;
wire [4:0] wrusedw = sub_wire5[4:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (sub_wire2),
.wrempty (sub_wire3),
.wrfull (sub_wire4),
.wrusedw (sub_wire5),
.eccstatus (),
.rdusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
dcfifo_mixed_widths_component.lpm_numwords = 32,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 32,
dcfifo_mixed_widths_component.lpm_widthu = 5,
dcfifo_mixed_widths_component.lpm_widthu_r = 4,
dcfifo_mixed_widths_component.lpm_width_r = 64,
dcfifo_mixed_widths_component.overflow_checking = "OFF",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "OFF",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "ON",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "64"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL "wrusedw[4..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo_bb.v TRUE
|
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test limited length strings in VHDL.
module vhdl_string_lim_test;
logic start, res;
vhdl_string_lim dut(start, res);
initial begin
#1;
if(res !== 1'b1) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
//__________________________________________________uart_tx
`define RDY 2'b11
`define LOAD_BIT 2'b01
`define SEND_BIT 2'b00
`define STOP 2'b10
//__________Test Bench
`define BIT_TMR_MAX 10'd869 // test bench <-- 115200 : tb #1738
//`define BIT_TMR_MAX 4'd10417//14'b10100010110000 // 14'd1023
//______________________________________________________________________
`define BIT_INDEX_MAX 4'd10
module uart_tx(
input clk,
input rst,
input send,
input [7:0] data_tx,
output done,
output txd
);
reg [9:0] bitTmr;
//wire bitDone;
reg [3:0] bitIndex;
wire txBit;
//reg [9:0] txdata_tx;
reg [1:0] txState;
assign done = (txState == `STOP) ? 1'b1 : 1'b0;
assign txd = (txState == `SEND_BIT) ? txBit : 1'b1;
//{1'b1,data_tx[7:0],1'b0}
assign txBit =( (bitIndex == 0) ? 1'b0 :
( (bitIndex == 1) ? data_tx[0] :
( (bitIndex == 2) ? data_tx[1] :
( (bitIndex == 3) ? data_tx[2] :
( (bitIndex == 4) ? data_tx[3] :
( (bitIndex == 5) ? data_tx[4] :
( (bitIndex == 6) ? data_tx[5] :
( (bitIndex == 7) ? data_tx[6] :
( (bitIndex == 8) ? data_tx[7] :
1'b1
)
)
)
)
)
)
)
)
);
always@(posedge clk) begin
if(rst)
txState<= `RDY;
else
case(txState)
`RDY :
begin
bitIndex <= 0;
bitTmr <= 0;
if(send == 1'b1)
txState<=`SEND_BIT;
else
txState<=`RDY;
end
`SEND_BIT : begin
if (bitTmr == `BIT_TMR_MAX-1)
begin
bitTmr <=0;
if (bitIndex == `BIT_INDEX_MAX-1)
begin
txState<=`STOP;
end
else
begin
bitIndex <= bitIndex + 1'b1;
txState<=`SEND_BIT;
end
end
else
begin
bitTmr <= bitTmr + 1'b1;
txState <= `SEND_BIT;
end
end
`STOP :
begin
if(send == 1'b1)
txState<=txState;
else //if(send == 1'b0)
txState<=`RDY;
end
default : txState <= `RDY;
endcase
end
/*
always@(posedge clk) begin
if(rst)
bitTmr <= 0;
else
if(txState[0] == 1) // if(txState == `RDY)
bitTmr <= 0;
else
if(bitDone)
bitTmr <= 0;
else
bitTmr <= bitTmr +1 ;
end
assign bitDone = (bitTmr == `BIT_TMR_MAX) ? 1 : 0;
always@(posedge clk) begin
if(rst)
bitIndex <= 0;
else
if(txState[1] == 1) // if(txState == `RDY)
bitIndex <= 0;
else
if(txState == `LOAD_BIT)
bitIndex <= bitIndex +1 ;
else
bitIndex <= bitIndex;
end
*/
/*
always@(posedge clk) begin
if(rst)
txdata_tx <= 0;
else
if(txState[1] == 0) // if(send == 1'b1)
txdata_tx <= {1'b1,data_tx,1'b0} ;
else
txdata_tx <= 10'b1_1111_1111_1;
end
always@(posedge clk) begin
if(rst)
txBit <= 1'b1;
else
if(txState[1] == 1) // if(txState == `RDY)
txBit <= 1'b1 ;
else //if(txState == `LOAD_BIT)
txBit <= txdata_tx[bitIndex];
end
assign txd = rst ? 1 : txBit;
*/
//assign ready = (txState == `RDY) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; vector<int> v; set<double> S; set<double>::iterator it, it2; int main() { int n, k; cin >> n >> k; cin >> s; for (int i = 0; i < s.size(); i++) if (s[i] == 0 ) v.push_back(i + 1); int i = 0, j = 0; for (i = 0; i <= k; i++) S.insert(v[i]); j = i - 1; i = 0; int mn = INT_MAX; n = v.size(); while (j < n) { double x = (v[i] + v[j]) / 2.0; it = S.lower_bound(x); it2 = it; it2--; int a = max(v[j] - *it, *it - v[i]); int b = max(*it2 - v[i], v[j] - *it2); mn = min(mn, min(a, b)); j++; if (j < n) { S.erase(v[i]); S.insert(v[j]); i++; } } cout << mn; return 0; }
|
module serial_rx #(
parameter CLK_PER_BIT = 50,
parameter CTR_SIZE = 6
)(
input clk,
input rst,
input rx,
output [7:0] data,
output new_data
);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
WAIT_HALF = 2'd1,
WAIT_FULL = 2'd2,
WAIT_HIGH = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg new_data_d, new_data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg rx_d, rx_q;
assign new_data = new_data_q;
assign data = data_q;
always @(*) begin
rx_d = rx;
state_d = state_q;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
new_data_d = 1'b0;
case (state_q)
IDLE: begin
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (rx_q == 1'b0) begin
state_d = WAIT_HALF;
end
end
WAIT_HALF: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == (CLK_PER_BIT >> 1)) begin
ctr_d = 1'b0;
state_d = WAIT_FULL;
end
end
WAIT_FULL: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
data_d = {rx_q, data_q[7:1]};
bit_ctr_d = bit_ctr_q + 1'b1;
ctr_d = 1'b0;
if (bit_ctr_q == 3'd7) begin
state_d = WAIT_HIGH;
new_data_d = 1'b1;
end
end
end
WAIT_HIGH: begin
if (rx_q == 1'b1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
bit_ctr_q <= 3'b0;
new_data_q <= 1'b0;
state_q <= IDLE;
end else begin
ctr_q <= ctr_d;
bit_ctr_q <= bit_ctr_d;
new_data_q <= new_data_d;
state_q <= state_d;
end
rx_q <= rx_d;
data_q <= data_d;
end
endmodule
|
`timescale 1ns / 1ps
module clock_tb();
parameter DELAY = 10;
parameter TIME = 1000;
reg clk_src, power, enable, reset;
reg [2:0] add_time, sub_time;
reg timing_clock_switch;
wire alarm, timing_clock_alarm;
wire [7:0] anodes, cnodes;
clock #(32, 0, 5, 4, 3, 5, 5) DUT (
.clk_src(clk_src),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time),
.sub_time(sub_time),
.timing_clock_switch(timing_clock_switch),
.alarm(alarm),
.timing_clock_alarm(timing_clock_alarm),
.anodes(anodes),
.cnodes(cnodes)
);
initial begin
clk_src <= 0;
power <= 0;
enable <= 0;
reset <= 0;
add_time <= 3'b000;
sub_time <= 3'b000;
timing_clock_switch <= 0;
#TIME $finish;
end
always begin
#DELAY clk_src <= ~clk_src;
end
always begin
// power = 0, enable = 0
// all buttons don't work
#(DELAY) add_time = 3'b111;
#(DELAY) add_time = 0;
#(DELAY) sub_time = 3'b111;
#(DELAY) sub_time = 0;
// power = 0, enable = 1
// all buttons don't work
#(DELAY) add_time = 3'b111;
#(DELAY) add_time = 0;
#(DELAY) sub_time = 3'b111;
#(DELAY) sub_time = 0;
// power = 1, enable = 1
// reset works, add_time/sub_time doesn't work
// feat: reset && count
#(DELAY) power = 1;
#(DELAY) enable = 1;
#(DELAY/2);
#(DELAY) add_time = 3'b111;
#(DELAY) add_time = 0;
#(DELAY) sub_time = 3'b111;
#(DELAY) sub_time = 0;
#(5*DELAY) reset = 1;
#(DELAY) reset = 0;
// power = 1, enable = 0
// reset works, add_time/sub_time works
// feat: add time && sub time
#(10*DELAY) enable = 0;
#(10*DELAY); // pause
#(DELAY) add_time = 3'b111;
#(2*DELAY) add_time = 0;
#(DELAY) sub_time = 3'b111;
#(DELAY) sub_time = 0;
// power = 0
// when power off, automatically reset all clock
#(DELAY) power = 0;
// test timing clock feature
#(DELAY) power = 1;
#(DELAY) timing_clock_switch = 1;
#(DELAY) add_time[0] = 1;
#(5*DELAY) add_time[1] = 0;
#(DELAY) timing_clock_switch = 0;
#(DELAY) enable = 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = long unsigned long; using ld = double long; template <class T, int N, int B> struct asym_ra { T a[N + 1]; T b[N / B + 2]; T get(int r) { if (r <= 0) return T(); if (r > N) r = N; return a[r] + b[r / B]; } T operator()(int l, int r) { return get(r) - get(l); } void add(int p, const T& v) { for (int i = p + 1; i % B && i <= N; i++) a[i] += v; for (int i = p / B + 1; i < N / B + 2; i++) b[i] += v; } }; int n; int a[200005]; const int H = 300000; asym_ra<ll, H + 5, 512> cnt; asym_ra<ll, H + 5, 512> sum; int main() { ios::sync_with_stdio(!cin.tie(0)); cin >> n; ll sol = 0; for (int i = 0; i < n; i++) { int x; cin >> x; for (int j = 0; j <= H; j += x) { sol += sum(j, j + x) - cnt(j, j + x) * 1ll * j; } for (int q = 1;;) { int r = x / q; int l = x / (q + 1) + 1; r++; sol += x * cnt(l, r) - q * sum(l, r); if (l == 1) break; q = x / (l - 1); } sol += x * 1ll * cnt(x + 1, H + 1); cout << sol << ; cnt.add(x, 1); sum.add(x, x); } cout << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O221A_PP_BLACKBOX_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_PP_BLACKBOX_V
|
module testbench ();
reg clk = 0;
reg rst = 1;
reg req3 = 0;
reg req2 = 0;
reg req1 = 0;
reg req0 = 0;
wire gnt3;
wire gnt2;
wire gnt1;
wire gnt0;
// Clock generator
always #1 clk = ~clk;
integer file;
always @(posedge clk)
$fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});
initial begin
file = $fopen(`outfile);
repeat (5) @ (posedge clk);
rst <= 0;
repeat (1) @ (posedge clk);
req0 <= 1;
repeat (1) @ (posedge clk);
req0 <= 0;
repeat (1) @ (posedge clk);
req0 <= 1;
req1 <= 1;
repeat (1) @ (posedge clk);
req2 <= 1;
req1 <= 0;
repeat (1) @ (posedge clk);
req3 <= 1;
req2 <= 0;
repeat (1) @ (posedge clk);
req3 <= 0;
repeat (1) @ (posedge clk);
req0 <= 0;
repeat (1) @ (posedge clk);
#10 $finish;
end
// Connect the DUT
arbiter U (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_multistage_accumulator(clock, resetn, clear, result, increment, go);
// This module tessellates the accumulator into SECTION_SIZE-bit chunks.
// it is important to note that this accumulator has been designed to work with kernel finish detector,
// and as such the increment signal is not pipelined. This means that you cannot simply use it for arbitrary purposes.
// To make it work as a pipelined accumulator, INCREMENT_WIDTH must be no greater than SECTION_SIZE. In a case that it is,
// pipelining of the increment signal should be added. However, in kernel finish detector it is unnecessary.
//
// Assumption 1 - increment does not change until the final result is computed or INCREMENT_WIDTH < SECTION_SIZE. In the
// latter case, increment only needs to be valid for one clock cycle.
// Assumption 2 - clear and go are never asserted at the same time.
parameter ACCUMULATOR_WIDTH = 96;
parameter INCREMENT_WIDTH = 1;
parameter SECTION_SIZE = 19;
input clock, resetn, clear;
input [INCREMENT_WIDTH-1:0] increment;
input go;
output [ACCUMULATOR_WIDTH-1:0] result;
function integer stage_count;
input integer width;
input integer size;
integer temp,i;
begin
temp = width/size;
if ((width % size) > 0) temp = temp+1;
stage_count = temp;
end
endfunction
function integer mymax;
input integer a;
input integer b;
integer temp;
begin
if (a > b) temp = a; else temp = b;
mymax = temp;
end
endfunction
localparam TOTAL_STAGES = stage_count(ACCUMULATOR_WIDTH, SECTION_SIZE);
localparam INCR_FILL = mymax(ACCUMULATOR_WIDTH, TOTAL_STAGES*SECTION_SIZE);
// This little trick is for modelsim to resolve its handling of generate statements.
// It prevents modelsim from thinking there is an out-of-bound access to increment.
// This also simplifies one of the if statements below.
reg [INCR_FILL-1:0] increment_ext;
initial
begin
increment_ext = {{INCR_FILL}{1'b0}};
end
always@(*)
begin
increment_ext = {{INCR_FILL}{1'b0}};
increment_ext[INCREMENT_WIDTH-1:0] = increment;
end
reg [TOTAL_STAGES-1 : -1] pipelined_go;
reg [SECTION_SIZE:0] stages [TOTAL_STAGES-1 : -1];
reg [TOTAL_STAGES-1 : -1] pipelined_dispatch;
reg [ACCUMULATOR_WIDTH-1:0] pipelined_data [TOTAL_STAGES-1 : 0];
integer j;
initial
begin
pipelined_go = {{TOTAL_STAGES+1}{1'b0}};
for (j=-1; j < TOTAL_STAGES; j = j + 1)
stages[j] = {{SECTION_SIZE}{1'b0}};
end
always@(*)
begin
pipelined_go[-1] = go;
stages[-1] = {{SECTION_SIZE}{1'b0}};
end
genvar i;
generate
for (i = 0; i < TOTAL_STAGES; i = i + 1)
begin: ndr_stage
always@(posedge clock or negedge resetn)
begin
if( ~resetn )
pipelined_go[i] <= 1'b0;
else if( clear )
pipelined_go[i] <= 1'b0;
else
pipelined_go[i] <= pipelined_go[i-1];
end
always@(posedge clock or negedge resetn)
begin
if( ~resetn )
stages[i] <= {{SECTION_SIZE}{1'bx}};
else if( clear )
stages[i] <= {{SECTION_SIZE}{1'b0}};
else if( pipelined_go[i-1] )
begin
if (i*SECTION_SIZE < INCREMENT_WIDTH)
begin
// Note that even when (i+1)*SECTION_SIZE-1 > INCREMENT_WIDTH, the increment_ext is extended with 0s,
// so it does not impact addition. But this does make Modelsim happy.
stages[i] <= stages[i][SECTION_SIZE-1:0] + increment_ext[(i+1)*SECTION_SIZE-1:i*SECTION_SIZE] + stages[i-1][SECTION_SIZE];
end
else
begin
stages[i] <= stages[i][SECTION_SIZE-1:0] + stages[i-1][SECTION_SIZE];
end
end
end
always@(posedge clock or negedge resetn)
begin
if( ~resetn )
pipelined_data[i] <= {{ACCUMULATOR_WIDTH}{1'bx}};
else if( clear )
pipelined_data[i] <= {{ACCUMULATOR_WIDTH}{1'b0}};
else if( pipelined_go[i-1] )
begin
pipelined_data[i] <= {{ACCUMULATOR_WIDTH}{1'b0}};
if (i==1)
pipelined_data[i] <= stages[i-1];
else if (i > 1)
begin
// Sadly Modelsim is kind of stupid here and for i=0 it actually evaluates the
// expressions here and finds that (i-1)*SECTION_SIZE - 1 = -SECTION_SIZE - 1 and thinks
// the indexing to pipelined_data[i-1] happens in opposite direction to the one declared.
// Quartus is smart enough to figure out that is not the case though, so the synthesized circuit
// is not affected. To fix this, I am putting a max((i-1)*SECTION_SIZE - 1,0) so that
// in the cases this statement is irrelevant, the access range for the bus is in the proper direction.
pipelined_data[i] <= {stages[i-1], pipelined_data[i-1][mymax((i-1)*SECTION_SIZE - 1,0):0]};
end
end
end
end
endgenerate
generate
if (TOTAL_STAGES == 1)
assign result = stages[TOTAL_STAGES-1];
else
assign result = {stages[TOTAL_STAGES-1], pipelined_data[TOTAL_STAGES-1][(TOTAL_STAGES-1)*SECTION_SIZE-1:0]};
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; vector<string> a; vector<string> ra; cin >> n >> m; for (int i = 0; i < n; ++i) { string s; cin >> s; a.push_back(s); reverse(s.begin(), s.end()); ra.push_back(s); } vector<int> selected; vector<int> arr(n, -1); vector<int> pallindrome; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (ra[i] == a[j]) { arr[i] = j; if (arr[j] != i) { selected.push_back(i); } else if (i == j) { pallindrome.push_back(i); } } } } cout << (selected.size() * 2 * m) + (pallindrome.size() > 0 ? 1 : 0) * m << endl; for (int i = 0; i < selected.size(); ++i) { cout << a[selected[i]]; } if (pallindrome.size() > 0) { cout << a[pallindrome[0]]; } for (int i = selected.size() - 1; i >= 0; --i) { cout << ra[selected[i]]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[200010], s[200010], b[200010]; int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; s[a[i]] = i; } int j = 0; for (int i = 1; i <= n; i++) { cin >> b[i]; int ans = s[b[i]] - j; if (ans < 0) ans = 0; else j = s[b[i]]; cout << ans << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v[1001]; int n, k, r; while (scanf( %d , &n) != EOF) { for (int i = 1; i <= n; i++) { v[i].clear(); scanf( %d , &k); while (k--) { scanf( %d , &r); v[i].push_back(r); } sort(v[i].begin(), v[i].end()); } int ans = 0; for (int i = 1; i <= n; i++) { int pre = i - 1; pre = pre == 0 ? n : pre; int next = i + 1; next = next == n + 1 ? 1 : next; for (int j = 1; j < v[i].size(); j++) { int x = upper_bound(v[pre].begin(), v[pre].end(), v[i][j]) - upper_bound(v[pre].begin(), v[pre].end(), v[i][j - 1]); int y = upper_bound(v[next].begin(), v[next].end(), v[i][j]) - upper_bound(v[next].begin(), v[next].end(), v[i][j - 1]); if (x != y) ans++; } } printf( %d n , ans); } return 0; }
|
/*
** -----------------------------------------------------------------------------**
** macros353.v
**
** I/O pads related circuitry
**
** Copyright (C) 2002 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// just make more convenient A[3:0] instead of 4 one-bit inputs
// TODO: Replace direct instances of SRL16 to imporve portability
module MSRL16 (Q, A, CLK, D);
output Q;
input [3:0] A;
input CLK, D;
`ifdef SIMULATION
SRL16_MOD #(.INVERT(1'b0)) i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`else
SRL16 i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`endif
endmodule
module MSRL16_1 (Q, A, CLK, D);
output Q;
input [3:0] A;
input CLK, D;
`ifdef SIMULATION
SRL16_MOD #(.INVERT(1'b1)) i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`else
SRL16_1 i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`endif
endmodule
module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR);
parameter DATA_WIDTH=16;
parameter DATA_DEPTH=4;
parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
input [DATA_WIDTH-1:0] D;
input WE,clk;
input [DATA_DEPTH-1:0] AW;
input [DATA_DEPTH-1:0] AR;
output [DATA_WIDTH-1:0] QW;
output [DATA_WIDTH-1:0] QR;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
always @ (posedge clk) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
module myRAM_WxD_D_1(D,WE,clk,AW,AR,QW,QR);
parameter DATA_WIDTH=16;
parameter DATA_DEPTH=4;
parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
input [DATA_WIDTH-1:0] D;
input WE,clk;
input [DATA_DEPTH-1:0] AW;
input [DATA_DEPTH-1:0] AR;
output [DATA_WIDTH-1:0] QW;
output [DATA_WIDTH-1:0] QR;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
always @ (negedge clk) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
// Modifying Xilinx SLR16_x to better simulate real hardware
module SRL16_MOD #(
parameter INIT = 16'h0000,
parameter INVERT = 0 // *_1 - invert
) (
output Q,
input A0,
input A1,
input A2,
input A3,
input CLK,
input D);
reg [15:0] data;
wire clk_;
wire [3:0] a = {A3, A2, A1, A0};
assign Q = (|data) ? ((&data) ? 1'b1 : data[a]) : 1'b0 ;
// assign Q = (data == 16'h0) ? 1'b0 :
// ((data == 16'hffff) ? 1'b1 : data[a]);
assign clk_ = INVERT? (~CLK) : CLK;
initial
begin
assign data = INIT;
while (clk_ === 1'b1 || clk_ === 1'bX)
#10;
deassign data;
end
always @(posedge clk_)
begin
{data[15:0]} <= #100 {data[14:0], D};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x1, y1, x2, y2, x3, y3, x4, y4; cin >> x1 >> y1 >> x2 >> y2; int x_diff = x1 - x2; int y_diff = y1 - y2; if (x_diff != 0 and y_diff != 0) { x3 = x1; y3 = y2; x4 = x2; y4 = y1; } else if (x_diff != 0) { x3 = x1; y3 = y1 + abs(x_diff); x4 = x2; y4 = y2 + abs(x_diff); } else { x3 = x1 + abs(y_diff); y3 = y1; x4 = x2 + abs(y_diff); y4 = y2; } if (x_diff != 0 and y_diff != 0 and abs(x_diff) != abs(y_diff)) cout << -1 << endl; else cout << x3 << << y3 << << x4 << << y4 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool nextper(int num[], int n) { int i; for (i = n - 1; i > 0; i--) { if (num[i] > num[i - 1]) { for (int j = n - 1; j >= i; j--) { if (num[j] > num[i - 1]) { int t = num[j]; num[j] = num[i - 1]; num[i - 1] = t; for (int m = i, k = n - 1; m < k; m++, k--) { t = num[m]; num[m] = num[k]; num[k] = t; } break; } } break; } } if (i > 0) { return true; } else return false; } int order[8] = {0, 1, 2, 3, 4, 5, 6, 7}; char s[8][9]; int main() { int n, k, i, j, min, max, num, ans = 2147483647; scanf( %d %d , &n, &k); for (i = 0; i < n; i++) scanf( %s , s[i]); do { min = 2147483647; max = 0; for (i = 0; i < n; i++) { num = 0; for (j = 0; j < k; j++) num = num * 10 + (s[i][order[j]] - 0 ); if (min > num) min = num; if (max < num) max = num; } if (max - min < ans) ans = max - min; } while (nextper(order, k)); printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; const int nax = 5005; const int mod = 1e9 + 7; const int inf = 1e9 + 120; int t[nax]; char sl[nax]; int pref[nax][nax]; int nxt[nax][nax]; int cmp(int i, int j) { if (t[i] < t[j]) return -1; if (t[i] > t[j]) return 1; return 0; } int dp(int a, int b) { int x = pref[a][b] - pref[a - 1][b]; if (x < 0) x += mod; return x; } int main() { int n; scanf( %d , &n); scanf( %s , sl); for (int i = (1); i <= ((n)); ++i) t[i] = sl[i - 1] - 0 ; for (int a = n; a >= 1; --a) for (int b = n; b > a; --b) { int& x = nxt[a][b]; if (t[a] != t[b]) x = a; else if (b == n) x = inf; else x = nxt[a + 1][b + 1]; } for (int i = (1); i <= ((n)); ++i) { for (int j = (1); j <= ((n)); ++j) pref[j][i] = 1; } for (int c = (2); c <= (n); ++c) for (int d = (c); d <= (n); ++d) { int& x = pref[c][d]; int b = c - 1; int a = b - (d - c); x = pref[b][b] - pref[max(a, 0)][b]; if (x < 0) x += mod; if (a >= 1) { int where = nxt[a][c]; if (where < c && t[where] < t[c + where - a]) { x += dp(a, b); if (x >= mod) x -= mod; } } if (t[c] == 0) x = 0; pref[c][d] = x + pref[c - 1][d]; if (pref[c][d] >= mod) pref[c][d] -= mod; } int ans = 0; for (int i = (1); i <= ((n)); ++i) ans = (ans + dp(i, n)) % mod; printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
/**
* udp_isolatchhv_pp$PLG$S: Power isolating latch (for HV). Includes
* VPWR, LVPWR, and VGND power pins with
* active high sleep pin (SLEEP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input SLEEP ,
input LVPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized "loopy" fifo. Model has output register which improves timing
module SizedFIFOL(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full || DEQ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFOL: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFOL: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFOL: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFOL: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, p[200005]; int pn; int main() { scanf( %I64d , &n); n *= 2; for (int k = 0; k < 60; ++k) { long long a = (1LL << (k + 1)) - 3; long long l = 0, r = 2000000000; if (a > 1) r = min(r, n / a + 1); while (r - l > 1) { long long x = (r + l) / 2; if (x * x + a * x <= n) l = x; else r = x; } if (l % 2 == 1 && l * l + a * l == n) p[pn++] = (l << k); } if (pn == 0) { puts( -1 ); exit(0); } sort(p, p + pn); for (int i = 0; i < pn; ++i) printf( %I64d n , p[i]); return 0; }
|
# include <algorithm> # include <iostream> # include <numeric> # include <vector> # include <set> using namespace std; int main() { int n, a, b; while (cin >> n >> a >> b) { string s; cin >> s; set<char> chars_set; for (char c : s) { chars_set.insert(c); } vector<char> chars(chars_set.begin(), chars_set.end()); int cc = (int)chars.size(); vector<int> L(cc, n + 1); vector<int> R(cc, -1); vector<int> cnt(cc, 0); for (int i = 0; i < n; i++) { for (int j = 0; j < cc; j++) { if (s[i] == chars[j]) { L[j] = min(L[j], i); R[j] = max(R[j], i); cnt[j] += 1; } } } vector<int> order(cc); iota(order.begin(), order.end(), 0); sort(order.begin(), order.end(), [&](int i, int j) { return L[i] < L[j]; }); vector<int> order2 = order; sort(order2.begin(), order2.end(), [&](int i, int j) { return R[i] < R[j]; }); vector<int> order3 = order; sort(order3.begin(), order3.end(), [&](int i, int j) { return (L[i] + R[i]) / 2 < (L[j] + R[j]) / 2; }); vector<int> order4 = order; sort(order4.begin(), order4.end(), [&](int i, int j) { return cnt[i] < cnt[j]; }); vector<bool> can(1 << cc, 0); can[0] = 1; for (int t = 1; t < (1 << cc); t++) { int max_R = -1; int min_L = -1; int total = 0; for (int i : order) { if (!(t & (1 << i))) { continue; } if (min_L == -1) { min_L = L[i]; } total += cnt[i]; max_R = max(max_R, R[i]); } int len = max_R - min_L + 1; if (total * b >= a * len) { can[t] = 0; for (int i = 0; i < cc; i++) { if (t & (1 << i)) { if (can[t ^ (1 << i)]) { can[t] = 1; break; } } } if (can[t]) { continue; } } int nt = 0; for (auto& v : {order, order2, order3, order4}) { for (int i : v) { if (!(t & (1 << i))) { continue; } nt |= (1 << i); if (nt != t && can[nt] && can[t ^ nt]) { can[t] = 1; break; } } } } string ret = ; for (int i = 0; i < cc; i++) { if (can[(1 << cc) - 1 - (1 << i)]) { ret += chars[i]; } } cout << ret.size(); for (char c : ret) { cout << << c; } cout << n ; } return 0; } //
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// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_even_parity (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_EVEN_PARITY";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_even_parity_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_even_parity_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_even_parity_psl_logic.v"
`else
`endmodule // ovl_even_parity
`endif
|
/*
- This is a material implementd for google summer of code 2017.
- I built this module to be more familiar with the design required, start edit, re-implement the whole thing
- The mentor feedback would really help me getting more and more clear vision about this project
--------------------------------------------------------------------------------------------------------------
Written by: Abdelrahman Elbehery
*/
module PWM_INTERFACE (
input CLK_IN, //Input clock [Faster than the PWM clocl]
input [7:0] PWM_DCycle, //The PWM duty cycle input [Coming from the i2c slave]
output reg PWM_OUT //module pulse width modulated output
);
//internal registers, signals and wire assignments are here
parameter [4:0] N = 31, K=1; //The division forumula is pwm_clk=(CLK_IN)/(K*2^n*2^8)
reg [31:0] clk_div =0; //clock division counter for the main clock
reg [7:0] pwm_clk =0; //the PWM clock counter
//code body goes here
always @ ( posedge CLK_IN ) begin
clk_div<=clk_div+K; //Increment the clock each cycle by K
end
always @ (posedge clk_div[N]) begin //Watch the change of the Nth bit
pwm_clk<=pwm_clk+1;
end
always @ ( * ) begin
if(pwm_clk<=PWM_DCycle & PWM_DCycle!=0)
PWM_OUT<=1;
else
PWM_OUT<=0;
end
endmodule // PWM_INTERFACE
|
#include <bits/stdc++.h> using namespace std; int main() { int a[16] = {15, 14, 12, 13, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7}; int n; cin >> n; cout << a[n]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k, a[10000]; cin >> n; cin >> m; string s[1000], f[1000]; for (int i = 0; i < n; i++) { cin >> s[i]; } for (int i = 0; i < m; i++) { cin >> f[i]; } cin >> k; for (int i = 0; i < k; i++) { cin >> a[i]; } for (int i = 0; i < k; i++) { a[i]--; cout << s[a[i] % n] << f[a[i] % m] << endl; } }
|
Require Export Iron.Language.SimpleData.SubstExpExp.
Require Export Iron.Language.SimpleData.Step.
Require Export Iron.Language.SimpleData.Exp.
Require Import Iron.Language.SimpleData.Preservation.
Require Import Iron.Language.SimpleData.TyJudge.
(* Big Step Evaluation
This is also called 'Natural Semantics'.
It provides a relation between the expression to be reduced
and its final value. *)
Inductive EVAL : exp -> exp -> Prop :=
| EvDone
: forall v2
, wnfX v2
-> EVAL v2 v2
| EvLamApp
: forall x1 t11 x12 x2 v2 v3
, EVAL x1 (XLam t11 x12)
-> EVAL x2 v2
-> EVAL (substX 0 v2 x12) v3
-> EVAL (XApp x1 x2) v3
| EvCon
: forall dc xs vs
, EVALS xs vs
-> EVAL (XCon dc xs) (XCon dc vs)
| EvCase
: forall x1 x2 v3 dc vs alts tsArgs
, EVAL x1 (XCon dc vs)
-> Forall wnfX vs
-> getAlt dc alts = Some (AAlt dc tsArgs x2)
-> EVAL (substXs 0 vs x2) v3
-> EVAL (XCase x1 alts) v3
with EVALS : list exp -> list exp -> Prop :=
| EvsNil
: EVALS nil nil
| EvsCons
: forall x v xs vs
, EVAL x v
-> EVALS xs vs
-> EVALS (x :: xs) (v :: vs).
Hint Constructors EVAL.
Hint Constructors EVALS.
(* Invert all hypothesis that are compound eval statements. *)
Ltac inverts_eval :=
repeat
(match goal with
| [ H: EVAL (XApp _ _) _ |- _ ] => inverts H
| [ H: EVAL (XCon _ _) _ |- _ ] => inverts H
| [ H: EVAL (XCase _ _) _ |- _ ] => inverts H
end).
Theorem EVAL_mutind
: forall (PE : exp -> exp -> Prop)
(PS : list exp -> list exp -> Prop)
, (forall v2
, wnfX v2
-> PE v2 v2)
-> (forall x1 t11 x12 x2 v2 v3
, EVAL x1 (XLam t11 x12) -> PE x1 (XLam t11 x12)
-> EVAL x2 v2 -> PE x2 v2
-> EVAL (substX 0 v2 x12) v3 -> PE (substX 0 v2 x12) v3
-> PE (XApp x1 x2) v3)
-> (forall dc xs vs
, EVALS xs vs -> PS xs vs
-> PE (XCon dc xs) (XCon dc vs))
-> (forall x1 x2 v3 dc vs alts tsArgs
, EVAL x1 (XCon dc vs) -> PE x1 (XCon dc vs)
-> Forall wnfX vs
-> getAlt dc alts = Some (AAlt dc tsArgs x2)
-> EVAL (substXs 0 vs x2) v3 -> PE (substXs 0 vs x2) v3
-> PE (XCase x1 alts) v3)
-> ( PS nil nil)
-> (forall x v xs vs
, EVAL x v -> PE x v
-> EVALS xs vs -> PS xs vs
-> PS (x :: xs) (v :: vs))
-> forall x1 x2
, EVAL x1 x2 -> PE x1 x2.
Proof.
intros PE PS.
intros Hdone Hlam Hcon Hcase Hnil Hcons.
refine (fix IHPE x x' (HE: EVAL x x') {struct HE}
: PE x x' := _
with IHPS xs xs' (HS: EVALS xs xs') {struct HS}
: PS xs xs' := _
for IHPE).
case HE; intros.
eapply Hdone; eauto.
eapply Hlam; eauto.
eapply Hcon; eauto.
eapply Hcase; eauto.
case HS; intros.
eapply Hnil.
eapply Hcons; eauto.
Qed.
(* A terminating big-step evaluation always produces a whnf.
The fact that the evaluation terminated is implied by the fact
that we have a finite proof of EVAL to pass to this lemma. *)
Lemma eval_produces_wnfX
: forall x1 v1
, EVAL x1 v1
-> wnfX v1.
Proof.
intros.
induction H using EVAL_mutind with
(PS := fun xs vs
=> EVALS xs vs
-> Forall wnfX vs);
intros; eauto.
Qed.
Hint Resolve eval_produces_wnfX.
Lemma evals_produces_wnfX
: forall xs vs
, EVALS xs vs
-> Forall wnfX vs.
Proof. intros. induction H; eauto. Qed.
Hint Resolve evals_produces_wnfX.
(* Big to Small steps
Convert a big-step evaluation into a list of individual
machine steps. *)
Lemma steps_of_eval
: forall ds x1 t1 x2
, TYPE ds nil x1 t1
-> EVAL x1 x2
-> STEPS x1 x2.
Proof.
intros ds x1 t1 v2 HT HE. gen t1.
induction HE using EVAL_mutind with
(PS := fun xs vs => forall ts
, Forall2 (TYPE ds nil) xs ts
-> EVALS xs vs
-> Forall2 STEPS xs vs)
; intros.
Case "EvDone".
intros. apply EsNone.
(* Function Application ***)
Case "EvLamApp".
intros. inverts HT.
lets E1: IHHE1 H3.
lets E2: IHHE2 H5.
lets T1: preservation_steps H3 E1. inverts keep T1.
lets T2: preservation_steps H5 E2.
lets T3: subst_exp_exp H2 T2.
lets E3: IHHE3 T3.
eapply EsAppend.
lets D: steps_context XcApp1. eapply D. eauto.
eapply EsAppend.
lets D: steps_context (XcApp2 (XLam t0 x12)). eauto.
eapply D. eauto.
eapply EsAppend.
eapply EsStep.
eapply EsLamApp. eauto. eauto.
(* Constructor evaluation ***)
Case "EvCon".
intros.
inverts HT.
lets D: IHHE H8 H.
eapply steps_in_XCon; eauto.
(* Case selection ***)
Case "EvCase".
intros. inverts keep HT.
lets Ex1: IHHE1 H3. clear IHHE1.
eapply EsAppend.
(* evaluate the discriminant *)
lets HSx1: steps_context XcCase. eapply HSx1.
eapply Ex1.
(* choose the alternative *)
lets HTCon: preservation_steps H3 Ex1. clear Ex1.
inverts HTCon.
assert (tsArgs0 = tsArgs).
eapply getAlt_ctorArgTypesMatchDataDef; eauto. subst.
lets HA: getAlt_in H0.
norm. rip.
apply H4 in HA.
inverts HA.
(* substitute ctor values into alternative *)
eapply EsAppend.
eapply EsStep.
eapply EsCaseAlt; burn.
burn using subst_exp_exp_list.
Case "EvsNil".
auto.
Case "EvsHead".
destruct ts.
inverts H0.
inverts H0. eauto.
Qed.
(* Small to Big steps
Convert a list of individual machine steps to a big-step
evaluation. The main part of this is the expansion lemma, which
we use to build up the overall big-step evaluation one small-step
at a time. The other lemmas are used to feed it small-steps. *)
(* Given an existing big-step evalution, we can produce a new one
that does an extra step before returning the original value.
*)
Lemma eval_expansion
: forall ds te x1 t1 x2 v3
, TYPE ds te x1 t1
-> STEP x1 x2 -> EVAL x2 v3
-> EVAL x1 v3.
Proof.
intros ds te x1 t1 x2 v3 HT HS. gen ds te t1 v3.
induction HS; intros;
try (solve [inverts H; eauto]);
try eauto.
Case "Context".
destruct H; inverts_type; eauto.
SCase "XcApp1".
inverts_eval; burn.
SCase "XcApp2".
inverts_eval; burn.
SCase "XcCon".
assert (exists t, TYPE ds te x t).
eapply exps_ctx_Forall2_exists_left; eauto.
dest t.
inverts_eval.
inverts H2.
eapply EvCon. clear H9.
induction H; intros.
inverts H5.
eapply EvsCons. eauto.
induction xs.
eauto.
inverts H6. eauto.
inverts H5. eauto.
eapply EvCon.
clear H3 H4 H9.
gen vs.
induction H; intros.
inverts H8. eauto.
inverts H8. eauto.
SCase "XcCase".
inverts H0. inverts H. eauto.
Qed.
(* Convert a list of small steps to a big-step evaluation. *)
Lemma eval_of_stepsl
: forall ds x1 t1 v2
, TYPE ds nil x1 t1
-> STEPSL x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros.
induction H0.
Case "EslNone".
apply EvDone. inverts H1. auto.
Case "EslCons".
eapply eval_expansion; eauto.
burn using preservation.
Qed.
(* Convert a multi-step evaluation to a big-step evaluation.
We use stepsl_of_steps to flatten out the append constructors
in the multi-step evaluation, leaving a list of individual
small-steps. *)
Lemma eval_of_steps
: forall ds x1 t1 v2
, TYPE ds nil x1 t1
-> STEPS x1 v2 -> value v2
-> EVAL x1 v2.
Proof.
intros.
eapply eval_of_stepsl; eauto.
apply stepsl_of_steps; auto.
Qed.
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 40005; int n, m, c, s, t, ct, cnt, ans, b[Maxn], dis[Maxn], head[Maxn], cur[Maxn], a[205][205], id[205][205]; long long tot; bool vis[Maxn]; struct edg { int nxt, to, w; } edge[10 * Maxn]; void add(int x, int y, int w) { edge[++cnt] = (edg){head[x], y, w}; head[x] = cnt; edge[++cnt] = (edg){head[y], x, 0}; head[y] = cnt; } int dfs(int u, int T, int mini) { if (u == T || !mini) return mini; int w, used = 0; vis[u] = true; for (int i = head[u]; i; i = edge[i].nxt) { int to = edge[i].to; if (!vis[to] && edge[i].w) { w = dfs(to, T, min(mini - used, edge[i].w)); used += w, edge[i].w -= w, edge[((i - 1) ^ 1) + 1].w += w; if (mini == used) return used; } } return used; } void dinic(int S = s, int T = t, int W = 0x3f3f3f3f, bool type = false) { int used; while (memset(vis, 0, sizeof(bool[ct + 1])), used = dfs(S, T, W)) W -= used, ans += type ? -used : used; } int main() { scanf( %d , &n); s = ++ct, t = ++ct; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { id[i][j] = ++ct; scanf( %d , &a[i][j]); if (a[i][j] > 0) b[++m] = a[i][j]; if (!a[i][j]) c++; } sort(b + 1, b + 1 + m); m = unique(b + 1, b + 1 + m) - b - 1; for (int j = 1; j <= n; j++) for (int k = 1; k <= n; k++) { if (a[j][k] == -1) continue; if (j != n && a[j + 1][k] != -1) add(id[j][k], id[j + 1][k], 1), add(id[j + 1][k], id[j][k], 1); if (k != n && a[j][k + 1] != -1) add(id[j][k], id[j][k + 1], 1), add(id[j][k + 1], id[j][k], 1); if (a[j][k] <= 0) continue; add(id[j][k], t, 0x3f3f3f3f); } for (int i = 1; i < m; i++) { for (int j = 1; j <= n; j++) for (int k = 1; k <= n; k++) if (a[j][k] == b[i]) { int w; for (int q = head[id[j][k]]; q; q = edge[q].nxt) if (edge[q].to == t) { w = edge[q].w; edge[q].w = edge[((q - 1) ^ 1) + 1].w = 0; break; } dinic(id[j][k], s, 0x3f3f3f3f - w, true); add(s, id[j][k], 0x3f3f3f3f); } dinic(); tot += ans * (long long)(b[i + 1] - b[i]); } printf( %lld , tot); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:47:14 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_stub.v
// Design : system_debounce_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "debounce,Vivado 2016.4" *)
module system_debounce_0_0(clk, signal_in, signal_out)
/* synthesis syn_black_box black_box_pad_pin="clk,signal_in,signal_out" */;
input clk;
input signal_in;
output signal_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 1000000007; const int N = 100003; int ld[N]; int a[N]; void sieve() { for (int i = 2; i * i < N; ++i) if (ld[i] == 0) for (int j = i * i; j < N; j += i) if (ld[j] == 0) ld[j] = i; for (int i = 2; i < N; ++i) if (ld[i] == 0) ld[i] = i; } vector<int> p; vector<int> k; vector<int> d; void genDivisors(int i, int x) { if (i == (int)p.size()) { d.push_back(x); return; } for (int c = 0; c <= k[i]; ++c) { genDivisors(i + 1, x); x *= p[i]; } } int expMod(int a, int n) { int res = 1; while (n > 0) { if (n & 1) res = (long long)res * a % M; n >>= 1; a = (long long)a * a % M; } return res; } int main() { sieve(); int n; scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , a + i); sort(a, a + n); int res = 0; for (int x = 1; x <= a[n - 1]; ++x) { p.clear(); k.clear(); d.clear(); int y = x; while (y > 1) { int z = ld[y]; p.push_back(ld[y]); k.push_back(1); y /= z; while (y % z == 0) { y /= z; ++k.back(); } } genDivisors(0, 1); sort(d.begin(), d.end()); k.clear(); k.resize(d.size()); for (int i = 0; i < (int)d.size(); ++i) k[i] = n - (lower_bound(a, a + n, d[i]) - a); y = 1; for (int i = 0; i < (int)d.size() - 1; ++i) { k[i] -= k[i + 1]; y = (long long)y * expMod(i + 1, k[i]) % M; } int z = (expMod(d.size(), k.back()) - expMod((int)d.size() - 1, k.back()) + M) % M; y = (long long)y * z % M; res = (res + y) % M; } printf( %d n , res); return 0; }
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This tests the rule in section 2.7.1:
* "Neither the leading backslash character nor the terminating
* white space is considered to be part of the identifier. There-
* fore, an escaped identifier \cpu3 is treated the same as a
* non escaped identifier cpu3."
*
* The cpu3 and \cpu3 notations are for the same object.
*/
module top;
reg \cpu3 ;
initial begin
cpu3 = 1;
$display("cpu3 == %b", \cpu3 );
if (top.\cpu3 !== cpu3) begin
$display("FAILED -- top.\\cpu3 !== cpu3");
$finish;
end
if (\top .cpu3 !== \cpu3 ) begin
$display("FAILED -- \\top .cpu3 !== cpu3");
$finish;
end
if (top.\cpu3 !== 1) begin
$display("FAILED -- top.\\cpu3 !== 1");
$finish;
end
$display("PASSED");
end
endmodule // top
|
#include <bits/stdc++.h> using namespace std; inline void out(int a) { printf( %d n , a); } inline void out(int a, int b) { printf( %d %d n , a, b); } inline void outf(double a) { printf( %3.lf n , a); } inline void outf(double a, double b) { printf( %3.lf %3.lf n , a, b); } inline void base() { ios_base::sync_with_stdio(false); cin.tie(0); } int tour(vector<int> ls) { while (ls.size() != 1) { vector<int> nx; for (int i = 0; i < ls.size(); i += 2) { if (i + 1 == ls.size()) { nx.push_back(ls[i]); break; } cout << ? << ls[i] << << ls[i + 1] << endl; char c; cin >> c; if (c == > ) { nx.push_back(ls[i]); } else if (c == < ) { nx.push_back(ls[i + 1]); } else if (c == = ) { nx.push_back(ls[i]); } } ls = nx; } return ls[0]; } int tour1(vector<int> ls) { while (ls.size() != 1) { vector<int> nx; for (int i = 0; i < ls.size(); i += 2) { if (i + 1 == ls.size()) { nx.push_back(ls[i]); break; } cout << ? << ls[i] << << ls[i + 1] << endl; char c; cin >> c; if (c == > ) { nx.push_back(ls[i + 1]); } else if (c == < ) { nx.push_back(ls[i]); } else if (c == = ) { nx.push_back(ls[i]); } } ls = nx; } return ls[0]; } int main() { base(); int t; cin >> t; while (t--) { int n; cin >> n; if (n == 1) { cout << ! 1 1 << endl; continue; } vector<int> lose; vector<int> win; for (int i = 1; i <= n; i += 2) { if (i + 1 <= n) { cout << ? << i << << i + 1 << endl; char c; cin >> c; if (c == > ) { win.push_back(i); lose.push_back(i + 1); } else if (c == < ) { win.push_back(i + 1); lose.push_back(i); } else { win.push_back(i); lose.push_back(i); } } else { win.push_back(i); lose.push_back(i); } } int mx = tour(win), mn = tour1(lose); cout << ! << mn << << mx << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (m - 1 >= n - m) m - 1 == 0 ? cout << m << endl : cout << m - 1 << endl; else cout << m + 1; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_8_V
`define SKY130_FD_SC_HDLL__PROBEC_P_8_V
/**
* probec_p: Virtual current probe point.
*
* Verilog wrapper for probec_p with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__probec_p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__probec_p_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__probec_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__probec_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__probec_p base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_8_V
|
#include <bits/stdc++.h> using namespace std; ifstream fin( A.in ); ofstream fout( A.out ); int n, m, i, j, a, b, y, minv = 1000000000, t = 0, ok, nr; char cor[256], s[1001][1001]; int wh[1001][1001]; int viz[1001 * 1001], pred[1001 * 1001], best[1001 * 1001], good[1001 * 1001], st[1001 * 1001]; queue<int> q; vector<int> G[1001 * 1001]; char c[4] = { D , I , M , A }; void dfs(int x) { viz[x] = 1; st[x] = 1; for (vector<int>::iterator it = G[x].begin(); it != G[x].end(); ++it) { if (!viz[*it]) dfs(*it); else if (st[*it]) ok = 1; } st[x] = 0; } int main() { cin >> n >> m; cor[ D ] = I ; cor[ I ] = M ; cor[ M ] = A ; cor[ A ] = D ; for (int i = 1; i <= n; ++i) { cin >> s[i]; for (int j = 0; j < m; ++j) { wh[i][j] = ++t; if (s[i][j] == D ) { good[wh[i][j]] = 1; } } } for (int k = 0; k < 4; ++k) { for (int i = 1; i <= n; ++i) { for (int j = 0; j < m; ++j) { if (s[i][j] == c[k] && good[wh[i][j]]) { if (i > 1) { if (s[i - 1][j] == cor[s[i][j]]) { G[wh[i][j]].push_back(wh[i - 1][j]); pred[wh[i - 1][j]]++; good[wh[i - 1][j]] = 1; } } if (j > 0) { if (s[i][j - 1] == cor[s[i][j]]) { G[wh[i][j]].push_back(wh[i][j - 1]); pred[wh[i][j - 1]]++; good[wh[i][j - 1]] = 1; } } if (i < n) { if (s[i + 1][j] == cor[s[i][j]]) { G[wh[i][j]].push_back(wh[i + 1][j]); pred[wh[i + 1][j]]++; good[wh[i + 1][j]] = 1; } } if (j < m - 1) { if (s[i][j + 1] == cor[s[i][j]]) { G[wh[i][j]].push_back(wh[i][j + 1]); pred[wh[i][j + 1]]++; good[wh[i][j + 1]] = 1; } } } } } } for (int i = 1; i <= t; ++i) { if (good[i] && !viz[i]) { dfs(i); } } if (ok) { cout << Poor Inna! ; return 0; } for (int i = 1; i <= t; ++i) { if (pred[i] == 0 && good[i]) q.push(i); best[i] = 1; } while (!q.empty()) { int x = q.front(); for (vector<int>::iterator it = G[x].begin(); it != G[x].end(); ++it) { --pred[*it]; if (pred[*it] == 0) q.push(*it); best[*it] = max(best[*it], best[x] + 1); } q.pop(); } int maxv = 0; for (int i = 1; i <= t; ++i) { maxv = max(best[i], maxv); } if (maxv / 4 == 0) { cout << Poor Dima! ; } else cout << maxv / 4; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 00:02:34 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_FlagReg_0_0/RAT_FlagReg_0_0_stub.v
// Design : RAT_FlagReg_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "FlagReg,Vivado 2016.4" *)
module RAT_FlagReg_0_0(IN_FLAG, LD, SET, CLR, CLK, OUT_FLAG)
/* synthesis syn_black_box black_box_pad_pin="IN_FLAG,LD,SET,CLR,CLK,OUT_FLAG" */;
input IN_FLAG;
input LD;
input SET;
input CLR;
input CLK;
output OUT_FLAG;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const long long mod = 998244353; inline long long add(long long v1, long long v2) { v1 += v2; if (v1 >= mod) v1 -= mod; if (v1 < 0) v1 += mod; return v1; } inline long long mul(long long v1, long long v2) { return v1 * v2 % mod; } inline long long mypow(long long v, long long t) { long long res = 1; while (t) { if (t & 1) res = res * v % mod; v = v * v % mod; t >>= 1; } return res; } inline void bye() { puts( ); exit(0); } const int N = 303030; int a[N]; long long cnt[N]; long long dp[8][N]; long long fac[N], ifac[N]; long long C(int v1, int v2) { if (v1 < v2) return 0; return mul(fac[v1], mul(ifac[v2], ifac[v1 - v2])); } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , a + i); cnt[a[i]]++; } fac[0] = 1; for (int i = 1; i < N; i++) { fac[i] = fac[i - 1] * i % mod; } ifac[N - 1] = mypow(fac[N - 1], mod - 2); for (int i = N - 2; i >= 0; i--) { ifac[i] = ifac[i + 1] * (i + 1) % mod; } for (int i = 1; i < N; i++) { for (int j = i * 2; j < N; j += i) { cnt[i] += cnt[j]; } } for (int i = 1; i < 8; i++) { for (int j = N - 1; j >= 1; j--) { dp[i][j] = C(cnt[j], i); for (int k = j * 2; k < N; k += j) { dp[i][j] = add(dp[i][j], -dp[i][k]); } } if (dp[i][1]) { printf( %d n , i); return 0; } } puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int N, M; char eat; cin >> N >> M; scanf( %c , &eat); char temp[5000]; vector<vector<bool>> grid(N, vector<bool>(M)); for (int r = 0; r < N; r++) { scanf( %s , temp); for (int c = 0; c < M; c++) grid[r][c] = (temp[c] == 1 ? 1 : 0); } int result = 0; vector<vector<int>> memo(N, vector<int>(M)); for (int r = 0; r < N; r++) { for (int c = M - 1; c >= 0; c--) { if (grid[r][c] == 1) memo[r][c] = 1 + (c != M - 1 ? memo[r][c + 1] : 0); } } for (int c = 0; c < M; c++) { vector<int> width; for (int r = 0; r < N; r++) { if (memo[r][c] != 0) width.push_back(memo[r][c]); } sort(width.rbegin(), width.rend()); for (int i = 0; i < width.size(); i++) { int area = (i + 1) * width[i]; result = max(result, area); } } cout << result << endl; }
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
(* ram_init_file = "hub_rom_low.hex" *) reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
(* ram_init_file = "hub_rom_high.hex" *) reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
// : !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> a(26), a2(26), a3(26); string s1, s2, s3; char ss1[100001], ss2[100001], ss3[100001]; scanf( %s%s%s , ss1, ss2, ss3); s1 = ss1; s2 = ss2; s3 = ss3; for (int i = 0; i < s1.size(); i++) a[s1[i] - a ]++; for (int i = 0; i < s2.size(); i++) a2[s2[i] - a ]++; for (int i = 0; i < s3.size(); i++) a3[s3[i] - a ]++; int max1 = 0, max2 = 0; int ma2 = 100000; for (int i = 0; i < 26; i++) if (a2[i]) ma2 = min(ma2, a[i] / a2[i]); for (int i = 0; i <= ma2; i++) { int r = 100000; for (int j = 0; j < 26; j++) if (a3[j]) r = min(r, (a[j] - i * a2[j]) / a3[j]); if (r + i > max1 + max2) max1 = i, max2 = r; } for (int i = 0; i < max1; i++) printf( %s , ss2); for (int i = 0; i < max2; i++) printf( %s , ss3); for (int i = 0; i < 26; i++) a[i] -= (a2[i] * max1 + a3[i] * max2); for (int i = 0; i < 26; i++) { while (a[i] > 0) { printf( %c , i + a ); a[i]--; } } return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: gsu_umult.v
// /___/ /\ Timestamp: Fri Oct 02 08:35:52 2020
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// Device : 3s400pq208-4
// Input file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// # of Modules : 1
// Design Name : gsu_umult
// Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module gsu_umult (
p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
output [15 : 0] p;
input [7 : 0] a;
input [7 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000011 ;
wire \NLW_blk00000001/blk00000003_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ;
MULT18X18 \blk00000001/blk00000003 (
.A({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , a[7], a[6],
a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , b[7], b[6],
b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk00000003_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ,
p[15], p[14], p[13], p[12], p[11], p[10], p[9], p[8], p[7], p[6], p[5], p[4], p[3], p[2], p[1], p[0]})
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000011 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
#include <bits/stdc++.h> //--------------------------------------------------- #define l_int long long int #define double long double #define inf INT64_MAX #define mod 100000 #define fo(i,a,b) for(l_int i=a;i<b;i++) //--------------------------------------------------- using namespace std; int factorial(int n) { int ans=1; while(n!=1) { ans*=n; n--; } return ans; } int main() { ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); int t,n,k; cin >> t; while(t--) { int n; cin >> n; int c=0; char s[n]; for(int i=0 ; i< n ;i++) { cin >> s[i]; } if(s[0]== 2 && s[1]== 0 && s[2]== 2 && s[3]== 0 ) { c=1; } if(s[n-1]== 0 && s[n-2]== 2 && s[n-3]== 0 && s[n-4]== 2 ) { c=1; } if(s[0]== 2 && s[n-3]== 0 && s[n-2]== 2 && s[n-1]== 0 ) { c=1; } if(s[0]== 2 && s[1]== 0 && s[n-2]== 2 && s[n-1]== 0 ) { c=1; } if(s[0]== 2 && s[1]== 0 && s[2]== 2 && s[n-1]== 0 ) { c=1; } if(c==1) { cout << YES << endl; }else if(c==0) { cout << NO << endl; } } }
|
`timescale 1 ns / 1 ps
module elink2_tb;
reg aclk;
reg aresetn;
reg start;
wire csysreq = 1'b0;
wire reset = ~aresetn;
wire [11:0] param_coreid = 12'h810;
wire [2:0] done;
wire [2:0] error;
// Create an instance of the example tb
elink_testbench dut
(.aclk (aclk),
.aresetn (aresetn),
.reset (reset),
.csysreq (csysreq),
.done0 (done[0]),
.done1 (done[1]),
.done2 (done[2]),
.error0 (error[0]),
.error1 (error[1]),
.error2 (error[2]),
.start (start),
.param_coreid (param_coreid));
// Reset Generator
initial begin
aresetn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge aclk);
aresetn = 1'b1;
end
// Clock Generator
initial aclk = 1'b0;
always #5 aclk = ~aclk;
// Drive the BFM
initial begin
start = 1'b0;
// Wait for end of reset
wait(aresetn === 0) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
#500 start = 1'b1;
$display("=== TB Started");
wait( done == 3'b111);
$display("=== TEST_FINISHED");
if ( error != 3'b000 ) begin
$display("===_TEST: FAILED!");
end else begin
$display("=== TEST: PASSED!");
end
end
always @ (posedge done[2])
$display("=== INIT Complete");
always @ (posedge done[0])
$display("=== GOLD->ELINK2 Complete");
always @ (posedge done[1])
$display("=== ELINK2->GOLD Complete");
always @ (posedge error[0])
if( error[0] == 1'b1 && done[0] == 1'b0)
$display("=== ERROR FLAG GOLD->ELINK2 @ %t", $time);
always @ (posedge error[1])
if( error[1] == 1'b1 && done[1] == 1'b0)
$display("=== ERROR FLAG ELINK2->GOLD @ %T", $time);
always @ (posedge error[2])
if( error[2] == 1'b1 && done[2] == 1'b0)
$display("=== ERROR FLAG INIT @ %T", $time);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_2_V
`define SKY130_FD_SC_HD__CLKBUF_2_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_2_V
|
// RS-232 RX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, RxD;
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle; // no data is being received
// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
////////////////////////////
reg [1:0] RxD_sync_inv;
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
reg [1:0] RxD_cnt_inv;
reg RxD_bit_inv;
always @(posedge clk)
if(Baud8Tick)
begin
if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
else
if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0;
else
if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1;
end
reg [3:0] state;
reg [3:0] bit_spacing;
// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);
always @(posedge clk)
if(state==0)
bit_spacing <= 4'b0000;
else
if(Baud8Tick)
bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000};
always @(posedge clk)
if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase
reg [7:0] RxD_data;
always @(posedge clk)
if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};
reg RxD_data_ready, RxD_data_error;
always @(posedge clk)
begin
RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received
end
reg [4:0] gap_count;
always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 5'h01;
assign RxD_idle = gap_count[4];
reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct piece { int x, y; char p[20][20]; piece(int _x, int _y) : x(_x), y(_y) {} bool operator<(const piece& rhs) const { if ((x * y) != (rhs.x * rhs.y)) return (x * y) < (rhs.x * rhs.y); else return x < rhs.x; } }; struct Piece { int x, y; char p[20][20]; Piece() {} bool operator==(const Piece& rhs) const { bool eq = true; for (int i = 0; i < x; i++) for (int j = 0; j < y; j++) if (p[i][j] != rhs.p[i][j]) { eq = false; goto n1; } n1: if (eq) return true; char tmp[20][20]; if (x == y) { for (int i = 0; i < x; i++) for (int j = 0; j < y; j++) tmp[i][j] = rhs.p[y - (j + 1)][i]; eq = true; for (int i = 0; i < x; i++) for (int j = 0; j < y; j++) if (p[i][j] != tmp[i][j]) { eq = false; goto n2; } n2: if (eq) return true; } for (int i = 0; i < x; i++) for (int j = 0; j < y; j++) tmp[i][j] = rhs.p[x - (i + 1)][y - (j + 1)]; eq = true; for (int i = 0; i < x; i++) for (int j = 0; j < y; j++) if (p[i][j] != tmp[i][j]) { eq = false; goto n3; } n3: if (eq) return true; if (x == y) { for (int i = 0; i < x; i++) for (int j = 0; j < y; j++) tmp[i][j] = rhs.p[j][x - (i + 1)]; eq = true; for (int i = 0; i < x; i++) for (int j = 0; j < y; j++) if (p[i][j] != tmp[i][j]) { eq = false; goto n4; } n4: if (eq) return true; } return false; } }; char p[20][20]; set<int> fa, fb; set<piece> P; int a, b; int good(int x, int y) { vector<Piece> ps; int ih = a / x, jh = b / y; for (int i = 1; i <= ih; i++) for (int j = 1; j <= jh; j++) { Piece tmp; tmp.x = x; tmp.y = y; int kh = (i - 1) * x + x - 1, lh = (j - 1) * y + y - 1; for (int k = (i - 1) * x, m = 0; k <= kh; k++, m++) for (int l = (j - 1) * y, n = 0; l <= lh; l++, n++) tmp.p[m][n] = p[k][l]; for (unsigned int k = 0; k < ps.size(); k++) if (ps[k] == tmp) return false; ps.push_back(tmp); } return true; } int main() { cin >> a >> b; for (int i = 0; i < a; i++) for (int j = 0; j < b; j++) cin >> p[i][j]; for (int i = 1; i <= a; i++) if (!(a % i)) fa.insert(i); for (int i = 1; i <= b; i++) if (!(b % i)) fb.insert(i); for (set<int>::iterator ita = fa.begin(); ita != fa.end(); ita++) for (set<int>::iterator itb = fb.begin(); itb != fb.end(); itb++) { int x = *ita, y = *itb; if (good(x, y)) P.insert(piece(x, y)); } cout << P.size() << endl; cout << (*(P.begin())).x << << (*(P.begin())).y << endl; return 0; }
|
//--------------------------------------------------------------------------------
//
// timer.v
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// 36-bit timer for advanced triggers. Gives range from 10ns to ~670 seconds.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module timer (
input wire clk,
input wire reset,
input wire wrenb,
input wire wraddr,
input wire [31:0] config_data,
input wire update_timers,
input wire fsm_start_timer,
input wire fsm_clear_timer,
input wire fsm_stop_timer,
output reg timer_elapsed
);
reg [35:0] timer, next_timer;
reg [35:0] timer_limit, next_timer_limit; // 10ns to 687 seconds
reg timer_active, next_timer_active;
reg next_timer_elapsed;
//
// 10ns resolution timer's...
//
initial
begin
timer = 36'h0;
timer_active = 1'b0;
timer_elapsed = 1'b0;
timer_limit = 36'h0;
end
always @ (posedge clk)
begin
timer <= next_timer;
timer_active <= next_timer_active;
timer_elapsed <= next_timer_elapsed;
timer_limit <= next_timer_limit;
end
always @*
begin
next_timer = (timer_elapsed) ? 36'h0 : timer;
next_timer_active = timer_active;
next_timer_elapsed = timer_elapsed;
next_timer_limit = timer_limit;
if (timer_active)
begin
next_timer = timer+1'b1;
if (timer >= timer_limit)
begin
next_timer_elapsed = 1'b1;
next_timer_active = 1'b0;
end
end
if (update_timers)
begin
if (fsm_start_timer) next_timer_active=1'b1;
if (fsm_clear_timer) begin next_timer=0; next_timer_elapsed=1'b0; end
if (fsm_stop_timer) next_timer_active=1'b0;
end
if (wrenb)
case (wraddr)
1'b0 : next_timer_limit[31:0] = config_data;
1'b1 : next_timer_limit[35:32] = config_data[3:0];
endcase
if (reset)
begin
next_timer = 0;
next_timer_active = 0;
next_timer_elapsed = 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3B_4_V
`define SKY130_FD_SC_MS__OR3B_4_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3B_4_V
|
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