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#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j; scanf( %d %d , &n, &m); for (i = 0; i < n / 2; i++) { for (j = 0; j < m; j++) { printf( %d %d n%d %d n , i + 1, j + 1, n - i, m - j); } } if (n % 2 == 1) { for (j = 0; j < m / 2; j++) { printf( %d %d n%d %d n , n / 2 + 1, j + 1, n / 2 + 1, m - j); } if (m % 2 == 1) { printf( %d %d n , n / 2 + 1, m / 2 + 1); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int search(long long int *array, int start_idx, int end_idx, long long int search_val) { if (start_idx == end_idx) return array[start_idx] <= search_val ? start_idx : -1; int mid_idx = start_idx + (end_idx - start_idx) / 2; if (search_val < array[mid_idx]) return search(array, start_idx, mid_idx, search_val); int ret = search(array, mid_idx + 1, end_idx, search_val); return ret == -1 ? mid_idx : ret; } long long int C(long long int k) { return (k * (k - 1)) / 2; } int main() { ios_base::sync_with_stdio; cin.tie(NULL); long long int n, d; cin >> n >> d; long long int arr[n]; for (long long int i = 0; i < n; i++) cin >> arr[i]; long long int ways = 0, current, maxallowed, index2, previndex2; for (long long int i = 0; i < n; i++) { current = arr[i]; maxallowed = current + d; index2 = search(arr, 0, n - 1, maxallowed); if (index2 - i + 1 >= 3) { ways += C(index2 - i); } } cout << ways; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_1_V
`define SKY130_FD_SC_HVL__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; void solve() { long long n; cin >> n; if (n < 6) cout << -1 << endl; else { cout << 1 2 n2 3 n2 4 n1 5 n1 6 n ; for (long long i = 7; i <= n; i++) { cout << 2 << << i << endl; } } cout << 1 2 n ; for (long long i = 3; i <= n; i++) { cout << 2 << << i << endl; } } signed main() { long long t = 1; ios_base::sync_with_stdio(false); cin.tie(NULL); while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; long long n, k; vector<vector<long long>> ft(12, vector<long long>(100005, 0)); void add(long long kk, long long ind, long long val) { while (ind <= n) { ft[kk][ind] += val; ind += ind & -ind; } } long long sum(long long kk, long long ind) { long long res = 0; while (ind > 0) { res += ft[kk][ind]; ind -= ind & -ind; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> k; vector<long long> arr(n + 1); for (int i = 1; i < n + 1; i++) cin >> arr[i]; for (int i = 1; i < n + 1; i++) { for (int j = 1; j < 12; j++) { if (j == 1) add(1, arr[i], 1); else { long long val = sum(j - 1, arr[i] - 1); add(j, arr[i], val); } } } cout << sum(k + 1, n); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void out(T x) { cout << x << endl; exit(0); } const int maxn = 2000 + 7; int n; long double p; int t; long double dp[maxn][maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> p >> t; dp[0][0] = 1.0; for (int i = 0; i < t; i++) { for (int j = 0; j < n; j++) { dp[i + 1][j] += (1.0 - p) * dp[i][j]; dp[i + 1][j + 1] += p * dp[i][j]; } dp[i + 1][n] += dp[i][n]; } long double ans = 0.0; for (int i = 1; i <= n; i++) { ans += 1.0 * i * dp[t][i]; } cout << fixed << setprecision(12) << ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_1_V
`define SKY130_FD_SC_HVL__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_1_V
|
///
/// Camera configuration
/// --------------------
///
/// This module configures the camera sensor through its control registers.
/// For in this way control and configure: the exposition time, the resolution
/// and the frame rate.
///
/// .. figure:: camera_config.png
///
/// Camera configuration block
///
/// For this, it generates the necessary signals for to control the I2C bus,
/// that communicates with the cammera registers.
///
/// So, each configuration register has 16 bits width, and they are used for
/// to configure the active image for to be tranfered by the camera sensor, so
/// that:
///
/// exposure (ie)
/// This is the level of exposition time value.
/// start_row (sr)
/// This is the configuration entry of start row (0x0036).
/// start_column (sc)
/// This is the configuration entry of start column (0x0010).
/// row_size (rs)
/// This is the configuration entry of row size (2 * skip * height - 1).
/// column_size (cs)
/// This is the configuration entry of column size (2 * skip * width - 1).
/// row_mode (rm)
/// This is the configuration entry of row mode (skip) [skip = 0, 1, 2] .
/// column_mode (cm)
/// This is the configuration entry of column mode (skip) [skip = 0, 1, 2].
///
module camera_config #(
// Clock settings
parameter CLK_FREQ = 50000000, // 50 MHz
parameter I2C_FREQ = 20000 // 20 kHz
) (
// Host Side
input clock,
input reset_n,
// Reg inputs
input [15:0] exposure,
input [15:0] start_row,
input [15:0] start_column,
input [15:0] row_size,
input [15:0] column_size,
input [15:0] row_mode,
input [15:0] column_mode,
// Ready output
output out_ready,
// I2C Side
output I2C_SCLK,
inout I2C_SDAT
);
//------------------------------------------------------------------------------
// I2C Control Clock
reg [15:0] mI2C_CLK_DIV;
reg [31:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
always@(posedge clock or negedge reset_n)
begin
if (!reset_n) begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else begin
if (mI2C_CLK_DIV < (CLK_FREQ / I2C_FREQ))
mI2C_CLK_DIV <= mI2C_CLK_DIV + 1;
else begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
// I2C controller
I2C_Controller u0 (
.CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(reset_n) //
);
//------------------------------------------------------------------------------
// LUT Data Number
parameter LUT_SIZE = 25;
// Configuration control
reg [23:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
reg _ready;
always @(posedge mI2C_CTRL_CLK or negedge reset_n)
begin
if (!reset_n) begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
_ready <= 1'b0;
end
else if (LUT_INDEX < LUT_SIZE) begin
case (mSetup_ST)
0: begin
mI2C_DATA <= {8'hBA, LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if (mI2C_END) begin
if (!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX + 1;
mSetup_ST <= 0;
end
endcase
_ready <= 1'b0;
end
else begin
_ready <= 1'b1;
end
end
// Generates ready signal for system initialization
reg ready;
always @(posedge clock)
begin
if (reset_n) begin
ready <= _ready;
end
else begin
ready <= 1'b0;
end
end
assign out_ready = ready;
// Config Data LUT
always begin
case (LUT_INDEX)
0: LUT_DATA <= 24'h000000;
1: LUT_DATA <= 24'h20c000; // Mirror Row and Columns
2: LUT_DATA <= {8'h09, exposure}; // Exposure
3: LUT_DATA <= 24'h050000; // H_Blanking
4: LUT_DATA <= 24'h060019; // V_Blanking
5: LUT_DATA <= 24'h0A8000; // Change latch
6: LUT_DATA <= 24'h2B0013; // Green 1 Gain
7: LUT_DATA <= 24'h2C009A; // Blue Gain
8: LUT_DATA <= 24'h2D019C; // Red Gain
9: LUT_DATA <= 24'h2E0013; // Green 2 Gain
10: LUT_DATA <= 24'h100051; // Set up PLL power on
// PLL_m_Factor << 8 + PLL_n_Divider. Default = h111807
11: LUT_DATA <= 24'h112003;
12: LUT_DATA <= 24'h120001; // PLL_p1_Divider
13: LUT_DATA <= 24'h100053; // Set USE PLL
14: LUT_DATA <= 24'h980000; // Disable calibration
`ifdef ENABLE_TEST_PATTERN
15: LUT_DATA <= 24'hA00001; // Test pattern control
16: LUT_DATA <= 24'hA10123; // Test green pattern value
17: LUT_DATA <= 24'hA20456; // Test red pattern value
`else
15: LUT_DATA <= 24'hA00000; // Test pattern control
16: LUT_DATA <= 24'hA10000; // Test green pattern value
17: LUT_DATA <= 24'hA20FFF; // Test red pattern value
`endif
18: LUT_DATA <= {8'h01, start_row}; // Set start row
19: LUT_DATA <= {8'h02, start_column}; // Set start column
20: LUT_DATA <= {8'h03, row_size}; // Set row size
21: LUT_DATA <= {8'h04, column_size}; // Set column size
22: LUT_DATA <= {8'h22, row_mode}; // Set row mode in bin mode
23: LUT_DATA <= {8'h23, column_mode}; // Set column mode in bin mode
24: LUT_DATA <= 24'h4901A8; // Row black target
//25: LUT_DATA <= 24'h1E4106; // Set snapshot mode
default: LUT_DATA <= 24'h000000;
endcase
end
//------------------------------------------------------------------------------
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:25:47 05/08/2012
// Design Name: cls_spi
// Module Name: G:/Projects/s6atlystest/cls_spi_tb.v
// Project Name: s6atlystest
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cls_spi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cls_spi_tb;
// Inputs
reg clock;
reg reset;
reg [31:0] data;
reg miso;
// Outputs
wire ss;
wire mosi;
wire sclk;
// Instantiate the Unit Under Test (UUT)
cls_spi uut (
.clock(clock),
.reset(reset),
.data(data),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sclk(sclk)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
data = 32'h89ABCDEF;
miso = 0;
// Wait 100 ns for global reset to finish
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; struct e { int a, b; }; e p[100005]; int n, k; bool use[100005]; priority_queue<int, vector<int>, std::greater<int> > Q; bool criteriu(e a, e b) { return a.b > b.b; } long long af; int main() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &p[i].a); } for (int i = 1; i <= n; i++) { scanf( %d , &p[i].b); } sort(p + 1, p + n + 1, criteriu); for (int i = 1; i <= n; i++) { if (!use[p[i].a]) { use[p[i].a] = true; } else { Q.push(p[i].b); } } for (int i = 1; i <= k; i++) { if (!use[i]) { af += Q.top(); Q.pop(); } } printf( %lld n , af); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; stack<char> stk; int cnt = 0; for (int i = s.size() - 1; i >= 0; i--) { if (stk.empty()) stk.push(s[i]); else { if (stk.top() == s[i]) { cnt++; stk.pop(); } else stk.push(s[i]); } } cout << (cnt & 1 ? Yes : No ) << endl; return 0; }
|
module step_ex_cpf(clk, rst_, ena_, rdy_, reg_id,
r0_din, r0_we_,
r0_dout, r1_dout, r2_dout, r3_dout, r4_dout, r5_dout, fl_dout, pc_dout);
input clk;
input rst_;
input ena_;
output rdy_;
input[3:0] reg_id;
output[7:0] r0_din;
output r0_we_;
input[7:0] r0_dout, r1_dout, r2_dout, r3_dout, r4_dout, r5_dout, fl_dout, pc_dout;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg r0_din_en;
assign r0_din = r0_din_en ? regs_dout[reg_id] : 8'bZ;
reg r0_we_en;
assign r0_we_ = r0_we_en ? 1'b0 : 1'bZ;
reg state;
tri0[7:0] regs_dout[15:0];
assign regs_dout[0] = r0_dout;
assign regs_dout[1] = r1_dout;
assign regs_dout[2] = r2_dout;
assign regs_dout[3] = r3_dout;
assign regs_dout[4] = r4_dout;
assign regs_dout[5] = r5_dout;
assign regs_dout[10] = fl_dout;
assign regs_dout[14] = 8'hff;
assign regs_dout[15] = pc_dout;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
r0_din_en <= 0;
r0_we_en <= 0;
state <= 0;
end else if(!ena_) begin
rdy_en <= 0;
r0_din_en <= 1;
r0_we_en <= 0;
state <= 1;
end else if(state) begin
rdy_en <= 1;
r0_din_en <= 1;
r0_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
r0_din_en <= 0;
r0_we_en <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0), cin.tie(0); int n, j = 0; cin >> n; int a[n], b[n]; pair<int, int> s[n]; for (auto &i : s) cin >> i.first, i.second = j++; sort(s, s + n); map<int, int> mp; for (int i = 0; i < n; i++) mp[s[i].second] = i; for (int i = 0; i < (n + 2) / 3; i++) a[i] = i; for (int i = (n + 2) / 3; i < (2 * n + 2) / 3; i++) b[i] = i; for (int i = n - 1; i >= (2 * n + 2) / 3; i--) b[i] = n - 1 - i; for (int i = (n + 2) / 3; i < n; i++) a[i] = s[i].first - b[i]; for (int i = 0; i < (n + 2) / 3; i++) b[i] = s[i].first - a[i]; cout << YES << n ; for (int i = 0; i < n; i++) cout << a[mp[i]] << ; cout << n ; for (int i = 0; i < n; i++) cout << b[mp[i]] << ; }
|
#include <bits/stdc++.h> using namespace std; namespace io { const int __SIZE = (1 << 21) + 1; char ibuf[__SIZE], *iS, *iT, obuf[__SIZE], *oS = obuf, *oT = oS + __SIZE - 1, __c, qu[55]; int __f, qr, _eof; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout), oS = obuf; } inline void gc(char& x) { x = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); } inline void pc(char x) { *oS++ = x; if (oS == oT) flush(); } inline void pstr(const char* s) { int __len = strlen(s); for (__f = 0; __f < __len; ++__f) pc(s[__f]); } inline void gstr(char* s) { for (__c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); __c < 32 || __c > 126 || __c == ;) __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); for (; __c > 31 && __c < 127 && __c != ; ++s, __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) *s = __c; *s = 0; } template <class I> inline bool gi(I& x) { _eof = 0; for (__f = 1, __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); (__c < 0 || __c > 9 ) && !_eof; __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) { if (__c == - ) __f = -1; _eof |= __c == EOF; } for (x = 0; __c <= 9 && __c >= 0 && !_eof; __c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, __SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) x = x * 10 + (__c & 15), _eof |= __c == EOF; x *= __f; return !_eof; } template <class I> inline void print(I x) { if (!x) pc( 0 ); if (x < 0) pc( - ), x = -x; while (x) qu[++qr] = x % 10 + 0 , x /= 10; while (qr) pc(qu[qr--]); } struct Flusher_ { ~Flusher_() { flush(); } } io_flusher_; } // namespace io using io::gc; using io::gi; using io::gstr; using io::pc; using io::print; using io::pstr; using ll = long long; using pii = pair<int, int>; const int MOD = 1000000007; ll c[500005]; int p2[500005]; map<ll, vector<pii>> NO; int bcj[500006], ltk; void binit() { memset(bcj, -1, sizeof bcj); } int bget(int i) { return (bcj[i] < 0) ? i : (bcj[i] = bget(bcj[i])); } void bmerge(int i, int j) { int ri = bget(i), rj = bget(j); if (ri == rj) { return; } ltk--; if (bcj[ri] > bcj[rj]) { swap(ri, rj); } bcj[ri] += bcj[rj]; bcj[rj] = ri; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m, k; gi(n), gi(m), gi(k); for (int i = (1); i < ((n) + 1); i++) gi(c[i]); p2[0] = 1; for (int i = (1); i < ((n) + 1); i++) { p2[i] = 2 * p2[i - 1]; if (p2[i] >= MOD) p2[i] -= MOD; } while (m--) { int u, v; gi(u), gi(v); auto& ref = NO[c[u] ^ c[v]]; ref.push_back({u, v}); } ll notinno = (1ll << k) - NO.size(); ll ans = 1ll * (notinno % MOD) * p2[n] % MOD; binit(); for (auto& k : NO) { ltk = n; for (auto& i : k.second) bmerge(i.first, i.second); ans += p2[ltk]; for (auto& i : k.second) bcj[i.first] = bcj[i.second] = -1; if (ans >= MOD) ans -= MOD; } print(ans); }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "mult.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
/*
r_A=31'h0402050f;
r_B=31'h0301020c;
e_r=31'h000c0006;
c_ww=`w8;
a_op=`aluwmuleu;
*/
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h03010202030303031004f505ff09fe10;
e_r=128'h000c0006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
// ======================================
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// ======================================
#10
// aluwmulos AND w8
/*
r_A=128'h010330405060708090aff0c0dff0ff02;
r_B=128'h01fa0202030303031004040508000f08;
*/
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmulos;
#10
// aluwmulos AND w16
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmulos;
// ======================================
#10
// aluwmules AND w8
/*
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
*/
r_A=128'h80010501f9015301040100013c010001;
r_B=128'h7f010901fa010001fd01f101b8010001;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmules;
#10
// aluwmules AND w16
/*
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
*/
r_A=128'h000211118000111120541111fff91111;
r_B=128'h0004ffff7fffffff0000fffffffdffff;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmules;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/* verilator lint_off STMTDLY */
module dv_ctrl_local(/*AUTOARG*/
// Outputs
nreset, clk1, clk2, start,
// Inputs
dut_active, stim_done, test_done
);
parameter CFG_CLK1_PERIOD = 10;
parameter CFG_CLK1_PHASE = CFG_CLK1_PERIOD/2;
parameter CFG_CLK2_PERIOD = 100;
parameter CFG_CLK2_PHASE = CFG_CLK2_PERIOD/2;
parameter CFG_TIMEOUT = 50000;
parameter TIMEOUT = 10000;
output nreset; // async active low reset
output clk1; // main clock
output clk2; // secondary clock
output start; // start test (level)
input dut_active; // reset sequence is done
input stim_done; //stimulus is done
input test_done; //test is done
//signal declarations
reg nreset;
reg start;
reg clk1=0;
reg clk2=0;
reg [6:0] clk1_phase;
reg [6:0] clk2_phase;
integer seed,r;
//#################################
// RANDOM NUMBER GENERATOR
// (SEED SUPPLIED EXERNALLY)
//#################################
initial
begin
r=$value$plusargs("SEED=%s", seed);
$display("SEED=%d", seed);
`ifdef CFG_RANDOM
clk1_phase = 1 + {$random(seed)}; //generate random values
clk2_phase = 1 + {$random(seed)}; //generate random values
`else
clk1_phase = CFG_CLK1_PHASE;
clk2_phase = CFG_CLK2_PHASE;
`endif
$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);
end
//#################################
//CLK1 GENERATOR
//#################################
always
#(clk1_phase) clk1 = ~clk1; //add one to avoid "DC" state
//#################################
//CLK2 GENERATOR
//#################################
always
#(clk2_phase) clk2 = ~clk2;
//#################################
//RESET
//#################################
initial
begin
#(1)
nreset = 'b0;
#(clk1_phase * 20 + 100) //hold reset for 20 clk cycles
nreset = 'b1;
end
//START TEST
always @ (posedge clk1 or negedge nreset)
if(!nreset)
start = 1'b0;
else if(dut_active)
start = 1'b1;
//STOP SIMULATION
always @ (posedge clk1)
//if(stim_done & test_done)
// #(CFG_TIMEOUT) $finish;
if(nreset)
#(TIMEOUT) $finish;
//WAVEFORM DUMP
//Better solution?
`ifndef VERILATOR
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, dv_top);
end
`endif
endmodule // dv_ctrl
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O211A_PP_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFXTP_PP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 0.001; const int mod = 1000000007; int main() { int n, pos, l, r, ans; scanf( %d%d%d%d , &n, &pos, &l, &r); if (l == 1 && r == n) ans = 0; else if (l == 1) ans = abs(pos - r) + 1; else if (r == n) ans = abs(pos - l) + 1; else ans = min(abs(pos - l), abs(pos - r)) + r - l + 2; printf( %d , ans); }
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2c_slave
*/
module test_i2c_slave;
// Parameters
parameter FILTER_LEN = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg release_bus = 0;
reg [7:0] s_axis_data_tdata = 0;
reg s_axis_data_tvalid = 0;
reg s_axis_data_tlast = 0;
reg m_axis_data_tready = 0;
reg scl_i = 1;
reg sda_i = 1;
reg enable = 0;
reg [6:0] device_address = 0;
reg [6:0] device_address_mask = 0;
// Outputs
wire s_axis_data_tready;
wire [7:0] m_axis_data_tdata;
wire m_axis_data_tvalid;
wire m_axis_data_tlast;
wire scl_o;
wire scl_t;
wire sda_o;
wire sda_t;
wire busy;
wire [6:0] bus_address;
wire bus_addressed;
wire bus_active;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
release_bus,
s_axis_data_tdata,
s_axis_data_tvalid,
s_axis_data_tlast,
m_axis_data_tready,
scl_i,
sda_i,
enable,
device_address,
device_address_mask
);
$to_myhdl(
s_axis_data_tready,
m_axis_data_tdata,
m_axis_data_tvalid,
m_axis_data_tlast,
scl_o,
scl_t,
sda_o,
sda_t,
busy,
bus_address,
bus_addressed,
bus_active
);
// dump file
$dumpfile("test_i2c_slave.lxt");
$dumpvars(0, test_i2c_slave);
end
i2c_slave #(
.FILTER_LEN(FILTER_LEN)
)
UUT (
.clk(clk),
.rst(rst),
.release_bus(release_bus),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tvalid(s_axis_data_tvalid),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tlast(s_axis_data_tlast),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tlast(m_axis_data_tlast),
.scl_i(scl_i),
.scl_o(scl_o),
.scl_t(scl_t),
.sda_i(sda_i),
.sda_o(sda_o),
.sda_t(sda_t),
.busy(busy),
.bus_address(bus_address),
.bus_addressed(bus_addressed),
.bus_active(bus_active),
.enable(enable),
.device_address(device_address),
.device_address_mask(device_address_mask)
);
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_alu.v
//
// *Module Description:
// openMSP430 ALU
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 34 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Di, 29 Dez 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_alu (
// OUTPUTs
alu_out, // ALU output value
alu_out_add, // ALU adder output value
alu_stat, // ALU Status {V,N,Z,C}
alu_stat_wr, // ALU Status write {V,N,Z,C}
// INPUTs
dbg_halt_st, // Halt/Run status from CPU
exec_cycle, // Instruction execution cycle
inst_alu, // ALU control signals
inst_bw, // Decoded Inst: byte width
inst_jmp, // Decoded Inst: Conditional jump
inst_so, // Single-operand arithmetic
op_dst, // Destination operand
op_src, // Source operand
status // R2 Status {V,N,Z,C}
);
// OUTPUTs
//=========
output [15:0] alu_out; // ALU output value
output [15:0] alu_out_add; // ALU adder output value
output [3:0] alu_stat; // ALU Status {V,N,Z,C}
output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
// INPUTs
//=========
input dbg_halt_st; // Halt/Run status from CPU
input exec_cycle; // Instruction execution cycle
input [11:0] inst_alu; // ALU control signals
input inst_bw; // Decoded Inst: byte width
input [7:0] inst_jmp; // Decoded Inst: Conditional jump
input [7:0] inst_so; // Single-operand arithmetic
input [15:0] op_dst; // Destination operand
input [15:0] op_src; // Source operand
input [3:0] status; // R2 Status {V,N,Z,C}
//=============================================================================
// 1) FUNCTIONS
//=============================================================================
function [4:0] bcd_add;
input [3:0] X;
input [3:0] Y;
input C;
reg [4:0] Z;
begin
Z = {1'b0,X}+{1'b0,Y}+C;
if (Z<10) bcd_add = Z;
else bcd_add = Z+6;
end
endfunction
//=============================================================================
// 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE
//=============================================================================
// SINGLE-OPERAND ARITHMETIC:
//-----------------------------------------------------------------------------
// Mnemonic S-Reg, Operation Status bits
// D-Reg, V N Z C
//
// RRC dst C->MSB->...LSB->C * * * *
// RRA dst MSB->MSB->...LSB->C 0 * * *
// SWPB dst Swap bytes - - - -
// SXT dst Bit7->Bit8...Bit15 0 * * *
// PUSH src SP-2->SP, src->@SP - - - -
// CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - -
// RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * *
//
//-----------------------------------------------------------------------------
// TWO-OPERAND ARITHMETIC:
//-----------------------------------------------------------------------------
// Mnemonic S-Reg, Operation Status bits
// D-Reg, V N Z C
//
// MOV src,dst src -> dst - - - -
// ADD src,dst src + dst -> dst * * * *
// ADDC src,dst src + dst + C -> dst * * * *
// SUB src,dst dst + ~src + 1 -> dst * * * *
// SUBC src,dst dst + ~src + C -> dst * * * *
// CMP src,dst dst + ~src + 1 * * * *
// DADD src,dst src + dst + C -> dst (decimaly) * * * *
// BIT src,dst src & dst 0 * * *
// BIC src,dst ~src & dst -> dst - - - -
// BIS src,dst src | dst -> dst - - - -
// XOR src,dst src ^ dst -> dst * * * *
// AND src,dst src & dst -> dst 0 * * *
//
//-----------------------------------------------------------------------------
// * the status bit is affected
// - the status bit is not affected
// 0 the status bit is cleared
// 1 the status bit is set
//-----------------------------------------------------------------------------
// Invert source for substract and compare instructions.
wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);
wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src;
// Mask the bit 8 for the Byte instructions for correct flags generation
wire op_bit8_msk = ~exec_cycle | ~inst_bw;
wire [16:0] op_src_in = {1'b0, op_src_inv[15:9], op_src_inv[8] & op_bit8_msk, op_src_inv[7:0]};
wire [16:0] op_dst_in = {1'b0, op_dst[15:9], op_dst[8] & op_bit8_msk, op_dst[7:0]};
// Clear the source operand (= jump offset) for conditional jumps
wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) |
(inst_jmp[`JGE] & (status[3]^status[2])) |
(inst_jmp[`JN] & ~status[2]) |
(inst_jmp[`JC] & ~status[0]) |
(inst_jmp[`JNC] & status[0]) |
(inst_jmp[`JEQ] & ~status[1]) |
(inst_jmp[`JNE] & status[1]);
wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}};
// Adder / AND / OR / XOR
wire [16:0] alu_add = op_src_in_jmp + op_dst_in;
wire [16:0] alu_and = op_src_in & op_dst_in;
wire [16:0] alu_or = op_src_in | op_dst_in;
wire [16:0] alu_xor = op_src_in ^ op_dst_in;
// Incrementer
wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |
inst_alu[`ALU_INC]);
wire [16:0] alu_add_inc = alu_add + {16'h0000, alu_inc};
// Decimal adder (DADD)
wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]);
wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]);
wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]);
wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};
// Shifter for rotate instructions (RRC & RRA)
wire alu_shift_msb = inst_so[`RRC] ? status[0] :
inst_bw ? op_src[7] : op_src[15];
wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8];
wire [16:0] alu_shift = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};
// Swap bytes / Extend Sign
wire [16:0] alu_swpb = {1'b0, op_src[7:0],op_src[15:8]};
wire [16:0] alu_sxt = {1'b0, {8{op_src[7]}},op_src[7:0]};
// Combine short paths toghether to simplify final ALU mux
wire alu_short_thro = ~(inst_alu[`ALU_AND] |
inst_alu[`ALU_OR] |
inst_alu[`ALU_XOR] |
inst_alu[`ALU_SHIFT] |
inst_so[`SWPB] |
inst_so[`SXT]);
wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) |
({16{inst_alu[`ALU_OR]}} & alu_or) |
({16{inst_alu[`ALU_XOR]}} & alu_xor) |
({16{inst_alu[`ALU_SHIFT]}} & alu_shift) |
({16{inst_so[`SWPB]}} & alu_swpb) |
({16{inst_so[`SXT]}} & alu_sxt) |
({16{alu_short_thro}} & op_src_in);
// ALU output mux
wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st |
inst_alu[`ALU_ADD]) ? alu_add_inc :
inst_alu[`ALU_DADD] ? alu_dadd : alu_short;
assign alu_out = alu_out_nxt[15:0];
assign alu_out_add = alu_add[15:0];
//-----------------------------------------------------------------------------
// STATUS FLAG GENERATION
//-----------------------------------------------------------------------------
wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) :
(op_src_in[15] & op_dst_in[15]);
wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) |
( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) :
((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) |
( op_src_in[15] & op_dst_in[15] & ~alu_out[15]));
wire N = inst_bw ? alu_out[7] : alu_out[15];
wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
wire C = inst_bw ? alu_out[8] : alu_out_nxt[16];
assign alu_stat = inst_alu[`ALU_SHIFT] ? {1'b0, N,Z,op_src_in[0]} :
inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z} :
inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C};
assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000;
endmodule // omsp_alu
`include "openMSP430_undefines.v"
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MinMax.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_MinMax
// Source Path: velocityControlHdl/Space_Vector_Modulation/MinMax
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_MinMax
(
in0,
in1,
in2,
out0
);
input signed [17:0] in0; // sfix18_En12
input signed [17:0] in1; // sfix18_En12
input signed [17:0] in2; // sfix18_En12
output signed [17:0] out0; // sfix18_En12
wire signed [17:0] MinMax_muxout [0:2]; // sfix18_En12 [3]
wire signed [17:0] MinMax_stage1_val [0:1]; // sfix18_En12 [2]
wire signed [17:0] MinMax_stage2_val; // sfix18_En12
assign MinMax_muxout[0] = in0;
assign MinMax_muxout[1] = in1;
assign MinMax_muxout[2] = in2;
// ---- Tree min implementation ----
// ---- Tree min stage 1 ----
assign MinMax_stage1_val[0] = (MinMax_muxout[0] <= MinMax_muxout[1] ? MinMax_muxout[0] :
MinMax_muxout[1]);
assign MinMax_stage1_val[1] = MinMax_muxout[2];
// ---- Tree min stage 2 ----
assign MinMax_stage2_val = (MinMax_stage1_val[0] <= MinMax_stage1_val[1] ? MinMax_stage1_val[0] :
MinMax_stage1_val[1]);
assign out0 = MinMax_stage2_val;
endmodule // velocityControlHdl_MinMax
|
/**
* Testbench file for components-shiftreg.v
*
* Verilib - A Verilog HDL development framework
* Copyright (c) 2014, Patrick Dear, All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3.0 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library.
*/
`include "tb-macros.v"
`include "components-shiftreg.v"
module components_shiftreg_tb;
`TESTBENCH_BEGIN("components-shiftreg")
//============================================================================
// Test setup for module components_shiftreg
//============================================================================
localparam UUT0_WIDTH = 8;
localparam UUT0_RESET_VAL = 0;
reg uut0_sh_en = 0;
reg uut0_load = 0;
reg [UUT0_WIDTH-1:0] uut0_d = 0;
reg uut0_sh_in = 0;
wire [UUT0_WIDTH-1:0] uut0_q;
wire uut0_sh_out;
components_shiftreg #(
.WIDTH(UUT0_WIDTH),
.RESET_VAL(UUT0_RESET_VAL)
) uut0 (
.clk(clk),
.rst(rst),
.sh_en(uut0_sh_en),
.load(uut0_load),
.d(uut0_d),
.sh_in(uut0_sh_in),
.q(uut0_q),
.sh_out(uut0_sh_out)
);
//----------------------------------------------------------------------------
// Test sequence for components_shiftreg
//----------------------------------------------------------------------------
`TEST_SEQUENCE_BEGIN(0, "components_shiftreg")
//----------------------------------------------------------------------------
`TEST_CASE_BEGIN("Reset functionality")
`CHECK_EQ(UUT0_RESET_VAL, uut0_q)
`TEST_CASE_END
//----------------------------------------------------------------------------
`TEST_CASE_BEGIN("Load functionality")
uut0_d = 8'hA1;
wait_cycles(1);
`CHECK_EQ(UUT0_RESET_VAL, uut0_q)
uut0_load = 1;
wait_cycles(1);
uut0_load = 0;
`CHECK_EQ(uut0_q, 8'hA1)
`TEST_CASE_END
//----------------------------------------------------------------------------
`TEST_CASE_BEGIN("Shift output functionality")
rst = 1'b1;
wait_cycles(1);
`CHECK_EQ(UUT0_RESET_VAL, uut0_q)
rst = 1'b0;
wait_cycles(1);
uut0_d = 8'hB4;
uut0_load = 1;
wait_cycles(1);
uut0_load = 0;
uut0_sh_en = 1;
`CHECK_EQ(uut0_sh_out, 1)
wait_cycles(1);
`CHECK_EQ(uut0_sh_out, 0)
wait_cycles(1);
`CHECK_EQ(uut0_sh_out, 1)
wait_cycles(1);
`CHECK_EQ(uut0_sh_out, 1)
wait_cycles(1);
`CHECK_EQ(uut0_sh_out, 0)
wait_cycles(1);
`CHECK_EQ(uut0_sh_out, 1)
wait_cycles(1);
`CHECK_EQ(uut0_sh_out, 0)
wait_cycles(1);
`CHECK_EQ(uut0_sh_out, 0)
uut0_sh_en = 0;
`TEST_CASE_END
//----------------------------------------------------------------------------
`TEST_CASE_BEGIN("Shift input functionality")
rst = 1'b1;
wait_cycles(1);
`CHECK_EQ(UUT0_RESET_VAL, uut0_q)
rst = 1'b0;
wait_cycles(1);
uut0_sh_en = 1;
uut0_sh_in = 1;
wait_cycles(1);
uut0_sh_in = 0;
wait_cycles(1);
uut0_sh_in = 1;
wait_cycles(1);
uut0_sh_in = 0;
wait_cycles(1);
uut0_sh_in = 0;
wait_cycles(1);
uut0_sh_in = 1;
wait_cycles(1);
uut0_sh_in = 1;
wait_cycles(1);
uut0_sh_in = 1;
wait_cycles(1);
uut0_sh_en = 0;
`CHECK_EQ(uut0_q, 8'hA7)
`TEST_CASE_END
//----------------------------------------------------------------------------
`TEST_SEQUENCE_END
`TESTBENCH_END(1)
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; if (k % 2 != 0) { cout << -1 ; return 0; } for (int i = 0; i < k; i++) { for (int j = 0; j < k; j++) { for (int t = 0; t < k; t++) { if (i % 2 == 0) { if ((j % 4 <= 1 && t % 4 <= 1) || (j % 4 >= 2 && t % 4 >= 2)) { cout << w ; } else { cout << b ; } } else { if ((j % 4 <= 1 && t % 4 <= 1) || (j % 4 >= 2 && t % 4 >= 2)) { cout << b ; } else { cout << w ; } } } cout << endl; } cout << endl; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF_DCIEN.v
// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 03/28/11 - CR 603466 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF_DCIEN (O, IO, DCITERMDISABLE, I, IBUFDISABLE, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
inout IO;
input DCITERMDISABLE;
input I;
input IBUFDISABLE;
input T;
// define constants
localparam MODULE_NAME = "IOBUF_DCIEN";
wire ts;
wire T_OR_IBUFDISABLE;
wire out_val;
wire disable_out;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
and a1 (disable_out, DCITERMDISABLE, IBUFDISABLE);
// buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUF_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-105] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
end // initial begin
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
end
default : begin
assign out_val = 1'b0;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE = ~T || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE == 1'b1) ? out_val : (T_OR_IBUFDISABLE == 1'b0) ? IO : 1'bx;
end
"FALSE" : begin
assign O = IO;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IO) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A32OI_PP_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_PP_SYMBOL_V
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top
(
input wire clk,
output wire ser_tx,
input wire ser_rx,
input wire [15:0] sw,
output wire [15:0] led
);
// ============================================================================
reg rst = 1;
reg rst1 = 1;
reg rst2 = 1;
reg rst3 = 1;
assign led[0] = rst;
assign led[13:1] = sw[13:1];
assign led[14] = ^sw;
assign led[15] = ser_rx;
always @(posedge clk) begin
rst3 <= 0;
rst2 <= rst3;
rst1 <= rst2;
rst <= rst1;
end
// ============================================================================
//
scalable_proc #
(
.NUM_PROCESSING_UNITS (3),
.UART_PRESCALER ((100000000) / (500000))
)
scalable_proc
(
.CLK (clk),
.RST (rst),
.UART_TX (ser_tx),
.UART_RX (ser_rx)
);
endmodule
|
#include <bits/stdc++.h> template <typename T> void scan(T &x) { x = 0; bool _ = 0; T c = getchar(); _ = c == 45; c = _ ? getchar() : c; while (c < 48 || c > 57) c = getchar(); for (; c < 48 || c > 57; c = getchar()) ; for (; c > 47 && c < 58; c = getchar()) x = (x << 3) + (x << 1) + (c & 15); x = _ ? -x : x; } template <typename T> void printn(T n) { bool _ = 0; _ = n < 0; n = _ ? -n : n; char snum[65]; int i = 0; do { snum[i++] = n % 10 + 48; n /= 10; } while (n); --i; if (_) putchar(45); while (i >= 0) putchar(snum[i--]); } template <typename First, typename... Ints> void scan(First &arg, Ints &...rest) { scan(arg); scan(rest...); } template <typename T> void print(T n) { printn(n); putchar(10); } template <typename First, typename... Ints> void print(First arg, Ints... rest) { printn(arg); putchar(32); print(rest...); } using namespace std; using ll = long long; const int MM = 505; int n; ll a[MM], ans; int main() { scan(n); for (int i = 0; i < n; i++) { scan(a[i]); } for (int i = 0; i < n; i++) { for (int j = 0; j <= i; j++) { for (int k = 0; k <= j; k++) { ans = max(ans, a[i] | a[j] | a[k]); } } } print(ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211OI_2_V
`define SKY130_FD_SC_HS__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211OI_2_V
|
//*************************************************************************
// > ÎļþÃû: adder_display.v
// > ÃèÊö £º¼Ó·¨Æ÷ÏÔʾģ¿é£¬µ÷ÓÃFPGA°åÉϵÄIO½Ó¿ÚºÍ´¥ÃþÆÁ
// > ×÷Õß : LOONGSON
// > ÈÕÆÚ : 2016-04-14
//*************************************************************************
module adder_display(
//ʱÖÓÓ븴λÐźÅ
input clk,
input resetn, //ºó׺"n"´ú±íµÍµçƽÓÐЧ
//²¦Â뿪¹Ø£¬ÓÃÓÚÑ¡ÔñÊäÈëÊýºÍ²úÉúcin
input input_sel, //0:ÊäÈëΪ¼ÓÊý1(add_operand1);1:ÊäÈëΪ¼ÓÊý2(add_operand2)
input sw_cin,
//ledµÆ£¬ÓÃÓÚÏÔʾcout
output led_cout,
//´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);
//-----{µ÷Óüӷ¨Ä£¿é}begin
reg [31:0] adder_operand1;
reg [31:0] adder_operand2;
wire adder_cin;
wire [31:0] adder_result ;
wire adder_cout;
adder adder_module(
.operand1(adder_operand1),
.operand2(adder_operand2),
.cin (adder_cin ),
.result (adder_result ),
.cout (adder_cout )
);
assign adder_cin = sw_cin;
assign led_cout = adder_cout;
//-----{µ÷Óüӷ¨Ä£¿é}end
//---------------------{µ÷Óô¥ÃþÆÁÄ£¿é}begin--------------------//
//-----{ʵÀý»¯´¥ÃþÆÁ}begin
//´ËС½Ú²»ÐèÒª¸ü¸Ä
reg display_valid;
reg [39:0] display_name;
reg [31:0] display_value;
wire [5 :0] display_number;
wire input_valid;
wire [31:0] input_value;
lcd_module lcd_module(
.clk (clk ), //10Mhz
.resetn (resetn ),
//µ÷Óô¥ÃþÆÁµÄ½Ó¿Ú
.display_valid (display_valid ),
.display_name (display_name ),
.display_value (display_value ),
.display_number (display_number),
.input_valid (input_valid ),
.input_value (input_value ),
//lcd´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
.lcd_rst (lcd_rst ),
.lcd_cs (lcd_cs ),
.lcd_rs (lcd_rs ),
.lcd_wr (lcd_wr ),
.lcd_rd (lcd_rd ),
.lcd_data_io (lcd_data_io ),
.lcd_bl_ctr (lcd_bl_ctr ),
.ct_int (ct_int ),
.ct_sda (ct_sda ),
.ct_scl (ct_scl ),
.ct_rstn (ct_rstn )
);
//-----{ʵÀý»¯´¥ÃþÆÁ}end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}begin
//¸ù¾Ýʵ¼ÊÐèÒªÊäÈëµÄÊýÐ޸ĴËС½Ú£¬
//½¨Òé¶Ôÿһ¸öÊýµÄÊäÈ룬±àдµ¥¶ÀÒ»¸öalways¿é
//µ±input_selΪ0ʱ£¬±íʾÊäÈëÊýΪ¼ÓÊý1£¬¼´operand1
always @(posedge clk)
begin
if (!resetn)
begin
adder_operand1 <= 32'd0;
end
else if (input_valid && !input_sel)
begin
adder_operand1 <= input_value;
end
end
//µ±input_selΪ1ʱ£¬±íʾÊäÈëÊýΪ¼ÓÊý2£¬¼´operand2
always @(posedge clk)
begin
if (!resetn)
begin
adder_operand2 <= 32'd0;
end
else if (input_valid && input_sel)
begin
adder_operand2 <= input_value;
end
end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}begin
//¸ù¾ÝÐèÒªÏÔʾµÄÊýÐ޸ĴËС½Ú£¬
//´¥ÃþÆÁÉϹ²ÓÐ44¿éÏÔʾÇøÓò£¬¿ÉÏÔʾ44×é32λÊý¾Ý
//44¿éÏÔʾÇøÓò´Ó1¿ªÊ¼±àºÅ£¬±àºÅΪ1~44£¬
always @(posedge clk)
begin
case(display_number)
6'd1 :
begin
display_valid <= 1'b1;
display_name <= "ADD_1";
display_value <= adder_operand1;
end
6'd2 :
begin
display_valid <= 1'b1;
display_name <= "ADD_2";
display_value <= adder_operand2;
end
6'd3 :
begin
display_valid <= 1'b1;
display_name <= "RESUL";
display_value <= adder_result;
end
default :
begin
display_valid <= 1'b0;
display_name <= 40'd0;
display_value <= 32'd0;
end
endcase
end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}end
//----------------------{µ÷Óô¥ÃþÆÁÄ£¿é}end---------------------//
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e4, SQN = 3e2; map<int, int> dst_idx, idx_dst; int n, d, dp[MAXN + 3][SQN + 3], a[MAXN + 3], max_idx; int fazdp(int idx, int li) { if (dp[idx][li] != -1) return dp[idx][li]; int di = idx_dst[li]; int ret = 0; for (int i = -1; i <= 1; i++) { int dd = di + i; if (dst_idx.find(dd) == dst_idx.end() || dd <= 0 || idx + dd > max_idx) continue; int iidx = idx + dd; ret = max(ret, fazdp(iidx, dst_idx[dd])); } return dp[idx][li] = a[idx] + ret; } int main() { for (int i = 0; i < MAXN + 3; i++) for (int j = 0; j < SQN + 3; j++) dp[i][j] = -1; scanf( %d %d , &n, &d); for (int i = 1; i <= n; i++) { int aux; scanf( %d , &aux); max_idx = max(max_idx, aux); a[aux]++; } int cnt = 0; for (int i = max(1, d - SQN); i <= min(max_idx, d + SQN); i++) { dst_idx[i] = cnt; idx_dst[cnt] = i; cnt++; } printf( %d , a[0] + fazdp(d, dst_idx[d])); }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e3 + 1; struct node { int w, x, y, z; }; queue<int> q; vector<int> g[N], rg[N]; int d[N][N], rd[N][N], vis[N]; vector<pair<int, int>> fg[N], frg[N]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; g[u].push_back(v); rg[v].push_back(u); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { vis[j] = 0; d[i][j] = n + 1; } vis[i] = 1; q.push(i); d[i][i] = 0; while (!q.empty()) { int v = q.front(); q.pop(); for (auto u : g[v]) { if (vis[u]) continue; vis[u] = 1; q.push(u); d[i][u] = d[i][v] + 1; } } for (int j = 1; j <= n; j++) { if (j == i) continue; if (d[i][j] != n + 1) fg[i].push_back({d[i][j], j}); } sort(fg[i].begin(), fg[i].end()); for (int j = 1; j <= n; j++) { vis[j] = 0; rd[i][j] = n + 1; } vis[i] = 1; q.push(i); rd[i][i] = 0; while (!q.empty()) { int v = q.front(); q.pop(); for (auto u : rg[v]) { if (vis[u]) continue; vis[u] = 1; q.push(u); rd[i][u] = rd[i][v] + 1; } } for (int j = 1; j <= n; j++) { if (j == i) continue; if (rd[i][j] != n + 1) frg[i].push_back({rd[i][j], j}); } sort(frg[i].begin(), frg[i].end()); } int ans = 0; node A; for (int b = 1; b <= n; b++) { for (int c = 1; c <= n; c++) { if (b == c || d[b][c] == n + 1) continue; int ans1 = 0, z = 0; node B; int sz1 = frg[b].size(), sz2 = fg[c].size(); for (int j = sz1 - 1; j >= max(z, sz1 - 3); j--) { int a = frg[b][j].second; for (int k = sz2 - 1; k >= max(z, sz2 - 3); k--) { int dd = fg[c][k].second; if (a == c || dd == b || a == dd) continue; int ans2 = d[b][c] + rd[b][a] + d[c][dd]; node C; C.w = a; C.x = b; C.y = c; C.z = dd; if (ans2 > ans1) { ans1 = ans2; B = C; } } } if (ans1 > ans) { ans = ans1; A = B; } } } cout << A.w << << A.x << << A.y << << A.z << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int m, n, arr[2000][2000], temp[2000][2000]; char ctrl(int i) { for (int j = 1; j <= n; j++) if (arr[i][j] and arr[i][j] != temp[i][j]) return 0; return 1; } char solve(int a, int b, int c, int d, int ttt = 0) { if (ttt) ttt = 3; for (int i = 1; i <= m; i++) { if (i & 1) { for (int j = 1; j <= n; j++) if (j & 1) temp[i][j] = a; else temp[i][j] = b; if (ctrl(i)) continue; for (int j = 1; j <= n; j++) if (j & 1) temp[i][j] = b; else temp[i][j] = a; if (ctrl(i)) continue; return 0; } else { for (int j = 1; j <= n; j++) if (j & 1) temp[i][j] = c; else temp[i][j] = d; if (ctrl(i)) continue; for (int j = 1; j <= n; j++) if (j & 1) temp[i][j] = d; else temp[i][j] = c; if (ctrl(i)) continue; return 0; } } while (ttt--) { for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) arr[j][m - i + 1] = temp[i][j]; swap(m, n); for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) temp[i][j] = arr[i][j]; } for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) cout << temp[i][j]; cout << endl; } return 1; } int main() { ios_base::sync_with_stdio(false); cin >> m >> n; char c; for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) { cin >> c; arr[i][j] = c - 0 ; } if (solve(1, 2, 3, 4)) return 0; if (solve(1, 3, 2, 4)) return 0; if (solve(1, 4, 2, 3)) return 0; if (solve(2, 3, 1, 4)) return 0; if (solve(2, 4, 1, 3)) return 0; if (solve(3, 4, 1, 2)) return 0; for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) temp[j][m - i + 1] = arr[i][j]; swap(m, n); for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) arr[i][j] = temp[i][j]; if (solve(1, 2, 3, 4, 1)) return 0; if (solve(1, 3, 2, 4, 1)) return 0; if (solve(1, 4, 2, 3, 1)) return 0; if (solve(2, 3, 1, 4, 1)) return 0; if (solve(2, 4, 1, 3, 1)) return 0; if (solve(3, 4, 1, 2, 1)) return 0; cout << 0 << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, a[1005]; long long int p[1005], f[1005], d; long long int power(long long int a, long long int b) { if (b == 0) return 1; if (b == 1) return a % 998244353; long long int c = power(a, b / 2); if (b & 1) return (((c * c) % 998244353) * a) % 998244353; else return (c * c) % 998244353; } long long int ret(int a, int b) { long long int c = f[a]; c *= power(f[b], 998244353 - 2); c %= 998244353; c *= power(f[a - b], 998244353 - 2); return c % 998244353; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); f[0] = 1; for (int i = 1; i < 1005; i++) { f[i] = i * f[i - 1]; f[i] %= 998244353; } cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } p[n + 1] = 1; for (int i = n; i > 0; i--) { p[i] = p[i + 1]; for (int j = i + a[i]; j <= n && a[i] > 0; j++) { d = ret(j - i - 1, a[i] - 1); p[i] += d * p[j + 1]; p[i] %= 998244353; } } cout << ((p[1] + 998244353 - 1) % 998244353); }
|
module main;
reg src;
reg clk;
wire dst0, dst1;
test #(.parm(0)) test0 (.dst(dst0), .src(src), .clk(clk));
test #(.parm(1)) test1 (.dst(dst1), .src(src), .clk(clk));
//Note: For Modelsim compatibility do instantiation as:
//test #(.parm(2'b10)) test0 (.dst(dst0), .src(src), .clk(clk));
//test #(.parm(2'b11)) test1 (.dst(dst1), .src(src), .clk(clk));
//The reason is that Modelsim handles single-bit std_logic as an
//enumeration, and enumeration values 2 and 3 correspond to the
//stdlogic '0' and '1' values. The integer to std_logic values
//in modelsim are:
// 0 - 'U'
// 1 - 'X'
// 2 - '0'
// 3 - '1'
// 4 - 'Z'
// 5 - 'W'
// 6 - 'L'
// 7 - 'H'
// 8 - '-'
//Maybe in the future we'll have to do something similar?
initial begin
clk = 0;
src = 0;
#1 clk = 1;
#1 if (dst0 !== 1'b0 || dst1 !== 1'b1) begin
$display("FAILED: src=%b, dst0=%b dst1=%b", src, dst0, dst1);
$finish;
end
clk = 0;
src = 1;
#1 clk = 1;
#1 if (dst0 !== 1'b1 || dst1 !== 1'b0) begin
$display("FAILED: src=%b, dst0=%b dst1=%b", src, dst0, dst1);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:55:33 09/09/2014
// Design Name:
// Module Name: sevensegdecoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sevensegdecoder(
input [3:0] nIn,
output reg [6:0] ssOut
);
always @(nIn)
case (nIn)
4'h0: ssOut = 7'b1000000;
4'h1: ssOut = 7'b1111001;
4'h2: ssOut = 7'b0100100;
4'h3: ssOut = 7'b0110000;
4'h4: ssOut = 7'b0011001;
4'h5: ssOut = 7'b0010010;
4'h6: ssOut = 7'b0000010;
4'h7: ssOut = 7'b1111000;
4'h8: ssOut = 7'b0000000;
4'h9: ssOut = 7'b0011000;
4'hA: ssOut = 7'b0001000;
4'hB: ssOut = 7'b0000011;
4'hC: ssOut = 7'b1000110;
4'hD: ssOut = 7'b0100001;
4'hE: ssOut = 7'b0000110;
4'hF: ssOut = 7'b0001110;
default: ssOut = 7'b1001001;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int a[300005] = {0}; int c1 = 0, c2 = 0, p1 = 0, p2 = 0; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; int maxn = -1; for (int i = 1; i <= n; i++) { if (c1 == 0) { p1 = i; c1 = a[i]; } else if (c2 == 0 && a[i] != c1) { p2 = i; c2 = a[i]; maxn = max(maxn, p2 - p1); } else if (a[i] == c1 && p2 != 0) { maxn = max(maxn, i - p2); } else if (a[i] == c2) { maxn = max(maxn, i - p1); } else if (a[i] != c1 && a[i] != c2) { maxn = max(maxn, i - p1); } } cout << maxn << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:200000000 ) const double EPS = 1E-9; const int INF = 1000000000; const long long INF64 = (long long)1E18; const double PI = 3.1415926535897932384626433832795; const int NMAX = 310000; set<pair<int, int> > q[3][3]; int a[NMAX], b[NMAX], n, w, c[NMAX][3]; long long s; char st[NMAX]; void out() { puts(st); exit(0); } void add(int id) { int cur = st[id] - 0 ; s += c[id][cur]; for (int i = 0; i < (int)(3); i++) { if (i == cur) continue; q[cur][i].insert(make_pair(c[id][i] - c[id][cur], id)); } } void erase(int id) { int cur = st[id] - 0 ; s -= c[id][cur]; for (int i = 0; i < (int)(3); i++) { if (i == cur) continue; q[cur][i].erase(make_pair(c[id][i] - c[id][cur], id)); } } void perf(int st1, int st2) { int id = q[st1][st2].begin()->second; erase(id); st[id] = st2 + 0 ; add(id); } bool can2(int f1, int t1, int f2, int t2) { if (q[f1][t1].empty()) return false; int id1 = q[f1][t1].begin()->second; int v1 = q[f1][t1].begin()->first; erase(id1); if (q[f2][t2].empty()) { add(id1); return false; } int id2 = q[f2][t2].begin()->second; int v2 = q[f2][t2].begin()->first; erase(id2); if (v1 + v2 >= 0) { add(id1); add(id2); return false; } st[id1] = t1 + 0 ; add(id1); st[id2] = t2 + 0 ; add(id2); return true; } bool can3(int f1, int t1, int f2, int t2, int f3, int t3) { if (q[f1][t1].empty()) return false; int id1 = q[f1][t1].begin()->second; long long v1 = q[f1][t1].begin()->first; erase(id1); if (q[f2][t2].empty()) { add(id1); return false; } int id2 = q[f2][t2].begin()->second; long long v2 = q[f2][t2].begin()->first; erase(id2); if (q[f3][t3].empty()) { add(id1); add(id2); return false; } int id3 = q[f3][t3].begin()->second; long long v3 = q[f3][t3].begin()->first; erase(id3); if (v1 + v2 + v3 >= 0) { add(id1); add(id2); add(id3); return false; } st[id1] = t1 + 0 ; add(id1); st[id2] = t2 + 0 ; add(id2); st[id3] = t3 + 0 ; add(id3); return true; } long long solve(long long ans = -1) { for (int i = 0; i < (int)(3); i++) for (int j = 0; j < (int)(3); j++) q[i][j].clear(); for (int i = 0; i < (int)(n); i++) st[i] = 0 ; for (int i = 0; i < (int)(n); i++) add(i); s = 0; int left = w; while (left) { if (left >= 2 && q[0][2].size()) { perf(0, 2); left -= 2; } else if (left >= 1 && q[0][1].size()) { perf(0, 1); left--; } } if (left) throw; long long res = s; if (s == ans) out(); bool change = true; while (change) { change = false; change |= can2(0, 1, 1, 0); change |= can2(0, 1, 2, 1); change |= can2(1, 2, 2, 1); change |= can2(1, 2, 1, 0); change |= can2(0, 2, 2, 0); change |= can3(0, 2, 2, 1, 2, 1); change |= can3(0, 2, 1, 0, 2, 1); change |= can3(0, 2, 1, 0, 1, 0); change |= can3(2, 0, 1, 2, 1, 2); change |= can3(2, 0, 0, 1, 1, 2); change |= can3(2, 0, 0, 1, 0, 1); if (res == ans) out(); res = min(res, s); } return res; } int main() { cin >> n >> w; for (int i = 0; i < (int)(n); i++) { scanf( %d%d , &a[i], &b[i]); c[i][0] = 0; c[i][1] = a[i]; c[i][2] = b[i]; } long long ans = solve(); cout << ans << endl; solve(ans); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33,
x33, w30, x30,
// Inputs
a, a40, a70
);
input [3:0] a;
input [39:0] a40;
input [69:0] a70;
// -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI()
// verilator lint_off WIDTH
output [3:0] i65 = 65'd3 ** a; // WWI
output [3:0] j65 = a ** 65'd3; // IIW
output [3:0] i33 = 33'd3 ** a; // QQI
output [3:0] j33 = a ** 33'd3; // IIQ
output [3:0] i30 = 30'd3 ** a; // III
output [3:0] j30 = a ** 30'd3; // III
output [39:0] q65 = 65'd3 ** a40; // WWQ
output [39:0] r65 = a40 ** 65'd3; // WWQ
output [39:0] q33 = 33'd3 ** a40; // QQQ
output [39:0] r33 = a40 ** 33'd3; // QQQ
output [39:0] q30 = 30'd3 ** a40; // QQI
output [39:0] r30 = a40 ** 30'd3; // QQI
output [69:0] w65 = 65'd3 ** a70; // WWW
output [69:0] x65 = a70 ** 65'd3; // WWW
output [69:0] w33 = 33'd3 ** a70; // WWW
output [69:0] x33 = a70 ** 33'd3; // WWW
output [69:0] w30 = 30'd3 ** a70; // WWW
output [69:0] x30 = a70 ** 30'd3; // WWW
// verilator lint_on WIDTH
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 2e5 + 8, inf = 1e18 + 9, mod = 1e9 + 7; char s[maxn]; long long n, m; void solve() { long long i, j, ans = 1; cin >> n >> (s + 1); for (i = 2; i <= n; i++) if (s[i] != s[i - 1]) ans++; cout << min(ans + 2, n) << endl; } signed main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long t = 1; while (t--) solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O311AI_FUNCTIONAL_PP_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5, OO = 1e14; const int di[] = {1, -1, 0, 0}; const int dj[] = {0, 0, 1, -1}; long long TC, n, m, k, a, b, c, cnt, u, mx, mn, ans, arr[N]; bool f, vis[N], mark[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> TC; while (TC--) { cin >> n >> m; cnt = f = 0; m += (2 * n); for (int i = 1; i <= n && !f; i++) { for (int j = i + 1; j <= n; j++) { cout << i << << j << n ; if (++cnt == m) { f = 1; break; } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<pair<int, int>, pair<int, int> > > way[222222]; queue<int> turn; bool was[222222]; int i, n, m, ans[222222], cost[222222]; int main() { cin >> n >> m; for (i = 1; i <= m; i++) { int a, b, c; cin >> a >> b >> c; cost[a] += c; cost[b] += c; way[a].push_back(make_pair(make_pair(i, c), make_pair(b, 0))); way[b].push_back(make_pair(make_pair(i, c), make_pair(a, 1))); } for (i = 1; i <= n; i++) cost[i] /= 2; turn.push(1); memset(was, 1, sizeof(was)); while (!turn.empty()) { int t = turn.front(); was[t] = 0; turn.pop(); for (i = 0; i < way[t].size(); i++) if (was[way[t][i].second.first]) { int u = way[t][i].second.first; ans[way[t][i].first.first] = way[t][i].second.second; cost[u] -= way[t][i].first.second; if (cost[u] == 0 && u != n) turn.push(u); } } for (i = 1; i <= m; i++) cout << ans[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool exitInput = false; int ntest = 1, itest = 1; const char* directions[4] = { NE , SE , SW , NW }; const long long Mod = 1000000000LL + 7; const int maxn = 100 + 2; const int maxv = 1000000 + 5; const int maxe = 600000 + 5; const int root = 1; int a, n, b; int isprime[1250002]; int base_prime[10000000 + 1], ans[10000000 + 1]; long long res; void sieve(int gh) { int i, j, k, x; int nBytes = gh / 8 + 1; isprime[0] = 0xFC; for (i = 1; i <= nBytes; ++i) { isprime[i] = 0xFF; } for (i = 2; i <= gh; ++i) { j = i >> 3; k = i - (j << 3); if (isprime[j] & (1 << k)) { for (x = i + i; x <= gh; x += i) { j = x >> 3; k = x - (j << 3); isprime[j] &= ~(1 << k); base_prime[x] = i; } base_prime[i] = i; } } } int main() { int i, j, k, t; scanf( %d %d , &a, &n); b = a + n - 1; sieve(b); res = 0; ans[1] = 1; for (i = 2; i <= b; ++i) { if (base_prime[i] == i) { ans[i] = i; } else { t = j = i / base_prime[i]; k = 0; while (j % base_prime[i] == 0) { j /= base_prime[i]; ++k; } j = t; if (k & 1) ans[i] = ans[j] / base_prime[i]; else ans[i] = ans[j] * base_prime[i]; } } for (i = a; i <= b; ++i) { res += ans[i]; } printf( %lld n , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> G[((int)2e5 + 10)]; int dis[((int)2e5 + 10)]; int n; int ans = 0; void dfs(int f, int son, int d) { int flag = 0; dis[son] = d; for (int i = 0; i < G[son].size(); i++) { if (G[son][i] == f) continue; dfs(son, G[son][i], d + 1); if (dis[G[son][i]] > 2) { flag = 1; dis[G[son][i]] = 2; dis[son] = 1; dis[f] = 2; } } ans += flag; } int main() { scanf( %d , &n); for (int i = 1; i <= n - 1; i++) { int x, y; scanf( %d %d , &x, &y); G[x].push_back(y); G[y].push_back(x); } dfs(-1, 1, 0); cout << ans << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A32OI_PP_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a32oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool condition(int year) { int year_arr[4]; int boo; for (int i = 3; i >= 0; i--) { year_arr[i] = year % 10; year = year / 10; } if (year_arr[0] == year_arr[1] || year_arr[0] == year_arr[2] || year_arr[0] == year_arr[3] || year_arr[1] == year_arr[2] || year_arr[1] == year_arr[3] || year_arr[2] == year_arr[3]) { boo = false; } else { boo = true; } return boo; } int main() { int prev_y, next_y; cin >> prev_y; next_y = prev_y + 1; while (condition(next_y) == false) { next_y += 1; } cout << next_y; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_b_e
//
// Generated
// by: wig
// on: Wed Jun 7 16:54:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_b_e.v,v 1.4 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_b_e.v,v $
// Revision 1.4 2006/06/22 07:19:59 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_b_e
//
// No user `defines in this module
module inst_b_e
//
// Generated Module inst_b
//
(
port_b_1
);
// Generated Module Inputs:
input port_b_1;
// Generated Wires:
wire port_b_1;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of inst_b_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_LP_V
`define SKY130_FD_SC_LP__OR4B_LP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4b_lp (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4b_lp (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_4_V
`define SKY130_FD_SC_LS__FILL_4_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_4_V
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#include <bits/stdc++.h> const int MAXN = 200005; int n, m, tot, a[MAXN], b[MAXN], pa[MAXN], pb[MAXN], tr[MAXN], ans[MAXN * 10]; bool tag[MAXN * 10], used[MAXN * 10]; template <typename T> inline void read(T &x) { int fl = 0, ch; while (ch = getchar(), ch < 48 || 57 < ch) fl ^= !(ch ^ 45); x = (ch & 15); while (ch = getchar(), 47 < ch && ch < 58) x = x * 10 + (ch & 15); if (fl) x = -x; } struct ASK { int opt, x, y, id; } q[MAXN * 10], qq[MAXN * 10]; void upd(int i, int x) { for (; i <= n; i += i & -i) tr[i] += x; } int qry(int i) { int res = 0; for (; i; i &= i - 1) res += tr[i]; return res; } void cdq(int l, int r) { if (l >= r) return; int mid = l + r >> 1; cdq(l, mid), cdq(mid + 1, r); int i = l, j = mid + 1; for (int k = l; k <= r; ++k) { if (i <= mid && (j > r || q[i].x <= q[j].x)) { if (q[i].opt == 2) upd(q[i].y, 1); if (q[i].opt == 3) upd(q[i].y, -1); qq[k] = q[i++], used[k] = 1; } else { if (q[j].opt == 1) ans[q[j].id] += qry(q[j].y); qq[k] = q[j++]; } } for (int k = l; k <= r; ++k) { q[k] = qq[k]; if (used[k] == 1) { if (q[k].opt == 2) upd(q[k].y, -1); else if (q[k].opt == 3) upd(q[k].y, 1); used[k] = 0; } } } int main() { read(n), read(m); for (int i = 1; i <= n; ++i) read(a[i]), pa[a[i]] = i; for (int i = 1; i <= n; ++i) read(b[i]), pb[b[i]] = i; for (int i = 1; i <= n; ++i) ++tot, q[tot] = (ASK){2, pa[i], pb[i]}; for (int i = 1; i <= m; ++i) { ++tot, read(q[tot].opt); if (q[tot].opt == 1) { int l1, r1, l2, r2; read(l1), read(r1), read(l2), read(r2); tag[tot--] = 1; ++tot, q[tot] = (ASK){1, r1, r2, tot}; ++tot, q[tot] = (ASK){1, l1 - 1, r2, tot}; ++tot, q[tot] = (ASK){1, r1, l2 - 1, tot}; ++tot, q[tot] = (ASK){1, l1 - 1, l2 - 1, tot}; } else { int x, y; read(x), read(y); --tot; ++tot, q[tot] = (ASK){3, pa[b[x]], x, 0}; ++tot, q[tot] = (ASK){3, pa[b[y]], y, 0}; ++tot, q[tot] = (ASK){2, pa[b[x]], y, 0}; ++tot, q[tot] = (ASK){2, pa[b[y]], x, 0}; std::swap(b[x], b[y]), std::swap(pb[b[x]], pb[b[y]]); } } cdq(1, tot); for (int i = 1; i <= tot; ++i) if (tag[i] == 1) printf( %d n , ans[i] - ans[i + 1] - ans[i + 2] + ans[i + 3]); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, i; long long a, b; cin >> n; i = a = 0, b = 1000000001; int arr[n]; while (i < n) { cin >> arr[i]; i++; } i = n - 1; while (i >= 0) { if (arr[i] < b) { a += arr[i]; b = arr[i]; if (b == 1) break; } else if (arr[i] >= b) { b--; a += b; if (b == 1) break; } i--; } cout << a << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; int sum = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; } int res = 0; for (int i = 0; i < n; i++) { if ((sum - arr[i]) % 2 == 0) res++; } cout << res << endl; return 0; }
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/*******************************************************
* File Name : hdl/ks26.v
* Module Name : Karatsuba Multiplier
* Author : Chester Rebeiro
* Institute : Indian Institute of Technology, Madras
* Creation Time :
* Comment : Automatically generated from ks.c
********************************************************/
//`include "ks13.v"
module Sks26(a, b, d);
input wire [25:0] a;
input wire [25:0] b;
output wire [50:0] d;
wire [24:0] m1;
wire [24:0] m2;
wire [24:0] m3;
wire [12:0] ahl;
wire [12:0] bhl;
Sks13 ksm1(a[12:0], b[12:0], m2);
Sks13 ksm2(a[25:13], b[25:13], m1);
assign ahl[12:0] = a[25:13] ^ a[12:0];
assign bhl[12:0] = b[25:13] ^ b[12:0];
Sks13 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04];
assign d[05] = m2[05];
assign d[06] = m2[06];
assign d[07] = m2[07];
assign d[08] = m2[08];
assign d[09] = m2[09];
assign d[10] = m2[10];
assign d[11] = m2[11];
assign d[12] = m2[12];
assign d[13] = m2[13] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[14] = m2[14] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[15] = m2[15] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[16] = m2[16] ^ m1[03] ^ m2[03] ^ m3[03];
assign d[17] = m2[17] ^ m1[04] ^ m2[04] ^ m3[04];
assign d[18] = m2[18] ^ m1[05] ^ m2[05] ^ m3[05];
assign d[19] = m2[19] ^ m1[06] ^ m2[06] ^ m3[06];
assign d[20] = m2[20] ^ m1[07] ^ m2[07] ^ m3[07];
assign d[21] = m2[21] ^ m1[08] ^ m2[08] ^ m3[08];
assign d[22] = m2[22] ^ m1[09] ^ m2[09] ^ m3[09];
assign d[23] = m2[23] ^ m1[10] ^ m2[10] ^ m3[10];
assign d[24] = m2[24] ^ m1[11] ^ m2[11] ^ m3[11];
assign d[25] = m1[12] ^ m2[12] ^ m3[12];
assign d[26] = m1[13] ^ m2[13] ^ m3[13] ^ m1[00];
assign d[27] = m1[14] ^ m2[14] ^ m3[14] ^ m1[01];
assign d[28] = m1[15] ^ m2[15] ^ m3[15] ^ m1[02];
assign d[29] = m1[16] ^ m2[16] ^ m3[16] ^ m1[03];
assign d[30] = m1[17] ^ m2[17] ^ m3[17] ^ m1[04];
assign d[31] = m1[18] ^ m2[18] ^ m3[18] ^ m1[05];
assign d[32] = m1[19] ^ m2[19] ^ m3[19] ^ m1[06];
assign d[33] = m1[20] ^ m2[20] ^ m3[20] ^ m1[07];
assign d[34] = m1[21] ^ m2[21] ^ m3[21] ^ m1[08];
assign d[35] = m1[22] ^ m2[22] ^ m3[22] ^ m1[09];
assign d[36] = m1[23] ^ m2[23] ^ m3[23] ^ m1[10];
assign d[37] = m1[24] ^ m2[24] ^ m3[24] ^ m1[11];
assign d[38] = m1[12];
assign d[39] = m1[13];
assign d[40] = m1[14];
assign d[41] = m1[15];
assign d[42] = m1[16];
assign d[43] = m1[17];
assign d[44] = m1[18];
assign d[45] = m1[19];
assign d[46] = m1[20];
assign d[47] = m1[21];
assign d[48] = m1[22];
assign d[49] = m1[23];
assign d[50] = m1[24];
endmodule
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#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } bool b[1000000 + 5]; int Q, last[1000000 + 5], s[1000000 / 5 + 5], num, p[1000000 * 2 + 5], inv[1000000 * 2 + 5], a[65], c[65], ans, f[8][8], sum[25]; inline int C(int n, int m) { return m > n || m < 0 ? 0 : 1LL * p[n] * inv[m] % 1000000007 * inv[n - m] % 1000000007; } inline int S(int n, int m) { return m ? C(n + m - 1, m - 1) : (n ? 0 : 1); } int main() { p[0] = p[1] = inv[0] = inv[1] = sum[0] = 1; for (int i = 2; i <= 1000000; ++i) { if (!b[i]) s[++num] = i, last[i] = i; for (int j = 1; s[j] * i <= 1000000; ++j) { b[s[j] * i] = 1; last[s[j] * i] = s[j]; if (i % s[j] == 0) break; } } for (int i = 2; i <= 1000000 * 2; ++i) p[i] = 1LL * p[i - 1] * i % 1000000007, inv[i] = 1LL * (1000000007 - 1000000007 / i) * inv[1000000007 % i] % 1000000007; for (int i = 2; i <= 1000000 * 2; ++i) inv[i] = 1LL * inv[i - 1] * inv[i] % 1000000007; for (Q = read(); Q--;) { int m = read(), n = read(); num = ans = 0; while (n > 1) { ++num; c[num] = 0; a[num] = last[n]; for (int t = last[n]; n % t == 0; n /= t) ++c[num]; } for (int i = 1; i <= 20; ++i) sum[i] = (sum[i - 1] + S(i, m)) % 1000000007; memset(f, 0, sizeof(f)); f[0][0] = 1; for (int i = 1; i <= num; ++i) for (int j = 0; j < i; ++j) { f[i][j] = (f[i][j] + 1LL * f[i - 1][j] * S(c[i], m)) % 1000000007; f[i][j + 1] = (f[i][j + 1] + 1LL * f[i - 1][j] * sum[c[i] - 1]) % 1000000007; } for (int i = 0; i <= num; ++i) ans = (ans + 1LL * (1 << i) * f[num][i]) % 1000000007; printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; struct Point { int num; int next[3001]; int count; }; Point a[3001]; int dis[3001]; int p[3001]; int cir[3001]; int cir1[3001]; int f(int n) { int i, num = 0, d = 1; loop: while (1) { num = 0; for (i = 1; i <= n; i++) { if (a[i].num - a[i].count == 1) { a[i].count++; p[num++] = i; } } for (i = 0; i < num; i++) { for (int j = 0; j < a[p[i]].num; j++) a[a[p[i]].next[j]].count++; } for (i = 1; i <= n; i++) { if (a[i].num - a[i].count > 0 && a[i].num - a[i].count != 2) goto loop; } num = 0; for (i = 1; i <= n; i++) { if (a[i].num - a[i].count == 2) cir[num++] = i; } return num; } } int main() { int b[4], n, i, t, sum, num, flag; int from, to; cin >> n; for (i = 1; i <= n; i++) { cin >> from >> to; a[from].next[a[from].num++] = to; a[to].next[a[to].num++] = from; } int step = 0; sum = num = f(n); memset(dis, 0xff, sizeof(dis)); for (i = 0; i < num; i++) dis[cir[i]] = step; while (sum < n) { int k = 0; step++; flag = 0; for (i = 0; i < num; i++) { for (int j = 0; j < a[cir[i]].num; j++) { int next = a[cir[i]].next[j]; if (dis[next] == -1) { sum++; flag = 1; dis[next] = step; cir1[k++] = next; continue; } } if (!flag) cir[i] = -1; } memcpy(cir, cir1, k * sizeof(cir1[0])); num = k; } for (i = 1; i <= n; i++) if (i != n) cout << dis[i] << ; else cout << dis[i] << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long> v[200010]; vector<long long> traversal; long long cnt; long long color[200010]; long long start[200010]; long long enddd[200010]; void dfs(long long curr) { start[curr] = cnt; traversal.push_back(curr); cnt++; for (int i = 0; i < v[curr].size(); i++) { dfs(v[curr][i]); } enddd[curr] = cnt; } long long tree[800010]; long long lazy[800010]; void build_tree(int node, int a, int b) { if (a > b) return; if (a == b) { tree[node] = color[traversal[a]]; return; } build_tree(node * 2, a, (a + b) / 2); build_tree(node * 2 + 1, 1 + (a + b) / 2, b); tree[node] = tree[node * 2] + tree[node * 2 + 1]; } void update_tree(int node, int a, int b, int i, int j, int value) { if (lazy[node] != 0) { tree[node] = (b - a + 1 - tree[node]); if (a != b) { lazy[node * 2] += lazy[node]; lazy[node * 2 + 1] += lazy[node]; lazy[node * 2] %= 2; lazy[node * 2 + 1] %= 2; } lazy[node] = 0; } if (a > b || a > j || b < i) return; if (a >= i && b <= j) { tree[node] = (b - a + 1 - tree[node]); if (a != b) { lazy[node * 2] += value; lazy[node * 2 + 1] += value; lazy[node * 2] %= 2; lazy[node * 2 + 1] %= 2; } return; } update_tree(node * 2, a, (a + b) / 2, i, j, value); update_tree(1 + node * 2, 1 + (a + b) / 2, b, i, j, value); tree[node] = tree[node * 2] + tree[node * 2 + 1]; } int query_tree(int node, int a, int b, int i, int j) { if (a > b || a > j || b < i) return 0; if (lazy[node] != 0) { tree[node] = (b - a + 1 - tree[node]); if (a != b) { lazy[node * 2] += lazy[node]; lazy[node * 2 + 1] += lazy[node]; lazy[node * 2] %= 2; lazy[node * 2 + 1] %= 2; } lazy[node] = 0; } if (a >= i && b <= j) return tree[node]; int q1 = query_tree(node * 2, a, (a + b) / 2, i, j); int q2 = query_tree(1 + node * 2, 1 + (a + b) / 2, b, i, j); int res = q1 + q2; return res; } char str[4]; int main() { long long n, temp; cin >> n; cnt = 0; for (int i = 2; i <= n; i++) { cin >> temp; v[temp].push_back(i); } for (int i = 1; i <= n; i++) { cin >> color[i]; } dfs(1); build_tree(1, 0, cnt - 1); long long q; cin >> q; long long vertex; while (q--) { scanf( %s , str); cin >> vertex; if (str[0] == p ) { update_tree(1, 0, cnt - 1, start[vertex], enddd[vertex] - 1, 1); } else { cout << query_tree(1, 0, cnt - 1, start[vertex], enddd[vertex] - 1) << endl; } } }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; using vi = vector<int>; using vll = vector<long long>; using vii = vector<pair<int, int>>; const int N = 105; int matrix[N][N]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &matrix[i][j]); int score = 0, replace = 0; for (int j = 0; j < m; j++) { int best = 0, chop = 0, one = 0; for (int i = 0; i < n; i++) { if (matrix[i][j] == 0) continue; int tmp = 0; for (int x = 0; x < k && i + x < n; x++) tmp += matrix[i + x][j]; if (tmp > best) { best = tmp; chop = one; } ++one; } score += best; replace += chop; } printf( %d %d n , score, replace); }
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// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Tue Jun 21 04:38:22 2016
// Host : jalapeno running 64-bit unknown
// Command : write_verilog -force -mode synth_stub {/home/hhassan/git/GateKeeper/FPGA
// Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/pcie3_7x_0_stub.v}
// Design : pcie3_7x_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "pcie3_7x_0_pcie_3_0_7vx,Vivado 2015.4" *)
module pcie3_7x_0(pci_exp_txn, pci_exp_txp, pci_exp_rxn, pci_exp_rxp, user_clk, user_reset, user_lnk_up, user_app_rdy, s_axis_rq_tlast, s_axis_rq_tdata, s_axis_rq_tuser, s_axis_rq_tkeep, s_axis_rq_tready, s_axis_rq_tvalid, m_axis_rc_tdata, m_axis_rc_tuser, m_axis_rc_tlast, m_axis_rc_tkeep, m_axis_rc_tvalid, m_axis_rc_tready, m_axis_cq_tdata, m_axis_cq_tuser, m_axis_cq_tlast, m_axis_cq_tkeep, m_axis_cq_tvalid, m_axis_cq_tready, s_axis_cc_tdata, s_axis_cc_tuser, s_axis_cc_tlast, s_axis_cc_tkeep, s_axis_cc_tvalid, s_axis_cc_tready, pcie_rq_seq_num, pcie_rq_seq_num_vld, pcie_rq_tag, pcie_rq_tag_vld, pcie_cq_np_req, pcie_cq_np_req_count, cfg_phy_link_down, cfg_phy_link_status, cfg_negotiated_width, cfg_current_speed, cfg_max_payload, cfg_max_read_req, cfg_function_status, cfg_function_power_state, cfg_vf_status, cfg_vf_power_state, cfg_link_power_state, cfg_err_cor_out, cfg_err_nonfatal_out, cfg_err_fatal_out, cfg_ltr_enable, cfg_ltssm_state, cfg_rcb_status, cfg_dpa_substate_change, cfg_obff_enable, cfg_pl_status_change, cfg_tph_requester_enable, cfg_tph_st_mode, cfg_vf_tph_requester_enable, cfg_vf_tph_st_mode, cfg_fc_ph, cfg_fc_pd, cfg_fc_nph, cfg_fc_npd, cfg_fc_cplh, cfg_fc_cpld, cfg_fc_sel, cfg_interrupt_int, cfg_interrupt_pending, cfg_interrupt_sent, cfg_interrupt_msi_enable, cfg_interrupt_msi_vf_enable, cfg_interrupt_msi_mmenable, cfg_interrupt_msi_mask_update, cfg_interrupt_msi_data, cfg_interrupt_msi_select, cfg_interrupt_msi_int, cfg_interrupt_msi_pending_status, cfg_interrupt_msi_sent, cfg_interrupt_msi_fail, cfg_interrupt_msi_attr, cfg_interrupt_msi_tph_present, cfg_interrupt_msi_tph_type, cfg_interrupt_msi_tph_st_tag, cfg_interrupt_msi_function_number, sys_clk, sys_reset)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txn[3:0],pci_exp_txp[3:0],pci_exp_rxn[3:0],pci_exp_rxp[3:0],user_clk,user_reset,user_lnk_up,user_app_rdy,s_axis_rq_tlast,s_axis_rq_tdata[127:0],s_axis_rq_tuser[59:0],s_axis_rq_tkeep[3:0],s_axis_rq_tready[3:0],s_axis_rq_tvalid,m_axis_rc_tdata[127:0],m_axis_rc_tuser[74:0],m_axis_rc_tlast,m_axis_rc_tkeep[3:0],m_axis_rc_tvalid,m_axis_rc_tready,m_axis_cq_tdata[127:0],m_axis_cq_tuser[84:0],m_axis_cq_tlast,m_axis_cq_tkeep[3:0],m_axis_cq_tvalid,m_axis_cq_tready,s_axis_cc_tdata[127:0],s_axis_cc_tuser[32:0],s_axis_cc_tlast,s_axis_cc_tkeep[3:0],s_axis_cc_tvalid,s_axis_cc_tready[3:0],pcie_rq_seq_num[3:0],pcie_rq_seq_num_vld,pcie_rq_tag[5:0],pcie_rq_tag_vld,pcie_cq_np_req,pcie_cq_np_req_count[5:0],cfg_phy_link_down,cfg_phy_link_status[1:0],cfg_negotiated_width[3:0],cfg_current_speed[2:0],cfg_max_payload[2:0],cfg_max_read_req[2:0],cfg_function_status[7:0],cfg_function_power_state[5:0],cfg_vf_status[11:0],cfg_vf_power_state[17:0],cfg_link_power_state[1:0],cfg_err_cor_out,cfg_err_nonfatal_out,cfg_err_fatal_out,cfg_ltr_enable,cfg_ltssm_state[5:0],cfg_rcb_status[1:0],cfg_dpa_substate_change[1:0],cfg_obff_enable[1:0],cfg_pl_status_change,cfg_tph_requester_enable[1:0],cfg_tph_st_mode[5:0],cfg_vf_tph_requester_enable[5:0],cfg_vf_tph_st_mode[17:0],cfg_fc_ph[7:0],cfg_fc_pd[11:0],cfg_fc_nph[7:0],cfg_fc_npd[11:0],cfg_fc_cplh[7:0],cfg_fc_cpld[11:0],cfg_fc_sel[2:0],cfg_interrupt_int[3:0],cfg_interrupt_pending[1:0],cfg_interrupt_sent,cfg_interrupt_msi_enable[1:0],cfg_interrupt_msi_vf_enable[5:0],cfg_interrupt_msi_mmenable[5:0],cfg_interrupt_msi_mask_update,cfg_interrupt_msi_data[31:0],cfg_interrupt_msi_select[3:0],cfg_interrupt_msi_int[31:0],cfg_interrupt_msi_pending_status[63:0],cfg_interrupt_msi_sent,cfg_interrupt_msi_fail,cfg_interrupt_msi_attr[2:0],cfg_interrupt_msi_tph_present,cfg_interrupt_msi_tph_type[1:0],cfg_interrupt_msi_tph_st_tag[8:0],cfg_interrupt_msi_function_number[2:0],sys_clk,sys_reset" */;
output [3:0]pci_exp_txn;
output [3:0]pci_exp_txp;
input [3:0]pci_exp_rxn;
input [3:0]pci_exp_rxp;
output user_clk;
output user_reset;
output user_lnk_up;
output user_app_rdy;
input s_axis_rq_tlast;
input [127:0]s_axis_rq_tdata;
input [59:0]s_axis_rq_tuser;
input [3:0]s_axis_rq_tkeep;
output [3:0]s_axis_rq_tready;
input s_axis_rq_tvalid;
output [127:0]m_axis_rc_tdata;
output [74:0]m_axis_rc_tuser;
output m_axis_rc_tlast;
output [3:0]m_axis_rc_tkeep;
output m_axis_rc_tvalid;
input m_axis_rc_tready;
output [127:0]m_axis_cq_tdata;
output [84:0]m_axis_cq_tuser;
output m_axis_cq_tlast;
output [3:0]m_axis_cq_tkeep;
output m_axis_cq_tvalid;
input m_axis_cq_tready;
input [127:0]s_axis_cc_tdata;
input [32:0]s_axis_cc_tuser;
input s_axis_cc_tlast;
input [3:0]s_axis_cc_tkeep;
input s_axis_cc_tvalid;
output [3:0]s_axis_cc_tready;
output [3:0]pcie_rq_seq_num;
output pcie_rq_seq_num_vld;
output [5:0]pcie_rq_tag;
output pcie_rq_tag_vld;
input pcie_cq_np_req;
output [5:0]pcie_cq_np_req_count;
output cfg_phy_link_down;
output [1:0]cfg_phy_link_status;
output [3:0]cfg_negotiated_width;
output [2:0]cfg_current_speed;
output [2:0]cfg_max_payload;
output [2:0]cfg_max_read_req;
output [7:0]cfg_function_status;
output [5:0]cfg_function_power_state;
output [11:0]cfg_vf_status;
output [17:0]cfg_vf_power_state;
output [1:0]cfg_link_power_state;
output cfg_err_cor_out;
output cfg_err_nonfatal_out;
output cfg_err_fatal_out;
output cfg_ltr_enable;
output [5:0]cfg_ltssm_state;
output [1:0]cfg_rcb_status;
output [1:0]cfg_dpa_substate_change;
output [1:0]cfg_obff_enable;
output cfg_pl_status_change;
output [1:0]cfg_tph_requester_enable;
output [5:0]cfg_tph_st_mode;
output [5:0]cfg_vf_tph_requester_enable;
output [17:0]cfg_vf_tph_st_mode;
output [7:0]cfg_fc_ph;
output [11:0]cfg_fc_pd;
output [7:0]cfg_fc_nph;
output [11:0]cfg_fc_npd;
output [7:0]cfg_fc_cplh;
output [11:0]cfg_fc_cpld;
input [2:0]cfg_fc_sel;
input [3:0]cfg_interrupt_int;
input [1:0]cfg_interrupt_pending;
output cfg_interrupt_sent;
output [1:0]cfg_interrupt_msi_enable;
output [5:0]cfg_interrupt_msi_vf_enable;
output [5:0]cfg_interrupt_msi_mmenable;
output cfg_interrupt_msi_mask_update;
output [31:0]cfg_interrupt_msi_data;
input [3:0]cfg_interrupt_msi_select;
input [31:0]cfg_interrupt_msi_int;
input [63:0]cfg_interrupt_msi_pending_status;
output cfg_interrupt_msi_sent;
output cfg_interrupt_msi_fail;
input [2:0]cfg_interrupt_msi_attr;
input cfg_interrupt_msi_tph_present;
input [1:0]cfg_interrupt_msi_tph_type;
input [8:0]cfg_interrupt_msi_tph_st_tag;
input [2:0]cfg_interrupt_msi_function_number;
input sys_clk;
input sys_reset;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int max_n = 1011, inf = 1000111222; int n, a[max_n][max_n], x[max_n]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { scanf( %d , &a[i][j]); } } long long val = 1LL * a[0][1] * a[0][2] / a[1][2]; x[0] = sqrtl(val); while (1LL * x[0] * x[0] < val) { ++x[0]; } printf( %d , x[0]); for (int i = 1; i < n; ++i) { printf( %d , a[0][i] / x[0]); } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[200010]; struct seg { int val, idx; } tree1[600010], tree2[600010]; void build(int node, int s, int e) { if (s > e) return; if (s == e) { tree1[node].val = a[s]; tree1[node].idx = s; tree2[node].val = a[s]; tree2[node].idx = s; return; } int mid = (s + e) / 2; build(2 * node, s, mid); build(2 * node + 1, mid + 1, e); if (tree1[2 * node].val > tree1[2 * node + 1].val) tree1[node].idx = tree1[2 * node + 1].idx; else tree1[node].idx = tree1[2 * node].idx; if (tree2[2 * node].val > tree2[2 * node + 1].val) tree2[node].idx = tree2[2 * node].idx; else tree2[node].idx = tree2[2 * node + 1].idx; tree1[node].val = min(tree1[2 * node].val, tree1[2 * node + 1].val); tree2[node].val = max(tree2[2 * node].val, tree2[2 * node + 1].val); } seg query1(int node, int s, int end, int l, int r) { if (s > end || s > r || end < l) { seg temp; temp.val = 1000000000; temp.idx = -1; return temp; } if (s >= l && end <= r) return tree1[node]; seg res1 = query1(2 * node, s, (s + end) / 2, l, r); seg res2 = query1(2 * node + 1, (s + end) / 2 + 1, end, l, r); seg res; if (res1.val < res2.val) { res.val = res1.val; res.idx = res1.idx; } else { res.val = res2.val; res.idx = res2.idx; } return res; } seg query2(int node, int s, int end, int l, int r) { if (s > end || s > r || end < l) { seg temp; temp.val = -1000000000; temp.idx = -1; return temp; } if (s >= l && end <= r) return tree2[node]; seg res1 = query2(2 * node, s, (s + end) / 2, l, r); seg res2 = query2(2 * node + 1, (s + end) / 2 + 1, end, l, r); seg res; if (res1.val > res2.val) { res.val = res1.val; res.idx = res1.idx; } else { res.val = res2.val; res.idx = res2.idx; } return res; } int main() { int n; cin >> n; int q; cin >> q; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } build(1, 0, n - 1); while (q--) { int l, r, x; scanf( %d %d %d , &l, &r, &x); l--; r--; seg mx = query1(1, 0, n - 1, l, r); seg mi = query2(1, 0, n - 1, l, r); if (mx.val == x && mi.val == x) { printf( -1 n ); } else if (mx.val == x) { printf( %d n , mi.idx + 1); } else printf( %d n , mx.idx + 1); } return 0; }
|
#include <bits/stdc++.h> int main() { int n; long long x; scanf( %d , &n); x = (n - 2); x = x * x; printf( %I64d , x); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:14:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: TF_EECS301_Lab4_TopLevel
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: EECS301 Lab 4 Top Level Test Bench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_EECS301_Lab4_TopLevel();
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * .0) / 2.0; // ns
reg CLOCK_50;
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
//
// Unit Under Test: CLS_LED_Output_Fader
//
wire [9:0] LEDR;
wire [6:0] HEX0;
wire [6:0] HEX1;
wire [6:0] HEX2;
wire [6:0] HEX3;
wire [6:0] HEX4;
wire [6:0] HEX5;
reg [3:0] KEY;
reg [9:0] SW;
EECS301_Lab4_TopLevel
#(
.KEY_LOCK_DELAY( 10000 ), // 10 us
.SW_DEBOUNCE_TIME( 100 ) // 100 nS
)
uut
(
// Clock Signals
.CLOCK_50( CLOCK_50 ),
// LED Signals
.LEDR( LEDR ),
// 7-Segment Display Signals (Active-Low)
.HEX0( HEX0 ),
.HEX1( HEX1 ),
.HEX2( HEX2 ),
.HEX3( HEX3 ),
.HEX4( HEX4 ),
.HEX5( HEX5 ),
// Button Signals (Active-Low)
.KEY( KEY ),
// Switch Signals
.SW( SW )
);
//
// Test Stimulus
//
initial
begin
// Initialize Signals
KEY = 4'hF; // Active-Low
SW = 10'h000;
#1000;
//
// Begin Testing
//
// Set input test value
SW = 10'h021;
#1000; // Wait 1uS for debounce
// Press Add Key
KEY[0] = 1'b0;
#1000; // Press for 1uS
KEY[0] = 1'b1;
#10000; // Wait 10 uS
// Press Sub Key
KEY[1] = 1'b0;
#1000; // Press for 1uS
KEY[1] = 1'b1;
#10000; // Wait 10 uS
// Press Sub Key
KEY[1] = 1'b0;
#1000; // Press for 1uS
KEY[1] = 1'b1;
#10000; // Wait 10 uS
SW = 10'h321;
#1000; // Wait 1uS for debounce
// Press Add Key
KEY[0] = 1'b0;
#1000; // Press for 1uS
KEY[0] = 1'b1;
#10000; // Wait 10 uS
// Press Clr Key
KEY[3] = 1'b0;
#1000; // Press for 1uS
KEY[3] = 1'b1;
#10000; // Wait 10 uS
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long int> facts; vector<long long int> inv_facts; long long int c(long long int n, long long int p) { if (p < 0 || n < p) return 0; return (facts[n] * inv_facts[p]) % 1000000007 * inv_facts[n - p] % 1000000007; } long long int pow_mod(long long int x, long long int n) { if (n == 0) return 1; if (n & 1) return x * pow_mod(x, n - 1) % 1000000007; long long int tmp = pow_mod(x, n / 2); return tmp * tmp % 1000000007; } int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); long long int X, Y, N; cin >> X >> Y >> N; facts.push_back(1); inv_facts.push_back(1); long long int maxF = X + Y + 1; for (long long int n = 1; n <= maxF; ++n) { long long int f = facts[n - 1] * n % 1000000007; facts.push_back(f); inv_facts.push_back(pow_mod(f, 1000000007 - 2)); } vector<pair<long long int, long long int> > xys; for (long long int n = 0; n < N; ++n) { long long int x, y; cin >> x >> y; xys.push_back(make_pair(x - 1, y - 1)); } xys.push_back(make_pair(X - 1, Y - 1)); sort(xys.begin(), xys.end()); vector<long long int> dp(N + 1); for (long long int n = 0; n <= N; ++n) { long long int x = xys[n].first, y = xys[n].second; long long int tmp = c(x + y, y); for (long long int m = 0; m < N; ++m) { long long int xm = xys[m].first, ym = xys[m].second; if (xm <= x && ym <= y) tmp = (tmp + 1000000007 - dp[m] * c(x - xm + y - ym, x - xm) % 1000000007) % 1000000007; } dp[n] = tmp; } cout << dp[N] << endl; return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: video_fifo.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module video_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
output [6:0] wrusedw;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire rdempty = sub_wire0;
wire [6:0] wrusedw = sub_wire1[6:0];
wire wrfull = sub_wire2;
wire [7:0] q = sub_wire3[7:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone II",
dcfifo_mixed_widths_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_mixed_widths_component.lpm_numwords = 128,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo",
dcfifo_mixed_widths_component.lpm_width = 32,
dcfifo_mixed_widths_component.lpm_widthu = 7,
dcfifo_mixed_widths_component.lpm_widthu_r = 9,
dcfifo_mixed_widths_component.lpm_width_r = 8,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "ON",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL video_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_fifo_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_fifo_wave*.jpg TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const long long int p = 1e9 + 7; const int N = 1e5 + 1; long long int fact[N]; long long int ncr[N]; long long int n_1cr[N]; void factorial() { fact[0] = fact[1] = 1; for (int i = 2; i < N; i++) { fact[i] = i * fact[i - 1]; fact[i] %= p; } } long long int fastPower(long long int a, long long int b) { if (b == 0) return 1; long long int tmp = fastPower(a, b / 2); if (b & 1) return (tmp % p * tmp % p * a % p) % p; return (tmp % p * tmp % p) % p; } long long int nCr(int n) { ncr[0] = 1; n_1cr[0] = 1; for (int i = 1; i <= n; i++) { long long int iPower = fastPower(i, p - 2); ncr[i] = (ncr[i - 1] * (n - i + 1)) % p; ncr[i] *= iPower; ncr[i] %= p; n_1cr[i] = (n_1cr[i - 1] % p * (n - i) % p) % p; n_1cr[i] *= iPower; n_1cr[i] %= p; } } long long int nCr(int n, int r) { long long ans = 1; ans = (fact[n - r] * fact[r]) % p; ans = (fact[n] * fastPower(ans, p - 2)) % p; return ans; } int main() { int n; long long int sum = 0; cin >> n; factorial(); for (int i = 1; i <= n; i++) { sum += nCr(n - 1, i - 1) * nCr(n, i); sum %= p; } sum *= 2; sum %= p; sum -= n; cout << sum << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dp[1000006][2]; long long pre[1000006][2]; void chkMinLog(long long& goal, long long t1, bool t2, bool curr) { if (dp[t1][t2] > goal) { dp[t1][t2] = goal; pre[t1][t2] = curr; } } void solve() { long long n; cin >> n; vector<long long> a(n + 2); for (long long i = (1); i <= (n); i++) cin >> a[i]; for (long long i = (1); i <= (n); i++) for (long long j = (0); j <= (1); j++) dp[i][j] = 1e18; a[0] = n + 1; dp[0][0] = dp[0][1] = -n - 1; for (long long i = (0); i <= (n - 1); i++) for (long long isPos = (0); isPos <= (1); isPos++) { long long sv = (isPos ? 1 : -1) * a[i], v = dp[i][isPos]; if (-a[i + 1] > v) chkMinLog(sv, i + 1, false, isPos); if (a[i + 1] > v) chkMinLog(sv, i + 1, true, isPos); if (-a[i + 1] > sv) chkMinLog(v, i + 1, false, isPos); if (a[i + 1] > sv) chkMinLog(v, i + 1, true, isPos); } if (dp[n][0] <= n || dp[n][1] <= n) { cout << YES << endl; long long ti = n, ts = 0; if (dp[n][1] <= n) ts = 1; while (ti >= 1) { if (ts == 0) a[ti] = -a[ti]; ts = pre[ti][ts], ti--; } for (long long i = (1); i <= (n); i++) cout << a[i] << ; cout << endl; } else { cout << NO << endl; } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long T = 1; cin >> T; while (T--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; bool mark = false; int main() { cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == 0 && mark == false) { mark = true; continue; } if (mark == false && i == s.size() - 1) return 0; cout << s[i]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 7; const int sz = 10; map<int, int> mp[11]; int n, k; unsigned long long a[maxn], ans; unsigned long long fac[13]; int main() { fac[0] = 1; for (int i = 1; i <= 10; i++) fac[i] = 10LL * fac[i - 1]; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %llu , &a[i]); for (int j = 1; j <= 10; j++) { int now = (a[i] * fac[j]) % k; mp[j][now]++; } } for (int i = 1; i <= n; i++) { int len = 0; unsigned long long now = a[i]; while (now) { now /= 10; len++; } int res = a[i] % k; int p = 0; if (res == 0) { int need = 0; if ((a[i] * fac[len]) % k == need) { ans += mp[len][need] - 1; } else { ans += mp[len][need]; } } else { int need = k - res; if ((a[i] * fac[len]) % k == need) { ans += mp[len][need] - 1; } else { ans += mp[len][need]; } } } printf( %lld n , ans); }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Run-Length encoder ////
//// ////
//// 1) Retreive zig-zag-ed samples (starting with DC coeff.) ////
//// 2) Translate DC-coeff. into 11bit-size and amplitude ////
//// 3) Translate AC-coeff. into zero-runs, size and amplitude ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_rle.v,v 1.4 2002/10/31 12:53:39 rherveille Exp $
//
// $Date: 2002/10/31 12:53:39 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_rle.v,v $
// Revision 1.4 2002/10/31 12:53:39 rherveille
// *** empty log message ***
//
// Revision 1.3 2002/10/23 18:58:54 rherveille
// Fixed a bug in the zero-run (run-length-coder)
//
// Revision 1.2 2002/10/23 09:07:04 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_rle(clk, rst, ena, dstrb, din, size, rlen, amp, douten, bstart);
//
// parameters
//
//
// inputs & outputs
//
input clk; // system clock
input rst; // asynchronous reset
input ena; // clock enable
input dstrb;
input [11:0] din; // data input
output [ 3:0] size; // size
output [ 3:0] rlen; // run-length
output [11:0] amp; // amplitude
output douten; // data output enable
output bstart; // block start
//
// variables
//
wire [ 3:0] rle_rlen, rz1_rlen, rz2_rlen, rz3_rlen, rz4_rlen;
wire [ 3:0] rle_size, rz1_size, rz2_size, rz3_size, rz4_size;
wire [11:0] rle_amp, rz1_amp, rz2_amp, rz3_amp, rz4_amp;
wire rle_den, rz1_den, rz2_den, rz3_den, rz4_den;
wire rle_dc, rz1_dc, rz2_dc, rz3_dc, rz4_dc;
//
// module body
//
reg ddstrb;
always @(posedge clk)
ddstrb <= #1 dstrb;
// generate run-length encoded signals
jpeg_rle1 rle(
.clk(clk),
.rst(rst),
.ena(ena),
.go(ddstrb),
.din(din),
.rlen(rle_rlen),
.size(rle_size),
.amp(rle_amp),
.den(rle_den),
.dcterm(rle_dc)
);
// Find (15,0) (0,0) sequences and replace by (0,0)
// There can be max. 4 (15,0) sequences in a row
// step1
jpeg_rzs rz1(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rle_rlen),
.sizei(rle_size),
.ampi(rle_amp),
.deni(rle_den),
.dci(rle_dc),
.rleno(rz1_rlen),
.sizeo(rz1_size),
.ampo(rz1_amp),
.deno(rz1_den),
.dco(rz1_dc)
);
// step2
jpeg_rzs rz2(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz1_rlen),
.sizei(rz1_size),
.ampi(rz1_amp),
.deni(rz1_den),
.dci(rz1_dc),
.rleno(rz2_rlen),
.sizeo(rz2_size),
.ampo(rz2_amp),
.deno(rz2_den),
.dco(rz2_dc)
);
// step3
jpeg_rzs rz3(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz2_rlen),
.sizei(rz2_size),
.ampi(rz2_amp),
.deni(rz2_den),
.dci(rz2_dc),
.rleno(rz3_rlen),
.sizeo(rz3_size),
.ampo(rz3_amp),
.deno(rz3_den),
.dco(rz3_dc)
);
// step4
jpeg_rzs rz4(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz3_rlen),
.sizei(rz3_size),
.ampi(rz3_amp),
.deni(rz3_den),
.dci(rz3_dc),
.rleno(rz4_rlen),
.sizeo(rz4_size),
.ampo(rz4_amp),
.deno(rz4_den),
.dco(rz4_dc)
);
// assign outputs
assign rlen = rz4_rlen;
assign size = rz4_size;
assign amp = rz4_amp;
assign douten = rz4_den;
assign bstart = rz4_dc;
endmodule
|
#include <bits/stdc++.h> using namespace std; int t, n, freq[201][212345]; int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); vector<int> pos[201]; for (int i = 0; i < 201; ++i) for (int j = 0; j <= n; ++j) freq[i][j] = 0; for (int x, i = 1; i <= n; ++i) scanf( %d , &x), freq[x][i] = 1, pos[x].push_back(i); map<pair<int, int>, int> mp; for (int i = 1; i < 201; ++i) { int ctr = 0; for (int j = n; j > 0; --j) if (freq[i][j]) mp[{i, ++ctr}] = j; for (int j = 1; j <= n; ++j) freq[i][j] += freq[i][j - 1]; } int ans = 1; for (int i = 1; i < 201; ++i) for (int j = 1; j < 201; ++j) if (i == j) ans = max(ans, freq[i][n]); else if (freq[i][n] > 1) { for (int idx1, idx2, p = 0; p < pos[i].size(); ++p) { idx1 = pos[i][p]; idx2 = mp[{i, freq[i][idx1]}]; if (idx1 >= idx2) break; ans = max(ans, 2 * freq[i][idx1] + freq[j][idx2 - 1] - freq[j][idx1]); } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, sum1 = 0, res1 = 0, last = 0; bool flag = true; cin >> n; unordered_map<long long int, long long int> m; vector<pair<long long int, long long int>> v; for (long long int i = 0; i < n; i++) { long long int element; cin >> element; m[element]++; v.emplace_back(make_pair(element, i)); } if (n == 1) { cout << 1 << n ; cout << v[0].first << << 0 n ; return 0; } sort(v.begin(), v.end()); vector<pair<long long int, long long int>> v1; for (long long int i = 0; i < v.size() - 1; i++) { flag = true; if (i < v.size() - 1 && v[i].first == v[i + 1].first) sum1 = v[i + 1].second - v[i].second; else if (i < v.size() - 1) sum1 = 0; while (i < v.size() - 1 && v[i].first == v[i + 1].first) { res1 = v[i + 1].second - v[i].second; if (res1 != sum1) { flag = false; break; } i++; } if (flag == true) { v1.push_back(make_pair(v[i].first, sum1)); } while (i < v.size() - 1 && v[i].first == v[i + 1].first) { i++; } } if (v[v.size() - 1].first != v[v.size() - 2].first) { v1.emplace_back(make_pair(v[v.size() - 1].first, 0)); } cout << v1.size() << n ; for (long long int i = 0; i < v1.size(); i++) { cout << v1[i].first << << v1[i].second << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, mx = 2, j; cin >> n; int a[n]; for (i = 0; i < n; i++) cin >> a[i]; if (n == 1) cout << 1 ; else if (n == 2) cout << 2 ; else { for (i = 2; i < n;) { int x = 0; for (j = i; j < n; j++) { if ((a[j] != (a[j - 1] + a[j - 2]))) break; x++; } i = ++j; mx = max(x + 2, mx); } cout << mx; } return 0; }
|
module top
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
output wire dac_cs,
output wire amp_cs,
output wire ad_conv,
output wire sf_ce0,
output wire fpga_init_b,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg CS_GO = 0;
reg CS_GO_PREP = 0;
reg CS_STOP = 0;
reg CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg RAM_WE = 0;
assign dac_cs = 1;
assign amp_cs = 1;
assign ad_conv = 0;
assign sf_ce0 = 1;
assign fpga_init_b = 1;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1'b0),
.DIB(RAM_DI),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(1'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TDI(TDI),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1'b0)
);
`include "bscan_common.v"
endmodule
|
#include <bits/stdc++.h> using namespace std; long long m, loc, t; long long now; class SegTree { private: long long F2(long long k) { return 1 << (long long)ceil(log2(k)); } vector<long long> seg; void Merge(long long cur) { seg[cur] = seg[2 * cur] + seg[2 * cur + 1]; } public: SegTree(long long n) { m = F2(n); for (long long i = 0; i < 2 * m + 2; i++) seg.push_back(0); } void Add(long long loc, long long cur = 1, long long l = 1, long long r = m) { if (r < l || r < loc || loc < l) return; else if (l == r) return void(seg[cur]++); long long mid = (l + r) / 2; Add(loc, 2 * cur, l, mid); Add(loc, 2 * cur + 1, mid + 1, r); Merge(cur); } long long Get(long long a, long long b, long long cur = 1, long long l = 1, long long r = m) { if (r < l || r < a || b < l) return 0; else if (a <= l && r <= b) return seg[cur]; long long mid = (l + r) / 2; long long x = Get(a, b, 2 * cur, l, mid); long long y = Get(a, b, 2 * cur + 1, mid + 1, r); return x + y; } long long BinarySearch(long long a, long long l = 1, long long r = now) { if (r < l) return a; long long mid = (l + r) / 2; if (!Get(a + 1, mid)) return max(mid, BinarySearch(a, mid + 1, r)); return BinarySearch(a, l, mid - 1); } }; vector<pair<long long, long long>> v; int main() { long long q; cin >> q; while (q--) { long long n; cin >> n; now = n; loc = 0; long long a[n + 1]; v.clear(); SegTree s(n); for (long long i = 0; i < n; i++) { cin >> t; if (t < loc) s.Add(i + 1); loc = t; a[i + 1] = t; } loc = 2; long long ans = 1; long long last = 1, cur = 0; while (loc <= n) { if (last == 0) swap(last, cur), ans++; last--; long long now = s.BinarySearch(loc + 1); if (loc == n) now = loc; else if (a[loc + 1] < a[loc]) now = loc; cur += now - loc + 1; loc = now + 1; } cout << ans << endl; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 22 13:46:37 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_buffer_0_0 -prefix
// system_vga_buffer_0_0_ system_vga_buffer_0_0_stub.v
// Design : system_vga_buffer_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_0_0(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long getres(long long n) { if (n == 0) { return 0; } vector<long long> now; for (long long i = 0;; i++) { long long t = pow(2, i); if (t <= n) { n -= t; now.push_back(t); if (n == 0) { break; } } else { now.push_back(n); break; } } long long even = 0, odd = 0; for (long long i = 0; i < now.size(); i++) { if (i % 2) { even = (even + now[i]) % mod; } else { odd = (odd + now[i]) % mod; } } long long odd_sum = (((odd) % mod) * (odd % mod)) % mod; long long even_sum = (((even) % mod) * ((even + 1) % mod)) % mod; long long res = (odd_sum + even_sum) % mod; return res; } int main() { ios_base::sync_with_stdio(false); long long l, r; cin >> l >> r; long long ans = (getres(r) - getres(l - 1) + mod) % mod; cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1000000 + 5; const long long DIFF = 2000; const long long mod = 1000000000 + 7; long long dp[DIFF + 5][DIFF + 5]; char s[maxn]; int main() { dp[0][0] = 1; for (int i = 1; i <= DIFF; dp[i][0] = dp[i - 1][1], i++) for (int j = 1; j <= i; j++) dp[i][j] = (dp[i - 1][j - 1] + dp[i - 1][j + 1]) % mod; long long n, m; scanf( %I64d%I64d%s , &n, &m, s); long long len = strlen(s), diff = 0, Min = 0, ans = 0; for (long long i = 0; i < len; i++) { diff += (s[i] == ( ? 1 : -1); Min = min(Min, diff); } for (long long i = 0; i <= n - m; i++) for (long long j = 0; j <= i; j++) if (j + Min >= 0 && j + diff >= 0 && j + diff <= n - m) ans = (ans + (dp[i][j] * dp[n - m - i][j + diff]) % mod) % mod; printf( %I64d n , ans); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_BEHAVIORAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A2BB2O_PP_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2O_PP_BLACKBOX_V
|
module commutation(
clk,
enable_i,
reset_i,
advance_i,
direction_i,
break_i,
align_i,
state_o
);
input wire clk, enable_i, reset_i, advance_i, direction_i, break_i, align_i;
reg[2:0] state_number;
output wire[3:0] state_o;
reg[3:0] state_table[7:0];
always @(posedge clk) begin
if (reset_i) begin
state_number <= 0;
state_table[0] <= 4'b0110;
state_table[1] <= 4'b0100;
state_table[2] <= 4'b1100;
state_table[3] <= 4'b1000;
state_table[4] <= 4'b1010;
state_table[5] <= 4'b0010;
state_table[6] <= 4'b0000;
state_table[7] <= 4'b1110;
end else if(enable_i) begin
if(advance_i && direction_i) begin
if(state_number == 5) begin
state_number <= 0;
end else begin
state_number <= state_number + 1;
end
end else if (advance_i && !direction_i) begin
if(state_number == 0) begin
state_number <= 5;
end else begin
state_number <= state_number - 1;
end
end else begin
state_number <= state_number;
end
if(break_i) begin
state_number <= 6;
end
if(align_i) begin
state_number <= 7;
end
end
end
assign state_o = state_table[state_number];
endmodule
|
module io1_sub(
/*AUTOARG*/
// Outputs
sec_out, lower_out,
// Inouts
sec_io, lower_io,
// Inputs
sec_ina, lower_ina
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina; // To instio of instio.v
input sec_ina; // To instio of instio.v
// End of automatics
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout lower_io; // To/From instio of instio.v
inout sec_io; // To/From instio of instio.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out; // From instio of instio.v
output sec_out; // From instio of instio.v
// End of automatics
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
instio instio (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
.sec_out (sec_out),
// Inouts
.lower_io (lower_io),
.sec_io (sec_io),
// Inputs
.lower_ina (lower_ina),
.sec_ina (sec_ina));
endmodule
module instio (/*AUTOARG*/
// Outputs
lower_out, sec_out,
// Inouts
lower_io, sec_io,
// Inputs
lower_ina, sec_ina
);
input lower_ina;
inout lower_io;
output lower_out;
input sec_ina;
inout sec_io;
output sec_out;
wire lower_out = lower_ina | lower_io;
wire sec_out = sec_ina | sec_io;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<double, pair<int, int> > > s; int n, x; pair<double, pair<int, int> > tmp; signed main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (register int i = 1; (1 < n) ? (i <= n) : (i >= n); i += (1 < n) ? 1 : (-1)) { cin >> x; s.push_back(make_pair(x, make_pair(i, i))); while (s.size() > 1 && s[s.size() - 2] > s.back()) { tmp = s.back(); s.pop_back(); tmp = make_pair((tmp.first * (tmp.second.second - tmp.second.first + 1) + s.back().first * (s.back().second.second - s.back().second.first + 1)) / (tmp.second.second - s.back().second.first + 1), make_pair(s.back().second.first, tmp.second.second)); s.pop_back(); s.push_back(tmp); } } for (auto i : s) { for (register int j = 1; (1 < i.second.second - i.second.first + 1) ? (j <= i.second.second - i.second.first + 1) : (j >= i.second.second - i.second.first + 1); j += (1 < i.second.second - i.second.first + 1) ? 1 : (-1)) { printf( %.9lf n , i.first); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, i, j, k, l, p = 0, q, x, y, z; scanf( %lld %lld %lld %lld , &n, &m, &k, &l); x = l * 2; x = min(x, n); i = x / 2; for (; i >= 0; i--) { x = i * 2; x = n - x; x = min(x, k); for (j = x; j >= 0; j--) { y = (i * 2) + j; y = n - y; y *= 2; if (y <= m) p++; } } printf( %lld , p); }
|
#include <bits/stdc++.h> using namespace std; int putere(long long int a, long long int b) { if (b == 0) { return 1; } else { if (b == 1) return a % 1000000007; else { long long int r; r = putere(a, b / 2); r = (r * r) % 1000000007; if (b % 2 == 0) return r; else return (r * a) % 1000000007; } } } int main() { long long int x, k, nr1, nr2; scanf( %lld%lld , &x, &k); if (x == 0) printf( 0 ); else { x = x % 1000000007; nr1 = putere(2, k); nr2 = nr1 * x * 2 % 1000000007; printf( %lld , (nr2 - nr1 + 1 + 1000000007) % 1000000007); } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; struct Hash { const long long int mod = 1791791791; const long long int base = 255; vector<long long int> h, p; Hash(const string& s) { long long int n = s.size(); h.resize(n + 1); p.resize(n + 1, 1); for (long long int i = 1; i <= n; i++) { h[i] = (h[i - 1] * base + s[i - 1]) % mod; p[i] = (p[i - 1] * base) % mod; } } long long int getSub(long long int l, long long int r) { return (h[r] - (h[l - 1] * p[r - l + 1]) % mod + mod) % mod; } ~Hash(){}; }; void rev(string& s) { for (auto& i : s) { if (i == 0 ) i = 1 ; else i = 0 ; } } signed main() { string s, t; cin >> s >> t; long long int n = t.size(); Hash h(t); long long int cnt0 = 0, cnt1 = 0; for (auto i : s) { cnt0 += (i == 0 ); cnt1 += (i == 1 ); } if (cnt0 < cnt1) { swap(cnt0, cnt1); rev(s); } long long int ans = 0; for (long long int len0 = 1; len0 < t.size() / cnt0; len0++) { if (cnt1 == 0 || (n - len0 * cnt0) % cnt1 == 0) { long long int len1 = 0; if (cnt1 > 0) len1 = (n - len0 * cnt0) / cnt1; long long int last = 1; unordered_set<long long int> se0, se1; for (long long int j = 0; j < s.size(); j++) { if (s[j] == 0 ) { se0.insert(h.getSub(last, last + len0 - 1)); last += len0; } else { se1.insert(h.getSub(last, last + len1 - 1)); last += len1; } } if (se0.size() <= 1 && se1.size() <= 1) ans++; if (se0.size() == 1 && se1.size() == 1 && (*se1.begin()) == (*se0.begin())) ans--; } } cout << ans; return 0; }
|
`include "defines.v"
module RouteCompute(
input `control_w control_in,
input `addrx_w addrx,
input `addry_w addry,
input `addrx_w addrx_max,
input `addry_w addry_max,
output `rmatrix_w rmatrix);
// Break out control signals
wire valid;
wire `addrx_w destx;
wire `addry_w desty;
/*******************
* Control In Format
* [12] Valid
* [11:8] Seq
* [7:4] Source
* [3:0] Dest
*******************/
assign valid = control_in[`valid_f];
assign destx = control_in[`destx_f];
assign desty = control_in[`desty_f];
/***************
* rmatrix format
* |West|East|South|North|
* | 3 | 2 | 1 | 0 |
* A result of 0 indicates that we are at our destination
***************/
assign rmatrix =
valid ?
{destx < addrx, destx > addrx, desty > addry, desty < addry} :
5'b0000;
// always @(rmatrix)
// $display("routecompute: control %04x rmatrix %x", control_in, rmatrix);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 333; long long n, ans[N], a[N][N], pos[N]; long long absv(long long val) { if (val < 0) val *= -1; return val; } int main() { std::ios::sync_with_stdio(false); cin >> n; for (int i = 0; i <= n; i++) { for (int j = 0; j < n; j++) cin >> a[i][j]; } for (int i = 0; i < n; i++) pos[i] = N; for (int i = 0; i < n; i++) { long long num = i + 1, num2 = i + 1, jx = 0; for (int j = 0; j < n; j++) { if (a[n][j] <= num) { num = a[n][j]; jx = j; break; } } for (int j = jx + 1; j < n; j++) { if (a[n][j] <= num2) { num2 = a[n][j]; break; } } for (int j = 0; j < n; j++) { long long tmp = num; if (j + 1 == num) if (num != num2) num = num2; else continue; for (int k = 0; k < n; k++) { if (a[j][k] == num) if (k < pos[j]) { pos[j] = k; ans[j] = i + 1; } } num = tmp; } } for (int i = 0; i < n; i++) cout << ans[i] << ; }
|
`timescale 1 ns / 100 ps
module top
(
);
reg clk;
reg rst;
reg start_i ;
reg [31:0] ray_adr_i ;
reg [31:0] root_adr_i ;
reg [2:0] dir_mask_i ;
reg [31:0] tx0_i ;
reg [31:0] ty0_i ;
reg [31:0] tz0_i ;
reg [31:0] tx1_i ;
reg [31:0] ty1_i ;
reg [31:0] tz1_i ;
wire node_req_o ;
wire node_req_far_o ;
wire [31:0] node_req_adr_o ;
reg node_ack_i ;
reg [31:0] node_data_i ;
reg [31:0] node_adr_i ;
wire finished_o;
// = Core =
raycast_core dut
(
.clk (clk ),
.rst (rst ),
.start_i (start_i ),
.ray_adr_i (ray_adr_i ),
.root_adr_i (root_adr_i ),
.dir_mask_i (dir_mask_i ),
.tx0_i (tx0_i ),
.ty0_i (ty0_i ),
.tz0_i (tz0_i ),
.tx1_i (tx1_i ),
.ty1_i (ty1_i ),
.tz1_i (tz1_i ),
.node_req_o (node_req_o ),
.node_req_far_o (node_req_far_o),
.node_req_adr_o (node_req_adr_o),
.node_ack_i (node_ack_i ),
.node_data_i (node_data_i ),
.node_adr_i (node_adr_i ),
.finished_o (finished_o )
);
// -- Clock Gen --
always
#10 clk = ~clk;
// -- Timeout --
initial
begin
#10000 $display("Timeout!");
$finish;
end
// -- Simulation Program --
initial
begin
// -- Setup --
$display("-- Simulation --");
$dumpfile("bench_core_output.vcd");
$dumpvars;
clk = 0;
rst = 0;
#20 rst = 1;
#20 rst = 0;
#20;
// -- Program --
$finish;
end
endmodule
|
/*
* Copyright (c) 2000 Guy Hutchison ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
//`define DEBUG
`define BUG_FIX
module drive_strength;
// strength values (append 1/0 to each):
// supply -> strong -> pull -> weak -> highz
/*
* Strength Value Table
* 1--> supply | strong | pull | weak | highz
* supply x | 0 | 0 | 0 | 0
* strong 1 | x | 0 | 0 | 0
* pull 1 | 1 | x | 0 | 0
* weak 1 | 1 | 1 | x | 0
* highz 1 | 1 | 1 | 1 | z
*/
wire su1su0, su1st0, su1pu0, su1we0, su1hz0;
wire st1su0, st1st0, st1pu0, st1we0, st1hz0;
wire pu1su0, pu1st0, pu1pu0, pu1we0, pu1hz0;
wire we1su0, we1st0, we1pu0, we1we0, we1hz0;
wire hz1su0, hz1st0, hz1pu0, hz1we0, hz1hz0;
/* supply assignments */
assign (supply1, supply0) su1su0 = 1'b1;
assign (supply1, supply0) su1st0 = 1'b1;
assign (supply1, supply0) su1pu0 = 1'b1;
assign (supply1, supply0) su1we0 = 1'b1;
assign (supply1, supply0) su1hz0 = 1'b1;
/* strong assignments */
assign (strong1, strong0) st1su0 = 1'b1;
assign (strong1, strong0) st1st0 = 1'b1;
assign (strong1, strong0) st1pu0 = 1'b1;
assign (strong1, strong0) st1we0 = 1'b1;
assign (strong1, strong0) st1hz0 = 1'b1;
/* pull assignments */
assign (pull1, pull0) pu1su0 = 1'b1;
assign (pull1, pull0) pu1st0 = 1'b1;
assign (pull1, pull0) pu1pu0 = 1'b1;
assign (pull1, pull0) pu1we0 = 1'b1;
assign (pull1, pull0) pu1hz0 = 1'b1;
/* weak assignments */
assign (weak1, weak0) we1su0 = 1'b1;
assign (weak1, weak0) we1st0 = 1'b1;
assign (weak1, weak0) we1pu0 = 1'b1;
assign (weak1, weak0) we1we0 = 1'b1;
assign (weak1, weak0) we1hz0 = 1'b1;
/* highz assignments */
assign (highz1, strong0) hz1su0 = 1'b1;
assign (highz1, strong0) hz1st0 = 1'b1;
assign (highz1, strong0) hz1pu0 = 1'b1;
assign (highz1, strong0) hz1we0 = 1'b1;
assign (highz1, strong0) hz1hz0 = 1'b1;
/* supply assignments */
assign (supply1, supply0) su1su0 = 1'b0;
assign (supply1, supply0) st1su0 = 1'b0;
assign (supply1, supply0) pu1su0 = 1'b0;
assign (supply1, supply0) we1su0 = 1'b0;
assign (supply1, supply0) hz1su0 = 1'b0;
/* strong assignments */
assign (strong1, strong0) su1st0 = 1'b0;
assign (strong1, strong0) st1st0 = 1'b0;
assign (strong1, strong0) pu1st0 = 1'b0;
assign (strong1, strong0) we1st0 = 1'b0;
assign (strong1, strong0) hz1st0 = 1'b0;
/* pull assignments */
assign (pull1, pull0) su1pu0 = 1'b0;
assign (pull1, pull0) st1pu0 = 1'b0;
assign (pull1, pull0) pu1pu0 = 1'b0;
assign (pull1, pull0) we1pu0 = 1'b0;
assign (pull1, pull0) hz1pu0 = 1'b0;
/* weak assignments */
assign (weak1, weak0) su1we0 = 1'b0;
assign (weak1, weak0) st1we0 = 1'b0;
assign (weak1, weak0) pu1we0 = 1'b0;
assign (weak1, weak0) we1we0 = 1'b0;
assign (weak1, weak0) hz1we0 = 1'b0;
/* highz assignments */
assign (strong1, highz0) su1hz0 = 1'b0;
assign (strong1, highz0) st1hz0 = 1'b0;
assign (strong1, highz0) pu1hz0 = 1'b0;
assign (strong1, highz0) we1hz0 = 1'b0;
assign (strong1, highz0) hz1hz0 = 1'b0;
initial
begin
`ifdef DEBUG
$dumpfile ("verilog.dump");
$dumpvars (0, drive_strength);
`endif
/* check all values for 1/x/0 */
#1; // Give things a chance to evaluate!!!
if ((su1su0 !== 1'bx) ||
(su1st0 !== 1'b1) ||
(su1pu0 !== 1'b1) ||
(su1we0 !== 1'b1) ||
(su1hz0 !== 1'b1) ||
(st1su0 !== 1'b0) ||
(st1st0 !== 1'bx) ||
(st1pu0 !== 1'b1) ||
(st1we0 !== 1'b1) ||
(st1hz0 !== 1'b1) ||
(pu1su0 !== 1'b0) ||
(pu1st0 !== 1'b0) ||
(pu1pu0 !== 1'bx) ||
(pu1we0 !== 1'b1) ||
(pu1hz0 !== 1'b1) ||
(we1su0 !== 1'b0) ||
(we1st0 !== 1'b0) ||
(we1pu0 !== 1'b0) ||
(we1we0 !== 1'bx) ||
(we1hz0 !== 1'b1) ||
(hz1su0 !== 1'b0) ||
(hz1st0 !== 1'b0) ||
(hz1pu0 !== 1'b0) ||
(hz1we0 !== 1'b0) ||
(hz1hz0 !== 1'bz))
$display ("FAILED - drive_strength");
else
$display ("PASSED");
#10;
$finish;
end // initial begin
`ifdef BUG_FIX
reg bug_fix;
initial
begin
bug_fix = 0;
#2;
bug_fix = 1;
#2;
bug_fix = 0;
end
`endif // ifdef BUG_FIX
endmodule
|
#include <bits/stdc++.h> int main() { float d, l, v1, v2, y, z, p, q, i, j; scanf( %f %f %f %f , &d, &l, &v1, &v2); float x = (l - d) / (v1 + v2); printf( %f n , x); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int a[n + 2]; a[0] = 0; for (int i = 1; i < n; i++) { scanf( %d , &a[i]); } for (int i = 1; i < n; i++) { a[i] = a[i - 1] + a[i]; } int x, y; scanf( %d%d , &x, &y); printf( %d , a[y - 1] - a[x - 1]); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_8_V
`define SKY130_FD_SC_LP__NOR2_8_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_8_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const long long maxu = 200005; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long i, j, k = 0, n, t = 1, m, l = 0; cin >> t; while (t--) { cin >> n; long long a[n]; long long b[n + 2]; long long cnt = 0; long long idx = -1; for (i = 0; i < n; i++) { cin >> a[i]; if (a[i] != i + 1) { if (idx == -1) { idx = i; } b[i] = 0; cnt++; } else b[i] = 1; } if (cnt == 0) { cout << 0 << n ; continue; } if (cnt == n) { cout << 1 << n ; continue; } long long ans = 0; for (i = idx; i <= idx + cnt - 1; i++) { if (b[i] == 0) ans++; } if (ans == cnt) { cout << 1 << n ; } else cout << 2 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 1) { cout << 1 << endl; } else if (n % 2 == 0) { cout << n / 2 << endl; } else if (n % 2 != 0) { cout << n / 2 + 1 << endl; } return 0; }
|
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