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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:05:49 12/16/2016
// Design Name:
// Module Name: x7segbc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module x7segbc(
input wire clk,
input wire [31:0] x,
output reg [ 6:0] a_to_g,
output reg [ 7:0] an,
output wire dp
);
wire [ 2:0] s;
reg [ 4:0] digit;
wire [ 7:0] aen;
reg [19:0] clkdiv;
assign dp = 1;
assign s = clkdiv[19:17];
// Set aen[7:0] for leading blanks
assign aen[7] = x[31] | x[30] | x[29] | x[28];
assign aen[6] = x[31] | x[30] | x[29] | x[28] |
x[27] | x[26] | x[25] | x[24];
assign aen[5] = x[31] | x[30] | x[29] | x[28] |
x[27] | x[26] | x[25] | x[24] |
x[23] | x[22] | x[21] | x[20];
assign aen[4] = x[31] | x[30] | x[29] | x[28] |
x[27] | x[26] | x[25] | x[24] |
x[23] | x[22] | x[21] | x[20] |
x[19] | x[18] | x[17] | x[16];
assign aen[3] = x[31] | x[30] | x[29] | x[28] |
x[27] | x[26] | x[25] | x[24] |
x[23] | x[22] | x[21] | x[20] |
x[19] | x[18] | x[17] | x[16] |
x[15] | x[14] | x[13] | x[12];
assign aen[2] = x[31] | x[30] | x[29] | x[28] |
x[27] | x[26] | x[25] | x[24] |
x[23] | x[22] | x[21] | x[20] |
x[19] | x[18] | x[17] | x[16] |
x[15] | x[14] | x[13] | x[12] |
x[11] | x[10] | x[ 9] | x[ 8];
assign aen[1] = x[31] | x[30] | x[29] | x[28] |
x[27] | x[26] | x[25] | x[24] |
x[23] | x[22] | x[21] | x[20] |
x[19] | x[18] | x[17] | x[16] |
x[15] | x[14] | x[13] | x[12] |
x[11] | x[10] | x[ 9] | x[ 8] |
x[ 7] | x[ 6] | x[ 5] | x[ 4];
assign aen[0] = 1; // Digit 0 always on
// MUX 8 to 1
always @*
case (s)
0: digit = {1'b0, x[ 3: 0]};
1: digit = {1'b0, x[ 7: 4]};
2: digit = {1'b0, x[11: 8]};
3: digit = {1'b0, x[15:12]};
4: digit = 5'b1_0000;
5: digit = 5'b1_0001;
6: digit = 5'b1_0010;
7: digit = 5'b1_0011;
default: digit = {1'b0, x[ 3: 0]};
endcase
// hex7seg
always @*
case (digit)
0: a_to_g = 7'b1000000;
1: a_to_g = 7'b1111001;
2: a_to_g = 7'b0100100;
3: a_to_g = 7'b0110000;
4: a_to_g = 7'b0011001;
5: a_to_g = 7'b0010010;
6: a_to_g = 7'b0000010;
7: a_to_g = 7'b1111000;
8: a_to_g = 7'b0000000;
9: a_to_g = 7'b0010000;
'hA: a_to_g = 7'b0001000;
'hB: a_to_g = 7'b0000011;
'hC: a_to_g = 7'b1000110;
'hD: a_to_g = 7'b0100001;
'hE: a_to_g = 7'b0000110;
'hF: a_to_g = 7'b0001110;
// User defined character
'h10: a_to_g = 7'b0001011; // h
'h11: a_to_g = 7'b0010000; // g
'h12: a_to_g = 7'b1111001; // I
'h13: a_to_g = 7'b0001001; // H
endcase
// Digit select
always @*
begin
an = 8'b1111_1111;
if (aen[s] == 1)
an[s] = 0;
end
// Clock divider
always @ (posedge clk)
begin
clkdiv <= clkdiv + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; double arr[550]; int m; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> arr[i]; double ans = 0; for (int i = 1; i <= m; i++) { int u, v; double w; cin >> u >> v; cin >> w; double rr = (arr[u] + arr[v]) / w; if (rr > ans) ans = rr; } printf( %.9lf n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; set<int> s; int cnt[1009]; int vec[1009]; vector<int> ans; int main() { int a, b, c, d, e, i, j, k, l, n, m, x, y, t, p; scanf( %d , &t); for (p = 1; p <= t; p++) { scanf( %d , &n); s.clear(); ans.clear(); for (i = 0; i <= n; i++) { s.insert(i); cnt[i] = 0; } for (i = 1; i <= n; i++) { scanf( %d , &vec[i]); s.erase(vec[i]); cnt[vec[i]]++; } c = 0; for (i = 2; i <= n; i++) { if (vec[i] < vec[i - 1]) { c = 1; break; } } if (c) { while (c) { auto it = s.begin(); a = *it; i = a; if (i == 0) { i = 1; for (j = 2; j <= n; j++) { if (vec[j] < vec[j - 1]) { if (vec[j] != j) { i = j; } else { i = j - 1; } break; } } } s.erase(it); ans.push_back(i); cnt[a]++; cnt[vec[i]]--; if (cnt[vec[i]] == 0) { s.insert(vec[i]); } vec[i] = a; c = 0; for (i = 2; i <= n; i++) { if (vec[i] < vec[i - 1]) { c = 1; break; } } } } l = ans.size(); printf( %d n , l); for (i = 0; i < l; i++) { printf( %d , ans[i]); } printf( n ); } } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module generates the finish signal for the entire kernel.
// There are two main ports on this module:
// 1. From work-group dispatcher: to detect when a work-GROUP is issued
// It is ASSUMED that the work-group dispatcher issues at most one work-group
// per cycle.
// 2. From exit points of each kernel copy: to detect when a work-ITEM is completed.
module acl_kernel_finish_detector #(
parameter integer NUM_COPIES = 1, // >0
parameter integer WG_SIZE_W = 1, // >0
parameter integer GLOBAL_ID_W = 32 // >0, number of bits for one global id dimension
)
(
input logic clock,
input logic resetn,
input logic start,
input logic [WG_SIZE_W-1:0] wg_size,
// From work-group dispatcher. It is ASSUMED that
// at most one work-group is dispatched per cycle.
input logic [NUM_COPIES-1:0] wg_dispatch_valid_out,
input logic [NUM_COPIES-1:0] wg_dispatch_stall_in,
input logic dispatched_all_groups,
// From copies of the kernel pipeline.
input logic [NUM_COPIES-1:0] kernel_copy_valid_out,
input logic [NUM_COPIES-1:0] kernel_copy_stall_in,
input logic pending_writes,
// The finish signal is a single-cycle pulse.
output logic finish
);
localparam NUM_GLOBAL_DIMS = 3;
localparam MAX_NDRANGE_SIZE_W = NUM_GLOBAL_DIMS * GLOBAL_ID_W;
// Count the total number of work-items in the entire ND-range. This count
// is incremented as work-groups are issued.
// This value is not final until dispatched_all_groups has been asserted.
logic [MAX_NDRANGE_SIZE_W-1:0] ndrange_items;
logic wg_dispatched;
always @(posedge clock or negedge resetn)
begin
if( ~resetn )
ndrange_items <= '0;
else if( start ) // ASSUME start and wg_dispatched are mutually exclusive
ndrange_items <= '0;
else if( wg_dispatched )
// This is where the one work-group per cycle assumption is used.
ndrange_items <= ndrange_items + wg_size;
end
// Here we ASSUME that at most one work-group is dispatched per cycle.
// This depends on the acl_work_group_dispatcher.
assign wg_dispatched = |(wg_dispatch_valid_out & ~wg_dispatch_stall_in);
// Count the number of work-items that have exited all kernel pipelines.
logic [NUM_COPIES-1:0] kernel_copy_item_exit;
logic [MAX_NDRANGE_SIZE_W-1:0] completed_items;
logic [$clog2(NUM_COPIES+1)-1:0] completed_items_incr_comb, completed_items_incr;
always @(posedge clock or negedge resetn)
begin
if( ~resetn )
begin
kernel_copy_item_exit <= '0;
completed_items_incr <= '0;
end
else
begin
kernel_copy_item_exit <= kernel_copy_valid_out & ~kernel_copy_stall_in;
completed_items_incr <= completed_items_incr_comb;
end
end
// This is not the best representation, but hopefully synthesis will do something
// intelligent here (e.g. use compressors?). Assuming that the number of
// copies will never be that high to have to pipeline this addition.
always @(*)
begin
completed_items_incr_comb = '0;
for( integer i = 0; i < NUM_COPIES; ++i )
completed_items_incr_comb = completed_items_incr_comb + kernel_copy_item_exit[i];
end
always @(posedge clock or negedge resetn)
begin
if( ~resetn )
completed_items <= '0;
else if( start ) // ASSUME that work-items do not complete on the same cycle as start
completed_items <= '0;
else
completed_items <= completed_items + completed_items_incr;
end
// Determine if the ND-range has completed. This is true when
// the ndrange_items counter is complete (i.e. dispatched_all_groups)
// and the completed_items counter is equal to the ndrang_items counter.
logic ndrange_done;
always @(posedge clock or negedge resetn)
begin
if( ~resetn )
ndrange_done <= 1'b0;
else if( start )
ndrange_done <= 1'b0;
else
// ASSUMING that dispatched_all_groups is asserted at least one cycle
// after the last work-group is issued
ndrange_done <= dispatched_all_groups & (ndrange_items == completed_items);
end
// The finish output needs to be a one-cycle pulse when the ndrange is completed
// AND there are no pending writes.
logic finish_asserted;
always @(posedge clock or negedge resetn)
begin
if( ~resetn )
finish <= 1'b0;
else
finish <= ~finish_asserted & ndrange_done & ~pending_writes;
end
always @(posedge clock or negedge resetn)
begin
if( ~resetn )
finish_asserted <= 1'b0;
else if( start )
finish_asserted <= 1'b0;
else if( finish )
finish_asserted <= 1'b1;
end
endmodule
|
`timescale 1ns / 1ps
module top_movil_TB;
reg clk;
// reg start;
reg reset;
reg rxd;
// wire [0:76] String;
wire [15:0] ledsOut;
top_movil uut ( .clk(clk), .rxd(rxd), .reset(reset), .ledsOut(ledsOut));
initial begin // Process for clk
forever
begin
#5
clk = 1'b0;
#5
clk = 1'b1;
end
end
/* initial begin
reset=1;
#100
reset=0;
start=0;
#200
reset=1;
#1000
start=1;
#20
reset=0;
#13998680
reset=1;
#200
reset=0;
end*/
initial begin
reset=1;
#200
reset=0;
rxd =1;
#2000
rxd=0; // simulacion de ruido
#40
rxd=1;
#208280
rxd=0; // Bit de Start 1
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1; // Se termina char
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 2
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1; // Se termina char
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 3
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0; // Se termina char
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 4
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0; // Se termina char
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 5
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0; // Se termina char
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 6
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1; // Se termina char
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 7
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0; // Se termina char
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 8
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1; // Se termina char
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 9
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0; // Se termina char
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 10
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0; // Se termina char
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 11
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0; // Se termina char
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop y queda en 1 como IDLE
end // initial begin
initial begin: TEST_CASE
$dumpfile("top_movil_TB.vcd");
$dumpvars(-1, uut);
#32000000 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const long long INF = 1000000000; struct wie { int il_50, il_100, str; }; int main() { ios_base::sync_with_stdio(0); int n, k; cin >> n >> k; int p = 0, s = 0; for (int i = 0; i < n; ++i) { int x; cin >> x; if (x == 50) ++p; else ++s; } vector<vector<long long> > C(51, vector<long long>(51)); for (int i = 0; i <= 50; ++i) { for (int j = 0; j <= i; ++j) { if (j == 0 || j == i) C[i][j] = 1; else C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % MOD; } } long long il[51][51][2]; long long odl[51][51][2]; bool odw[51][51][2]; for (int i = 0; i < 51; ++i) { for (int j = 0; j < 51; ++j) { for (int l = 0; l < 2; ++l) { odw[i][j][l] = false; odl[i][j][l] = -1; } } } queue<wie> Q; Q.push({p, s, 1}); odw[p][s][1] = true; while (!Q.empty()) { wie akt = Q.front(); Q.pop(); if (akt.il_100 == s && akt.il_50 == p && akt.str == 1) { odl[akt.il_50][akt.il_100][akt.str] = 0; il[akt.il_50][akt.il_100][akt.str] = 1; for (int i = 0; i <= akt.il_50; ++i) { for (int j = 0; j <= akt.il_100; ++j) { wie nowy = {p - akt.il_50 + i, s - akt.il_100 + j, (akt.str ^ 1)}; if (i + j != 0 && 50 * i + 100 * j <= k) { Q.push(nowy); odw[nowy.il_50][nowy.il_100][nowy.str] = true; } } } } else { odl[akt.il_50][akt.il_100][akt.str] = INF; il[akt.il_50][akt.il_100][akt.str] = 0; for (int i = 0; i <= akt.il_50; ++i) { for (int j = 0; j <= akt.il_100; ++j) { wie nowy = {p - akt.il_50 + i, s - akt.il_100 + j, (akt.str ^ 1)}; if (i + j != 0 && 50 * i + 100 * j <= k) { if (odw[nowy.il_50][nowy.il_100][nowy.str]) { if (odl[nowy.il_50][nowy.il_100][nowy.str] != -1) { odl[akt.il_50][akt.il_100][akt.str] = min(odl[akt.il_50][akt.il_100][akt.str], odl[nowy.il_50][nowy.il_100][nowy.str] + 1); il[akt.il_50][akt.il_100][akt.str] = (il[akt.il_50][akt.il_100][akt.str] + (C[akt.il_50][i] * C[akt.il_100][j]) % MOD * il[nowy.il_50][nowy.il_100][nowy.str]) % MOD; } } else { Q.push(nowy); odw[nowy.il_50][nowy.il_100][nowy.str] = true; } } } } } } if (odw[p][s][0]) cout << odl[p][s][0] << << il[p][s][0]; else cout << -1 0 ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100000 + 10; int n; int a[N]; long long query(int l, int r) { vector<pair<long long, long long> > stack; long long ret = 0; long long cur = 0; for (int i = l + 1; i <= r; ++i) { long long diff = abs(a[i] - a[i - 1]); long long tot = 1; for (; stack.size();) { if (stack.back().first <= diff) { tot += stack.back().second; cur -= stack.back().first * stack.back().second; stack.pop_back(); } else { break; } } stack.push_back(make_pair(diff, tot)); cur += diff * tot; ret += cur; } return ret; } void solve() { int q; cin >> n >> q; for (int i = 0; i < n; ++i) { scanf( %d , a + i); } for (; q--;) { int l, r; scanf( %d%d , &l, &r); --l, --r; cout << query(l, r) << endl; } } int main() { solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O211A_PP_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, a[100003], i; int main() { cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; long long p = clock(); while (clock() - p < 1400) ; sort(a + 1, a + 1 + n); for (i = 1; i <= n; i++) cout << a[i] << ; return 0; } |
module limb_test_top (
// LIMB interface - toplevel should combine limb_d_in, limb_d_out, and
// limb_d_oe into a single 'inout' bus.
input [7:0] limb_d_in,
output [7:0] limb_d_out,
output limb_d_oe,
input limb_clk,
input limb_nrd,
input limb_start,
output limb_nwait,
output [35:0] wb_adr_o,
output [31:0] wb_dat_o,
output wb_we_o,
output wb_stb_o,
input clk
);
wire [35:0] wb_adr_full;
wire [5:0] wb_adr;
wire wb_we;
wire [3:0] wb_sel;
wire wb_stb;
wire wb_cyc;
wire [31:0] wb_dat_to_ram;
wire [31:0] wb_dat_from_ram;
wire wb_ack;
assign wb_adr = {wb_adr_full[3:0], 2'b00};
assign wb_adr_o = wb_adr_full;
assign wb_dat_o = wb_dat_to_ram;
assign wb_we_o = wb_we;
assign wb_stb_o = wb_stb;
limb_interface limb_interface_inst (
.limb_d_in(limb_d_in),
.limb_d_out(limb_d_out),
.limb_d_oe(limb_d_oe),
.limb_clk(limb_clk),
.limb_nrd(limb_nrd),
.limb_start(limb_start),
.limb_nwait(limb_nwait),
.wb_adr_o(wb_adr_full),
.wb_we_o(wb_we),
.wb_sel_o(wb_sel),
.wb_stb_o(wb_stb),
.wb_cyc_o(wb_cyc),
.wb_dat_o(wb_dat_to_ram),
.wb_dat_i(wb_dat_from_ram),
.wb_ack_i(wb_ack),
.clk(clk) );
wb_ram #( .ADDR_WIDTH(6) ) wb_ram_inst (
.clk(clk),
.adr_i(wb_adr),
.dat_i(wb_dat_to_ram),
.dat_o(wb_dat_from_ram),
.we_i(wb_we),
.sel_i(wb_sel),
.stb_i(wb_stb),
.ack_o(wb_ack),
.cyc_i(wb_cyc) );
initial begin
$dumpfile("out.vcd");
$dumpvars();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5005; const long long INF = 1e18; struct node { int u, v, w; node(int u = 0, int v = 0, int w = 0) : u(u), v(v), w(w) {} } a[2 * N]; int fst[N], nxt[2 * N], tot, n, size[N]; bool vis[N]; long long ans, sum[N], ans0, mn; void build(int x, int y, int z) { a[tot] = node(x, y, z); nxt[tot] = fst[x]; fst[x] = tot++; } void calc(int x) { int y; size[x] = 1; for (int p = fst[x]; ~p; p = nxt[p]) { if (vis[p / 2]) continue; vis[p / 2] = 1; y = a[p].v; calc(y); size[x] += size[y]; ans += (long long)a[p].w * size[y] * (n - size[y]); } } void dfs1(int x) { int y; sum[x] = 0; size[x] = 1; for (int p = fst[x]; ~p; p = nxt[p]) { if (vis[p / 2]) continue; vis[p / 2] = 1; y = a[p].v; dfs1(y); sum[x] = (long long)sum[y] + (long long)size[y] * a[p].w; size[x] += size[y]; } } void dfs2(int x, int all) { int y; for (int p = fst[x]; ~p; p = nxt[p]) { if (vis[p / 2]) continue; vis[p / 2] = 1; y = a[p].v; sum[y] = sum[x] - (long long)size[y] * a[p].w + (long long)(all - size[y]) * a[p].w; mn = min(mn, sum[y]); dfs2(y, all); } } long long work(int x, int i) { for (int j = 0; j < n - 1; j++) vis[j] = i == j ? 1 : 0; dfs1(x); for (int j = 0; j < n - 1; j++) vis[j] = i == j ? 1 : 0; mn = sum[x]; dfs2(x, size[x]); return (long long)(mn - sum[x]) * (n - size[x]); } int main() { int x, y, z; scanf( %d , &n); tot = 0; memset(fst, -1, sizeof(fst)); for (int i = 0; i < n - 1; i++) { scanf( %d%d%d , &x, &y, &z); x--; y--; build(x, y, z); build(y, x, z); } ans = 0; calc(0); ans0 = ans; long long tmp; for (int i = 0; i < n - 1; i++) { tmp = ans0 + work(a[i * 2].u, i) + work(a[i * 2].v, i); ans = min(ans, tmp); } cout << ans << n ; return 0; } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
state = 0;
invalid_rd = 0;
end else begin
case (state)
0 : begin
state = 0;
invalid_rd = 0;
if(req)begin
state = 1;
invalid_rd = invalid_rd_req;
end
end
1 : begin
state = 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
state = 0;
invalid_rd = 0;
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CONB_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CONB_PP_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__conb (
HI ,
LO ,
VPWR,
VGND
);
output HI ;
output LO ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CONB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; int val = n - a; if (val > (b + 1)) { cout << b + 1 << endl; } else { cout << val << endl; } } |
module my_uart_tx(rst_n, baud_clk, tx_start, tx_data, tx_enable, tx_complete, uart_tx);
input rst_n;
input baud_clk;
input tx_start;
input[7:0] tx_data;
output tx_enable;
output tx_complete;
output uart_tx;
/*************************************************************************************
* Update tx_enable_reg
************************************************************************************/
reg tx_enable_reg;
always @ (negedge tx_start or negedge tx_complete_reg or negedge rst_n)
begin
if (!rst_n)
begin
tx_enable_reg <= 1'b0;
end
else if (!tx_complete_reg)
tx_enable_reg <= 1'b0;
else if (!tx_start)
tx_enable_reg <= 1'b1;
end
assign tx_enable = tx_enable_reg;
/*************************************************************************************
* Update tx_complete_flag
************************************************************************************/
reg tx_complete_reg;
always @ (negedge baud_clk or negedge tx_enable_reg or negedge rst_n)
begin
if (!rst_n)
begin
tx_complete_reg <= 1'b1;
end
else if (!tx_enable_reg)
tx_complete_reg <= 1'b1;
else if (!baud_clk)
begin
if (!tx_count)
tx_complete_reg <= 1'b0;
end
end
assign tx_complete = tx_complete_reg;
/*************************************************************************************
* Update tx_count
************************************************************************************/
reg[3:0] tx_count;
always @ (posedge baud_clk or negedge rst_n)
begin
if (!rst_n)
begin
tx_count <= 4'd0;
end
else if (baud_clk)
begin
case (tx_count)
4'd1: tx_count <= 4'd2;
4'd2: tx_count <= 4'd3;
4'd3: tx_count <= 4'd4;
4'd4: tx_count <= 4'd5;
4'd5: tx_count <= 4'd6;
4'd6: tx_count <= 4'd7;
4'd7: tx_count <= 4'd8;
4'd8: tx_count <= 4'd9;
4'd9: tx_count <= 4'd0;
4'd0: tx_count <= 4'd1;
endcase
end
end
/*************************************************************************************
* Transmit data
************************************************************************************/
reg[7:0] tx_data_reg;
reg uart_tx_reg;
always @ (negedge baud_clk or negedge rst_n)
begin
if (!rst_n)
begin
uart_tx_reg <= 1'bz;
tx_data_reg <= 8'dz;
end
else if (!baud_clk)
begin
case (tx_count)
4'd1: begin uart_tx_reg <= 1'b0; tx_data_reg <= tx_data; end
4'd2: uart_tx_reg <= tx_data_reg[0];
4'd3: uart_tx_reg <= tx_data_reg[1];
4'd4: uart_tx_reg <= tx_data_reg[2];
4'd5: uart_tx_reg <= tx_data_reg[3];
4'd6: uart_tx_reg <= tx_data_reg[4];
4'd7: uart_tx_reg <= tx_data_reg[5];
4'd8: uart_tx_reg <= tx_data_reg[6];
4'd9: uart_tx_reg <= tx_data_reg[7];
4'd0: begin uart_tx_reg <= 1'b1;end
default: uart_tx_reg <= 1'bz;
endcase
end
end
assign uart_tx = uart_tx_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, ara[100005], i, j, k, ind, mx, sum, ans, ans1; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> ara[i]; } for (i = 0; i < n; i++) { if (ara[i] >= k) { k = ara[i]; ind = i; } } for (i = 0; i < n; i++) { if (i != ind) { sum += ara[i]; } } if (k >= sum) ans = k - sum + 1; else ans = sum - k + 1; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using PII = pair<int, int>; using PLL = pair<long long, long long>; using VLL = vector<long long>; using VI = vector<int>; inline void fastio() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); } const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fL; const int mod1 = 998244353; const int mod2 = 1e9 + 7; void solve() { int n, m, k; cin >> n >> m >> k; if (k <= 1) { cout << NO << endl; return; } if (m < n - 1) { cout << NO << endl; return; } long long cnt = 1ll * n * (n - 1) / 2; if (m > cnt) { cout << NO << endl; return; } if (k == 2 && n > 1) { cout << NO << endl; return; } if (k >= 2 && n == 1) { cout << YES << endl; return; } if (k > 3) { cout << YES << endl; return; } if (m == cnt) { cout << YES << endl; } else { cout << NO << endl; } } signed main() { fastio(); int t; cin >> t; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 1e5 + 5; int n, a[N]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , a + i); sort(a, a + n); for (int i = 0, eq = 0; i < n - 1; ++i) { if (a[i] == a[i + 1]) { if ((++eq) > 1 || (i > 0 && a[i] - 1 == a[i - 1]) || a[i] == 0) { puts( cslnb ); return 0; } } } ll sum = 0; for (int i = 0; i < n; ++i) sum += a[i] - i; if ((sum & 1) == 0) puts( cslnb ); else puts( sjfnb ); return 0; } |
/* #include <ext/pb_ds/assoc_container.hpp> #include <ext/pb_ds/priority_queue.hpp> using namespace __gnu_pbds; __gnu_pbds::priority_queue<int, less<int>> pq; gp_hash_table<int, int> mp; */ /** Begin fast allocation */ /* const int mx_MEM = 10 * 1e7; int mpos = 0; char mem[mx_MEM]; inline void *operator new(size_t n) { assert((mpos += n) <= mx_MEM); return (void *) (mem + mpos - n); } inline void operator delete(void *) noexcept {} // must have! */ /** End fast allocation */ /** Pragmas */ // mt19937 gen(2281337); //#pragma GCC optimize( O3 , Ofast , unroll-loops , unswitch-loops , fast-math , no-stack-protector ) //#pragma GCC target( sse,sse2,sse3,ssse3,sse4,sse4.1,sse4.2,abm,mmx,avx ) // sse,sse2,sse3,ssse3,sse4,sse4.1,sse4.2,abm,mmx, //#pragma comment(linker, /STACK:66777216 ) /* * @author kamil.sharipov */ #include <bits/stdc++.h> //#define int long long #define all(x) (x).begin(), (x).end() #define fo(i, a, b) for (int i = a; i < b; ++i) #define ll long long #define pii pair<int, int> using namespace std; int n, m, inf = 2e9, dst = 51; vector<vector<pii > > adj; vector<vector<vector<int> > > we; int dist[100001][51]; signed main() { #ifdef _LOCAL freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif cin >> n >> m; adj.resize(n), we.resize(n); for (int i = 0; i < n; ++i) { we[i].resize(dst); } for (int i = 0; i < m; ++i) { int u, v, w; cin >> u >> v >> w; --u, --v; adj[u].push_back({v, w}); adj[v].push_back({u, w}); } for (int i = 0; i < n; ++i) { for (int j = 0; j < dst; ++j) { dist[i][j] = inf; } } dist[0][0] = 0; set<pair<int, pii > > st; st.insert({0, {0, 0}}); while (!st.empty()) { auto[w, p] = *st.begin(); st.erase(st.begin()); int v = p.first; int d = p.second; if (w > dist[v][d]) continue; if (d == 0) { for (int i = 0; i < adj[v].size(); ++i) { int to = adj[v][i].first; int wei = adj[v][i].second; if (dist[to][wei] > w) { dist[to][wei] = w; st.insert({dist[to][wei], {to, wei}}); } } } else { for (int i = 0; i < adj[v].size(); ++i) { int to = adj[v][i].first; int wei = adj[v][i].second; int len = (d + wei) * (d + wei) + w; if (dist[to][0] > len) { dist[to][0] = len; st.insert({dist[to][0], {to, 0}}); } } } } for (int i = 0; i < n; ++i) { if (dist[i][0] == inf) cout << -1 ; else cout << dist[i][0] << ; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
class Cls;
int c_no = 2;
//automatic int c_au = 2; // automatic not a legal keyword here
static int c_st = 22;
function int f_c_no ();
++c_no; return c_no;
endfunction
function int f_c_st ();
++c_st; return c_st;
endfunction
static function int f_cs_st ();
++c_st; return c_st;
endfunction
endclass
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
Cls a = new;
Cls b = new;
int v;
initial begin
v = a.f_c_no(); `checkh(v, 3);
v = a.f_c_no(); `checkh(v, 4);
v = b.f_c_no(); `checkh(v, 3);
v = b.f_c_no(); `checkh(v, 4);
v = a.f_c_st(); `checkh(v, 23);
v = a.f_c_st(); `checkh(v, 24);
v = b.f_c_st(); `checkh(v, 25);
v = b.f_c_st(); `checkh(v, 26);
//
v = Cls::f_cs_st(); `checkh(v, 27);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O211A_FUNCTIONAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_FUNCTIONAL_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file BRAM_larg.v when simulating
// the core, BRAM_larg. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module BRAM_larg(
clka,
dina,
addra,
wea,
clkb,
addrb,
doutb);
input clka;
input [31 : 0] dina;
input [11 : 0] addra;
input [0 : 0] wea;
input clkb;
input [11 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_8 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex2"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_SSRA(0),
.C_HAS_SSRB(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(3000),
.C_READ_DEPTH_B(3000),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_SIM_COLLISION_CHECK("ALL"),
.C_SINITA_VAL("0"),
.C_SINITB_VAL("0"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_RAMB16BWER_RST_BHV(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(3000),
.C_WRITE_DEPTH_B(3000),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex2"))
inst (
.CLKA(clka),
.DINA(dina),
.ADDRA(addra),
.WEA(wea),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.ENA(),
.REGCEA(),
.SSRA(),
.DOUTA(),
.DINB(),
.ENB(),
.REGCEB(),
.WEB(),
.SSRB(),
.DBITERR(),
.SBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of BRAM_larg is "black_box"
endmodule
|
#include <bits/stdc++.h> long long int mod = 1000000007; using namespace std; void solve() { long long int n, k; cin >> n >> k; char ans[4][n]; int nval = n - 2; for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) { ans[i][j] = . ; } } int mid = nval / 2; mid++; if (k % 2 == 1) { for (int i = 1; i < 3; i++) { if (k <= 0) break; for (int j = mid; j >= 1; j--) { if (i > 1 && k % 2 == 0 && k < nval) { ans[i][1] = # ; ans[i][n - 2] = # ; k--; k--; } if (k > 0) { ans[i][j] = # ; k--; if (k <= 0) break; ans[i][mid + (mid - j)] = # ; if (j != mid) k--; } else break; } } } else { for (int i = 1; i < n - 1; i++) { for (int j = 1; j < 3; j++) { if (k) { ans[j][i] = # ; k--; } } } } cout << YES << endl; for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) { cout << ans[i][j]; } cout << endl; } } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma optimize( -O3 ) int cnt; int t[1200005]; int lazy[1200005]; long long int ans[300005]; void push(int v, int tl, int tr) { int tm = (tl + tr) / 2; if (lazy[v] == 2) { t[v * 2] = tm - tl + 1; t[2 * v + 1] = tr - tm; lazy[2 * v] = 2; lazy[2 * v + 1] = 2; lazy[v] = 0; } else if (lazy[v] == 3) { t[2 * v] = 0; t[2 * v + 1] = 0; lazy[2 * v] = 3; lazy[2 * v + 1] = 3; lazy[v] = 0; } else if (lazy[v]) { t[2 * v] = (tm - tl + 1) - t[2 * v]; t[2 * v + 1] = (tr - tm) - t[2 * v + 1]; lazy[2 * v] ^= 1; lazy[2 * v + 1] ^= 1; lazy[v] = 0; } } void update(int v, int tl, int tr, int l, int r, int type) { if (l > r) return; if (l == tl && tr == r) { push(v, tl, tr); if (type == 1) { t[v] = (tr - tl + 1); lazy[v] = 2; } else if (type == 2) { t[v] = 0; lazy[v] = 3; } else if (type == 3) { t[v] = (tr - tl + 1) - t[v]; lazy[v] ^= 1; } } else { push(v, tl, tr); int tm = (tl + tr) / 2; update(v * 2, tl, tm, l, min(r, tm), type); update(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r, type); t[v] = (t[v * 2] + t[v * 2 + 1]); } } int first(int v, int tl, int tr) { if (tl == tr) { return tl; } int tm = (tl + tr) / 2; push(v, tl, tr); if (t[v * 2] != (tm - tl + 1)) { return first(v * 2, tl, tm); } else { return first(v * 2 + 1, tm + 1, tr); } } void solve() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; vector<pair<int, pair<long long int, long long int>>> v; set<long long int> se; for (int i = 0; i < n; i++) { long long int t, l, r; cin >> t >> l >> r; v.push_back({t, {l, r}}); se.insert(l); se.insert(r + 1); } se.insert(1); map<long long int, int> m; int pt = 0; for (auto u : se) { m[u] = pt; ans[pt] = u; pt++; }; for (auto u : v) { cnt++; int ti = u.first; int l = m[u.second.first]; int r = m[u.second.second + 1] - 1; ; update(1, 0, 200001, l, r, ti); int val = first(1, 0, 200001); cout << ans[val] << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 , unroll-loops ) #pragma GCC target( avx2 ) using namespace std; template <class T, class U> inline void checkmin(T &x, U y) { if (y < x) x = y; } template <class T, class U> inline void checkmax(T &x, U y) { if (y > x) x = y; } template <class T, class U> inline bool ifmax(T &x, U y) { if (y > x) return x = y, true; return false; } template <class T, class U> inline bool ifmin(T &x, U y) { if (y < x) return x = y, true; return false; } template <class T> inline void sort(T &a) { sort(a.begin(), a.end()); } template <class T> inline void rsort(T &a) { sort(a.rbegin(), a.rend()); } template <class T> inline void reverse(T &a) { reverse(a.begin(), a.end()); } template <class T, class U> inline istream &operator>>(istream &str, pair<T, U> &p) { return str >> p.first >> p.second; } template <class T> inline istream &operator>>(istream &str, vector<T> &a) { for (auto &i : a) str >> i; return str; } template <class T> inline T sorted(T a) { sort(a); return a; } void read(int &x) { static char c; c = getchar(); if (c == - ) { x = 0; while ((c = getchar()) >= 0 ) x = (x << 3) + (x << 1) + (c - 0 ); x = -x; } else { x = c - 0 ; while ((c = getchar()) >= 0 ) x = (x << 3) + (x << 1) + (c - 0 ); } } void print(int x) { if (x >= 10) print(x / 10); putchar(x % 10 + 0 ); } const int N = 1e6 + 1; int a[N], ind[N]; bool used[N]; void solve() { int n; read(n); for (int i = 0; i < n; ++i) read(a[i]), used[i] = 0; int v = 0, pind = 0; while (!used[v]) { used[v] = true; ind[pind++] = v; v -= a[v]; } bool flag = false; for (int i = 0;; ++i) if (ind[i] == v) { print(pind - i); putchar( n ); for (int j = i; j < pind; ++j) print(ind[j] + 1), putchar( ); putchar( n ); return; } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(12); srand(94385); int t; read(t); while (t--) solve(); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module descrypt_salt(
input [63:0] Din,
input [63:0] K,
input [11:0] salt,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
// TODO: fix bit reversal of salt!!!
wire [31:0] L_out_tmp;
wire [31:0] R_out_tmp;
wire [63:0] D_ip;
wire [31:0] Ltmp [23:0];
wire [31:0] Rtmp [23:0];
wire [67:0] Ktmp [23:0];
wire [55:0] Kcrypt;
PC1 PC1_instance(K, Kcrypt);
IP IP_instance(Din, D_ip);
crypt_cycle_salt crypt_shift_instance1 (D_ip[63:32], D_ip[31:0], {salt, Kcrypt}, Ktmp[0], CLK, Ltmp[0], Rtmp[0]);
crypt_cycle_salt crypt_shift_instance2 (Ltmp[0], Rtmp[0], Ktmp[0], Ktmp[1], CLK, Ltmp[1], Rtmp[1]);
crypt_cycle_salt crypt_shift_instance3 (Ltmp[1], Rtmp[1], Ktmp[1], Ktmp[2], CLK, Ltmp[2], Rtmp[2]);
crypt_cycle_salt crypt_shift_instance4 (Ltmp[2], Rtmp[2], Ktmp[2], Ktmp[3], CLK, Ltmp[3], Rtmp[3]);
crypt_cycle_salt crypt_shift_instance5 (Ltmp[3], Rtmp[3], Ktmp[3], Ktmp[4], CLK, Ltmp[4], Rtmp[4]);
crypt_cycle_salt crypt_shift_instance6 (Ltmp[4], Rtmp[4], Ktmp[4], Ktmp[5], CLK, Ltmp[5], Rtmp[5]);
crypt_cycle_salt crypt_shift_instance7 (Ltmp[5], Rtmp[5], Ktmp[5], Ktmp[6], CLK, Ltmp[6], Rtmp[6]);
crypt_cycle_salt crypt_shift_instance8 (Ltmp[6], Rtmp[6], Ktmp[6], Ktmp[7], CLK, Ltmp[7], Rtmp[7]);
crypt_cycle_salt crypt_shift_instance9 (Ltmp[7], Rtmp[7], Ktmp[7], Ktmp[8], CLK, Ltmp[8], Rtmp[8]);
crypt_cycle_salt crypt_shift_instance10(Ltmp[8], Rtmp[8], Ktmp[8], Ktmp[9], CLK, Ltmp[9], Rtmp[9]);
crypt_cycle_salt crypt_shift_instance11(Ltmp[9], Rtmp[9], Ktmp[9], Ktmp[10], CLK, Ltmp[10], Rtmp[10]);
crypt_cycle_salt crypt_shift_instance12(Ltmp[10], Rtmp[10], Ktmp[10], Ktmp[11], CLK, Ltmp[11], Rtmp[11]);
crypt_cycle_salt crypt_shift_instance13(Ltmp[11], Rtmp[11], Ktmp[11], Ktmp[12], CLK, Ltmp[12], Rtmp[12]);
crypt_cycle_salt crypt_shift_instance14(Ltmp[12], Rtmp[12], Ktmp[12], Ktmp[13], CLK, Ltmp[13], Rtmp[13]);
crypt_cycle_salt crypt_shift_instance15(Ltmp[13], Rtmp[13], Ktmp[13], Ktmp[14], CLK, Ltmp[14], Rtmp[14]);
crypt_cycle_salt crypt_shift_instance16(Ltmp[14], Rtmp[14], Ktmp[14], Ktmp[15], CLK, Ltmp[15], Rtmp[15]);
crypt_cycle_salt crypt_shift_instance17(Ltmp[15], Rtmp[15], Ktmp[15], Ktmp[16], CLK, Ltmp[16], Rtmp[16]);
crypt_cycle_salt crypt_shift_instance18(Ltmp[16], Rtmp[16], Ktmp[16], Ktmp[17], CLK, Ltmp[17], Rtmp[17]);
crypt_cycle_salt crypt_shift_instance19(Ltmp[17], Rtmp[17], Ktmp[17], Ktmp[18], CLK, Ltmp[18], Rtmp[18]);
crypt_cycle_salt crypt_shift_instance20(Ltmp[18], Rtmp[18], Ktmp[18], Ktmp[19], CLK, Ltmp[19], Rtmp[19]);
crypt_cycle_salt crypt_shift_instance21(Ltmp[19], Rtmp[19], Ktmp[19], Ktmp[20], CLK, Ltmp[20], Rtmp[20]);
crypt_cycle_salt crypt_shift_instance22(Ltmp[20], Rtmp[20], Ktmp[20], Ktmp[21], CLK, Ltmp[21], Rtmp[21]);
crypt_cycle_salt crypt_shift_instance23(Ltmp[21], Rtmp[21], Ktmp[21], Ktmp[22], CLK, Ltmp[22], Rtmp[22]);
crypt_cycle_salt crypt_shift_instance24(Ltmp[22], Rtmp[22], Ktmp[22], Ktmp[23], CLK, Ltmp[23], Rtmp[23]);
crypt_cycle_salt crypt_shift_instance25(Ltmp[23], Rtmp[23], Ktmp[23], Kout, CLK, L_out_tmp, R_out_tmp);
IP_1 IP_1_instance({L_out_tmp, R_out_tmp}, {L_out, R_out});
endmodule |
// Modified from John Loomis, http://www.johnloomis.org/
module LCD_display_string(index,out,state_code);
input [4:0] index;
input [4:0] state_code;
output [7:0] out;
reg [7:0] out;
// ASCII hex values for LCD Display
// Line 1
always
case (index)
5'h00: case (state_code)
5'b10000: out <= 8'h44;//D
default: out <= 8'h53;//S
endcase
5'h01: case (state_code)
5'b00000: out <= 8'h74;//t
5'b10000: out <= 8'h6F;//o
default: out <= 8'h65;//e
endcase
5'h02: case (state_code)
5'b00000: out <= 8'h61;//a
5'b10000: out <= 8'h6E;//n
default: out <= 8'h74;//t
endcase
5'h03: case (state_code)
5'b00000: out <= 8'h72;//r
5'b10000: out <= 8'h65;//e
default: out <= 8'h20;//sp
endcase
5'h04: case (state_code)
5'b00000: out <= 8'h74;//t
5'b00001: out <= 8'h43;//C
5'b00010: out <= 8'h4D;//M
5'b00100: out <= 8'h54;//T
5'b01000: out <= 8'h53;//S
5'b10000: out <= 8'h20;//sp
default: out <= 8'h20;//sp
endcase
5'h05: case (state_code)
5'b00001: out <= 8'h6C;//l
5'b00010: out <= 8'h65;//e
5'b00100: out <= 8'h69;//i
5'b01000: out <= 8'h69;//i
default: out <= 8'h20;//sp
endcase
5'h06: case (state_code)
5'b00001: out <= 8'h6F;//o
5'b00010: out <= 8'h61;//a
5'b00100: out <= 8'h6D;//m
5'b01000: out <= 8'h7A;//z
default: out <= 8'h20;//sp
endcase
5'h07: case (state_code)
5'b00001: out <= 8'h63;//l
5'b00010: out <= 8'h6C;//l
5'b00100: out <= 8'h65;//e
5'b01000: out <= 8'h65;//e
default: out <= 8'h20;//sp
endcase
5'h08: case (state_code)
5'b00001: out <= 8'h6B;//k
default: out <= 8'h20;//sp
endcase
// Line 2
5'h10: out <= 8'h50;//P
5'h11: out <= 8'h72;//r
5'h12: out <= 8'h65;//e
5'h13: out <= 8'h73;//s
5'h14: out <= 8'h73;//s
5'h15: out <= 8'h20;//sp
5'h16: out <= 8'h4F;//O
5'h17: out <= 8'h6B;//k
default: out <= 8'h20;
endcase
endmodule
|
/*
*******************************************************************************
* File Name : ada_reg_file.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 2nd, 2014
* Author : Angel Terrones <>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Regiser file for the ADA processor.
* Contains 32 general-purpose 32-bits registers,
* 2 read ports, and 1 write port.
* Register 0 always reads as Zero.
*******************************************************************************
*/
module ada_reg_file(
input clk, // clock
input [4:0] read_addr_a, // Address port A
input [4:0] read_addr_b, // Address port B
input [4:0] write_addr, // Write address
input [31:0] write_data, // Data to write
input we, // Write enable
output [31:0] read_data_a, // Data port A
output [31:0] read_data_b // Data port B
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] registers [1:31]; // Register file of 32 32-bit registers. Register 0 is hardwired to 0s
//--------------------------------------------------------------------------
// Sequential (clocked) write.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (write_addr != 0)
registers[write_addr] <= (we) ? write_data : registers[write_addr];
end
//--------------------------------------------------------------------------
// Combinatorial Read. Register 0 is all 0s.
//--------------------------------------------------------------------------
assign read_data_a = (read_addr_a == 5'b0) ? 32'h0000_0000 : registers[read_addr_a];
assign read_data_b = (read_addr_b == 5'b0) ? 32'h0000_0000 : registers[read_addr_b];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V |
#include <bits/stdc++.h> const int N = 2010; const int M = 200010; struct Edge { int u, v, idx; char tp; } edge[M]; struct ROAD { int v, idx; void push(int _v, int _idx) { v = _v; idx = _idx; } }; std::vector<ROAD> road[N]; struct PREVEVE { int u, idx; void push(int _u, int _idx) { u = _u; idx = _idx; } } prev[N]; int que[N], fr, bk; bool vst[N]; int p[N], ok[M], size[N]; int find(int a) { return a == p[a] ? a : p[a] = find(p[a]); } void uni(int a, int b) { p[find(a)] = find(b); } int main() { int n, m, x, y; char s[20]; while (~scanf( %d %d , &n, &m)) { for (int i = 0; i < m; i++) { scanf( %d %d %s , &edge[i].u, &edge[i].v, s); edge[i].tp = s[0]; edge[i].u--; edge[i].v--; edge[i].idx = i; } if (n == 1) { puts( 0 ); } else { if (n % 2 == 0) puts( -1 ); else { ROAD tmp; x = y = 0; for (int i = 0; i < n; i++) p[i] = i, road[i].clear(); ; for (int i = 0; i < m; i++) { if (find(edge[i].u) != find(edge[i].v)) { uni(edge[i].u, edge[i].v); tmp.push(edge[i].v, i); road[edge[i].u].push_back(tmp); tmp.push(edge[i].u, i); road[edge[i].v].push_back(tmp); ok[i] = true; if (edge[i].tp == S ) x++; else y++; } else ok[i] = false; } if (x + y != n - 1) { puts( -1 ); } else { if (x < y) { std::swap(x, y); for (int i = 0; i < m; i++) { if (edge[i].tp == S ) edge[i].tp = M ; else edge[i].tp = S ; } } int done = 0; if (x != y) { for (int i = 0; i < n; i++) size[i] = road[i].size(); for (int i = 0, u, v; i < m; i++) { if (!ok[i] && edge[i].tp == M ) { memset(vst, false, sizeof(vst)); fr = bk = 0; que[bk++] = edge[i].u; vst[edge[i].u] = 1; while (fr < bk) { u = que[fr++]; for (int l = 0; l < size[u]; l++) { v = road[u][l].v; if (!vst[v]) { que[bk++] = v; vst[v] = 1; prev[v].push(u, road[u][l].idx); } } } v = edge[i].v; while (v != edge[i].u) { if (edge[prev[v].idx].tp == S ) { done++; ok[i] = true; ok[prev[v].idx] = false; int idx = prev[v].idx; u = edge[idx].u; v = edge[idx].v; for (int j = 0; j < size[u]; j++) { if (road[u][j].v == v) { for (int k = j + 1; k < size[u]; k++) road[u][k - 1] = road[u][k]; road[u].pop_back(); size[u]--; break; } } u = edge[idx].v; v = edge[idx].u; for (int j = 0; j < size[u]; j++) { if (road[u][j].v == v) { for (int k = j + 1; k < size[u]; k++) road[u][k - 1] = road[u][k]; road[u].pop_back(); size[u]--; break; } } u = edge[i].u; v = edge[i].v; tmp.push(v, i); road[u].push_back(tmp); size[u]++; tmp.push(u, i); road[v].push_back(tmp); size[v]++; break; } v = prev[v].u; } if (2 * done == x - y) break; } } } if (2 * done == x - y) { printf( %d n , n - 1); bool flg = false; for (int i = 0; i < m; i++) { if (ok[i]) { if (flg) putchar( ); printf( %d , i + 1); flg = true; } } puts( ); } else puts( -1 ); } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void smin(T &a, T b) { if (a > b) a = b; } template <class T> inline void smax(T &a, T b) { if (a < b) a = b; } int V, E, src, tar; int head[60000], work[60000], dis[60000]; int to[2000000], cap[2000000], nxt[2000000]; int q[60000], qf, qb; void init(int n) { memset(head, -1, sizeof(int) * n); V = n; E = 0; } void add_edge(int u, int v, int c) { to[E] = v; cap[E] = c; nxt[E] = head[u]; head[u] = E++; to[E] = u; cap[E] = 0; nxt[E] = head[v]; head[v] = E++; } bool bfs() { memset(dis, -1, sizeof(dis)); qf = qb = 0; q[qb++] = src; dis[src] = 0; while (qf < qb && dis[tar] == -1) { int u = q[qf++]; for (int i = head[u]; i >= 0; i = nxt[i]) { int v = to[i]; if (dis[v] == -1 && cap[i] > 0) { dis[v] = dis[u] + 1; q[qb++] = v; } } } return dis[tar] >= 0; } int dfs(int u, int &bot) { int v, bot1, delta; if (u == tar) return bot; for (int &i = work[u]; i >= 0; i = nxt[i]) { v = to[i]; if (dis[v] != dis[u] + 1 || cap[i] == 0) continue; bot1 = min(bot, cap[i]); if (delta = dfs(v, bot1)) { cap[i] -= delta; cap[i ^ 1] += delta; bot = bot1; return delta; } } return 0; } int dinic() { int ans = 0, delta, bot; while (bfs()) { memcpy(work, head, sizeof(int) * V); delta = 0x3f3f3f3f; while (delta = dfs(src, bot = 0x3f3f3f3f)) ans += delta; } return ans; } int dx[] = {-1, 0, 1, 0}, dy[] = {0, 1, 0, -1}; int n, m, dst[33][33][33][33]; char grid[33][33]; int c[2], x[2][33 * 33], y[2][33 * 33], t[2][33 * 33]; bool can(long long mid) { int A = c[0], nm = n * m; src = A * 2 + 2 * nm, tar = src + 1; init(tar + 10); for (int i = (0); i < (A); i++) add_edge(src, i, 1); for (int i = (0); i < (A); i++) add_edge(A + 2 * nm + i, tar, 1); for (int i = (0); i < (nm); i++) add_edge(A + i, A + nm + i, 1); for (int r = (0); r < (2); r++) for (int k = (0); k < (A); k++) for (int i = (0); i < (n); i++) for (int j = (0); j < (m); j++) { if (grid[i][j] == # ) continue; int xx = x[r][k], yy = y[r][k], tt = t[r][k]; if (dst[xx][yy][i][j] < 1000 && (long long)dst[xx][yy][i][j] * tt <= mid) { if (!r) add_edge(k, A + i * m + j, 1); else add_edge(A + nm + i * m + j, k + A + 2 * nm, 1); } } return dinic() == A; } int main() { ; scanf( %d%d%d%d , &n, &m, &c[0], &c[1]); for (int i = (0); i < (n); i++) scanf( %s , grid[i]); int u, v, w; scanf( %d%d%d , &u, &v, &w); u--; v--; for (int i = (0); i < (2); i++) for (int j = (0); j < (c[i]); j++) { scanf( %d%d%d , &x[i][j], &y[i][j], &t[i][j]); x[i][j]--; y[i][j]--; } if (c[0] < c[1]) { x[0][c[0]] = u; y[0][c[0]] = v; t[0][c[0]++] = w; } else { x[1][c[1]] = u; y[1][c[1]] = v; t[1][c[1]++] = w; } if (c[0] != c[1]) { puts( -1 ); return 0; } memset(dst, 0x3f, sizeof(dst)); for (int i = (0); i < (n); i++) for (int j = (0); j < (m); j++) { if (grid[i][j] == # ) continue; qb = qf = 0; q[qb++] = i; q[qb++] = j; dst[i][j][i][j] = 0; while (qb > qf) { u = q[qf++]; v = q[qf++]; for (int k = (0); k < (4); k++) { int uu = u + dx[k], vv = v + dy[k]; if ((uu < 0 || vv < 0 || uu >= n || vv >= m)) continue; if (grid[uu][vv] == # ) continue; if (dst[i][j][uu][vv] > dst[i][j][u][v] + 1) { dst[i][j][uu][vv] = dst[i][j][u][v] + 1; q[qb++] = uu; q[qb++] = vv; } } } } long long st = -1, ed = (1LL << 40), mid; while (st + 1 < ed) { mid = (st + ed) >> 1; if (can(mid)) ed = mid; else st = mid; } if (ed == (1LL << 40)) puts( -1 ); else printf( %I64d n , ed); return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_top.v
// Version : 2.4
//----------------------------------------------------------------------------//
// File: axi_basic_top.v //
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[100010]; vector<int> qe[710000]; map<pair<int, int>, int> dp; long long hehe[20]; long long find(int x, int y) { int k = y, n = 1; while (k) { n++; k /= 10; } return hehe[n] * x + y; } int get(char a[], int n) { int ans = 0; for (int i = 0; i < n; i++) { ans = ans * 27 + a[i] - a + 1; } return ans; } int getans(int x, int y, int n1, int n2) { int ans = 78974453; int ll, rr, l, r; for (int i = 0; i < qe[x].size(); i++) { l = qe[x][i]; r = l + n1; int p = int(lower_bound(qe[y].begin(), qe[y].end(), l) - qe[y].begin()); if (p < qe[y].size()) { rr = qe[y][p] + n2; if (r > rr) rr = r; ans = min(ans, rr - l); } p--; if (p >= 0) { rr = qe[y][p] + n2; if (r > rr) rr = r; ans = min(ans, rr - qe[y][p]); } } return ans; } int main() { int n, i, j, k, m; int x, y; char s1[5], s2[5]; hehe[1] = 1; for (i = 2; i <= 15; i++) hehe[i] = hehe[i - 1] * 10; scanf( %s , a); n = strlen(a); for (i = 0; i < n; i++) { for (j = 1; j < 5; j++) { if (j + i > n) break; k = get(a + i, j); qe[k].push_back(i); } } scanf( %d , &m); while (m--) { scanf( %s%s , s1, s2); int xx = strlen(s1); int yy = strlen(s2); x = get(s1, xx); y = get(s2, yy); if (qe[x].size() > qe[x].size() || (qe[x].size() == qe[y].size() && x > y)) { swap(x, y); swap(xx, yy); } int &ans = dp[pair<int, int>(x, y)]; if (!ans) ans = getans(x, y, xx, yy); printf( %d n , ans == 78974453 ? -1 : ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long ex(long long a, long long b) { long long tmp = 1; for (int i = 0; i < b; i++) { tmp = tmp * a; } return tmp; } int main() { long long r, l, tmp, ans = -1; bool good = 1; cin >> l >> r; for (long long i = l; i <= r; i++) { for (long long k = 0; k <= 5; k++) { for (long long j = 0; j <= 5; j++) { if (i / (ex(10, j)) % 10 == (i / (ex(10, k))) % 10 && ex(10, k) <= i && ex(10, j) <= i && j != k) { good = 0; } } } if (good) { ans = i; } good = 1; } cout << ans << endl; } |
(*
Copyright © 2008 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Export Metric.
Require Import Classification.
Require Import UniformContinuity.
Require Import Prelength.
Require Import Complete.
Require Import CornTac.
Set Implicit Arguments.
(**
** Product Metric
The product of two metric spaces forms a metric space *)
Section ProductSetoid.
Variable X Y : RSetoid.
Definition prod_st_eq (a b:X*Y) :=
st_eq (fst a) (fst b) /\ st_eq (snd a) (snd b).
Lemma prodST : Setoid_Theory _ prod_st_eq.
Proof.
split; unfold prod_st_eq.
intros; split; reflexivity.
intros x y [H1 H2]; split; symmetry; assumption.
intros x y z [H1 H2] [H3 H4]; split.
transitivity (fst y); assumption.
transitivity (snd y); assumption.
Qed.
Definition prodS : RSetoid := Build_RSetoid prodST.
End ProductSetoid.
Section ProductMetric.
Variable X Y : MetricSpace.
Definition prod_ball e (a b:X*Y) :=
ball e (fst a) (fst b) /\ ball e (snd a) (snd b).
Lemma prod_ball_refl : forall e a, prod_ball e a a.
Proof.
intros e a.
split; auto with *.
Qed.
Lemma prod_ball_sym : forall e a b, prod_ball e a b -> prod_ball e b a.
Proof.
intros e a b [H1 H2].
split; auto with *.
Qed.
Lemma prod_ball_triangle : forall e1 e2 a b c, prod_ball e1 a b -> prod_ball e2 b c -> prod_ball (e1 + e2) a c.
Proof.
intros e1 e2 a b c [H1 H2] [H3 H4].
split; eauto with metric.
Qed.
Lemma prod_ball_closed : forall e a b, (forall d, prod_ball (e + d) a b) -> prod_ball e a b.
Proof.
intros e a b H.
unfold prod_ball in *.
split; apply ball_closed; firstorder.
Qed.
Lemma prod_ball_eq : forall a b, (forall e, prod_ball e a b) -> prod_st_eq _ _ a b.
Proof.
intros a b H.
unfold prod_ball in *.
split; apply ball_eq; firstorder.
Qed.
Lemma prod_is_MetricSpace : is_MetricSpace (prodS X Y) prod_ball.
Proof.
split.
exact prod_ball_refl.
exact prod_ball_sym.
exact prod_ball_triangle.
exact prod_ball_closed.
exact prod_ball_eq.
Qed.
Definition ProductMS : MetricSpace.
Proof.
exists (prodS X Y) prod_ball.
abstract ( intros e1 e2 He a1 a2 [Ha0 Ha1] b1 b2 [Hb0 Hb1]; unfold prod_ball;
change (QposEq e1 e2) in He; rewrite -> He, Ha0, Ha1, Hb0, Hb1; reflexivity) using prod_ball_wd.
apply prod_is_MetricSpace.
Defined.
(** Product metrics preserve properties of metric spaces such as
being a prelenght space, being stable, being located, and being deciable
*)
Lemma ProductMS_prelength : PrelengthSpace X -> PrelengthSpace Y -> PrelengthSpace ProductMS.
Proof.
intros HX HY a b e d1 d2 Hed Hab.
destruct (HX (fst a) (fst b) e d1 d2 Hed (proj1 Hab)) as [c1 Hc1].
destruct (HY (snd a) (snd b) e d1 d2 Hed (proj2 Hab)) as [c2 Hc2].
exists (c1,c2); split; assumption.
Defined.
Lemma ProductMS_stable : stableMetric X -> stableMetric Y -> stableMetric ProductMS.
Proof.
unfold stableMetric.
intros H0 H1 e [xl xr] [yl yr] H.
simpl in H.
unfold prod_ball in H.
split.
apply H0; tauto.
apply H1; tauto.
Qed.
(** Furthermore, if a product space is stable, then the components are
stable (assuming the components are non-zero). *)
Lemma ProductMS_stableX : Y -> stableMetric ProductMS -> stableMetric X.
Proof.
unfold stableMetric.
intros a H0 e x y H.
assert (Z:~ ~ ball (m:=ProductMS) e (x,a) (y,a)).
revert H.
cut (ball (m:=X) e x y -> ball (m:=ProductMS) e (x, a) (y, a)).
tauto.
intros H.
split; auto.
apply ball_refl.
destruct (H0 _ _ _ Z).
assumption.
Qed.
Lemma ProductMS_stableY : X -> stableMetric ProductMS -> stableMetric Y.
Proof.
unfold stableMetric.
intros a H0 e x y H.
assert (Z:~ ~ ball (m:=ProductMS) e (a,x) (a,y)).
revert H.
cut (ball (m:=Y) e x y -> ball (m:=ProductMS) e (a,x) (a, y)).
tauto.
intros H.
split; auto.
apply ball_refl.
destruct (H0 _ _ _ Z).
assumption.
Qed.
Lemma ProductMS_located : locatedMetric X -> locatedMetric Y -> locatedMetric ProductMS.
Proof.
unfold locatedMetric.
intros H0 H1 e d x y Hed.
destruct (H0 _ _ (fst x) (fst y) Hed) as [A | A].
destruct (H1 _ _ (snd x) (snd y) Hed) as [B | B].
left.
split; assumption.
right; intros [_ H].
apply B; assumption.
right; intros [H _].
apply A; assumption.
Defined.
Lemma ProductMS_decidable : decidableMetric X -> decidableMetric Y -> decidableMetric ProductMS.
Proof.
unfold decidableMetric.
intros H0 H1 e x y.
destruct (H0 e (fst x) (fst y)) as [A | A].
destruct (H1 e (snd x) (snd y)) as [B | B].
left.
split; assumption.
right; intros [_ H].
apply B; assumption.
right; intros [H _].
apply A; assumption.
Defined.
(** This defines a pairing function with types of a metric space *)
Definition PairMS (x:X) (y:Y) : ProductMS := (x,y).
End ProductMetric.
(* begin hide *)
Implicit Arguments PairMS [X Y].
Add Parametric Morphism X Y : (@PairMS X Y) with signature (@st_eq _) ==> (@st_eq _) ==> (@st_eq _) as PairMS_wd.
Proof.
intros.
split; assumption.
Qed.
(* end hide *)
Open Local Scope uc_scope.
(** [together] forms the tensor of two functions operating between
metric spaces *)
Lemma together_uc : forall A B C D (f:A --> C) (g:B --> D),
is_UniformlyContinuousFunction (fun (p:ProductMS A B) => (f (fst p), g (snd p)):ProductMS C D) (fun x => QposInf_min (mu f x) (mu g x)).
Proof.
intros A B C D f g e a b H.
split; simpl; apply uc_prf; apply ball_ex_weak_le with (QposInf_min (mu f e) (mu g e)).
apply QposInf_min_lb_l.
destruct (QposInf_min (mu f e) (mu g e)) as [q|]; auto.
destruct H; auto.
apply QposInf_min_lb_r.
destruct (QposInf_min (mu f e) (mu g e)) as [q|]; auto.
destruct H; auto.
Qed.
Definition together A B C D (f:A --> C) (g:B --> D) : (ProductMS A B --> ProductMS C D) :=
Build_UniformlyContinuousFunction (together_uc f g).
(** Uniformly continuous functions on the product space can be curried: *)
Section uc_curry.
Context {A B C: MetricSpace} (f: ProductMS A B --> C).
Definition uc_curry_help_prf (a: A): is_UniformlyContinuousFunction (fun b => f (a, b)) (mu f).
Proof with auto.
repeat intro.
destruct f. clear f. simpl in *.
apply uc_prf.
destruct (mu e)...
split... apply ball_refl.
Qed.
Definition uc_curry_help (a: A): B --> C := Build_UniformlyContinuousFunction (uc_curry_help_prf a).
Definition uc_curry_prf: is_UniformlyContinuousFunction uc_curry_help (mu f).
Proof with auto.
repeat intro. simpl.
destruct f. clear f. simpl in *.
apply uc_prf.
destruct (mu e)...
split... apply ball_refl.
Qed.
Definition uc_curry: A --> B --> C := Build_UniformlyContinuousFunction uc_curry_prf.
End uc_curry.
(** Uncurry probably cannot be defined because because there is no way to construct a
uniform modulus of continuity from the domain-indexed set of uni-formly continuous functions.
Hence, we can convert only one way, and so non-curried versions of binary functions are
strictly more valuable than their curried representations. Consequently, it can be argued
that binary functions should always be defined in non-curried form. *)
(** Completion distributes over products: *)
Section completion_distributes.
Context {X Y: MetricSpace}.
Program Definition distrib_Complete (xy: Complete (ProductMS X Y)): ProductMS (Complete X) (Complete Y) :=
(@Build_RegularFunction _ (fun e => fst (approximate xy e)) _, @Build_RegularFunction _ (fun e => snd (approximate xy e)) _).
Next Obligation. repeat intro. apply xy. Qed.
Next Obligation. repeat intro. apply xy. Qed.
Lemma distrib_Complete_uc_prf: is_UniformlyContinuousFunction distrib_Complete (fun e => e).
Proof.
unfold distrib_Complete.
intros ??? H. split; repeat intro; simpl; apply H.
Qed.
Definition distrib_Complete_uc: Complete (ProductMS X Y) --> ProductMS (Complete X) (Complete Y) :=
Build_UniformlyContinuousFunction distrib_Complete_uc_prf.
Program Definition undistrib_Complete (xy: ProductMS (Complete X) (Complete Y)): Complete (ProductMS X Y) :=
@Build_RegularFunction _ (fun e => (approximate (fst xy) e, approximate (snd xy) e)) _.
Next Obligation. split. apply r. apply r0. Qed.
Lemma undistrib_Complete_uc_prf: is_UniformlyContinuousFunction undistrib_Complete (fun e => e).
Proof.
unfold distrib_Complete.
intros ??? H. split; repeat intro; simpl; apply H.
Qed.
Definition undistrib_Complete_uc: ProductMS (Complete X) (Complete Y) --> Complete (ProductMS X Y) :=
Build_UniformlyContinuousFunction undistrib_Complete_uc_prf.
Lemma distrib_after_undistrib_Complete xy: st_eq (distrib_Complete (undistrib_Complete xy)) xy.
Proof.
intros. unfold distrib_Complete, undistrib_Complete. simpl.
unfold prod_st_eq. simpl.
split; apply regFunEq_e; simpl; intros; apply ball_refl.
Qed.
Lemma undistrib_after_distrib_Complete xy: st_eq (undistrib_Complete (distrib_Complete xy)) xy.
Proof.
intros. unfold undistrib_Complete. simpl.
apply regFunEq_e.
split; simpl; apply ball_refl.
Qed.
End completion_distributes.
(** The diagonal function [x ⟼ (x,x)] is a uniformly continuous function
from a metric space X to the product space [X × X] *)
Section diag.
Require Import Unicode.Utf8.
Variable X:MetricSpace.
Definition diag_raw : X → (ProductMS X X) := λ x, (x,x).
Lemma diag_uc : (is_UniformlyContinuousFunction diag_raw (λ ε, ε)%Qpos).
Proof.
repeat try red; intuition.
Qed.
Definition diag: X --> (ProductMS X X) := Build_UniformlyContinuousFunction diag_uc.
End diag. |
#include <bits/stdc++.h> using namespace std; int main() { string s, p; cin >> s; int sz = s.size(); for (char ch = a ; ch <= z ; ch++) { for (int i = 0; i <= s.size(); i++) { p = s.substr(0, i) + ch + s.substr(i, sz); if (p == string(p.rbegin(), p.rend())) { cout << p << n ; return 0; } } } cout << NA n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_PP_SYMBOL_V
`define SKY130_FD_SC_MS__OR4_PP_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_PP_V
/**
* lsbufiso1p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso1p (
X ,
A ,
SLEEP ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_SLEEP;
wire or0_out_X ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SLEEP, SLEEP, DESTPWR, VGND );
or or0 (or0_out_X , SLEEP, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp2 (X , or0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const signed long long int LINF = LLONG_MAX; const double EPS = 1e-9; const int MOD = 1000000007; const int MAXN = 100001; const int ALPH = 26; const int DALPH = 52; int q; map<string, string> match, rmatch; set<string> current; int main() { scanf( %d , &q); while (q--) { string s1, s2; cin >> s1 >> s2; if (current.find(s1) == current.end()) { current.insert(s2); match[s1] = s2; rmatch[s2] = s1; } else { current.erase(s1); current.insert(s2); match[rmatch[s1]] = s2; rmatch[s2] = rmatch[s1]; rmatch.erase(s1); } } printf( %d n , (int)(match).size()); for (pair<string, string> p : match) { cout << p.first << << p.second << n ; } } |
#include <bits/stdc++.h> using namespace std; vector<int> a; int main() { string s; cin >> s; int cur = 0, mul = 1; for (int i = s.length() - 1; i >= 0; --i) { if (s[i] == , ) { a.push_back(cur); mul = 1; cur = 0; } else { cur += mul * (s[i] - 48); mul *= 10; } } a.push_back(cur); sort(a.begin(), a.end()); int L; int last = a[0]; bool ok = 0; printf( %d , a[0]); L = a[0]; for (int i = 1; i < a.size(); ++i) { if (a[i] == last) continue; if (a[i] == last + 1) { ok = 1; last = a[i]; } else { if (ok && L != last) { printf( -%d , last); L = last; } last = a[i]; printf( ,%d , a[i]); L = a[i]; } } if (ok && L != last) printf( -%d , last); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; char s[10001000]; int n; vector<int> sep; void lindon() { for (int i = 0; i < n;) { sep.push_back(i); int p1 = i, p2 = i + 1; while (p2 < n && s[p1] <= s[p2]) { if (s[p1] == s[p2]) ++p1, ++p2; else p1 = i, ++p2; } int len = p2 - p1; while (i <= p1) i += len; } } int z[10001000]; void exkmp() { int id, mx = -1; for (int i = 1; i <= 2 * n; ++i) { int p = 0; if (mx > i) p = max(p, min(mx - i, z[i - id])); while (p <= 2 * n && s[p] == s[i + p]) ++p; z[i] = p; if (i + p > mx) id = i, mx = i + p; } z[0] = 2 * n + 1; } string ans; bool same(string s) { string t = s; reverse(t.begin(), t.end()); return s == t; } int T, m; void rua3() { sep.push_back(n); m = sep.size() - 2; while (T >= 3 && m >= 0) { ans += string(s + sep[m], sep[m + 1] - sep[m]); --m; if (!(m >= 0 && same(string(s + sep[m], sep[m + 1] - sep[m])) && same(string(s + sep[m + 1], sep[m + 2] - sep[m + 1])))) --T; } } int rev(int x) { return 2 * n - x; } string fix(string s) { string t = s; reverse(t.begin(), t.end()); return min(s, t); } long long bas1, bas2, mod1, mod2, hasinit; bool ispri(int x) { for (int i = 2; i * i <= x; ++i) if (x % i == 0) return 0; return 1; } int ranpri(int l, int r) { for (;;) { long long tmp = rand() % 10000 * (1e8) + rand() % 10000 * (1e4) + rand() % 10000; tmp = tmp % (r - l + 1) + l; if (ispri(tmp)) return tmp; } } struct HASH { static const int mxlen = 1e7 + 10; int nn, h1[mxlen + 233], h2[mxlen + 233], p1[mxlen + 233], p2[mxlen + 233]; void init(char *s, int n) { if (!hasinit) { srand(time(0)); hasinit = 1; bas1 = ranpri(1e3, 1e4); bas2 = ranpri(1e3, 1e4); mod1 = ranpri(5e8, 1e9); mod2 = ranpri(5e8, 1e9); } nn = n; h1[0] = h2[0] = 0; p1[0] = p2[0] = 1; for (int i = 1; i <= n; ++i) { h1[i] = (h1[i - 1] * bas1 + s[i - 1]) % mod1; h2[i] = (h2[i - 1] * bas2 + s[i - 1]) % mod2; p1[i] = p1[i - 1] * bas1 % mod1; p2[i] = p2[i - 1] * bas2 % mod2; } } pair<int, int> gay(int l, int r) { if (r > nn) return (pair<int, int>){rand(), rand()}; int res1 = (h1[r] - (long long)h1[l] * p1[r - l] % mod1 + mod1) % mod1; int res2 = (h2[r] - (long long)h2[l] * p2[r - l] % mod2 + mod2) % mod2; return (pair<int, int>){res1, res2}; } } hs; int fuck(int pa, int pb, int lim) { int lcp = 0; for (int i = 25; i >= 0; --i) if (hs.gay(pa, pa + (1 << i)) == hs.gay(pb, pb + (1 << i))) { pa += 1 << i; pb += 1 << i; lcp += 1 << i; } if (lcp >= lim) return 0; return s[pa] < s[pb] ? 1 : -1; } vector<pair<int, int> > hashmin(vector<pair<int, int> > a, vector<pair<int, int> > b) { if (!a.size() || !b.size()) return max(a, b); if (a[0].second > b[0].second) swap(a, b); { int t = fuck(a[0].first, b[0].first, a[0].second); if (t) return t == 1 ? a : b; } { int t = fuck(a[1].first, b[0].first + a[0].second, b[0].second - a[0].second); if (t) return t == 1 ? a : b; } { int t = fuck(a[1].first + b[0].second - a[0].second, b[1].first, b[1].second); if (t) return t == 1 ? a : b; } return a; } string gaolas() { int l = sep[m + 1]; string res = fix(string(s, l)); if (T <= 1 || m <= 0) return res; { int mn = 0; char c1, c2; for (int i = 1; i < l - 1; ++i) { int lcp1 = z[rev(i)]; if (lcp1 < i - mn) { c1 = s[i - lcp1]; c2 = s[lcp1]; } else { int lcp2 = z[i - mn]; c1 = s[lcp2]; c2 = s[i - mn + lcp2]; } if (c1 > c2) mn = i; } string t1(s, mn + 1), t2(s + mn + 1, l - mn - 1); reverse(t2.begin(), t2.end()); string t = t2 + t1; res = min(res, t); } { vector<pair<int, int> > best; for (int i = m; i >= 0 && i >= m - 25; --i) { { vector<pair<int, int> > v; v.push_back({sep[i], l - sep[i]}); v.push_back({0, sep[i]}); best = hashmin(best, v); } { vector<pair<int, int> > v; v.push_back({sep[i], l - sep[i]}); v.push_back({rev(sep[i] - 1), sep[i]}); best = hashmin(best, v); } } string tmp = string(s + best[0].first, best[0].second) + string(s + best[1].first, best[1].second); res = min(res, tmp); } return res; } int main() { scanf( %s%d , s, &T); n = strlen(s); for (int i = 0; i < n; ++i) s[i + n + 1] = s[i]; reverse(s, s + n); s[n] = # ; s[n * 2 + 1] = $ ; lindon(); exkmp(); hs.init(s, 2 * n + 1); rua3(); ans += gaolas(); printf( %s n , ans.c_str()); } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; struct segtree { int n; vector<pair<int, int>> st; segtree(int _n) { n = _n; st.assign(4 * n + 5, make_pair(0, 0)); } pair<int, int> merge(pair<int, int> a, pair<int, int> b) { pair<int, int> res = make_pair(min(a.first, b.first), 0); if (a.first == res.first) res.second += a.second; if (b.first == res.first) res.second += b.second; if (res.second >= mod) res.second -= mod; return res; } void update(int id, int l, int r, int pos, int val, int num) { if (l > pos || r < pos) return; if (l == r) { st[id] = make_pair(val, num); return; } int mid = (l + r) >> 1; update(id << 1, l, mid, pos, val, num); update(id << 1 | 1, mid + 1, r, pos, val, num); st[id] = merge(st[id << 1], st[id << 1 | 1]); } pair<int, int> get(int id, int l, int r, int u, int v) { if (l > v || r < u) return make_pair((int)2e9, 0); if (l >= u && r <= v) return st[id]; int mid = (l + r) >> 1; pair<int, int> lnode = get(id << 1, l, mid, u, v); pair<int, int> rnode = get(id << 1 | 1, mid + 1, r, u, v); return merge(lnode, rnode); } void update(int pos, int val, int num) { update(1, 1, n, pos, val, num); } pair<int, int> get(int l, int r) { return get(1, 1, n, l, r); } }; const int N = 2e5 + 5; pair<int, int> a[N]; pair<int, int> dp[N]; int n; int maxpre[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i].first >> a[i].second; } sort(a + 1, a + n + 1); segtree st(n); for (int i = 1; i <= n; i++) { swap(a[i].first, a[i].second); int lo = 0; int hi = i; while (hi - lo > 1) { int mid = (lo + hi) >> 1; if (a[mid].second <= a[i].first) lo = mid; else hi = mid; } if (!lo) dp[i] = make_pair(a[i].first, 1); else { dp[i] = st.get(1, lo); dp[i].first += a[i].first; } st.update(i, dp[i].first - a[i].second, dp[i].second); } pair<int, int> ans = make_pair((int)2e9, 0); int mx = 0; for (int i = n; i >= 1; i--) if (a[i].second > mx) { if (ans.first == dp[i].first) { ans.second += dp[i].second; if (ans.second >= mod) ans.second -= mod; } else if (ans.first > dp[i].first) ans = dp[i]; mx = max(mx, a[i].first); } cout << ans.second; return 0; } |
#include <bits/stdc++.h> using namespace std; int maxrob(int p, int f, int cnt_s, int cnt_w, int s, int w) { if (p > f) { swap(p, f); } if (s > w) { swap(cnt_s, cnt_w); swap(s, w); } long long s_total = (long long)cnt_s * s; if ((p + f) <= s_total) { return (p / s) + (f / s); } int w_cnt_max = min(((p + f) - s_total) / w, (long long)cnt_w); int answer = 0; for (int k = 0; k <= w_cnt_max; ++k) { if ((long long)w * k > p) break; int res = 0; int s_cnt_p = min((p - w * k) / s, cnt_s); int s_cnt_f = cnt_s - s_cnt_p; res += s_cnt_p; if ((long long)s * s_cnt_f > f) { s_cnt_f = (f / s); } res += s_cnt_f; res += min((p - s * s_cnt_p) / w + (f - s * s_cnt_f) / w, cnt_w); if (answer < res) answer = res; } return answer; } int main() { int T; cin >> T; while (T-- != 0) { int p, f; cin >> p >> f; int cnt_s, cnt_w; cin >> cnt_s >> cnt_w; int s, w; cin >> s >> w; cout << maxrob(p, f, cnt_s, cnt_w, s, w) << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<long long int> v; for (int i = 1; i <= n; i++) { long long int a; cin >> a; v.push_back(a); } sort(v.begin(), v.end()); long long int total = 0; int cnt = 0; for (int i = 0; i < v.size(); i++) { total += v[i]; if (total - v[i] <= v[i]) ++cnt; else total -= v[i]; } cout << cnt << endl; } |
#include <bits/stdc++.h> using namespace std; int p[2001]; int a[2001]; int find(int v) { if (p[v] != v) p[v] = find(p[v]); return p[v]; } void merge(int u, int v) { int pu = find(u); int pv = find(v); p[pu] = pv; } int main() { int n, m, k, i, l, r; cin >> n >> m >> k; for (i = 0; i < n; i++) p[i] = i; for (i = 0; i < n; i++) { l = i; r = i + k - 1; if (r >= n) break; while (l < r) { merge(l, r); l++; r--; } } for (i = 0; i < n; i++) { p[i] = find(i); a[p[i]]++; } long long re = 1; for (i = 0; i < n; i++) if (a[i] > 0) { re *= m; re %= 1000000007; } cout << re; return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_top.v
//----------------------------------------------------------------------------//
// File: axi_basic_top.v //
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
// Extended by Martin Whitaker
module test();
// variables used in casting
byte var_08;
shortint var_16;
int var_32;
longint var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = byte'(4'sh5); if (var_08 !== 8'sh05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = shortint'(var_08); if (var_16 !== 16'sh05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = int'(var_16); if (var_32 !== 32'sh05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = longint'(var_32); if (var_64 !== 64'sh05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = byte'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = shortint'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = int'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = longint'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = byte'(4'hf); if (var_08 !== 8'sh0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
var_08 = byte'(4'shf); if (var_08 !== 8'shff) begin $display("FAILED -- var_08 = 'h%0h != 8'hff", var_08); err=1; end
var_16 = byte'(16'h0f0f); if (var_16 !== 16'sh0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
var_16 = byte'(4'shf) + 'd0; if (var_16 !== 16'shff) begin $display("FAILED -- var_16 = 'h%0h != 16'hff", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O2BB2AI_FUNCTIONAL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2ai (
VPWR,
VGND,
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire nand1_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probec_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.0sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long cc = 0; unordered_map<long long, long long> c, rc; vector<vector<long long> > graph(1e6); vector<bool> visited(1e6, false); vector<vector<long long> > answers(1e6); void dfs(long long node) { visited[node] = true; answers[cc].push_back(node); for (auto i : graph[node]) if (!visited[i]) dfs(i); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; vector<long long> nums(n); for (int i = 0; i < (int)(n); i++) cin >> (nums)[i]; ; vector<long long> nums_copy((nums).begin(), (nums).end()); sort((nums_copy).begin(), (nums_copy).end()); for (int i = 0; i < n; i++) c[i] = nums_copy[i], rc[nums_copy[i]] = i; vector<long long> modified(n); for (int i = 0; i < n; i++) modified[i] = rc[nums[i]]; for (int i = 0; i < n; i++) { graph[i].push_back(modified[i]); } for (int i = 0; i < n; i++) { if (!visited[i]) dfs(i), cc++; } cout << cc << endl; for (int i = 0; i < cc; i++) { long long k = answers[i].size(); cout << k << ; for (int j = 0; j < k; j++) cout << answers[i][j] + 1 << ; cout << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_SYMBOL_V
`define SKY130_FD_SC_HD__A221OI_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a221oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_SYMBOL_V
|
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 2
*/
// Behavioral model for the PISO convertor
module PISO(serial_out, out_valid, data_in, load, reset_b, clk);
/**
* Take input in when load and reset_b are HIGH, and out_valid
* is LOW, at the positive edge of the clock.
*
* Subsequently, output the values, and set out_valid to HIGH
* Ignore all inputs when out_valid is HIGH; and clock all the
* data out
*
* Reset is active LOW
*
* Ignore otherwise
*/
// Output signals representing the end of the transaction
// Output of the PISO convertor
output serial_out;
/**
* Indicate if the data is valid at serial_out
* out_valid = 1 when data is valid; it is ZERO otherwise
*/
output out_valid;
// ===============================================================
// Input signals
// Input data bit sequence coming in to the PISO convertor
input [7:0] data_in;
/**
* Clock signal for the finite state machine to facilitate
* state transitions
*/
input clk;
/**
* Active low reset signal for the finite state machine to
* bring it to the initial state
*/
input reset_b;
/**
* Active high flag to enable data to be loaded at the positive
* edge of the clock
*/
input load;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg out_valid; // Output signal
reg serial_out; // Output signal
// Outputs of the D flip-flops in the PISO converter
reg q_dff1; // Output of the 1st D flip-flop
reg q_dff2; // Output of the 2nd D flip-flop
reg q_dff3; // Output of the 3rd D flip-flop
reg q_dff4; // Output of the 4th D flip-flop
reg q_dff5; // Output of the 5th D flip-flop
reg q_dff6; // Output of the 6th D flip-flop
reg q_dff7; // Output of the 7th D flip-flop
// Output of the 8th D flip-flop = out_valid
/**
* Flag to indicate if input shall be used as input to the
* flip-flops; set flag=0 to use output of previous flip-flop
*/
//reg flag1; // flag of the 1st D flip-flop
reg flag2; // flag of the 2nd D flip-flop
reg flag3; // flag of the 3rd D flip-flop
reg flag4; // flag of the 4th D flip-flop
reg flag5; // flag of the 5th D flip-flop
reg flag6; // flag of the 6th D flip-flop
reg flag7; // flag of the 7th D flip-flop
//reg flag8; // flag of the 8th D flip-flop
// ===============================================================
// Definitions for the states in the PISO convertor
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Logic for active low reset signal to reset the PISO convertor
always @(~reset_b)
begin
// When "reset_b" goes low, out_valid=0
out_valid<=1'd0;
// Set the output of the 1st D flip-flop to ZERO
q_dff1<=1'd0;
// Set the output of the 2nd D flip-flop to ZERO
q_dff2<=1'd0;
// Set the output of the 3rd D flip-flop to ZERO
q_dff3<=1'd0;
// Set the output of the 4th D flip-flop to ZERO
q_dff4<=1'd0;
// Set the output of the 5th D flip-flop to ZERO
q_dff5<=1'd0;
// Set the output of the 6th D flip-flop to ZERO
q_dff6<=1'd0;
// Set the output of the 7th D flip-flop to ZERO
q_dff7<=1'd0;
// Set the output of the 8th D flip-flop to ZERO
serial_out<=1'd0;
flag2<=1'd1;
flag3<=1'd1;
flag4<=1'd1;
flag5<=1'd1;
flag6<=1'd1;
flag7<=1'd1;
end
// ===============================================================
// 1st D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(load && reset_b && (~out_valid))
begin
// Process input data - get the MSB
q_dff1<=data_in[7];
end
else
begin
/**
* Send in unknown value to indicate that data_in[7]
* has been processed
*/
q_dff1<=1'dx;
end
end
// ===============================================================
// 2nd D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(load && reset_b && (~out_valid))
begin
// Process input data
q_dff2<=data_in[6];
end
else if(out_valid)
begin
$display($time, ">>>>>>> Bring in value from prev dff1");
q_dff2<=q_dff1;
end
end
// ===============================================================
// 3rd D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(load && reset_b && (~out_valid))
begin
// Process input data
q_dff3<=data_in[5];
end
else if(out_valid)
begin
$display($time, ">>>>>>> Bring in value from prev dff2");
q_dff3<=q_dff2;
end
end
// ===============================================================
// 4th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(load && reset_b && (~out_valid))
begin
// Process input data
q_dff4<=data_in[4];
end
else if(out_valid)
begin
$display($time, ">>>>>>> Bring in value from prev dff3");
q_dff4<=q_dff3;
end
end
// ===============================================================
// 5th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(load && reset_b && (~out_valid))
begin
// Process input data
q_dff5<=data_in[3];
end
else if(out_valid)
begin
$display($time, ">>>>>>> Bring in value from prev dff4");
q_dff5<=q_dff4;
end
end
// ===============================================================
// 6th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(load && reset_b && (~out_valid))
begin
// Process input data
q_dff6<=data_in[2];
end
else if(out_valid)
begin
$display($time, ">>>>>>> Bring in value from prev dff5");
q_dff6<=q_dff5;
end
end
// ===============================================================
// 7th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(load && reset_b && (~out_valid))
begin
// Process input data
q_dff7<=data_in[1];
end
else if(out_valid)
begin
$display($time, ">>>>>>> Bring in value from prev dff6");
$display("q_dff6:::",q_dff6);
q_dff7<=q_dff6;
$display("q_dff7:::",q_dff7);
end
end
// ===============================================================
// 8th/Final/Last D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(load && reset_b && (~out_valid))
begin
serial_out<=data_in[0];
// Set "out_valid"=1
out_valid<=1'd1;
end
else if((out_valid==1) && (q_dff7!==1'dz) && (q_dff7!==1'dx))
begin
$display($time, ">>>>>>> Bring in value from prev dff7");
if((q_dff7==1'dz) || (q_dff7==1'dx))
begin
serial_out<=1'd0;
end
else
begin
serial_out<=q_dff7;
end
end
else
begin
$display($time, "########### REady for new input");
// Set "out_valid"=0
out_valid<=1'd0;
serial_out<=1'd0;
// Set flags to HIGH
/*
flag2<=1'd1;
flag3<=1'd1;
flag4<=1'd1;
flag5<=1'd1;
flag6<=1'd1;
flag7<=1'd1;
*/
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:00:47 10/13/2014
// Design Name: uart_rx
// Module Name: C:/ece4743/projects/lab9_solution/tb_uart_rx.v
// Project Name: lab9_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: uart_rx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_uart_rx;
// Inputs
reg clk;
reg reset;
reg wren;
reg rden;
reg [7:0] din;
reg rxin;
reg [2:0] addr;
// Outputs
wire [8:0] dout;
parameter CLK_PERIOD=20; //clock period in ns. 20 ns = 50 MHZ
//parameter UUT_PERIOD=8'h1A; //57600 baudrate
parameter UUT_PERIOD=8'h0C; //115200 baudrate
parameter CLK16X_PERIOD=(CLK_PERIOD*(UUT_PERIOD+1)*2);
parameter CHARACTER_PERIOD = (CLK16X_PERIOD * 16 * 10);
// Instantiate the Unit Under Test (UUT)
uart_rx uut (
.clk(clk),
.reset(reset),
.wren(wren),
.rden(rden),
.din(din),
.dout(dout),
.rxin(rxin),
.addr(addr)
);
`define FSIZE 1024
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer errors;
initial begin
clk = 0;
#100 //reset delay
forever #10 clk = ~clk;
end
//timeout process
initial begin
#(CHARACTER_PERIOD*35); //wait 35 characters
if (head != tail) begin
$display("%t: TIMEOUT, not all characters processed.",$time);
$display("The timeout is probably due to the DATARDY bit never going high.");
end
end
reg [9:0] shiftdata;
integer i;
task putserialdata;
input [8:0] outdata;
begin
infifo[head] = outdata;
head = head + 1;
if (head == `FSIZE) head = 0;
shiftdata ={1'b1,outdata[7:0],1'b0};
i = 0;
while (i != 10) begin
rxin = shiftdata[0];
#(CLK16X_PERIOD*16) //wait one bit time
i = i + 1;
shiftdata = {1'b1,shiftdata[9:1]};
end
end
endtask
task putserialdata_badstop;
input [8:0] outdata;
begin
infifo[head] = outdata;
head = head + 1;
if (head == `FSIZE) head = 0;
shiftdata ={1'b1,outdata[7:0],1'b0};
i = 0;
while (i != 10) begin
if (i == 9) rxin = 0;
else rxin = shiftdata[0];
#(CLK16X_PERIOD*16) //wait one bit time
i = i + 1;
shiftdata = {1'b1,shiftdata[9:1]};
end
end
endtask
task putserialdata_badstart;
input [8:0] outdata;
begin
infifo[head] = outdata;
head = head + 1;
if (head == `FSIZE) head = 0;
shiftdata ={1'b1,outdata[7:0],1'b0};
i = 0;
while (i != 10) begin
if (i == 0) begin
rxin = 0;
#(CLK16X_PERIOD*2);
rxin = 1; //bad start
#(CLK16X_PERIOD*14);
end else begin
rxin = shiftdata[0];
#(CLK16X_PERIOD*16); //wait one bit time
end
i = i + 1;
shiftdata = {1'b1,shiftdata[9:1]};
end
end
endtask
reg [8:0] expecteddata;
task readdata;
begin
//read status register, wait for TXDONE bit to be set
@(negedge clk);
rden = 1;
addr = 7; //status register
@(negedge clk);
while (dout[1] == 0) begin
@(negedge clk); //wait for DataRdy bit
end
addr = 5; //FIFO register
@(posedge clk); //must latch FIFO out data on posedge
if (expecteddata[8] == 1) begin
//expected framing error, just check ferr bit
if (dout[8] != 1) begin
errors = errors + 1;
$display("%t: FAIL,did not receive expected framing error",$time);
end else begin
$display("%t: PASS,received expected framing error",$time);
end
end else begin
//no expected framing error
if (expecteddata != dout) begin
errors = errors + 1;
$display("%t: FAIL,expected serial out of %h, found: %h",$time,expecteddata,dout);
end else begin
$display("%t: PASS,got expected serial out of %h",$time,expecteddata);
end
end
addr = 7;
rden = 0;
@(negedge clk);
end
endtask
task checkdata;
begin
while (head != tail) begin
expecteddata = infifo[tail];
tail = tail + 1;
if (tail == `FSIZE) tail = 0;
readdata();
end
end
endtask
task writerxen; //this writes a 'expectedbit' to the EN bit of the control register
input expectedbit;
begin
@(negedge clk);
din = {7'b0000000,expectedbit};
wren = 1;
addr = 7;
@(negedge clk);
wren = 0;
rden = 1;
@(negedge clk);
@(negedge clk);
if (dout[0] != expectedbit) begin
errors = errors + 1;
$display("%t: FAIL, writing UART RXEN bit = %h failed.",$time,expectedbit);
end else begin
$display("%t: PASS, writing UART RXEN bit = %h.",$time, expectedbit);
end
rden = 0;
@(negedge clk);
end
endtask
task rdoverrun; //read the overrun flag
input expectedbit;
begin
@(negedge clk);
addr = 7;
rden = 1;
@(negedge clk);
if (dout[2] != expectedbit) begin
errors = errors + 1;
$display("%t: FAIL, reading UART OVERRUN bit, expected: %h, actual: %h.",$time,expectedbit,dout[2]);
end else begin
$display("%t: PASS, reading UART OVERRUN bit: %h.",$time, expectedbit);
end
rden = 0;
end
endtask
task rddatardy; //read the data rdy flag
input expectedbit;
begin
@(negedge clk);
addr = 7;
rden = 1;
@(negedge clk);
if (dout[1] != expectedbit) begin
errors = errors + 1;
$display("%t: FAIL, reading UART DATARDY bit, expected: %h, actual: %h.",$time,expectedbit,dout[1]);
end else begin
$display("%t: PASS, reading UART DATARDY bit.",$time);
end
rden = 0;
end
endtask
integer j;
initial begin
// Initialize Inputs
#1
clk = 0;
reset = 1;
wren = 0;
rden = 0;
din = 0;
rxin = 1;
addr = 0;
errors = 0;
head = 0;
tail = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
// Add stimulus here
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
//first need to write the period register
din = UUT_PERIOD;
wren = 1;
addr = 4;
@(negedge clk);
wren = 0;
rden = 1;
@(negedge clk);
@(negedge clk);
if (dout != UUT_PERIOD) begin
errors = errors + 1;
$display("%t: FAIL, PERIOD register write/read failed: %h, expected: %h",$time,UUT_PERIOD,dout);
end else begin
$display("%t: PASS, Period register read/write",$time);
end
rden = 0;
@(negedge clk);
writerxen(1); //write a '1' to UART to get it started
putserialdata(9'h039);
checkdata();
putserialdata(9'h012);
putserialdata(9'h0D3);
putserialdata(9'h0B7);
#(CHARACTER_PERIOD*3)
#(CLK16X_PERIOD*16)
checkdata();
$display("Testing bad stop bit");
putserialdata_badstop(9'h155); //test bad stop bit
checkdata();
$display("Testing bad start bit");
putserialdata_badstop(9'h1AA); //test bad stop bit
checkdata();
putserialdata(9'h084);
checkdata();
//now test overrun
j = 0;
while (j != 18) begin
putserialdata(j+ 9'h030);
j = j + 1;
end
//check the overrun bit
@(negedge clk);
@(negedge clk);
@(negedge clk);
rdoverrun(0);
//send one more character, will set the overrun bit.
putserialdata(j+ 9'h030);
@(negedge clk);
@(negedge clk);
@(negedge clk);
rdoverrun(1);
//now reset the uart
writerxen(0); //write a '0' to UART RXEN to reset it.
//overrun should now be 0.
@(negedge clk);
@(negedge clk);
rdoverrun(0);
//data avaialble bit should be 0 as well
rddatardy(0);
//re-enable the modem
writerxen(1); //write a '1' to UART RXEN to enable it.
//we need flush our internal FIFO
head = 0; tail = 0;
//write one more datum to verify FIFO is restarted
putserialdata(9'h0A7);
checkdata();
$display("%t: All vectors done.",$time);
if (errors != 0)
$display("%t: FAIL, had %d errors during simulation.",$time,errors);
else
$display("%t: PASS, no errors during simulation.",$time);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1001; int n, a, b, u; int sol[N][N]; void W() { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { printf( %d , sol[i][j]); } printf( n ); } } int main() { cin >> n >> a >> b; if (a != 1 && b != 1) { cout << NO ; return 0; } if (a == 1 && b == 1) { if (n == 1) { printf( YES n0 ); return 0; } if (n <= 3) { cout << NO ; return 0; } printf( YES n ); for (int i = 1; i < n; i++) { sol[i][i + 1] = 1; sol[i + 1][i] = 1; } W(); return 0; } printf( YES n ); if (a != 1) u = a; else u = b; for (int i = 1; i <= n - u; i++) { sol[i][i + 1] = 1; sol[i + 1][i] = 1; } if (a != 1) { W(); return 0; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i != j) { sol[i][j] ^= 1; } } } W(); return 0; } |
#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; using ll = long long; using pll = pair<ll, ll>; template <class T> ostream &operator<<(ostream &os, const vector<T> &v) { for (const T &t : v) os << t << t; return os << endl; } template <class T> istream &operator>>(istream &is, vector<T> &v) { for (T &a : v) is >> a; return is; } template <class T, class U> ostream &operator<<(ostream &os, const pair<T, U> &v) { return os << < << v.first << << v.second << > ; } bool solve() { int q; cin >> q; map<pll, ll> cost; for (int i = 0; i < (int)(q); i++) { int t; cin >> t; if (t == 1) { ll v, u, w; cin >> v >> u >> w; set<ll> visited; { ll vv = v; while (vv) { visited.insert(vv); vv /= 2; } } ll lca = -1; { ll uu = u; while (!visited.count(uu)) uu /= 2; lca = uu; } assert(lca > 0); while (v > lca) { cost[make_pair(v / 2, v)] += w; v /= 2; } while (u > lca) { cost[make_pair(u / 2, u)] += w; u /= 2; } } else if (t == 2) { ll v, u; cin >> v >> u; ll sum = 0; set<ll> visited; { ll vv = v; while (vv) { visited.insert(vv); vv /= 2; } } ll lca = -1; { ll uu = u; while (!visited.count(uu)) uu /= 2; lca = uu; } assert(lca > 0); while (v > lca) { sum += cost[make_pair(v / 2, v)]; v /= 2; } while (u > lca) { sum += cost[make_pair(u / 2, u)]; u /= 2; } cout << sum << endl; } else assert(0); } return false; } int main() { cin.tie(0); ios::sync_with_stdio(false); while (solve()) ; return 0; } |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// Simualtion only memory controller
module mem_ctrl(
CLK,
RESETn,
ADDR,
DATA_IN,
MEM_REQ,
MEM_WRITE,
DATA_OUT,
MEM_ACK_OUT
);
parameter MEM_DEPTH = 65536;
parameter LC_MEM_DATA_WIDTH = 32;
parameter LC_MEM_ADDR_WIDTH = 32;
input CLK;
input RESETn;
input [LC_MEM_ADDR_WIDTH-3:0] ADDR;
input [LC_MEM_DATA_WIDTH-1:0] DATA_IN;
input MEM_REQ;
input MEM_WRITE;
output reg [LC_MEM_DATA_WIDTH-1:0] DATA_OUT;
output reg MEM_ACK_OUT;
`include "include/mbus_func.v"
wire [log2(MEM_DEPTH-1)-1:0] addr_equal = ADDR[log2(MEM_DEPTH-1)-1:0];
reg [LC_MEM_DATA_WIDTH-1:0] mem_array [0:MEM_DEPTH-1];
reg [1:0] fsm;
parameter IDLE = 2'b00;
parameter CLEAR = 2'b01;
parameter WRITE = 2'b10;
parameter READ = 2'b11;
integer idx;
initial
begin
for (idx=0; idx<(MEM_DEPTH); idx=idx+1)
begin
mem_array[idx] <= 0;
end
end
always @ (posedge CLK or negedge RESETn)
begin
if (~RESETn)
begin
fsm <= IDLE;
MEM_ACK_OUT <= 0;
DATA_OUT <= 0;
end
else
begin
case (fsm)
IDLE:
begin
if ((MEM_REQ) && (ADDR<MEM_DEPTH))
begin
if (MEM_WRITE)
fsm <= WRITE;
else
fsm <= READ;
end
end
WRITE:
begin
mem_array[addr_equal] <= DATA_IN;
MEM_ACK_OUT <= 1;
fsm <= CLEAR;
end
READ:
begin
DATA_OUT <= mem_array[addr_equal];
MEM_ACK_OUT <= 1;
fsm <= CLEAR;
end
CLEAR:
begin
if (~MEM_REQ)
begin
fsm <= IDLE;
MEM_ACK_OUT <= 0;
end
end
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_order_a (/*AUTOARG*/
// Outputs
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12,
// Inputs
clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
);
input clk;
input [7:0] a_to_clk_levm3;
input [7:0] b_to_clk_levm1;
input [7:0] c_com_levs10;
input [7:0] d_to_clk_levm2;
input [7:0] one;
output [7:0] m_from_clk_lev1_r;
output [7:0] n_from_clk_lev2;
output [7:0] o_from_com_levs11;
output [7:0] o_from_comandclk_levs12;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] m_from_clk_lev1_r;
// End of automatics
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
wire [7:0] a_to_clk_levm1;
wire [7:0] a_to_clk_levm2;
wire [7:0] c_com_levs11;
reg [7:0] o_from_comandclk_levs12;
wire [7:0] n_from_clk_lev2;
wire [7:0] n_from_clk_lev3;
assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2;
assign a_to_clk_levm2 = a_to_clk_levm3 + 0;
always @ (posedge clk) begin
m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1;
end
assign c_com_levs11 = c_com_levs10 + one;
always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3;
assign n_from_clk_lev2 = m_from_clk_lev1_r;
assign n_from_clk_lev3 = n_from_clk_lev2;
wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
#include <cstdio> #include <algorithm> using namespace std; #define ADD(x) ((x>=mod)?x-mod:x) const int mod=1e9+7; int n,c[110],b[110],sum[110],sum1[110],sumc[110],dp[110][10010],ans,Min,T,x; int main() { scanf( %d ,&n); for (int i=1;i<=n;i++) scanf( %d ,&c[i]),sumc[i]=sumc[i-1]+c[i]; for (int i=1;i<n;i++) scanf( %d ,&b[i]),sum[i]=sum[i-1]+b[i]; for (int i=1;i<=n;i++) sum1[i]=sum1[i-1]+sum[i-1]; scanf( %d%d ,&T,&x); dp[0][0]=1; for (int i=1;i<=n;i++) for (int j=x*i+sum1[i];j<=sumc[i];j++) for (int k=min(j,c[i]);k>=0;k--) dp[i][j]=ADD(dp[i][j]+dp[i-1][j-k]); for (int i=0;i<=sumc[n];i++) ans=ADD(ans+dp[n][i]); printf( %d n ,ans); return 0; } |
module VGA_Controller( // Host Side
iCursor_RGB_EN,
iCursor_X,
iCursor_Y,
iCursor_R,
iCursor_G,
iCursor_B,
iRed,
iGreen,
iBlue,
oAddress,
oCoord_X,
oCoord_Y,
// VGA Side
oVGA_R,
oVGA_G,
oVGA_B,
oVGA_H_SYNC,
oVGA_V_SYNC,
oVGA_SYNC,
oVGA_BLANK,
oVGA_CLOCK,
// Control Signal
iCLK,
iRST_N );
`include "VGA_Param.h"
// Host Side
output reg [19:0] oAddress;
output reg [9:0] oCoord_X;
output reg [9:0] oCoord_Y;
input [3:0] iCursor_RGB_EN;
input [9:0] iCursor_X;
input [9:0] iCursor_Y;
input [9:0] iCursor_R;
input [9:0] iCursor_G;
input [9:0] iCursor_B;
input [9:0] iRed;
input [9:0] iGreen;
input [9:0] iBlue;
// VGA Side
output [9:0] oVGA_R;
output [9:0] oVGA_G;
output [9:0] oVGA_B;
output reg oVGA_H_SYNC;
output reg oVGA_V_SYNC;
output oVGA_SYNC;
output oVGA_BLANK;
output oVGA_CLOCK;
// Control Signal
input iCLK;
input iRST_N;
// Internal Registers and Wires
reg [9:0] H_Cont;
reg [9:0] V_Cont;
reg [9:0] Cur_Color_R;
reg [9:0] Cur_Color_G;
reg [9:0] Cur_Color_B;
wire mCursor_EN;
wire mRed_EN;
wire mGreen_EN;
wire mBlue_EN;
assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC;
assign oVGA_SYNC = 1'b0;
assign oVGA_CLOCK = iCLK;
assign mCursor_EN = iCursor_RGB_EN[3];
assign mRed_EN = iCursor_RGB_EN[2];
assign mGreen_EN = iCursor_RGB_EN[1];
assign mBlue_EN = iCursor_RGB_EN[0];
assign oVGA_R = R_R;
//assign oVGA_R = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&
// V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
// ? (mRed_EN ? Cur_Color_R : 0) : 0;
assign oVGA_G = G_G;
//assign oVGA_G = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&
// V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
// ? (mGreen_EN ? Cur_Color_G : 0) : 0;
assign oVGA_B = B_B;
//assign oVGA_B = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&
// V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
// ? (mBlue_EN ? Cur_Color_B : 0) : 0;
// Pixel LUT Address Generator
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
oCoord_X <= 0;
oCoord_Y <= 0;
oAddress <= 0;
end
else
begin
if( H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
begin
oCoord_X <= H_Cont-X_START;
oCoord_Y <= V_Cont-Y_START;
oAddress <= oCoord_Y*H_SYNC_ACT+oCoord_X-3;
end
end
end
// Cursor Generator
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
Cur_Color_R <= 0;
Cur_Color_G <= 0;
Cur_Color_B <= 0;
end
else
begin
if( H_Cont>=X_START+8 && H_Cont<X_START+H_SYNC_ACT+8 &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
begin
if( ( (H_Cont==X_START + 8 + iCursor_X) ||
(H_Cont==X_START + 8 + iCursor_X+1) ||
(H_Cont==X_START + 8 + iCursor_X-1) ||
(V_Cont==Y_START + iCursor_Y) ||
(V_Cont==Y_START + iCursor_Y+1) ||
(V_Cont==Y_START + iCursor_Y-1) )
&& mCursor_EN )
begin
Cur_Color_R <= iCursor_R;
Cur_Color_G <= iCursor_G;
Cur_Color_B <= iCursor_B;
end
else
begin
Cur_Color_R <= iRed;
Cur_Color_G <= iGreen;
Cur_Color_B <= iBlue;
end
end
else
begin
Cur_Color_R <= iRed;
Cur_Color_G <= iGreen;
Cur_Color_B <= iBlue;
end
end
end
// H_Sync Generator, Ref. 25.175 MHz Clock
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_H_SYNC <= 0;
end
else
begin
// H_Sync Counter
if( H_Cont < H_SYNC_TOTAL )
H_Cont <= H_Cont+1;
else
H_Cont <= 0;
// H_Sync Generator
if( H_Cont < H_SYNC_CYC )
oVGA_H_SYNC <= 0;
else
oVGA_H_SYNC <= 1;
end
end
// V_Sync Generator, Ref. H_Sync
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_V_SYNC <= 0;
end
else
begin
// When H_Sync Re-start
if(H_Cont==0)
begin
// V_Sync Counter
if( V_Cont < V_SYNC_TOTAL )
V_Cont <= V_Cont+1;
else
V_Cont <= 0;
// V_Sync Generator
if( V_Cont < V_SYNC_CYC )
oVGA_V_SYNC <= 0;
else
oVGA_V_SYNC <= 1;
end
end
end
reg [9:0] R_R;
reg [9:0] G_G;
reg [9:0] B_B;
always@(posedge iCLK)
begin
R_R = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
? (mRed_EN ? Cur_Color_R : 0) : 0;
G_G = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
? (mGreen_EN ? Cur_Color_G : 0) : 0;
B_B = ( H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
? (mBlue_EN ? Cur_Color_B : 0) : 0;
end
endmodule |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_brams_7x.v
// Version : 1.11
// Description : pcie bram wrapper
// arrange and connect brams
// implement address decoding, datapath muxing and pipeline stages
//
// banks of brams are used for 1,2,4,8,18 brams
// brams are stacked for other values of NUM_BRAMS
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_brams_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
parameter TCQ = 1;
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
//synthesis translate_off
initial
begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_q;
reg [12:0] waddr_q;
reg [71:0] wdata_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
wen_q <= #TCQ 1'b0;
waddr_q <= #TCQ 13'b0;
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
// wdata_q <= #TCQ 72'b0;
end
else
begin
wen_q <= #TCQ wen;
waddr_q <= #TCQ waddr;
wdata_q <= #TCQ wdata;
end
end
assign wen_int = wen_q;
assign waddr_int = waddr_q;
assign wdata_int = wdata_q;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_q;
reg [12:0] raddr_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
ren_q <= #TCQ 1'b0;
raddr_q <= #TCQ 13'b0;
end
else
begin
ren_q <= #TCQ ren;
raddr_q <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_q;
assign raddr_int = raddr_q;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_q;
always @(posedge user_clk_i) begin
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
//if (reset_i)
//begin
// rdata_q <= #TCQ 72'b0;
//end
//else
//begin
rdata_q <= #TCQ rdata_int;
//end // else: !if(reset_i)
end
assign rdata = rdata_q;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar ii;
for (ii = 0; ii < NUM_BRAMS; ii = ii + 1) begin : brams
pcie_7x_v1_11_0_pcie_bram_7x #(
.LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.IMPL_TARGET (IMPL_TARGET),
.DOB_REG (DOB_REG),
.WIDTH (WIDTH)
)
ram (
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.wen_i(wen_int),
.waddr_i(waddr_int),
.wdata_i(wdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.ren_i(ren_int),
.raddr_i(raddr_int),
.rdata_o(rdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.rce_i(rce)
);
end
endgenerate
endmodule // pcie_brams_7x
|
#include <bits/stdc++.h> using namespace std; void dfs3(int v, vector<vector<int>> &graf, vector<int> &ways) { ways[v] = -1; for (auto el : graf[v]) { if (ways[el] != -1) { dfs3(el, graf, ways); } } } void dfs2(int v, vector<vector<int>> &graf, vector<int> &ways) { ways[v] = 2; for (auto el : graf[v]) { if (ways[el] == 1) { dfs2(el, graf, ways); } } } void dfs(int v, vector<int> &vis, vector<int> &cycle, vector<vector<int>> &graf, vector<int> &ways, vector<int> &progr) { if (progr[v] == 1) { cycle.push_back(v); ways[v] = -1; } else if (progr[v] == 2) { vis.push_back(v); ways[v] = 2; } else { progr[v] = 1; for (auto el : graf[v]) { dfs(el, vis, cycle, graf, ways, progr); } progr[v] = 2; ways[v] = 1; } } int main() { ios::sync_with_stdio(false); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; if (m == 0) { cout << 1 << ; for (int i = 1; i != n; i++) { cout << 0 << ; } } else { vector<vector<int>> graf(n); vector<int> ways(n, 0); vector<int> progr(n, 0); // 1 - in progress, 0 - new, 2 - visited vector<int> cycle; vector<int> vis; for (int i = 0; i != m; i++) { int s, f; cin >> s >> f; graf[s - 1].push_back(f - 1); } dfs(0, vis, cycle, graf, ways, progr); for (auto el : vis) { dfs2(el, graf, ways); } for (auto el : cycle) { dfs3(el, graf, ways); } for (auto el : ways) { cout << el << ; } } cout << n ; } return 0; } |
module CARRY4(
output [3:0] CO,
output [3:0] O,
input CI,
input CYINIT,
input [3:0] DI, S
);
parameter _TECHMAP_CONSTMSK_CI_ = 1;
parameter _TECHMAP_CONSTVAL_CI_ = 1'b0;
parameter _TECHMAP_CONSTMSK_CYINIT_ = 1;
parameter _TECHMAP_CONSTVAL_CYINIT_ = 1'b0;
localparam [0:0] IS_CI_ZERO = (
_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 0 &&
_TECHMAP_CONSTMSK_CYINIT_ == 1 && _TECHMAP_CONSTVAL_CYINIT_ == 0);
localparam [0:0] IS_CI_ONE = (
_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 0 &&
_TECHMAP_CONSTMSK_CYINIT_ == 1 && _TECHMAP_CONSTVAL_CYINIT_ == 1);
localparam [0:0] IS_CYINIT_FABRIC = _TECHMAP_CONSTMSK_CYINIT_ == 0;
localparam [0:0] IS_CI_DISCONNECTED = _TECHMAP_CONSTMSK_CI_ == 1 &&
_TECHMAP_CONSTVAL_CI_ != 1;
localparam [0:0] IS_CYINIT_DISCONNECTED = _TECHMAP_CONSTMSK_CYINIT_ == 1 &&
_TECHMAP_CONSTVAL_CYINIT_ != 1;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
wire [3:0] O;
wire [3:0] CO;
wire [3:0] CO_output;
// Put in a placeholder object CARRY_CO_DIRECT.
//
// It will be used for 3 purposes:
// - Remain as CARRY_CO_DIRECT when OUT only connects to CARRY_COUT_PLUG
// - Remain as CARRY_CO_DIRECT when CO is used, but O is not used.
// - Change into CARRY_CO_LUT when O and CO are required (e.g. compute CO
// from O ^ S).
genvar i;
generate for (i = 0; i < 3; i = i + 1) begin:co_outputs
CARRY_CO_DIRECT #(.TOP_OF_CHAIN(0)) co_output(
.CO(CO_output[i]),
.O(O[i+1]),
.S(S[i+1]),
.OUT(CO[i])
);
end endgenerate
CARRY_CO_DIRECT #(.TOP_OF_CHAIN(1)) co_output(
.CO(CO_output[3]),
.O(O[3]),
.S(S[3]),
.DI(DI[3]),
.OUT(CO[3])
);
if(IS_CYINIT_FABRIC) begin
CARRY4_VPR #(
.CYINIT_AX(1'b1),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.CYINIT(CYINIT),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3])
);
end else if(IS_CI_ZERO || IS_CI_ONE) begin
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(IS_CI_ZERO),
.CYINIT_C1(IS_CI_ONE)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3])
);
end else begin
wire cin_from_below;
CARRY_COUT_PLUG cin_plug(
.CIN(CI),
.COUT(cin_from_below)
);
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3]),
.CIN(cin_from_below)
);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool cmp1(vector<int> a, vector<int> b) { int q = a[4] + a[1] + a[2] + a[3] - a[0]; int p = b[4] + b[1] + b[2] + b[3] - b[0]; return q < p; } bool cmp2(vector<int> a, vector<int> b) { int q = a[0] + a[4] + a[2] + a[3] - a[1]; int p = b[0] + b[4] + b[2] + b[3] - b[1]; return q < p; } bool cmp3(vector<int> a, vector<int> b) { int q = a[0] + a[1] + a[4] + a[3] - a[2]; int p = b[0] + b[1] + b[4] + b[3] - b[2]; return q < p; } bool cmp4(vector<int> a, vector<int> b) { int q = a[0] + a[1] + a[2] + a[4] - a[3]; int p = b[0] + b[1] + b[2] + b[4] - b[3]; return q < p; } bool cmp5(vector<int> a, vector<int> b) { int q = a[0] + a[1] + a[2] + a[3] - a[4]; int p = b[0] + b[1] + b[2] + b[3] - b[4]; return q < p; } int main() { ios::sync_with_stdio(false); cin.tie(0); int T = 1; cin >> T; while (T--) { int n; cin >> n; vector<vector<int>> fr(n, vector<int>(5, 0)); string s[n]; for (int i = 0; i < n; i++) { cin >> s[i]; for (int j = 0; j < s[i].size(); j++) { if (s[i][j] == a ) fr[i][0]++; if (s[i][j] == b ) fr[i][1]++; if (s[i][j] == c ) fr[i][2]++; if (s[i][j] == d ) fr[i][3]++; if (s[i][j] == e ) fr[i][4]++; } } int ans = 0, cw = 0; sort(fr.begin(), fr.end(), cmp1); int cs = 0, co = 0; for (int i = 0; i < n; i++) { cs = cs + fr[i][0]; co = co + fr[i][1] + fr[i][2] + fr[i][3] + fr[i][4]; if (cs > co) cw++; } ans = max(ans, cw); cw = 0; cs = 0, co = 0; sort(fr.begin(), fr.end(), cmp2); for (int i = 0; i < n; i++) { cs = cs + fr[i][1]; co = co + fr[i][0] + fr[i][2] + fr[i][3] + fr[i][4]; if (cs > co) cw++; } ans = max(ans, cw); cw = 0; cs = 0, co = 0; sort(fr.begin(), fr.end(), cmp3); for (int i = 0; i < n; i++) { cs = cs + fr[i][2]; co = co + fr[i][1] + fr[i][0] + fr[i][3] + fr[i][4]; if (cs > co) cw++; } ans = max(ans, cw); cw = 0; cs = 0, co = 0; sort(fr.begin(), fr.end(), cmp4); for (int i = 0; i < n; i++) { cs = cs + fr[i][3]; co = co + fr[i][1] + fr[i][2] + fr[i][0] + fr[i][4]; if (cs > co) cw++; } ans = max(ans, cw); cw = 0; cs = 0, co = 0; sort(fr.begin(), fr.end(), cmp5); for (int i = 0; i < n; i++) { cs = cs + fr[i][4]; co = co + fr[i][1] + fr[i][2] + fr[i][3] + fr[i][0]; if (cs > co) cw++; } ans = max(ans, cw); cout << ans << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_SYMBOL_V
`define SKY130_FD_SC_LS__NAND4_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n, m; cin >> n >> m; vector<int> a(n), b(n); for (int i = (0); i < (m); i++) { int x, y; cin >> x >> y; --x; --y; y = (y - x + n) % n; b[x] = a[x]++ ? min(b[x], y) : y; } for (int i = (0); i < (n); i++) if (a[i]) { a[i] = a[i] * n + b[i] + i; b[i] = a[i] - n; } for (int i = (0); i < (n); i++) if (i) a[i] = max(a[i], a[i - 1]); for (int i = (n); i-- > (0);) if (i < n - 1) b[i] = max(b[i], b[i + 1]); for (int i = (0); i < (n); i++) cout << max(i ? a[i - 1] : 0, b[i]) - i << ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:22:15 11/18/2013
// Design Name:
// Module Name: text_editor_RAM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module text_editor_RAM(
input clk,
input Reset,
input write,
input [ADDR_WIDTH-1:0] write_address,
input [DATA_WIDTH-1:0] write_data,
input [ADDR_WIDTH-1:0] read_address,
output [DATA_WIDTH-1:0] read_data
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] data [0:RAM_DEPTH-1]; // Array to store 512 8-bit words (characters)
always @ (posedge clk, posedge Reset) begin: RAM_logic
if (Reset) begin: Reset
integer i;
for (i = 0; i < RAM_DEPTH; i = i + 1) begin
data[i] <= 8'h29; // a "Space"
end
end else if (write) begin
data[write_address] <= write_data;
end
end
assign read_data = data[read_address];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__AND4_BEHAVIORAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; vector<long long int> v(n), vv; for (int i = 0; i < n; i++) cin >> v[i]; long long int mx = *max_element(v.begin(), v.end()); int len = 0, fg = 0; for (long long int i = 0; i < n; i++) { if (v[i] == mx) { long long int j = i; while (v[j] == mx && j <= n - 1) j++; vv.push_back(j - i); i = j; } } sort(vv.begin(), vv.end()); cout << vv[vv.size() - 1]; return 0; } |
module cpu_vreg(
input wire clk,
input wire copy_in_progress,
input wire cpu_rd,
input wire cpu_wr,
input wire cpu_mreq,
output reg [7:0] copy_enable,
input wire [15:0] cpu_addr,
inout wire [7:0] cpu_data,
output reg back_vram_wr_low,
output reg back_vram_rd_low,
output reg [12:0] back_vram_addr,
output reg [7:0] back_vram_data
);
reg vram_read;
assign cpu_data = vram_read ? back_vram_data : 8'bzzzzzzzz;
always @(posedge clk)
begin
if(cpu_rd == 1 && cpu_wr == 0 && cpu_mreq == 0 && cpu_addr == 16'h92c1) begin
copy_enable = cpu_data;
end
else if(copy_in_progress == 0 && cpu_rd == 1 && cpu_wr == 0 && cpu_mreq == 0 && cpu_addr >= 16'h8000 && cpu_addr <= 16'h92bf) begin
back_vram_addr = cpu_addr[12:0];
back_vram_data = cpu_data;
back_vram_wr_low = 0;
vram_read = 0;
end
else if(copy_in_progress == 0 && cpu_rd == 0 && cpu_wr == 1 && cpu_mreq == 0 && cpu_addr >= 16'h8000 && cpu_addr <= 16'h92bf) begin
back_vram_addr = cpu_addr[12:0];
back_vram_rd_low = 0;
vram_read = 1;
end
else begin
back_vram_wr_low = 1;
back_vram_addr = 13'bzzzzzzzzzzzzz;
back_vram_data = 8'bzzzzzzzz;
back_vram_rd_low = 1'bz;
vram_read = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = LLONG_MAX; int main() { string s; cin >> s; int x = s.size(); cout << 26 * (x + 1) - x; return 0; } |
#include <bits/stdc++.h> using namespace std; int t[35], mp[400][400], n; void dfs(int step, int x, int y, int dir) { if (step > n) return; if (dir == 0) { dfs(step + 1, x, y + t[step], 1 - dir); for (int i = 0; i < 400; i++) for (int j = 0; j < 400; j++) if (mp[i][j]) { mp[i][j] = mp[x * 2 - i][j] = 1; } for (int i = 1; i <= t[step]; i++) mp[x][y + i] = 1; } else { dfs(step + 1, x + t[step], y + t[step], 1 - dir); int b = y - x; for (int i = 0; i < 400; i++) for (int j = 0; j < 400; j++) if (mp[i][j]) { mp[i][j] = mp[j - b][i + b] = 1; } for (int i = 1; i <= t[step]; i++) { mp[x + i][y + i] = 1; } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , t + i); memset(mp, 0, sizeof(mp)); dfs(1, 200, 199, 0); int ans = 0; for (int i = 0; i < 400; i++) for (int j = 0; j < 400; j++) if (mp[i][j]) ans++; cout << ans << endl; return 0; } |
/*TODO:
Test byte masks
Add timeout
Test linear burst from 0xffffffff
Add support for settings address ranges
*/
module wb_master
#(parameter aw = 32,
parameter dw = 32,
parameter VERBOSE = 0,
parameter MAX_BURST_LEN = 500)
(input wb_clk_i,
input wb_rst_i,
output [aw-1:0] wb_adr_o,
output [dw-1:0] wb_dat_o,
output [3:0] wb_sel_o,
output wb_we_o,
output wb_cyc_o,
output wb_stb_o,
output [2:0] wb_cti_o,
output [1:0] wb_bte_o,
input [dw-1:0] wb_dat_i,
input wb_ack_i,
input wb_err_i,
input wb_rty_i);
`include "wb_bfm_params.v"
integer SEED = 2;
integer TRANSACTIONS;
initial
if(!$value$plusargs("transaction=%d", TRANSACTIONS))
TRANSACTIONS = 1000;
wb_bfm_master
#(.MAX_BURST_LENGTH (MAX_BURST_LEN))
bfm
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wb_adr_o),
.wb_dat_o (wb_dat_o),
.wb_sel_o (wb_sel_o),
.wb_we_o (wb_we_o),
.wb_cyc_o (wb_cyc_o),
.wb_stb_o (wb_stb_o),
.wb_cti_o (wb_cti_o),
.wb_bte_o (wb_bte_o),
.wb_dat_i (wb_dat_i),
.wb_ack_i (wb_ack_i),
.wb_err_i (wb_err_i),
.wb_rty_i (wb_rty_i));
reg [dw*MAX_BURST_LEN-1:0] write_data;
reg [dw*MAX_BURST_LEN-1:0] read_data;
reg [dw*MAX_BURST_LEN-1:0] expected_data;
integer word;
integer burst_length;
reg [2:0] burst_type;
integer transaction;
integer tmp, burst_wrap;
reg err;
reg [aw-1:0] address;
initial begin
for(transaction = 0 ; transaction < TRANSACTIONS; transaction = transaction + 1) begin
tmp = $random;
address = {20'h0000,tmp[11:0]};//FIXME Check address range against memory model
burst_length = ({$random(SEED)} % MAX_BURST_LEN) + 1;
for(word = 0; word < burst_length; word = word + 1)
write_data[dw*word+:dw] = $random;
burst_type = ({$random(SEED)} % 4);
bfm.write_burst(address, write_data, 4'hf, burst_length, burst_type, err);
@(posedge wb_clk_i);
bfm.read_burst(address, read_data, 4'hf, burst_length, burst_type, err);
@(posedge wb_clk_i);
case (burst_type)
LINEAR_BURST : burst_wrap = burst_length;
WRAP_4_BURST : burst_wrap = 4;
WRAP_8_BURST : burst_wrap = 8;
WRAP_16_BURST : burst_wrap = 16;
CONSTANT_BURST : burst_wrap = 1;
default : $error("%d : Illegal burst type (%b)", $time, burst_type);
endcase
tmp = burst_length-1;
for(word = burst_length-1 ; word >= 0 ; word = word - 1) begin
expected_data[dw*word+:dw] = write_data[dw*tmp+:dw];
tmp = tmp - 1;
if(tmp < burst_length - burst_wrap)
tmp = burst_length-1;
end
for(word = 0 ; word < burst_length ; word = word +1)
if(read_data[word*dw+:dw] !== expected_data[word*dw+:dw]) begin
$error("Read data mismatch on address %h (burst length=%0d, burst_type=%0d, iteration %0d)", address, burst_length, burst_type, word);
$error("Expected %h", expected_data[word*dw+:dw]);
$error("Got %h", read_data[word*dw+:dw]);
$finish;
end
if (VERBOSE) $display("Read ok from address %h (burst length=%0d, burst_type=%0d)", address, burst_length, burst_type);
end // for (i = 1 ; i < 10; i = i + 1)
$display("All tests passed!");
#3 $finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/01/23 23:55:53
// Design Name:
// Module Name: VGA_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VGA_top(
input clk,
input rst,
input [1:0]snake,
input [5:0]apple_x,
input [4:0]apple_y,
output [9:0]x_pos,
output [9:0]y_pos,
output hsync,
output vsync,
output [11:0] color_out
);
wire clk_n;
clk_unit myclk(
.clk(clk),
.rst(rst),
.clk_n(clk_n)
);
VGA_Control VGA
(
.clk(clk_n),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.snake(snake),
.color_out(color_out),
.x_pos(x_pos),
.y_pos(y_pos),
.apple_x(apple_x),
.apple_y(apple_y)
);
endmodule
|
#include <bits/stdc++.h> int res[1000008]; using namespace std; int main() { bool pr[1000008 + 1]; memset(pr, true, sizeof(pr)); int cnt = 0; for (int p = 2; p * p <= 1000008; p++) { if (pr[p] == true) { for (int j = p * p; j <= 1000008; j += p) pr[j] = false; } } for (int i = 2; i <= 1000008; i++) { if (pr[i]) { cnt++; } res[i] = cnt; } ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; int k = sqrt(n); int r = res[n] - res[k]; cout << r + 1 << n ; } } |
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4,
CFG_MM_ST_CONV_REG = 0
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
localparam AVL_BE_WIDTH = AVL_DATA_WIDTH / 8;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_BE_WIDTH-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_BE_WIDTH-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
wire [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
reg avl_read_req_reg;
reg avl_write_req_reg;
reg [AVL_SIZE_WIDTH-1:0] avl_size_reg;
reg avl_burstbegin_reg;
reg [AVL_ADDR_WIDTH-1:0] avl_addr_reg;
reg [AVL_DATA_WIDTH-1:0] avl_wdata_reg;
reg [AVL_DATA_WIDTH/8-1:0] avl_be_reg;
reg itf_rd_data_valid_reg;
reg [AVL_DATA_WIDTH-1:0] itf_rd_data_reg;
reg [3:0] itf_rd_data_error_reg;
reg local_multicast_reg;
reg local_autopch_req_reg;
reg local_priority_reg;
generate
if (CFG_MM_ST_CONV_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
avl_read_req_reg <= 1'b0;
avl_write_req_reg <= 1'b0;
avl_size_reg <= {AVL_SIZE_WIDTH{1'b0}};
avl_burstbegin_reg <= 1'b0;
avl_addr_reg <= {AVL_ADDR_WIDTH{1'b0}};
avl_wdata_reg <= {AVL_DATA_WIDTH{1'b0}};
avl_be_reg <= {AVL_BE_WIDTH{1'b0}};
itf_rd_data_valid_reg <= 1'b0;
itf_rd_data_reg <= {AVL_DATA_WIDTH{1'b0}};
itf_rd_data_error_reg <= 4'b0;
local_multicast_reg <= 1'b0;
local_autopch_req_reg <= 1'b0;
local_priority_reg <= 1'b0;
end else
begin
if (int_ready)
begin
avl_read_req_reg <= avl_read_req;
avl_write_req_reg <= avl_write_req;
avl_size_reg <= avl_size;
avl_burstbegin_reg <= avl_burstbegin;
avl_addr_reg <= avl_addr;
avl_wdata_reg <= avl_wdata;
avl_be_reg <= avl_be;
local_multicast_reg <= local_multicast;
local_autopch_req_reg <= local_autopch_req;
local_priority_reg <= local_priority;
end
itf_rd_data_valid_reg <= itf_rd_data_valid;
itf_rd_data_reg <= itf_rd_data;
itf_rd_data_error_reg <= itf_rd_data_error;
end
end
end else
begin
always @ (*)
begin
avl_read_req_reg = avl_read_req;
avl_write_req_reg = avl_write_req;
avl_size_reg = avl_size;
avl_burstbegin_reg = avl_burstbegin;
avl_addr_reg = avl_addr;
avl_wdata_reg = avl_wdata;
avl_be_reg = avl_be;
itf_rd_data_valid_reg = itf_rd_data_valid;
itf_rd_data_reg = itf_rd_data;
itf_rd_data_error_reg = itf_rd_data_error;
local_multicast_reg = local_multicast;
local_autopch_req_reg = local_autopch_req;
local_priority_reg = local_priority;
end
end
endgenerate
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req_reg | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req_reg & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr_reg ;
assign itf_cmd_burstlen = avl_size_reg ;
assign itf_cmd_autopercharge = local_autopch_req_reg ;
assign itf_cmd_priority = local_priority_reg ;
assign itf_cmd_multicast = local_multicast_reg ;
assign itf_cmd = avl_write_req_reg;
assign itf_cmd_id = {LOCAL_ID_WIDTH{1'b0}};
assign itf_wr_data_begin = 1'b0;
assign itf_wr_data_last = 1'b0;
assign itf_wr_data_id = {LOCAL_ID_WIDTH{1'b0}};
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req_reg : itf_cmd_ready & avl_write_req_reg;
assign itf_wr_data = avl_wdata_reg ;
assign itf_wr_data_byte_en = avl_be_reg ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid_reg;
assign avl_rdata = itf_rd_data_reg;
assign local_rdata_error = itf_rd_data_error_reg;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= {AVL_SIZE_WIDTH{1'b0}};
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
burst_counter <= avl_size_reg - 1'b1;
else if (avl_write_req_reg && itf_wr_data_ready)
burst_counter <= burst_counter - 1'b1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 1'b0;
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
data_pass <= 1'b1;
else if (burst_counter == 1 && avl_write_req_reg && itf_wr_data_ready)
data_pass <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 10; const int B = 1e3 + 10; bool vis[N], inque[2 * N]; int n, k; vector<int> v; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < k; i++) { int t; scanf( %d , &t); if (!vis[t]) { vis[t] = true; v.push_back(t); } } for (int i = 0; i < v.size(); i++) { v[i] -= n; } queue<pair<int, int>> Q; Q.push(make_pair(0, 0)); inque[B] = true; while (!Q.empty()) { pair<int, int> t = Q.front(); Q.pop(); inque[t.first + B] = 0; for (int i = 0; i < v.size(); i++) { int u = v[i] + t.first; if (u < -1000 || u > 1000) continue; if (!inque[u + B]) { if (u == 0) { printf( %d n , t.second + 1); return 0; } inque[u + B] = true; Q.push(make_pair(u, t.second + 1)); } } } printf( -1 n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_TB_V
`define SKY130_FD_SC_LP__AND2_TB_V
/**
* and2: 2-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__and2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_TB_V
|
#include <bits/stdc++.h> using namespace std; int a[300007][15]; int ans[300007], cnt[15]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (auto i = (1); i <= (n); ++i) { for (auto j = (1); j <= (m); ++j) { scanf( %d , &a[i][j]); } } for (auto i = (1); i <= (k); ++i) { int x, y; scanf( %d%d , &x, &y); --ans[x]; ++cnt[y]; } for (auto j = (1); j <= (m); ++j) { for (auto i = (1); i <= (n); ++i) { if (a[i][j]) ans[i] += cnt[j]; } } for (auto i = (1); i <= (n); ++i) printf( %d , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int maxn = 205; int fail[maxn + 5]; int nxt[maxn + 5][maxn + 5]; long long dp[maxn + 5][maxn + 5][maxn + 5]; char s[maxn + 5]; int n, len; void Get_fail() { fail[0] = -1; int j = 0, k = -1; while (j <= len) { if (k == -1 || s[j] == s[k]) fail[++j] = ++k; else k = fail[k]; } } void Get_nxt() { for (int i = 0; i <= len; i++) { for (int j = 0; j <= 1; j++) { if (i == len) nxt[i + 1][j] = len; else { char ch = (j == 0 ? ) : ( ); int r = i; while (r >= 0 && s[r] != ch) r = fail[r]; if (s[r] == ch || r == -1) r++; nxt[i + 1][j] = r; } } } } long long DP() { dp[0][0][0] = 1; for (int i = 0; i <= 2 * n; i++) { for (int j = 0; j <= min(i, n); j++) { for (int k = 0; k <= len; k++) { for (int p = 0; p <= 1; p++) { if (dp[i][j][k] == 0) continue; int nj = j - (p == 0 ? 1 : -1); if (nj >= 0 && nj <= n) { int nk = nxt[k + 1][p]; dp[i + 1][nj][nk] = (dp[i + 1][nj][nk] + dp[i][j][k]) % mod; } } } } } return dp[2 * n][0][len]; } void Init() { len = strlen(s); Get_fail(); Get_nxt(); } int main() { scanf( %d , &n); scanf( %s , s); Init(); printf( %lld n , DP()); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_SYMBOL_V
`define SKY130_FD_SC_HS__O21AI_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; long long cur = 9; long long ans = 0; long long dig = 1; cin >> n; while (n > 0) { ans += min(n * dig, cur * dig); n -= cur; cur *= 10; dig++; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { ios::sync_with_stdio(false); long long n, m, k; cin >> n >> m >> k; long long x, s; cin >> x >> s; pair<long long, long long> a[m]; for (int i = 0; i < m; i++) cin >> a[i].second; for (int i = 0; i < m; i++) cin >> a[i].first; sort(a, a + m); pair<long long, long long> c[k]; for (int i = 0; i < k; i++) cin >> c[i].first; for (int i = 0; i < k; i++) cin >> c[i].second; long long mn[m]; mn[0] = a[0].second; for (int i = 1; i < m; i++) { mn[i] = min(mn[i - 1], a[i].second); } long long ans = n * x; for (int i = 0; i < m; i++) { if (a[i].first <= s) ans = min(ans, n * a[i].second); } for (int i = 0; i < k; i++) { if (c[i].second > s) break; int t = c[i].first; int k = upper_bound(a, a + m, pair<long long, long long>(s - c[i].second, 1LL << 60)) - a; k--; if (k >= 0) { ans = min(ans, (n - t) * min(x, mn[k])); } ans = min(ans, (n - t) * x); } ans = max(ans, 0LL); printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> int main() { int n, s, p, i, c; scanf( %d , &n); s = 1; while (1) { c = 0; p = n * s + 1; for (i = 2; i < p; i++) { if (p % i == 0) { c++; } } if (c >= 1) { break; } s++; } printf( %d n , s); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; pair<int, int> calc(int a, int b) { if (a <= b) return {a, 0}; int r = a / b; if (a % b == 0) return {b, r - 1}; return {a / (r + 1), r}; } vector<pair<int, int>> compact(const vector<pair<int, int>>& V) { vector<pair<int, int>> R; int p = -1, c = 0; for (auto [a, b] : V) { if (a != p && p != -1) { R.emplace_back(p, c); c = 0; } p = a; c += b; } R.emplace_back(p, c); return R; } int main() { ios_base::sync_with_stdio(false); int tn; cin >> tn; for (int ti = 0; ti < tn; ++ti) { int n; cin >> n; vector<int> A(n); for (int& a : A) cin >> a; vector<pair<int, int>> B; uint64_t r = 0; for (int i = n - 1; i > 0; --i) { B.emplace_back(A[i], 1); vector<pair<int, int>> C; for (auto [x, y] : B) { auto [z, t] = calc(A[i - 1], x); C.emplace_back(z, y); r = (r + 1ull * t * i * y) % MOD; } sort(C.begin(), C.end()); B = compact(C); } cout << r << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int N, ANS, X[201], Y[201]; char S[205]; int main() { scanf( %d %s , &N, S); for (int i = 0; i < N; i++) { X[i + 1] += X[i], Y[i + 1] += Y[i]; char c = S[i]; if (c == U ) Y[i + 1]++; if (c == R ) X[i + 1]++; if (c == D ) Y[i + 1]--; if (c == L ) X[i + 1]--; } for (int i = 1; i <= N; i++) for (int j = i; j <= N; j++) ANS += (X[j] - X[i - 1] == 0 && Y[j] - Y[i - 1] == 0); printf( %d n , ANS); } |
#include <bits/stdc++.h> namespace { using namespace std; template <typename T> inline bool whitespace(const vector<T> &) { return false; } template <typename T> inline bool whitespace(const T &) { return true; } inline bool whitespace(const char) { return false; } template <typename S, typename T> ostream &operator<<(ostream &os, const pair<S, T> &p) { os << p.first << (whitespace(p.second) ? : ) << p.second << n ; return os; } template <typename S, typename T> istream &operator>>(istream &is, pair<S, T> &p) { is >> p.first >> p.second; return is; } template <typename T> istream &operator>>(istream &is, vector<T> &v) { for (T &t : v) is >> t; return is; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (const T &t : v) { os << t << (whitespace(t) ? : ); } os << n ; return os; } template <typename T> istream &operator>>(istream &is, deque<T> &v) { for (T &t : v) is >> t; return is; } template <typename T> ostream &operator<<(ostream &os, const deque<T> &v) { for (const T &t : v) { os << t << (whitespace(t) ? : ); } os << n ; return os; } template <typename T> T gcd(T a, T b) { while (b) { T mod = a % b; a = b; b = mod; } return a; } template <typename T> T sum(const vector<T> &v) { T s = 0; for (T value : v) s += value; return s; } template <typename T> vector<T> prefix_sum(const vector<T> &v) { vector<T> res(v.size() + 1); res[0] = 0; for (long long i = 0; i < v.size(); ++i) res[i + 1] = res[i] + v[i]; return res; } template <typename S, typename T> S min(S a, T b) { return a < (S)b ? a : b; } template <typename S, typename T> S max(S a, T b) { return a < (S)b ? b : a; } class exit_exception : exception {}; istream &in = cin; ostream &out = cout; template <typename T> void answer(T ans) { out << ans << n ; throw exit_exception(); } struct autoint { long long x; autoint() { in >> x; } operator long long() { return x; } autoint(autoint &i) { x = i.x; } long long operator--() { return --x; } long long operator--(signed) { return x--; } long long operator++() { return ++x; } long long operator++(signed) { return x++; } }; template <typename T> struct autoread : T { template <typename... Args> autoread(Args &&...args) : T(args...) { in >> *dynamic_cast<T *>(this); } }; } // namespace void solve(); signed main() { cin.tie(nullptr); cout.tie(nullptr); ios::sync_with_stdio(false); long long t = 1; cin >> t; do { try { solve(); } catch (exit_exception &) { } } while (--t); return 0; } void solve() { autoint n, k; string s; cin >> s; vector<map<char, long long>> groups((k + 1) / 2); for (long long i = 0; i < (k + 1) / 2; ++i) { for (long long j = i; j < n; j += k) groups[i][s[j]]++; if (i + i < k - 1) for (long long j = k - i - 1; j < n; j += k) groups[i][s[j]]++; } long long ans = 0; for (auto m : groups) { vector<long long> cnts; for (auto p : m) cnts.push_back(p.second); stable_sort(cnts.rbegin(), cnts.rend()); ans += accumulate(cnts.begin(), cnts.end(), 0ll) - cnts.front(); } answer(ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_SYMBOL_V
|
#include <bits/stdc++.h> #define ff first #define ss second #define ll long long #define ld long double #define pb push_back #define eb emplace_back #define mp make_pair #define mt make_tuple #define pii pair<int, int> #define pll pair<ll,ll> #define vi vector<int> #define vl vector<ll> #define vii vector<pii> #define sws ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); #define endl n #define teto(a, b) ((a+b-1)/(b)) using namespace std; // Extra #define forn(i, n) for(int i = 0; i < (int)n; i++) #define forne(i, a, b) for(int i = a; i <= b; i++) #define all(x) x.begin(), x.end() #define dbg(msg, var) cout << msg << << var << endl; // const int MAX = 200010; const ll MOD = (int)1e9 +7; const int INF = 1e9; const ll LLINF = 0x3f3f3f3f3f3f3f3f; const ld EPS = 1e-8; int n, l, r, s; vector<vector<bool>> tab; vector<vector<bool>> btab; int dp(int idx, int soma) { if(soma > s) return 0; if(idx >= n) { return (soma == s); } if(btab[idx][soma]) return tab[idx][soma]; // cout << idx << << soma << endl; int res = 0; int pega = dp(idx+1, soma + idx+1); int npega = dp(idx+1, soma); if(npega >= pega) { res = npega; } else { res = pega; } btab[idx][soma] = true; return tab[idx][soma] = res; } vi solve(vi vals, int sz, bool& ruim) { int t = vals.size(); vi foi(n+1, 0); forn(i, t) foi[vals[i]] = 1; ruim = false; while(t < sz and !ruim) { bool brk = false; forne(i, 1, n) { if(!foi[i]) continue; forne(j, 1, i-1) { if(j == i-j) continue; if(!foi[j] and !foi[i-j]) { foi[i] = 0; foi[j] = 1; foi[i-j] = 1; t++; brk = true; break; } } if(brk) break; } if(!brk) ruim = true; } return foi; } int32_t main() { // sws; int t; cin >> t; while(t--) { cin >> n >> l >> r >> s; tab.assign(n, vector<bool>(s+1, -1)); btab.assign(n, vector<bool>(s+1, 0)); bool win = dp(0, 0); if(win) { vi vals, p(n+1, -1); set<int> pos; forne(i, 1, n) pos.insert(i); int idx = 0, soma = 0; while(idx < n) { if(dp(idx+1, soma)) { idx++; } else { soma += idx+1; vals.pb(idx+1); idx++; } } if(vals.size() > (r-l+1)) { cout << -1 << endl; continue; } bool ruim; // for(auto val : vals) cout << val << ; // cout << endl; vi foi = solve(vals, (r-l+1), ruim); // cout << ruim = << ruim << endl; // forne(i, 1, n) cout << foi[i] << ; // cout << endl; if(ruim) cout << -1 << endl; else { int id1 = 1, id2 = 1; forne(i, 1, n) { if(l <= i and i <= r) { while(id1 <= n and !foi[id1]) id1++; cout << id1 << ; id1++; } else { while(id2 <= n and foi[id2]) id2++; cout << id2 << ; id2++; } } cout << endl; } } else { cout << -1 << endl; } } // verificar limites, long long return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = 0; while (s.at(n) != . ) n++; if (s.at(n - 1) == 9 ) cout << GOTO Vasilisa. ; else { if (s.at(n + 1) < 53) cout << s.substr(0, n); else { cout << s.substr(0, n - 1); cout << (char)(s.at(n - 1) + 1); } } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; string s1, s2; int n, m; long long dp[maxn][3][3]; int p1[maxn], p2[maxn]; int f(char a) { return a == G ? 0 : (a == R ? 1 : 2); } void init(const string s, int n, const string t, int m, int p[]) { p[0] = 0; while (p[0] < m && s[0] != t[p[0]]) p[0]++; p[0] = min(p[0], m - 1); for (int i = 1; i < n; i++) { p[i] = p[i - 1] + 1; while (p[i] < m && s[i] != t[p[i]]) p[i]++; p[i] = min(p[i], m - 1); } } int main() { cin >> s1; cin >> s2; n = s1.size(); m = s2.size(); init(s1, n, s2, m, p1); init(s2, m, s1, n, p2); memset(dp, 0ll, sizeof(dp)); for (int i = 1; i < m; i++) { for (int j = 0; j < 3; j++) { for (int k = 0; k < 3; k++) { if (f(s2[i - 1]) == j && f(s2[i]) == k) dp[i][j][k] = dp[i - 1][j][k] + 1; else dp[i][j][k] = dp[i - 1][j][k]; } } } long long ret = 0; int l = 0, r; for (int i = 0; i < n; i++) { r = p1[i]; while (l < m && p2[l] < i) l++; ret += max(r - l + 1, 0); if (i && l <= r) { int j = f(s1[i - 1]), k = f(s1[i]); if (j != k) { ret -= dp[r][k][j]; if (l - 1 >= 0) ret += dp[l - 1][k][j]; } } } cout << ret << endl; return 0; } |
//#############################################################################
//# Function: Maps Emesh Signals to Packet #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module emesh2packet #(parameter AW = 32, // address width
parameter PW = 104) // packet width
(
//Emesh signal bundle
input write_out,
input [1:0] datamode_out,
input [4:0] ctrlmode_out,
input [AW-1:0] dstaddr_out,
input [AW-1:0] data_out,
input [AW-1:0] srcaddr_out,
//Output packet
output [PW-1:0] packet_out
);
// ---- FORMAT -----
//
// [0] =write bit
// [2:1]=datamode
// [7:3]=ctrlmode
// [39:8]=dstaddr(lo)
//
// ---- 32-BIT ADDRESS ----
// [71:40] data (lo) | xxxx
// [103:72] srcaddr(lo) | data (hi)
//
// ---- 64-BIT ADDRESS ----
// [71:40] D0 | srcaddr(hi)
// [103:72] D1 | srcaddr(lo)
// [135:104] dstaddr(hi)
assign packet_out[0] = write_out;
assign packet_out[2:1] = datamode_out[1:0];
assign packet_out[7:3] = ctrlmode_out[4:0];
generate
if(PW==136)
begin : p136
assign packet_out[39:8] = dstaddr_out[31:0];
assign packet_out[71:40] = data_out[31:0]; // | srcaddr_out[63:32]
assign packet_out[103:72] = srcaddr_out[31:0]; // (data_out[63:32])
assign packet_out[135:104] = dstaddr_out[63:32];
end
else if(PW==104)
begin : p104
assign packet_out[39:8] = dstaddr_out[31:0];
assign packet_out[71:40] = data_out[31:0];
assign packet_out[103:72] = srcaddr_out[31:0];
end
else if(PW==72)
begin : p72
assign packet_out[39:8] = dstaddr_out[31:0];
assign packet_out[71:40] = data_out[31:0];
end
else if(PW==40)
begin : p40
assign packet_out[23:8] = dstaddr_out[15:0];
assign packet_out[39:24] = data_out[15:0];
end
endgenerate
endmodule // emesh2packet
|
#include <bits/stdc++.h> int n; long long l[100001], r[100001], ans = 0; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d%I64d , &l[i], &r[i]); std::sort(l + 1, l + n + 1); std::sort(r + 1, r + n + 1); for (int i = 1; i <= n; i++) { ans += l[i] > r[i] ? l[i] : r[i]; } printf( %I64d n , ans + 1ll * n); return 0; } |
#include <bits/stdc++.h> using namespace std; char c[55][55]; int n, i, j, m1, m2, m3, m4; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %s , c[i] + 1); m1 = m3 = n + 1; for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) if (c[i][j] == 4 ) { m1 = min(m1, i); m2 = max(m2, i); m3 = min(m3, j); m4 = max(m4, j); } for (i = m1; i <= m2; i++) { for (j = m3; j <= m4; j++) if (c[i][j] != 4 ) break; if (j <= m4) break; } if (i <= m2) { puts( No ); return 0; } for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) if (c[i][j] != 0 && (i < m1 - 1 || i > m2 + 1 || j < m3 - 1 || j > m4 + 1)) break; if (j <= n) break; } if (i <= n) { puts( No ); return 0; } for (i = m1; i <= m2; i++) if (m3 > 1 && c[i][m3 - 1] != 2 || m4 < n && c[i][m4 + 1] != 2 ) break; if (i <= m2) { puts( No ); return 0; } for (i = m3; i <= m4; i++) if (m1 > 1 && c[m1 - 1][i] != 2 || m2 < n && c[m2 + 1][i] != 2 ) break; if (i <= m4) { puts( No ); return 0; } if (m1 > 1 && m3 > 1 && c[m1 - 1][m3 - 1] != 1 || m1 > 1 && m4 < n && c[m1 - 1][m4 + 1] != 1 || m2 < n && m3 > 1 && c[m2 + 1][m3 - 1] != 1 || m2 < n && m4 < n && c[m2 + 1][m4 + 1] != 1 ) { puts( No ); return 0; } puts( Yes ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_2_V
`define SKY130_FD_SC_HDLL__EINVN_2_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_2_V
|
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`timescale 1ns / 1ps
module bd_c3fe_ila_lib_0 (
clk,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9,
probe10,
probe11,
probe12,
probe13,
probe14,
probe15
);
input clk;
input [1 : 0] probe0;
input [8 : 0] probe1;
input [1 : 0] probe2;
input [8 : 0] probe3;
input [1 : 0] probe4;
input [1 : 0] probe5;
input [1 : 0] probe6;
input [31 : 0] probe7;
input [1 : 0] probe8;
input [31 : 0] probe9;
input [3 : 0] probe10;
input [1 : 0] probe11;
input [1 : 0] probe12;
input [1 : 0] probe13;
input [1 : 0] probe14;
input [1 : 0] probe15;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__EBUFN_PP_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:43:34 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub
// /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/mult_17x16_stub.v
// Design : mult_17x16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module mult_17x16(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[16:0],B[15:0],P[24:0]" */;
input CLK;
input [16:0]A;
input [15:0]B;
output [24:0]P;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_PP_SYMBOL_V
|
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