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#include <bits/stdc++.h> using namespace std; int a[200002], ans[200002]; int main() { int n, i, k = 0, sum = 0; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &a[i]); sum += a[i]; } for (i = 0; i < n; i++) { if (((sum - a[i]) / (n - 1) == a[i]) && ((sum - a[i]) % (n - 1) == 0)) ans[k++] = i + 1; } printf( %d n , k); for (i = 0; i < k; i++) printf( %d , ans[i]); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) #pragma comment(linker, /STACK:2000000 ) using namespace std; template <int D, typename T> struct Vec : public vector<Vec<D - 1, T>> { static_assert(D >= 1, Vector dimension must be greater than zero! ); template <typename... Args> Vec(int n = 0, Args... args) : vector<Vec<D - 1, T>>(n, Vec<D - 1, T>(args...)) {} }; template <typename T> struct Vec<1, T> : public vector<T> { Vec(int n = 0, T val = T()) : vector<T>(n, val) {} }; using ll = long long; using db = long double; using ii = pair<int, int>; const int N = 2e5 + 5, LG = 19, MOD = 998244353; const int SQ = 320; const long double EPS = 1e-7; void printCase(int cs) { cout << Case # << cs << : ; } int p[N], n, q; int fast(int b, int e) { int res = 1; for (; e; e >>= 1, b = 1ll * b * b % MOD) if (e & 1) { res = 1ll * res * b % MOD; } return res; } int t[N << 2], lz[N << 2], cur = 1; void build(int node, int s, int e) { lz[node] = 1; if (s == e) { t[node] = cur; cur = 1ll * cur * p[s] % MOD; return; } int md = (s + e) >> 1; build(node << 1, s, md); build(node << 1 | 1, md + 1, e); t[node] = t[node << 1] + t[node << 1 | 1]; if (t[node] >= MOD) t[node] -= MOD; } void push(int node, int s, int e) { if (lz[node] == 1) return; t[node] = 1ll * t[node] * lz[node] % MOD; if (s != e) { lz[node << 1] = 1ll * lz[node] * lz[node << 1] % MOD; lz[node << 1 | 1] = 1ll * lz[node] * lz[node << 1 | 1] % MOD; } lz[node] = 1; } int qry(int node, int s, int e, int l, int r) { push(node, s, e); if (r < s || e < l) return 0; if (l <= s && e <= r) return t[node]; int md = (s + e) >> 1; int ret = qry(node << 1, s, md, l, r) + qry(node << 1 | 1, md + 1, e, l, r); if (ret >= MOD) ret -= MOD; return ret; } void upd(int node, int s, int e, int l, int r, int v) { push(node, s, e); if (r < s || e < l) return; if (l <= s && e <= r) { lz[node] = 1ll * lz[node] * v % MOD; push(node, s, e); return; } int md = (s + e) >> 1; upd(node << 1, s, md, l, r, v); upd(node << 1 | 1, md + 1, e, l, r, v); t[node] = t[node << 1] + t[node << 1 | 1]; if (t[node] >= MOD) t[node] -= MOD; } int sum[N]; int qry(int l, int r) { return 1ll * sum[r] * fast(sum[l - 1], MOD - 2) % MOD; } int get(int l, int r) { return 1ll * qry(1, 1, n, l, r) * fast(qry(l, r), MOD - 2) % MOD; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> q; const int INV100 = fast(100, MOD - 2); sum[0] = 1; for (int i = 1; i < n + 1; i++) { cin >> p[i]; p[i] = 1ll * p[i] * INV100 % MOD; sum[i] = 1ll * sum[i - 1] * p[i] % MOD; } build(1, 1, n); set<int> checkPoints({1, n + 1}); int ans = get(1, n); while (q--) { int x; cin >> x; if (checkPoints.count(x)) { int l = *(--checkPoints.find(x)); int r = *(checkPoints.upper_bound(x)); ans -= get(l, x - 1); if (ans < 0) ans += MOD; ans -= get(x, r - 1); if (ans < 0) ans += MOD; int toMul = 1ll * qry(1, 1, n, x - 1, x - 1) * p[x - 1] % MOD; upd(1, 1, n, x, r - 1, toMul); ans += get(l, r - 1); if (ans >= MOD) ans -= MOD; checkPoints.erase(x); } else { int l = *(--checkPoints.upper_bound(x)); int r = *(checkPoints.upper_bound(x)); ans = (ans - get(l, r - 1)); if (ans < 0) ans += MOD; ans += get(l, x - 1); if (ans >= MOD) ans -= MOD; int toDivide = 1ll * qry(1, 1, n, x - 1, x - 1) * p[x - 1] % MOD; toDivide = fast(toDivide, MOD - 2); upd(1, 1, n, x, r - 1, toDivide); ans += get(x, r - 1); if (ans >= MOD) ans -= MOD; checkPoints.insert(x); } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> E[1 << 18]; pair<int, int> R[1 << 18]; int dfs(int a, int p, int d) { int cnt = 1; for (auto it = (E[a]).begin(); it != (E[a]).end(); ++it) { int b = *it; if (b == p) continue; cnt += dfs(b, a, d + 1); } R[a] = pair<int, int>(cnt - 1 - d, a); return cnt; } int main() { int n, k; cin >> n >> k; int i; for (i = (1); i < (n); ++i) { int a, b; cin >> a >> b; --a; --b; E[a].push_back(b); E[b].push_back(a); } dfs(0, -1, 0); sort(R, R + n); long long res = 0; for (i = (k); i < (n); ++i) res += R[i].first; cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN = (int)2E5 + 5; int n, x, y; vector<int> Adj[maxN]; int deg[maxN]; bool avail[maxN]; bool marked[maxN]; int Count[maxN]; int DFS(int u) { marked[u] = true; Count[u] = 0; int cnt = 0; for (int i = 0, sz = Adj[u].size(); i < sz; ++i) { int v = Adj[u][i]; if (marked[v]) continue; DFS(v); Count[u] += Count[v]; if (avail[v]) ++cnt; } if (cnt == 0) avail[u] = true; else if (cnt == 1) avail[u] = true, ++Count[u]; else avail[u] = false, Count[u] += 2; return Count[u]; } int main() { scanf( %d %d %d , &n, &x, &y); for (int u = 1; u <= n; ++u) Adj[u].clear(); memset(deg, 0, sizeof(deg)); for (int i = 0; i < n - 1; ++i) { int u, v; scanf( %d %d , &u, &v); Adj[u].push_back(v); Adj[v].push_back(u); ++deg[u]; ++deg[v]; } if (x >= y) { for (int u = 1; u <= n; ++u) if (deg[u] == n - 1) { cout << (long long)(n - 2) * y + x << endl; return 0; } cout << (long long)(n - 1) * y << endl; return 0; } DFS(1); memset(marked, false, sizeof(marked)); cout << (long long)Count[1] * x + (long long)(n - 1 - Count[1]) * y << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_1_V
`define SKY130_FD_SC_LP__INVLP_1_V
/**
* invlp: Low Power Inverter.
*
* Verilog wrapper for invlp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_1_V
|
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize( Ofast ) using namespace std; namespace ywy { inline int get() { int n = 0; char c; while ((c = getchar()) || 23333) { if (c >= 0 && c <= 9 ) break; if (c == - ) goto s; } n = c - 0 ; while ((c = getchar()) || 23333) { if (c >= 0 && c <= 9 ) n = n * 10 + c - 0 ; else return (n); } s: while ((c = getchar()) || 23333) { if (c >= 0 && c <= 9 ) n = n * 10 - c + 0 ; else return (n); } } typedef struct _b { int dest; int nxt; } bian; bian memchi[1000001]; int gn = 1, heads[500001], deep[500001], ance[500001][19], lg[500001]; inline void add(int s, int t) { memchi[gn].dest = t; memchi[gn].nxt = heads[s]; heads[s] = gn; gn++; } int stk[500001]; vector<int> vec[500001]; int dfn[500001], gdfn = 1; void dfs(int pt) { dfn[pt] = gdfn; gdfn++; for (register int i = heads[pt]; i; i = memchi[i].nxt) { deep[memchi[i].dest] = deep[pt] + 1; dfs(memchi[i].dest); } } long long dp[500001]; inline int lca(int a, int b) { if (deep[a] > deep[b]) swap(a, b); for (register int i = lg[deep[b]]; i >= 0; i--) { if (deep[ance[b][i]] >= deep[a]) b = ance[b][i]; } if (a == b) return (a); for (register int i = lg[deep[a]]; i >= 0; i--) { if (ance[a][i] != ance[b][i]) a = ance[a][i], b = ance[b][i]; } return (ance[a][0]); } inline int cmp(const int &a, const int &b) { return (dfn[a] < dfn[b]); } inline void solve(int x) { int sp = 0; long long sig = 0; for (register int i = 1; i < vec[x].size(); i++) { int dpb = deep[lca(vec[x][i - 1], vec[x][i])]; while (sp) { int a = deep[lca(vec[x][stk[sp - 1]], vec[x][i])]; if (a < dpb) { sig += (i - stk[sp - 1] - 1) * (long long)dpb; break; } if (sp == 1) { sig -= (stk[sp - 1] + 1) * (long long)deep[lca(vec[x][stk[sp - 1]], vec[x][i - 1])]; } else sig -= (stk[sp - 1] - stk[sp - 2]) * (long long)deep[lca(vec[x][stk[sp - 1]], vec[x][i - 1])]; sp--; } if (!sp) sig += i * (long long)dpb; stk[sp] = i - 1; sp++; dp[vec[x][i]] += sig; } } void ywymain() { deep[0] = -1; int n = get(), rt = 0; lg[0] = -1; for (register int i = 1; i <= n; i++) { int f = get(); ance[i][0] = f; if (!f) rt = i; else add(f, i); lg[i] = lg[i - 1] + (i == (i & -i)); } deep[rt] = 1; dfs(rt); for (register int i = 1; i <= n; i++) vec[deep[i]].push_back(i); for (register int i = 1; i <= lg[n]; i++) { for (register int j = 1; j <= n; j++) ance[j][i] = ance[ance[j][i - 1]][i - 1]; } for (register int i = 2; i <= n && vec[i].size(); i++) { sort(vec[i].begin(), vec[i].end(), cmp); for (register int j = 0; j < vec[i].size(); j++) { dp[vec[i][j]] = dp[ance[vec[i][j]][0]] + deep[ance[vec[i][j]][0]]; } solve(i); reverse(vec[i].begin(), vec[i].end()); solve(i); } for (register int i = 1; i <= n; i++) printf( %lld , dp[i]); } } // namespace ywy int main() { ywy::ywymain(); return (0); } |
#include <bits/stdc++.h> using namespace std; int N, M, K; int color[200002]; vector<int> edge[200002]; int id[200002]; int ite = 1; int siz[200002]; map<int, int> m[200002]; int ans; void dfs(int a) { if (id[a]) { return; } id[a] = ite; for (int i = 0; i < edge[a].size(); i++) { dfs(edge[a][i]); } } int32_t main() { ios_base::sync_with_stdio(false); if (fopen( cf731c.in , r )) { freopen( cf731c.in , r , stdin); freopen( cf731c.out , w , stdout); } cin >> N >> M >> K; for (int i = 0; i < N; i++) { cin >> color[i]; } for (int i = 0; i < M; i++) { int a, b; cin >> a >> b; a--; b--; edge[a].push_back(b); edge[b].push_back(a); } for (int i = 0; i < N; i++) { if (id[i] == 0) { dfs(i); ite++; } } for (int i = 0; i < N; i++) { siz[id[i]]++; m[id[i]][color[i]]++; } for (int i = 1; i < ite; i++) { int mx = -1; for (auto it = m[i].begin(); it != m[i].end(); it++) { mx = max(mx, it->second); } ans += (siz[i] - mx); } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100100; pair<long double, long double> a[N]; int n; bool f(long double mid) { long double l[n], r[n]; multiset<pair<long double, int>> xex; for (int i = 0; i < n; i++) { l[i] = 1.0 * a[i].first - a[i].second * mid; xex.insert({l[i], -1}); r[i] = 1.0 * a[i].first + a[i].second * mid; xex.insert({r[i], 1}); } int cnt = 0; for (auto it = xex.begin(); it != xex.end(); it++) { if ((*it).second == -1) { cnt++; } else { cnt--; } if (cnt == n) return true; } { bool f = true; for (int i = 0; i < n; i++) { if (l[i] <= a[0].first) { f = false; break; } } if (f) return true; } { bool f = true; for (int i = 0; i < n; i++) { if (a[n - 1].first <= r[i]) { f = false; break; } } if (f) return true; } return false; } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i].first; } for (int i = 0; i < n; i++) { cin >> a[i].second; } sort(a, a + n); long double ans = 1e9; long double l = 0.0, r = 1e9; while (r - l >= 0.0000001) { long double mid = (1.0 * l + r) / 2.0; if (f(mid)) { ans = mid; r = mid; } else { l = mid; } } cout << fixed << setprecision(8) << ans << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:21:26 03/28/2014
// Design Name:
// Module Name: cu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cu(inst,zero,rs1,rs2,rd,erd,mrd,ewreg,mwreg,esld,
wreg,sst,m2reg,shift,aluimm,sext,aluc,wmem,pcsource,adepend,bdepend,sdepend,loaddepend,wzero);
input[31:0] inst;
input zero;
input[4:0] rs1,rs2,rd,erd,mrd;
input ewreg,mwreg,esld;
output wreg,sst,m2reg,shift,aluimm,sext,wmem;
output[3:0] aluc;
output[1:0] pcsource;
output[1:0] adepend,bdepend,sdepend;
output loaddepend,wzero;
wire i_and = ~inst[31]&~inst[30]&~inst[29]&~inst[28]&~inst[27]&~inst[26];
wire i_andi = ~inst[31]&~inst[30]&~inst[29]&~inst[28]&~inst[27]&inst[26];
wire i_or = ~inst[31]&~inst[30]&~inst[29]&~inst[28]&inst[27]&~inst[26];
wire i_ori = ~inst[31]&~inst[30]&~inst[29]&~inst[28]&inst[27]&inst[26];
wire i_add = ~inst[31]&~inst[30]&~inst[29]&inst[28]&~inst[27]&~inst[26];
wire i_addi = ~inst[31]&~inst[30]&~inst[29]&inst[28]&~inst[27]&inst[26];
wire i_sub = ~inst[31]&~inst[30]&~inst[29]&inst[28]&inst[27]&~inst[26];
wire i_subi = ~inst[31]&~inst[30]&~inst[29]&inst[28]&inst[27]&inst[26];
wire i_load = ~inst[31]&~inst[30]&inst[29]&~inst[28]&~inst[27]&~inst[26];
wire i_store = ~inst[31]&~inst[30]&inst[29]&~inst[28]&~inst[27]&inst[26];
wire i_beq = ~inst[31]&~inst[30]&inst[29]&~inst[28]&inst[27]&~inst[26];
wire i_bne = ~inst[31]&~inst[30]&inst[29]&~inst[28]&inst[27]&inst[26];
wire i_branch = ~inst[31]&~inst[30]&inst[29]&inst[28]&~inst[27]&~inst[26];
wire i_sll = ~inst[31]&~inst[30]&inst[29]&inst[28]&~inst[27]&inst[26];
wire i_srl = ~inst[31]&~inst[30]&inst[29]&inst[28]&inst[27]&~inst[26];
wire i_sra = ~inst[31]&~inst[30]&inst[29]&inst[28]&inst[27]&inst[26];
wire eequ_rs1 = (rs1==erd);
wire mequ_rs1 = (rs1==mrd);
wire eequ_rs2 = (rs2==erd);
wire mequ_rs2 = (rs2==mrd);
wire erd_equ = (rd==erd);
wire mrd_equ = (rd==mrd);
wire rs2isReg = i_and|i_or|i_add|i_sub|i_sll|i_srl|i_sra;
assign wreg = (i_and|i_andi|i_or|i_ori|i_add| i_addi|i_sub|i_subi|i_load|i_sll|i_srl|i_sra)&~loaddepend; //д¼Ä´æÆ÷£¬Îª1ʱд¼Ä´æÆ÷£¬·ñÔò²»Ð´
assign sst = i_store; //ÊÇ·ñΪstoreÖ¸Á Ϊ1ʱѡÔñrdдÈë¼Ä´æÆ÷¶Ñ£¬·ñÔòÑ¡Ôñrs2
assign m2reg = i_load; //´æ´¢Æ÷Êý¾ÝдÈë¼Ä´æÆ÷ Ϊ1ʱѡÔñ´æ´¢Æ÷Êý¾Ý£¬·ñÔòÑ¡ÔñALU½á¹û
assign shift = i_sll|i_srl|i_sra; //ALU aʹÓÃÒÆλλÊý Ϊ1ʱʹÓÃÒÆλλÊý£¬·ñÔòʹÓüĴæÆ÷Êý¾Ý
assign aluimm = i_andi|i_ori|i_addi|i_subi|i_store|i_load; //ALU bʹÓÃÁ¢¼´Êý Ϊ1ʱʹÓÃÁ¢¼´Êý£¬·ñÔòʹÓüĴæÆ÷Êý¾Ý
assign sext = i_addi|i_subi; //Á¢¼´Êý·ûºÅÀ©Õ¹ Ϊ1ʱ·ûºÅÀ©Õ¹£¬·ñÔòÁãÀ©Õ¹
assign wmem = i_store&~loaddepend; //д´æ´¢Æ÷ Ϊ1ʱд´æ´¢Æ÷£¬·ñÔò²»Ð´
//ALU²Ù×÷¿ØÖÆÂë
assign aluc[3] = i_beq|i_bne|i_branch;
assign aluc[2] = i_load|i_store|i_sll|i_srl|i_sra;
assign aluc[1] = i_add|i_sub|i_srl|i_sra|i_addi|i_subi;
assign aluc[0] = i_or|i_ori|i_sub|i_subi|i_sll|i_sra;
//ÏÂÒ»ÌõÖ¸ÁîµØÖ·µÄÑ¡Ôñ 00Ñ¡PC+4£¬01ѡתÒƵØÖ·£¬11Ñ¡ÌøתµØÖ·
assign pcsource[1] = i_branch;
assign pcsource[0] = i_branch|(i_beq&zero)|(i_bne&(~zero));
//adepend
assign adepend[1] = ((ewreg&eequ_rs1)|(mwreg&mequ_rs1))&~shift;
assign adepend[0] = (mwreg&mequ_rs1&(~ewreg|~eequ_rs1))|shift;
//bdepend
assign bdepend[1] = rs2isReg&((ewreg&eequ_rs2)|(mwreg&mequ_rs2));
assign bdepend[0] = ~rs2isReg|(mwreg&mequ_rs2&(~ewreg|~eequ_rs2));
//sdepend
/*
sdepend == 00 -> Ñ¡ mqb
sdepend == 01 -> ÎÞ¶¨Òå
sdepend == 10 -> ÓëerdÏà¹Ø£¬Ñ¡Ôñ d
sdepend == 11 -> ÓëmrdÏà¹Ø£¬Ñ¡Ôñ pre_d
*/
assign sdepend[1] = ((ewreg&erd_equ)|(mwreg&mrd_equ))&i_store;
assign sdepend[0] = (mwreg&mrd_equ&(~ewreg|~erd_equ))&i_store;
//loaddepend
assign loaddepend = esld & ( (adepend[1]&~adepend[0]) | (bdepend[1]&~bdepend[0]) );
// wzero
assign wzero = (i_add|i_addi|i_sub|i_subi)&~loaddepend;
endmodule
|
#include <bits/stdc++.h> using namespace std; #ifdef tabr #include library/debug.cpp #else #define debug(...) #endif template <long long mod> struct modular { long long value; modular(long long x = 0) { value = x % mod; if (value < 0) value += mod; } modular& operator+=(const modular& other) { if ((value += other.value) >= mod) value -= mod; return *this; } modular& operator-=(const modular& other) { if ((value -= other.value) < 0) value += mod; return *this; } modular& operator*=(const modular& other) { value = value * other.value % mod; return *this; } modular& operator/=(const modular& other) { long long a = 0, b = 1, c = other.value, m = mod; while (c != 0) { long long t = m / c; m -= t * c; swap(c, m); a -= t * b; swap(a, b); } a %= mod; if (a < 0) a += mod; value = value * a % mod; return *this; } modular operator+(const modular& rhs) const { return modular(*this) += rhs; } modular operator-(const modular& rhs) const { return modular(*this) -= rhs; } modular operator*(const modular& rhs) const { return modular(*this) *= rhs; } modular operator/(const modular& rhs) const { return modular(*this) /= rhs; } modular& operator++() { return *this += 1; } modular& operator--() { return *this -= 1; } modular operator++(int) { modular res(*this); *this += 1; return res; } modular operator--(int) { modular res(*this); *this -= 1; return res; } modular operator-() const { return modular(-value); } bool operator==(const modular& rhs) const { return value == rhs.value; } bool operator!=(const modular& rhs) const { return value != rhs.value; } bool operator<(const modular& rhs) const { return value < rhs.value; } }; template <long long mod> string to_string(const modular<mod>& x) { return to_string(x.value); } template <long long mod> ostream& operator<<(ostream& stream, const modular<mod>& x) { return stream << x.value; } template <long long mod> istream& operator>>(istream& stream, modular<mod>& x) { stream >> x.value; x.value %= mod; if (x.value < 0) x.value += mod; return stream; } constexpr long long mod = (long long) 1e9 + 7; using mint = modular<mod>; mint power(mint a, long long n) { mint res = 1; while (n > 0) { if (n & 1) { res *= a; } a *= a; n >>= 1; } return res; } vector<mint> fact(1, 1); vector<mint> finv(1, 1); mint C(int n, int k) { if (n < k || k < 0) { return mint(0); } while ((int) fact.size() < n + 1) { fact.emplace_back(fact.back() * (int) fact.size()); finv.emplace_back(mint(1) / fact.back()); } return fact[n] * finv[k] * finv[n - k]; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> c(n), b(n - 1); for (int i = 0; i < n; i++) { cin >> c[i]; } for (int i = 0; i < n - 1; i++) { cin >> b[i]; } vector<int> d(n); for (int i = 1; i < n; i++) { for (int j = 0; j < i; j++) { d[i] += b[j]; } } int q; cin >> q; map<int, mint> mp; mp[(int) 2e9] = 0; mp[(int) -2e9] = 1; for (int i = 0; i < n; i++) { mp[(int) -2e9] *= c[i] + 1; } while (q--) { int x; cin >> x; if (mp.count(x)) { cout << mp[x] << n ; continue; } auto nxt = mp.lower_bound(x); auto pre = prev(nxt); if ((*pre).second == (*nxt).second) { cout << (*pre).second << n ; continue; } int m = 10100; vector<mint> dp(m); dp[0] = 1; int t = 0; for (int i = 0; i < n; i++) { vector<mint> new_dp(m); new_dp[0] = dp[0]; for (int j = 1; j < m; j++) { new_dp[j] = new_dp[j - 1] + dp[j]; if (j - c[i] - 1 >= 0) { new_dp[j] -= dp[j - c[i] - 1]; } } swap(dp, new_dp); t += x + d[i]; for (int j = 0; j < min(m, t); j++) { dp[j] = 0; } } mp[x] = accumulate(dp.begin(), dp.end(), mint(0)); cout << mp[x] << n ; } return 0; } |
`include "../lib/flip_flop.v"
module reg_32bits (
input [31:0] d,
input we, clk,
output [31:0] q);
d_flip_flop dff0 (.q(q[0 ]), .d(d[0 ]), .we(we), .clk(clk));
d_flip_flop dff1 (.q(q[1 ]), .d(d[1 ]), .we(we), .clk(clk));
d_flip_flop dff2 (.q(q[2 ]), .d(d[2 ]), .we(we), .clk(clk));
d_flip_flop dff3 (.q(q[3 ]), .d(d[3 ]), .we(we), .clk(clk));
d_flip_flop dff4 (.q(q[4 ]), .d(d[4 ]), .we(we), .clk(clk));
d_flip_flop dff5 (.q(q[5 ]), .d(d[5 ]), .we(we), .clk(clk));
d_flip_flop dff6 (.q(q[6 ]), .d(d[6 ]), .we(we), .clk(clk));
d_flip_flop dff7 (.q(q[7 ]), .d(d[7 ]), .we(we), .clk(clk));
d_flip_flop dff8 (.q(q[8 ]), .d(d[8 ]), .we(we), .clk(clk));
d_flip_flop dff9 (.q(q[9 ]), .d(d[9 ]), .we(we), .clk(clk));
d_flip_flop dff10(.q(q[10]), .d(d[10]), .we(we), .clk(clk));
d_flip_flop dff11(.q(q[11]), .d(d[11]), .we(we), .clk(clk));
d_flip_flop dff12(.q(q[12]), .d(d[12]), .we(we), .clk(clk));
d_flip_flop dff13(.q(q[13]), .d(d[13]), .we(we), .clk(clk));
d_flip_flop dff14(.q(q[14]), .d(d[14]), .we(we), .clk(clk));
d_flip_flop dff15(.q(q[15]), .d(d[15]), .we(we), .clk(clk));
d_flip_flop dff16(.q(q[16]), .d(d[16]), .we(we), .clk(clk));
d_flip_flop dff17(.q(q[17]), .d(d[17]), .we(we), .clk(clk));
d_flip_flop dff18(.q(q[18]), .d(d[18]), .we(we), .clk(clk));
d_flip_flop dff19(.q(q[19]), .d(d[19]), .we(we), .clk(clk));
d_flip_flop dff20(.q(q[20]), .d(d[20]), .we(we), .clk(clk));
d_flip_flop dff21(.q(q[21]), .d(d[21]), .we(we), .clk(clk));
d_flip_flop dff22(.q(q[22]), .d(d[22]), .we(we), .clk(clk));
d_flip_flop dff23(.q(q[23]), .d(d[23]), .we(we), .clk(clk));
d_flip_flop dff24(.q(q[24]), .d(d[24]), .we(we), .clk(clk));
d_flip_flop dff25(.q(q[25]), .d(d[25]), .we(we), .clk(clk));
d_flip_flop dff26(.q(q[26]), .d(d[26]), .we(we), .clk(clk));
d_flip_flop dff27(.q(q[27]), .d(d[27]), .we(we), .clk(clk));
d_flip_flop dff28(.q(q[28]), .d(d[28]), .we(we), .clk(clk));
d_flip_flop dff29(.q(q[29]), .d(d[29]), .we(we), .clk(clk));
d_flip_flop dff30(.q(q[30]), .d(d[30]), .we(we), .clk(clk));
d_flip_flop dff31(.q(q[31]), .d(d[31]), .we(we), .clk(clk));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_BLACKBOX_V
`define SKY130_FD_SC_HS__FILL_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > data; vector<vector<int> > sticks; vector<int> h; int dfs(int vertex, int last) { int longest = 0; for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (to == last) continue; int len = dfs(to, vertex) + 1; sticks[vertex].push_back(len); longest = max(longest, len); } h[vertex] = longest; return longest; } void dfs2(int vertex, int last, int fup) { if (vertex != 0) { sticks[vertex].push_back(fup); } fup++; int mx1 = -100, mx2 = -100; for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (to == last) continue; if (h[to] + 1 > mx1) { mx2 = mx1; mx1 = h[to] + 1; } else mx2 = max(mx2, h[to] + 1); } for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (to == last) continue; if (h[to] + 1 != mx1) { dfs2(to, vertex, max(fup, mx1 + 1)); } else dfs2(to, vertex, max(fup, mx2 + 1)); } } int dfslong, dfslen; void dfs3(int vertex, int last, int d) { if (d > dfslen) { dfslen = d, dfslong = vertex; } for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (to == last) continue; dfs3(to, vertex, d + 1); } } int find_diameter() { dfslong = 0, dfslen = 0; dfs3(0, -1, 0); int Q = dfslong; dfs3(dfslong, -1, 0); return dfslen; } vector<bool> deleted; void dlt(int first) { deleted[first] = true; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; data.assign(n, {}); sticks.assign(n, {}); h.assign(n, {}); deleted.assign(n, false); vector<pair<int, int> > edges; for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; if (u > v) swap(u, v); u--, v--; data[u].push_back(v), data[v].push_back(u); edges.push_back({u, v}); } dfs(0, -1); dfs2(0, -1, 0); for (int i = 0; i < n; ++i) { sort(sticks[i].begin(), sticks[i].end(), greater<int>()); } vector<pair<int, int> > kek; for (int i = 0; i < n; ++i) { for (int j = 0; j < sticks[i].size(); ++j) { kek.push_back({sticks[i][j], i}); } } sort(kek.begin(), kek.end()); int d = find_diameter(); for (int i = 0; i < n; ++i) { if (data[i].size() <= 2) dlt(i); } set<pair<int, int> > W; for (int i = 0; i < n; ++i) { W.insert({-sticks[i].size(), i}); } auto thtol = W.begin(); cout << -(*thtol).first + 1 << ; int u = 0; vector<int> stake; for (int k = 2; k <= n; ++k) { if (k > d) { cout << 1 << ; continue; } if (k % 2 == 0) { while (u < kek.size() && kek[u].first < k / 2) { stake.push_back(kek[u++].second); } for (int i = 0; i < stake.size(); ++i) { int T = stake[i]; W.erase(W.find({-sticks[T].size(), T})); while (sticks[T].size() && sticks[T].back() < k / 2) sticks[T].pop_back(); if (sticks[T].size() <= 2) dlt(T); W.insert({-sticks[T].size(), T}); } auto aaa = W.begin(); int tut = max(2, -(*aaa).first); int st = 0; while (st < edges.size()) { int A = edges[st].first, B = edges[st].second; if (deleted[A] || deleted[B]) { swap(edges[st], edges.back()); edges.pop_back(); continue; } tut = max(tut, (int)(sticks[A].size() + sticks[B].size() - 2)); st++; } cout << tut << ; stake.clear(); } else { while (u < kek.size() && kek[u].first < (k + 1) / 2) { stake.push_back(kek[u++].second); } for (int i = 0; i < stake.size(); ++i) { int T = stake[i]; W.erase(W.find({-sticks[T].size(), T})); while (sticks[T].size() > 1 && sticks[T][sticks[T].size() - 2] < (k + 1) / 2) sticks[T].pop_back(); if (sticks[T].size() <= 2) dlt(T); W.insert({-sticks[T].size(), T}); } auto aaa = W.begin(); int tut = max(2, -(*aaa).first); cout << tut << ; } } } |
#include <bits/stdc++.h> using namespace std; template <class T> long long size(const T& x) { return x.size(); } template <class T> T smod(T a, T b) { return (a % b + b) % b; } long long n, k; vector<long long> X; vector<pair<long long, pair<long long, long long> > > A; vector<vector<long long> > mem; long long dp(int at, int chosen) { if (at >= n) return 0; if (mem[at][chosen] != -1) return mem[at][chosen]; long long mx = 0; if (chosen < 2) { mx = max(mx, A[at].first + dp(A[at].second.second + 1, chosen + 1)); } mx = max(mx, dp(at + 1, chosen)); return mem[at][chosen] = mx; } void solve() { cin >> n >> k; mem = vector<vector<long long> >(n + 10, vector<long long>(3, -1)); X = vector<long long>(n); A = vector<pair<long long, pair<long long, long long> > >(n); for (long long i = (0); i < (n); ++i) { cin >> X[i]; } sort(X.begin(), X.end()); for (long long i = (0); i < (n); ++i) { long long a; cin >> a; } for (long long i = (0); i < (n); ++i) { auto r = upper_bound(X.begin(), X.end(), X[i] + k); int index = r - X.begin() - 1; A[i] = pair<long long, pair<long long, long long> >( index - i + 1, pair<long long, long long>(i, index)); } cout << dp(0, 0) << endl; } int main() { cin.sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long t; cin >> t; while (t--) solve(); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// Author: Yu-Sheng Lin
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
state,
// Inputs
clk
);
input clk;
int cyc;
reg rstn;
output [4:0] state;
parameter real fst_gparam_real = 1.23;
localparam real fst_lparam_real = 4.56;
real fst_real = 1.23;
integer fst_integer;
bit fst_bit;
logic fst_logic;
int fst_int;
shortint fst_shortint;
longint fst_longint;
byte fst_byte;
parameter fst_parameter = 123;
localparam fst_lparam = 456;
supply0 fst_supply0;
supply1 fst_supply1;
tri0 fst_tri0;
tri1 fst_tri1;
tri fst_tri;
wire fst_wire;
Test test (/*AUTOINST*/
// Outputs
.state (state[4:0]),
// Inputs
.clk (clk),
.rstn (rstn));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
rstn <= ~'1;
end
else if (cyc<10) begin
rstn <= ~'1;
end
else if (cyc<90) begin
rstn <= ~'0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input clk,
input rstn,
output logic [4:0] state
);
logic [4:0] state_w;
logic [4:0] state_array [3];
assign state = state_array[0];
always_comb begin
state_w[4] = state_array[2][0];
state_w[3] = state_array[2][4];
state_w[2] = state_array[2][3] ^ state_array[2][0];
state_w[1] = state_array[2][2];
state_w[0] = state_array[2][1];
end
always_ff @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 3; i++)
state_array[i] <= 'b1;
end
else begin
for (int i = 0; i < 2; i++)
state_array[i] <= state_array[i+1];
state_array[2] <= state_w;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire SCE_GATE ;
// Delay Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDLCLKP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 10; struct ft_t { long long d[N], t[N]; void init() { memset(d, 0, sizeof(d)); memset(t, 0, sizeof(t)); } void put(long long x, long long k) { for (int i = x + 1; i < N; i += -i & i) d[i] ^= k; for (int i = x + 1; (x & 1) && i < N; i += -i & i) t[i] ^= k; } long long ask(long long x, long long lrv = 0, long long rrv = 0) { for (int i = x + 1; i; i -= -i & i) lrv ^= d[i]; for (int i = x + 1; i; i -= -i & i) rrv ^= t[i]; return (x + 1 & 1) * lrv ^ rrv; } }; struct ft2_t { ft_t d[N], t[N]; void init() { for (int i = 0; i < N; i++) { d[i].init(); t[i].init(); } } void put(long long x, long long y, long long k) { for (int i = x + 1; i < N; i += -i & i) d[i].put(y, k); for (int i = x + 1; (x & 1) && i < N; i += -i & i) t[i].put(y, k); } long long ask(long long x, long long y, long long lrv = 0, long long rrv = 0) { for (int i = x + 1; i; i -= -i & i) lrv ^= d[i].ask(y); for (int i = x + 1; i; i -= -i & i) rrv ^= t[i].ask(y); return (x + 1 & 1) * lrv ^ rrv; } void draw(long long x0, long long y0, long long x1, long long y1, long long k) { put(x0, y0, k), put(x1 + 1, y0, k), put(x0, y1 + 1, k), put(x1 + 1, y1 + 1, k); } long long pick(long long x0, long long y0, long long x1, long long y1) { return ask(x1, y1) ^ ask(x0 - 1, y1) ^ ask(x1, y0 - 1) ^ ask(x0 - 1, y0 - 1); } }; int n, m; ft2_t zkl; int main() { for (; ~scanf( %d%d , &n, &m);) { zkl.init(); for (int op, x0, y0, x1, y1; m--;) { scanf( %d%d%d%d%d , &op, &x0, &y0, &x1, &y1); if (op == 1) { cout << zkl.pick(x0, y0, x1, y1) << endl; } else { long long k; scanf( %lld , &k); zkl.draw(x0, y0, x1, y1, k); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, a[N]; int cnt[N], odd, neg, sum; int f[N]; long long res; bool check(int L, int R) { for (int i = 1; i <= n; ++i) if (!(L <= (i) && (i) <= R) && !(L <= (n - i + 1) && (n - i + 1) <= R) && a[i] != a[n - i + 1]) return 0; for (int i = 1; i <= n; ++i) cnt[i] = 0; for (int i = 1; i <= n; ++i) { if ((L <= (i) && (i) <= R)) { ++cnt[a[i]]; } else if ((L <= (n - i + 1) && (n - i + 1) <= R)) --cnt[a[i]]; } int sum = 0; for (int i = 1; i <= n; ++i) if (cnt[i] < 0) return 0; else sum += (cnt[i] & 1); return sum <= (n & 1); } bool ok(int l, int r) { if (r <= n / 2) return (f[r] - f[l - 1] == sum); if (l >= (n + 1) / 2 + 1) { l = n - l + 1; r = n - r + 1; return (f[l] - f[r - 1] == sum); } r = n - r + 1; return (f[n / 2] - f[min(l, r) - 1] == sum); } void work() { int i, j, k; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d , &a[i]); for (i = 1; i <= n / 2; ++i) f[i] = f[i - 1] + (a[i] != a[n - i + 1]); sum = f[n / 2]; i = 1, j = 0; while (i <= n) { while (j <= n && (j < i || (!ok(i, j) || neg || odd > (n & 1)))) { ++j; k = n - j + 1; if (cnt[a[j]] < 0) --neg; if (cnt[a[j]] & 1) --odd; if (a[j] != a[k]) { if (cnt[a[k]] < 0) --neg; if (cnt[a[k]] & 1) --odd; } ++cnt[a[j]]; if (i <= k && k <= j) { if (j != k) ++cnt[a[j]]; } else --cnt[a[k]]; if (cnt[a[j]] < 0) ++neg; if (cnt[a[j]] & 1) ++odd; if (a[j] != a[k]) { if (cnt[a[k]] < 0) ++neg; if (cnt[a[k]] & 1) ++odd; } } k = n - i + 1; if (cnt[a[i]] < 0) --neg; if (cnt[a[i]] & 1) --odd; if (a[i] != a[k]) { if (cnt[a[k]] < 0) --neg; if (cnt[a[k]] & 1) --odd; } --cnt[a[i]]; if (i < k && k <= j) { if (i != k) --cnt[a[i]]; } else { ++cnt[a[k]]; } if (cnt[a[i]] < 0) ++neg; if (cnt[a[i]] & 1) ++odd; if (a[i] != a[k]) { if (cnt[a[k]] < 0) ++neg; if (cnt[a[k]] & 1) ++odd; } res += n - j + 1; ++i; } cout << res << endl; } int main() { work(); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) #pragma GCC optimize( unroll-loops ) using namespace std; const int MAX = 1e6 + 5; const long long MOD = 1000000007; struct state { int len, link, cnt; int nx[26]; } st[MAX << 1]; int id, last, cur; vector<int> v[MAX]; inline void sa_init() { st[0].link = -1; memset(st[0].nx, 0, sizeof st[0].nx); id = last = st[0].cnt = 0; } inline void sa_extend(int c) { int clone; st[last].nx[c] = cur = ++id; st[cur].len = st[last].len + 1; v[st[cur].len].push_back(cur); st[cur].cnt = 1; int p = last; while (1) { if ((p = st[p].link) == -1) { st[cur].link = 0; break; } if (st[p].nx[c]) { int q = st[p].nx[c]; if (st[p].len + 1 == st[q].len) st[cur].link = q; else { clone = ++id; st[clone] = st[q]; st[clone].cnt = 0; st[clone].len = st[p].len + 1; v[st[clone].len].push_back(clone); st[q].link = st[cur].link = clone; while (p != -1 && st[p].nx[c] == q) { st[p].nx[c] = clone; p = st[p].link; } } break; } else st[p].nx[c] = cur; } last = cur; return; } inline int lcs(string &s, string &t) { sa_init(); for (char c : s) sa_extend(c - a ); int best = 0, len = 0; cur = 0; for (char c : t) { c -= a ; while (cur && !st[cur].nx[c]) cur = st[cur].link, len = st[cur].len; if (st[cur].nx[c]) { cur = st[cur].nx[c]; best = max(best, ++len); } } return best; } bool vis[MAX << 1]; vector<int> del; inline int solve(string &s) { int n = s.size(), ans = 0, len = 0; del.clear(); s += s; cur = 0; for (char c : s) { c -= a ; while (cur && !st[cur].nx[c]) cur = st[cur].link, len = st[cur].len; if (st[cur].nx[c]) { cur = st[cur].nx[c], ++len; if (len == n) { if (!vis[cur]) ans += st[cur].cnt, vis[cur] = 1, del.push_back(cur); --len; if (len == st[st[cur].link].len) cur = st[cur].link; } } } for (int i : del) vis[i] = 0; return ans; } string s; int q; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); sa_init(); cin >> s; for (char c : s) sa_extend(c - a ); for (int i = s.size(); i >= 1; --i) for (int j : v[i]) st[st[j].link].cnt += st[j].cnt; cin >> q; while (q--) { cin >> s; cout << solve(s) << n ; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:20:24 02/22/2015
// Design Name:
// Module Name: Add
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AddProcess(
input [31:0] z_postAllign,
input [3:0] Opcode_Allign,
input idle_Allign,
input [35:0] cout_Allign,
input [35:0] zout_Allign,
input [31:0] sout_Allign,
input [7:0] InsTagAllign,
input clock,
output reg idle_AddState,
output reg [31:0] sout_AddState,
output reg [27:0] sum_AddState,
output reg [3:0] Opcode_AddState,
output reg [31:0] z_postAddState,
output reg [7:0] InsTagAdder
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Allign[35];
assign z_exponent = zout_Allign[34:27] - 127;
assign z_mantissa = {zout_Allign[26:0]};
assign c_sign = cout_Allign[35];
assign c_exponent = cout_Allign[34:27] - 127;
assign c_mantissa = {cout_Allign[26:0]};
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10,
PreProcess = 4'd11;
always @ (posedge clock)
begin
InsTagAdder <= InsTagAllign;
z_postAddState <= z_postAllign;
Opcode_AddState <= Opcode_Allign;
//if(Opcode_Allign == PreProcess) begin
idle_AddState <= idle_Allign;
if (idle_Allign != put_idle) begin
sout_AddState[30:23] <= c_exponent;
sout_AddState[22:0] <= 0;
if (c_sign == z_sign) begin
sum_AddState <= c_mantissa + z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
if (c_mantissa >= z_mantissa) begin
sum_AddState <= c_mantissa - z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
sum_AddState <= z_mantissa - c_mantissa;
sout_AddState[31] <= z_sign;
end
end
end
else begin
sout_AddState <= sout_Allign;
sum_AddState <= 0;
end
//end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:14:49 05/10/2016
// Design Name:
// Module Name: prob_computer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module prob_computer(
input clk,
input rst,
input [31:0] new,
input [31:0] old,
input [31:0] Tinv,
input inp_valid,
output [31:0] out,
output out_valid
);
// The circuitry to compute e^-((new-old)/T) = 1 / (e^((new-old)*(1/T)))
reg [31:0] diff_q, diff_d, t_q, t_d;
reg processing_q, processing_d;
wire [31:0] floatval;
wire floatval_valid;
fixed2float f2f(
.aclk(clk),
.s_axis_a_tvalid(processing_q),
.s_axis_a_tdata(diff_q),
.m_axis_result_tvalid(floatval_valid),
.m_axis_result_tdata(floatval)
);
wire [31:0] floatval2_data;
wire floatval2_valid;
floating_point_mult m1(
.aclk(clk),
.s_axis_a_tvalid(processing_q),
.s_axis_a_tdata(t_q),
.s_axis_b_tvalid(floatval_valid),
.s_axis_b_tdata(floatval),
.m_axis_result_tvalid(floatval2_valid),
.m_axis_result_tdata(floatval2_data)
);
wire [31:0] exp_res;
wire [7:0] exp_debug;
wire exp_res_valid;
negexp negexp(
.clk(clk),
.rst(rst),
.inp(floatval2_data),
.inp_valid(floatval2_valid),
.out(exp_res),
.out_valid(exp_res_valid),
.debug(exp_debug)
);
wire [31:0] recip_data;
wire recip_valid;
floating_point_reciprocal recip(
.aclk(clk),
.s_axis_a_tvalid(exp_res_valid),
.s_axis_a_tdata(exp_res),
.m_axis_result_tvalid(recip_valid),
.m_axis_result_tdata(recip_data)
);
assign out = {8'b0,1'b1,recip_data[22:0]}; // Cheap floating-to-fixed, because we know the output is in [0,1]
assign out_valid = recip_valid;
always @(*) begin
processing_d = processing_q;
diff_d = diff_q;
t_d = t_q;
if (processing_q) begin
if (recip_valid) begin
processing_d = 0;
end
end else if (inp_valid) begin
diff_d = new - old;
t_d = Tinv;
processing_d = 1;
end
end
always @(posedge clk) begin
t_q <= t_d;
processing_q <= processing_d;
diff_q <= diff_d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INFL = 1LL << 60; const long long INF = INFL; long long MOD = 1000000007; vector<long long> dy = {0, -1, 0, 1, 1, 1, -1, -1, 0}; vector<long long> dx = {1, 0, -1, 0, 1, -1, 1, -1, 0}; void pres(double A, long long x = 10) { cout << fixed << setprecision(x) << A << endl; } void BinarySay(long long x, long long y = 60) { for (long long i = 0; i < (y); i++) cout << (x >> (y - 1 - i) & 1); cout << endl; } long long get_bit(long long x) { return __builtin_popcountll(x); } long long pow_long(long long x, long long k) { long long res = 1; while (k > 0) { if (k % 2) res *= x; x *= x; k /= 2; } return res; } long long pow_mod(long long x, long long k) { long long res = 1; while (k > 0) { if (k % 2) { res *= x; res %= MOD; } x *= x; x %= MOD; k /= 2; } return res; } long long inverse(long long x) { return pow_mod(x, MOD - 2); }; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long x, long long y) { return x / gcd(x, y) * y; }; long long kai_mod(long long x) { if (x == 0) return 1; return x * kai_mod(x - 1) % MOD; } vector<long long> divisor(long long n) { vector<long long> res(0); for (long long i = 1; i * i <= n; i++) { if (n % i == 0) { res.push_back(i); if (i != n / i) res.push_back(n / i); } } sort(res.begin(), res.end()); return res; } vector<long long> MakePrimeList(long long x) { vector<long long> res; for (long long k = 2; k * k <= x; k++) { if (x % k == 0) { res.push_back(k); while (x % k == 0) x /= k; } } if (x > 1) res.push_back(x); return res; } const int MAXcomb = 2000100; long long fac[MAXcomb], finv[MAXcomb], inv[MAXcomb]; void COMinit() { fac[0] = fac[1] = 1; finv[0] = finv[1] = 1; inv[1] = 1; for (int i = 2; i < MAXcomb; i++) { fac[i] = fac[i - 1] * i % MOD; inv[i] = MOD - inv[MOD % i] * (MOD / i) % MOD; finv[i] = finv[i - 1] * inv[i] % MOD; } } long long comb(int n, int k) { if (n < k) return 0; if (n < 0 || k < 0) return 0; return fac[n] * finv[k] % MOD * finv[n - k] % MOD; } long long disit(long long x, long long d = 10) { long long res = 0; while (x) { res++; x /= d; } return res; } void compress(vector<long long> &S) { vector<long long> xs; for (long long i = 0; i < (S.size()); i++) xs.push_back(S[i]); sort(xs.begin(), xs.end()); xs.erase(unique(xs.begin(), xs.end()), xs.end()); for (long long i = 0; i < (S.size()); i++) { S[i] = lower_bound(xs.begin(), xs.end(), S[i]) - xs.begin(); } } void solve() { long long N; cin >> N; vector<long long> A(N); for (long long i = 0; i < (N); i++) cin >> A[i]; compress(A); long long M = A[0] + 1; vector<long long> cnt(M, 0); for (long long i = 0; i < (N); i++) cnt[A[i]]++; long long g = cnt[M - 1]; long long second = 0; long long at = M; for (long long i = (M)-1; i >= 0; i--) { if (i == M - 1) continue; second += cnt[i]; at = i; if (second > g) break; } long long B = 0; long long b = 0; for (long long i = at - 1; i >= 0; i--) { b += cnt[i]; if (b <= g) continue; if ((g + second + b) * 2 > N) break; B = b; } if (B == 0) g = second = 0; cout << g << << second << << B << endl; } int main() { cin.tie(0); ios::sync_with_stdio(false); long long T; cin >> T; for (long long i = 0; i < (T); i++) { solve(); } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_bkb_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_bkb_rom.dat", ram0);
$readmemh("./Loop_loop_height_bkb_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_bkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_bkb_rom Loop_loop_height_bkb_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
`timescale 1ns/1ns
`define LOG_EVENTS
`define LOG_SAMPLES
module fx2_timetag_bench();
reg clk;
wire fx2_clk;
wire [7:0] fd;
wire [2:0] flags;
wire [1:0] fifoadr;
wire sloe, slrd, slwr, pktend;
reg [3:0] strobe_in;
wire [35:0] counter = uut.tagger.apdtimer.tagger.timer;
// External Clock
initial clk = 0;
always #2 clk = ~clk;
// Simulate strobe inputs
reg [31:0] strobe_count;
initial strobe_count = 0;
initial strobe_in = 0;
always begin
#100 strobe_in[0] = 1;
`ifdef LOG_EVENTS
$display($time, " Strobe channel 0 (event %d, counter=%d)", strobe_count, counter);
`endif
#5 strobe_in[0] = 0;
if (uut.tagger.apdtimer.capture_operate)
strobe_count = strobe_count + 1;
end
always begin
#80 strobe_in[1] = 1;
`ifdef LOG_EVENTS
$display($time, " Strobe channel 1 (event %d, counter=%d)", strobe_count, counter);
`endif
#5 strobe_in[1] = 0;
if (uut.tagger.apdtimer.capture_operate)
strobe_count = strobe_count + 1;
end
reg [31:0] delta_count;
initial delta_count = 0;
wire [3:0] delta_chs;
`ifdef LOG_EVENTS
always @(posedge delta_chs[0])
$display($time, " Delta channel event %d", delta_count);
`endif
reg [7:0] cmd;
reg cmd_wr, cmd_commit;
wire cmd_sent;
wire [7:0] reply_data;
wire reply_rdy;
wire [7:0] sample_data;
wire sample_rdy;
fx2_test_fixture fx2(
.ifclk(fx2_clk),
.fd(fd),
.slrd(slrd),
.slwr(slwr),
.sloe(sloe),
.fifoadr(fifoadr),
.pktend(pktend),
.flags(flags),
.cmd_data(cmd),
.cmd_wr(cmd_wr),
.cmd_commit(cmd_commit),
.cmd_sent(cmd_sent),
.reply_data(reply_data),
.reply_rdy(reply_rdy),
.data(sample_data),
.data_rdy(sample_rdy)
);
// Instantiate the UUT
fx2_timetag uut(
.fx2_clk(fx2_clk),
.fx2_flags(flags),
.fx2_slwr(slwr),
.fx2_slrd(slrd),
.fx2_sloe(sloe),
.fx2_wu2(),
.fx2_pktend(pktend),
.fx2_fd(fd),
.fx2_fifoadr(fifoadr),
.ext_clk(clk),
.delta_chs(delta_chs),
.strobe_in(strobe_in),
.led()
);
reg [31:0] reply_buf;
task reg_cmd;
input write;
input [15:0] addr;
input [31:0] value;
begin
$display($time, " Register transaction on %04x with value %08x (wr=%d)", addr, value, write);
#12 cmd=8'hAA; cmd_wr=1;
#12 cmd=write;
#12 cmd=addr[7:0];
#12 cmd=addr[15:8];
#12 cmd=value[7:0];
#12 cmd=value[15:8];
#12 cmd=value[23:16];
#12 cmd=value[31:24];
#12 cmd_wr=0; cmd_commit=1;
#12 cmd_commit=0;
@(cmd_sent);
@(posedge fx2_clk && reply_rdy); // HACK perhaps
@(posedge fx2_clk && reply_rdy) reply_buf[7:0] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[15:8] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[23:16] = reply_data;
@(posedge fx2_clk && reply_rdy) reply_buf[31:24] = reply_data;
$display($time, " Register %04x = %08x", addr, reply_buf);
end
endtask
`ifdef LOG_SAMPLES
reg [47:0] sample_buf;
reg [31:0] sample_count;
initial sample_count = 0;
initial begin
#100 ; // Wait until things stabilize
forever begin
@(posedge fx2_clk && sample_rdy);
@(posedge fx2_clk && sample_rdy) sample_buf[47:40] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[39:32] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[31:24] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[23:16] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[15:8] = sample_data;
@(posedge fx2_clk && sample_rdy) sample_buf[7:0] = sample_data;
sample_count = sample_count + 1;
$display($time, " Sample #%d: %012x", sample_count, sample_buf);
end
end
`endif
//always @(posedge fx2_clk && sample_rdy) $display($time, " sample: %02x", sample_data);
// This just prints the results in the ModelSim text window
// You can leave this out if you want
//initial $monitor($time, " cmd(%b %x)", cmd_wr, cmd);
// These statements conduct the actual circuit test
initial begin
$display($time, " Starting...");
#100 ;
$display($time, " Starting with garbage");
#12 cmd=8'hFF; cmd_wr=1;
#12 cmd=8'hFF;
#12 cmd=8'hFF;
#12 cmd_wr=0; cmd_commit=1;
#12 cmd_commit=0;
@(cmd_sent);
#50 ;
$display($time, " Testing version register");
reg_cmd(0, 16'h1, 0);
#50 ;
$display($time, " Testing clockrate register");
reg_cmd(0, 16'h2, 0);
#50 ;
$display($time, " Resetting counter");
reg_cmd(1, 16'h3, 32'h04);
#50 ;
$display($time, " Enabling strobe channels");
reg_cmd(1, 16'h4, 32'h0f);
#50 ;
$display($time, " Starting capture");
reg_cmd(1, 16'h3, 32'h03);
$display($time, " Waiting for some data");
#4000 ;
#50 ;
$display($time, " Disabling strobe channels");
reg_cmd(1, 16'h4, 0);
#1000;
$display($time, " Setting up sequencer");
reg_cmd(1, 16'h28, 31'h03); // Enable channel 0, initial_state=1
reg_cmd(1, 16'h29, 31'd40); // Channel 0 initial count
reg_cmd(1, 16'h2a, 31'd80); // Channel 0 low count
reg_cmd(1, 16'h2b, 31'd60); // Channel 0 high count
reg_cmd(1, 16'h20, 31'h02); // Reset
reg_cmd(1, 16'h20, 31'h01); // Operate
#50 ;
$display($time, " Enabling delta channels");
reg_cmd(1, 16'h5, 32'h0f);
#4000 ;
#50 ;
$display($time, " Disabling delta channels");
reg_cmd(1, 16'h5, 0);
#50 ;
$display($time, " Stopping capture");
reg_cmd(1, 16'h3, 32'h02);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; while (~scanf( %d , &n)) { int cnt = 0; for (int i = 1; i < n; i++) { for (int j = i + 1; j < n; j++) { int sum = i * i + j * j; if (sum <= n * n) { if ((int)sqrt(sum) * (int)sqrt(sum) == sum) cnt++; } } } printf( %d n , cnt); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); string a, b; cin >> a >> b; if (a.size() == b.size()) { int ca = 0, cb = 0; for (int i = 0; i < a.size(); i++) { ca += a[i] == 1 ; cb += b[i] == 1 ; } if (!ca && cb || ca && !cb) cout << NO ; else cout << YES ; } else cout << NO ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: Convert_Float_To_Fixed
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module Convert_Float_To_Fixed(
//INPUTS
input wire CLK, //CLOCK
input wire [31:0] FLOAT, //VALOR DEL NUMERO EN PUNTO FLOTANTE
input wire EN_REG1, //ENABLE PARA EL REGISTRO 1 QUE GUARDA EL NUMERO EN PUNTO FLOTANTE
input wire LOAD, //SELECCION CARGA REGISTRO DE DESPLZAMIENTOS
input wire MS_1, //SELECCIONA EL MUX PARA UN VALOR DIFERENTE O IGUAL A 127 SEGUN SEA EL CASO
input wire RST,
input wire EN_REG2,
//OUTPUTS
output wire Exp_out, //INIDICA SI EL EXPONENTE ES MAYOR QUE 127
output wire [31:0] FIXED, //CONTIENE EL RESULTADO EN COMA FIJA
output wire [7:0] Exp //CONTIENE EL VALOR INICIAL DEL EXPONENTE
);
parameter P = 32;
parameter W = 8;
wire [31:0] float;
FF_D #(.P(P)) REG_FLOAT_I (
.CLK(CLK),
.RST(RST),
.EN(EN_REG1),
.D(FLOAT),
.Q(float)
);
Comparador_Mayor EXP127_I(
.CLK(CLK),
.A(float[30:23]),
.B(8'b01111111),
.Out(Exp_out)
);
wire [31:0] IN_BS;
wire [31:0] P_RESULT;
wire [31:0] MUX32;
wire [31:0] MUX32_OUT;
wire [31:0] NORM;
wire [7:0] MUX1;
wire [7:0] MUX2;
wire [7:0] SUBT_1;
wire [7:0] SUBT_2;
assign IN_BS [31:27] = 5'b00000;
assign IN_BS [26] = 1'b1;
assign IN_BS [25:3] = float[22:0];
assign IN_BS [2:0] = 3'b000;
assign Exp = float[30:23];
Barrel_Shifter #(.SWR(32),.EWR(8)) S_REG_I(
.clk(CLK),
.rst(RST),
.load_i(LOAD),
.Shift_Value_i(MUX2),
.Shift_Data_i(IN_BS),
.Left_Right_i(Exp_out),
.Bit_Shift_i(1'b0),
.N_mant_o(P_RESULT)
);
S_SUBT #(.P(W),.W(W)) SUBT_EXP_1_I (
.A(float[30:23]),
.B(8'b01111111),
.Y(SUBT_1)
);
S_SUBT #(.P(W),.W(W)) SUBT_EXP_2_I (
.A(8'b01111111),
.B(float[30:23]),
.Y(SUBT_2)
);
Mux_2x1_8Bits MUX2x1_1_I (
.MS(Exp_out),
.D_0(SUBT_2),
.D_1(SUBT_1),
.D_out(MUX1)
);
Mux_2x1_8Bits MUX2x1_2_I (
.MS(MS_1),
.D_0(8'b00000000),
.D_1(MUX1),
.D_out(MUX2)
);
SUBT_32Bits SUBT_RESULT_I (
.A(32'b00000000000000000000000000000000),
.B(P_RESULT),
.Y(MUX32)
);
Mux_2x1 #(.P(P)) MUX2x1_32Bits (
.MS(float[31]),
.D_0(P_RESULT),
.D_1(MUX32),
.D_out(MUX32_OUT)
);
FF_D #(.P(P)) REG_FIXED (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2),
.D(MUX32_OUT),
.Q(FIXED)
);
endmodule |
module ALU (
input [31:0] in1, in2,
input [5:0] ALUFun,
input sign,
output reg [31:0] out
);
reg zero, overflow;
wire negative;
reg [31:0] out00, out01, out10, out11;
reg nega;
assign negative = sign&nega;
always @ (*) begin
case (ALUFun[0])
1'b0: begin
out00 = in1 + in2;
zero = (out00 == 1'b0)? 1'b1 : 1'b0;
overflow = (sign&(in1[31]&in2[31]) ^ (in1[30]&in2[30])) | (~sign&(in1[31]&in2[31]));
nega = out00[31];
end
1'b1: begin
out00 = in1 + ~in2 + 32'b1;
zero = (out00 == 1'b0)? 1'b1 : 1'b0;
overflow = (sign&(in1[31]&in2[31]) ^ (in1[30]&in2[30])) | (~sign&(in1[31]&in2[31]));
nega = out00[31];
end
default : out00 = 32'b0;
endcase
case (ALUFun[3:1])
3'b001: out11 = zero ? 32'b1 : 32'b0;
3'b000: out11 = zero ? 32'b0 : 32'b1;
3'b010: out11 = nega ? 32'b1 : 32'b0;
3'b110: out11 = (nega|zero) ? 32'b1 : 32'b0; // blez
3'b100: out11 = (~in1[31]) ? 32'b1 : 32'b0; // bgez
3'b111: out11 = (~in1[31]&~zero) ? 32'b1 : 32'b0; // bgtz
default : out11 = 32'b0;
endcase
case (ALUFun[3:0])
4'b1000: out01 = in1 & in2;
4'b1110: out01 = in1 | in2;
4'b0110: out01 = in1 ^ in2;
4'b0001: out01 = ~(in1 | in2);
4'b1010: out01 = in1;
default : out01 = 32'b0;
endcase
case (ALUFun[1:0])
2'b00: begin // sll
out10 = in2;
if (in1[4]) out10 = out10<<16;
if (in1[3]) out10 = out10<<8;
if (in1[2]) out10 = out10<<4;
if (in1[1]) out10 = out10<<2;
if (in1[0]) out10 = out10<<1;
end
2'b01: begin // srl
out10 = in2;
if (in1[4]) out10 = out10>>16;
if (in1[3]) out10 = out10>>8;
if (in1[2]) out10 = out10>>4;
if (in1[1]) out10 = out10>>2;
if (in1[0]) out10 = out10>>1;
end
2'b11: begin // sra
out10 = in2;
if (in1[4]) out10 = (out10>>16) | {{16{in2[31]}},{16{1'b0}}};
if (in1[3]) out10 = ((out10>>8) | {{8{in2[31]}},{24{1'b0}}});
if (in1[2]) out10 = (out10>>4) | {{4{in2[31]}},{28{1'b0}}};
if (in1[1]) out10 = (out10>>2) | {{2{in2[31]}},{30{1'b0}}};
if (in1[0]) out10 = (out10>>1) | {{1{in2[31]}},{31{1'b0}}};
end
default : out10 = 32'b0;
endcase
case(ALUFun[5:4])
2'b00: out = out00;
2'b01: out = out01;
2'b10: out = out10;
2'b11: out = out11;
default: out<= 32'b0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T In() { T x; cin >> x; return x; } int main() { ios::sync_with_stdio(false), cin.tie(0); cout << ((In<int>() & 1) ? Ehab : Mahmoud ); return cout << endl, 0; } |
#include <bits/stdc++.h> using namespace std; uint64_t mat[5][5] = {{0, 0, 1, 0, 0}, {1, 0, 1, 0, 0}, {0, 1, 1, 0, 0}, {0, 0, 1, 1, 0}, {0, 0, 0, 1, 1}}; uint64_t ex[5][5] = {{0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}, {0, 0, 0, 0, 0}}; static const uint64_t mod = 1000000000 + 6; static const uint64_t mod2 = 1000000000 + 7; void mult(int i) { uint64_t tmp[5][5]; uint64_t tmp2[5][5]; if (i == 1) { for (int c = 0; c < 5; c++) { for (int d = 0; d < 5; d++) { tmp[c][d] = ex[c][d]; } } } else { for (int c = 0; c < 5; c++) { for (int d = 0; d < 5; d++) { tmp[c][d] = mat[c][d]; } } } for (int c = 0; c < 5; c++) { for (int d = 0; d < 5; d++) { tmp2[c][d] = ex[c][d]; } } for (int c = 0; c < 5; c++) { for (int d = 0; d < 5; d++) { ex[c][d] = 0; for (int k = 0; k < 5; k++) { ex[c][d] += (tmp2[c][k] * tmp[k][d]) % mod; ex[c][d] %= mod; } } } } void expo(uint64_t n) { if (n == 1) { for (int c = 0; c < 5; c++) { for (int d = 0; d < 5; d++) { ex[c][d] = mat[c][d]; } } return; } if (n % 2 == 0) { expo(n / 2); mult(1); } else { expo(n - 1); mult(0); } } static inline uint64_t calcCoeff(uint64_t a[5]) { uint64_t ans = 0; for (int c = 0; c < 5; c++) { ans += (a[c] * ex[c][2]) % mod; ans %= mod; } return ans; } uint64_t sexp(uint64_t a, uint64_t n) { if (n == 0) { return 1; } if (n % 2 == 0) { uint64_t ans = sexp(a, n / 2); return (ans * ans) % mod2; } else { return (a * sexp(a, n - 1)) % mod2; } } int main(void) { uint64_t n, f1, f2, f3, mc; cin >> n >> f1 >> f2 >> f3 >> mc; expo(n - 3); uint64_t nf1, nf2, nf3; uint64_t nc; uint64_t a, b, c; { uint64_t init[5] = {1, 0, 0, 0, 0}; nf1 = calcCoeff(init); } { uint64_t init[5] = {0, 1, 0, 0, 0}; nf2 = calcCoeff(init); } { uint64_t init[5] = {0, 0, 1, 0, 0}; nf3 = calcCoeff(init); } { uint64_t init[5] = {0, 0, 0, 2, 2}; nc = calcCoeff(init); } uint64_t ans = (((sexp(f1, nf1) * sexp(f2, nf2)) % mod2 * sexp(f3, nf3)) % mod2 * sexp(mc, nc)) % mod2; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[4], i, n, x; int main() { for (cin >> n, i = 0; i < n; ++i) cin >> x, --x, a[0] += !x, a[1] = max(a[0], a[1] + x), a[2] = max(a[1], a[2] + !x), a[3] = max(a[2], a[3] + x); cout << a[3] << endl; } |
#include <bits/stdc++.h> using namespace std; vector<int> adj[200005]; int visited[200005]; int dfs(int u) { visited[u] = 1; int iscycle = ((adj[u].size() == 2) ? (1) : (0)); for (int i = 0; i < adj[u].size(); ++i) { if (visited[adj[u][i]] == 0 and dfs(adj[u][i]) == 0) iscycle = 0; } return iscycle; } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) { int u, v; scanf( %d%d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } for (int i = 0; i <= n; ++i) visited[i] = 0; int ans = 0; for (int i = 1; i <= n; ++i) if (visited[i] == 0) ans += dfs(i); printf( %d n , ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_SYMBOL_V
`define SKY130_FD_SC_HS__O211A_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_SYMBOL_V
|
#include <bits/stdc++.h> const int S = 400004; int last, tr[S][26], fail[S], len[S], tot = 0, eg = 1, h[S], nx[S << 1], v[S << 1], e[S]; char c[S]; void insert(int &last, char c) { c -= a ; int p = last, now = ++tot; len[now] = len[last] + 1; while (p != -1 && !tr[p][c]) { tr[p][c] = now; p = fail[p]; } if (p == -1) fail[now] = 0; else { int q = tr[p][c]; if (len[p] + 1 == len[q]) fail[now] = q; else { int w = ++tot; len[w] = len[p] + 1; fail[w] = fail[q]; for (int i = 0; i < 26; ++i) tr[w][i] = tr[q][i]; fail[q] = fail[now] = w; while (p != -1 && tr[p][c] == q) { tr[p][c] = w; p = fail[p]; } } } last = now; } inline void egadd(int uu, int vv) { nx[++eg] = h[uu]; h[uu] = eg; v[eg] = vv; } long long res = 0; void dfs(int x) { for (int i = h[x]; i; i = nx[i]) { dfs(v[i]); e[x] += e[v[i]]; } res += (len[x] - len[fail[x]]) * 1ll * e[x] * e[x]; } int main() { int T; scanf( %d , &T); while (T--) { tot = last = 0; fail[0] = -1; res = 0; scanf( %s , c + 1); for (int i = 1; c[i]; ++i) insert(last, c[i]); int p = 0; for (int i = 1; c[i]; ++i) { p = tr[p][c[i] - a ]; e[p] = 1; } for (int i = 1; i <= tot; ++i) egadd(fail[i], i); dfs(0); printf( %lld n , res); for (int i = 0; i <= tot; ++i) { fail[i] = len[i] = 0; h[i] = 0; e[i] = 0; for (int j = 0; j < 26; ++j) tr[i][j] = 0; } eg = 1; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A41OI_FUNCTIONAL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, sum = 0, sum1 = 0; int x; cin >> n; for (int i = 0; i < (int)n - 1; ++i) { cin >> x; sum += x; } for (int i = 1; i <= n; i++) sum1 += i; cout << sum1 - sum << endl; return 0; } |
#include <bits/stdc++.h> constexpr int P = 998244353; struct Matrix { int a[4]; Matrix() : a{} {} friend Matrix operator*(const Matrix &lhs, const Matrix &rhs) { Matrix res; res.a[0] = (1ll * lhs.a[0] * rhs.a[0] + 1ll * lhs.a[1] * rhs.a[2]) % P; res.a[1] = (1ll * lhs.a[0] * rhs.a[1] + 1ll * lhs.a[1] * rhs.a[3]) % P; res.a[2] = (1ll * lhs.a[2] * rhs.a[0] + 1ll * lhs.a[3] * rhs.a[2]) % P; res.a[3] = (1ll * lhs.a[2] * rhs.a[1] + 1ll * lhs.a[3] * rhs.a[3]) % P; return res; } }; struct SegmentTree { const int n; std::vector<int> a; std::vector<Matrix> t; SegmentTree(const std::vector<int> &a) : n(a.size()), a(a), t(4 * n) { build(1, 0, n); } void build(int p, int l, int r) { if (r - l == 1) { t[p].a[0] = a[l] + 1; t[p].a[1] = 1; t[p].a[2] = (l && a[l - 1] == 1) ? (9 - a[l]) : 0; } else { int m = (l + r) / 2; build(2 * p, l, m); build(2 * p + 1, m, r); t[p] = t[2 * p] * t[2 * p + 1]; } } void update(int p, int l, int r, int x) { if (r - l == 1) { t[p].a[0] = a[l] + 1; t[p].a[2] = (l && a[l - 1] == 1) ? (9 - a[l]) : 0; } else { int m = (l + r) / 2; if (x < m) { update(2 * p, l, m, x); } else { update(2 * p + 1, m, r, x); } t[p] = t[2 * p] * t[2 * p + 1]; } } void modify(int x, int y) { a[x] = y; update(1, 0, n, x); if (x + 1 < n) update(1, 0, n, x + 1); } int query() { return t[1].a[0]; } }; int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); int n, m; std::cin >> n >> m; std::vector<int> a(n); for (int i = 0; i < n; ++i) { char c; std::cin >> c; a[i] = c - 0 ; } SegmentTree t(a); while (m--) { int x, y; std::cin >> x >> y; --x; t.modify(x, y); std::cout << t.query() << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const unsigned long long MOD = 1e8 + 7; const unsigned long long base = 71; const unsigned long long max_n = 2e5 + 400; unsigned long long n, m, k, q; string s; unsigned long long pw[2 * max_n + 200]; unsigned long long save[20][2 * max_n + 200]; unsigned long long seg[10 * max_n], lazy[10 * max_n]; void init(unsigned long long v, unsigned long long b, unsigned long long e) { lazy[v] = -1; if (b == e) { seg[v] = s[b]; return; } unsigned long long mid = (b + e) / 2; init(v << 1, b, mid); init(v << 1 ^ 1, mid + 1, e); seg[v] = (seg[v << 1] * pw[e - mid] + seg[v << 1 ^ 1]) % MOD; } void shift(unsigned long long v, unsigned long long b, unsigned long long e, unsigned long long mid) { if (lazy[v] == -1) return; lazy[v << 1] = lazy[v << 1 ^ 1] = lazy[v]; seg[v << 1] = save[lazy[v]][mid - b]; seg[v << 1 ^ 1] = save[lazy[v]][e - mid - 1]; lazy[v] = -1; } void update(unsigned long long v, unsigned long long b, unsigned long long e, unsigned long long l, unsigned long long r, unsigned long long val) { if (b > r || l > e) return; if (l <= b && e <= r) { seg[v] = save[val][e - b]; lazy[v] = val; return; } unsigned long long mid = (b + e) / 2; shift(v, b, e, mid); update(v << 1, b, mid, l, r, val); update(v << 1 ^ 1, mid + 1, e, l, r, val); seg[v] = (seg[v << 1] * pw[e - mid] + seg[v << 1 ^ 1]) % MOD; } unsigned long long get(unsigned long long v, unsigned long long b, unsigned long long e, unsigned long long l, unsigned long long r) { if (b > r || l > e) return 0; if (l <= b && e <= r) return seg[v]; unsigned long long mid = (b + e) / 2; shift(v, b, e, mid); unsigned long long first = get(v << 1, b, mid, l, r); unsigned long long second = get(v << 1 ^ 1, mid + 1, e, l, r); first = (first * pw[max(0, int(min(r, e) - mid))] + second) % MOD; return first; } int main() { ios_base::sync_with_stdio(false), cin.tie(0); cin >> n >> m >> k; q = m + k; cin >> s; pw[0] = 1; for (unsigned long long i = 1; i < max_n; i++) pw[i] = (pw[i - 1] * base) % MOD; for (unsigned long long i = 0; i < 10; i++) { save[i][0] = i + 48; for (unsigned long long j = 1; j < max_n; j++) save[i][j] = (save[i][j - 1] * base + (i + 48)) % MOD; } init(1, 0, n - 1); while (q--) { unsigned long long type, l, r; cin >> type >> l >> r; l--, r--; if (type == 1) { unsigned long long c; cin >> c; update(1, 0, n - 1, l, r, c); continue; } bool fl = 0; unsigned long long d; cin >> d; if (d == r - l + 1) fl = 1; if (!fl) fl = get(1, 0, n - 1, l, r - d) == get(1, 0, n - 1, l + d, r); if (fl) cout << YES n ; else cout << NO n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int wall[110][110] = {0}; int r, c; scanf( %d %d%*c , &r, &c); char a[110]; for (int i = 1; i < r; i++) gets(a); int flag = 0; int seg = 0; for (int i = 0; i < c; i++) { char x; scanf( %c , &x); if (flag == 0) { if (x == B ) { flag++; seg++; } else continue; } else { if (x == B ) continue; else flag = 0; } } printf( %d n , seg); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/27/2014 12:04:19 PM
// Design Name:
// Module Name: keyed_permutation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module keyed_permutation #(
parameter UNIT_WIDTH = 1,
parameter NUNITS = 32,
parameter INDEX_WIDTH = 5
)(
input wire i_clk,
input wire [NUNITS*UNIT_WIDTH-1:0] i_dat,
input wire [NUNITS*INDEX_WIDTH-1:0] i_key,
input wire i_inverse,
output reg [NUNITS*UNIT_WIDTH-1:0] o_dat
);
function [INDEX_WIDTH-1:0] get_nth_zero_index;
input [NUNITS-1:0] in;
input [INDEX_WIDTH-1:0] index;
integer i;
reg [INDEX_WIDTH-1:0] zero_index;
reg [INDEX_WIDTH-1:0] out;
begin
out = {INDEX_WIDTH{1'bx}};
zero_index = 0;
for(i=0;i<NUNITS;i=i+1) begin
if(~in[i]) begin
if(index==zero_index) begin
out = i;
end
zero_index = zero_index + 1;
end
end
get_nth_zero_index = out;
end
endfunction
function [NUNITS*INDEX_WIDTH-1:0] compute_map;
input [NUNITS*INDEX_WIDTH-1:0] key;
reg [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS-1:0] done;
reg [INDEX_WIDTH-1:0] outPos;
reg [NUNITS-1:0] outDone;reg [8:0] pos;
reg [INDEX_WIDTH:0] remaining;
integer i;
reg [INDEX_WIDTH-1:0] index;
integer indexWidth;
begin
indexWidth = INDEX_WIDTH;
outDone = {NUNITS{1'b0}};
pos = 0;
outPos = 0;
remaining = NUNITS;
for(i=0;i<NUNITS;i=i+1) begin
/*if(i<16) indexWidth = 5;
else if(i<24) indexWidth = 4;
else if(i<28) indexWidth = 3;
else if(i<30) indexWidth = 2;
else indexWidth = 1;*/
index = {INDEX_WIDTH{1'b0}};
if(i!=31) begin
index = key[pos+:INDEX_WIDTH] % remaining;
remaining = remaining - 1;
pos = pos + indexWidth;
end
outPos = get_nth_zero_index(outDone,index);
//$display("%02d -> %02d",i,outPos);
outDone[outPos]=1'b1;
map[outPos*INDEX_WIDTH+:INDEX_WIDTH]=i;
end
compute_map = map;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] permute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[i*UNIT_WIDTH+:UNIT_WIDTH] = in[index*UNIT_WIDTH+:UNIT_WIDTH];
end
permute = out;
end
endfunction
function [NUNITS*UNIT_WIDTH-1:0] unpermute;
input [NUNITS*UNIT_WIDTH-1:0] in;
input [NUNITS*INDEX_WIDTH-1:0] map;
reg [NUNITS*UNIT_WIDTH-1:0] out;
integer i;
reg [INDEX_WIDTH-1:0] index;
begin
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
out[index*UNIT_WIDTH+:UNIT_WIDTH] = in[i*UNIT_WIDTH+:UNIT_WIDTH];
end
unpermute = out;
end
endfunction
reg [NUNITS*INDEX_WIDTH-1:0] map;
always @(posedge i_clk) begin
map <= compute_map(i_key);
o_dat <= i_inverse ? unpermute(i_dat,map) : permute(i_dat,map);
end
/*
always @(i_dat) begin: PERMUTE
reg [INDEX_WIDTH-1:0] i;
reg [INDEX_WIDTH-1:0] index;
map = 0;//compute_map(i_key);
for(i=0;i<NUNITS;i=i+1) begin
index = map[i*INDEX_WIDTH+:INDEX_WIDTH];
if(i_inverse) o_dat[index*UNIT_WIDTH+:UNIT_WIDTH] = i_dat[i*UNIT_WIDTH+:UNIT_WIDTH];
else o_dat[i*UNIT_WIDTH+:UNIT_WIDTH] = i_dat[index*UNIT_WIDTH+:UNIT_WIDTH];
end
end*/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 6100, EMAX = 13000, VMAX = 6100; struct Edge { int x; int y; int next; }; int N, R[NMAX], ans; short f[NMAX][NMAX], g[NMAX][NMAX]; int V[VMAX], eid; Edge E[EMAX]; void insert(int x, int y) { E[++eid] = (Edge){x, y, V[x]}; V[x] = eid; } int calc(int x, int y) { int i, j, res = max(f[x][0], g[y][0]); for (i = 1, j = g[y][0]; i <= f[x][0]; i += 1) { while (j && R[f[x][i]] >= R[g[y][j]]) j -= 1; res = max(res, i + j); } return res; } void DFS(int pre, int x) { int i, j, y, l, r, m; f[x][0] = g[x][0] = 1; f[x][1] = g[x][1] = x; for (i = V[x]; i; i = E[i].next) { if ((y = E[i].y) == pre) continue; DFS(x, y); ans = max(ans, calc(x, y)); ans = max(ans, calc(y, x)); if (R[x] <= R[f[y][1]]) f[y][1] = x; else if (R[f[y][f[y][0]]] < R[x]) f[y][++f[y][0]] = x; else { for (l = 1, r = f[y][0]; l + 1 < r;) { m = (l + r) >> 1; if (R[f[y][m]] < R[x]) l = m; else r = m; } f[y][r] = x; } if (R[x] >= R[g[y][1]]) g[y][1] = x; else if (R[g[y][g[y][0]]] > R[x]) g[y][++g[y][0]] = x; else { for (l = 1, r = g[y][0]; l + 1 < r;) { m = (l + r) >> 1; if (R[g[y][m]] > R[x]) l = m; else r = m; } g[y][r] = x; } f[x][0] = max(f[x][0], f[y][0]); g[x][0] = max(g[x][0], g[y][0]); for (j = 1; j <= f[y][0]; j += 1) { f[x][j] = f[x][j] && R[f[x][j]] < R[f[y][j]] ? f[x][j] : f[y][j]; } for (j = 1; j <= g[y][0]; j += 1) { g[x][j] = g[x][j] && R[g[x][j]] > R[g[y][j]] ? g[x][j] : g[y][j]; } } } int main() { int i, x, y; scanf( %d , &N); for (i = 1; i <= N; i += 1) scanf( %d , &R[i]); for (i = 1; i < N; i += 1) { scanf( %d %d , &x, &y); insert(x, y); insert(y, x); } DFS(-1, 1); printf( %d n , ans); exit(0); } |
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, c; cin >> a >> b >> c; if (a >= c || b >= c) { cout << 0 ; } else if (a <= 0 && b <= 0) { cout << -1 ; } else { long long int count = 0; while (a < c && b < c) { if (a > b) { swap(a, b); } else if (a < 0) { count += (abs(a) / b + (abs(a) % b != 0)); if (abs(a) % b) { long long int r = abs(a) % b; a = (b - r); } else { a = 0; } } else { long long int p = b; b += a; a = p; count++; } } cout << count; } } |
// qmem_sram_tb.v
// 2013,
`timescale 1ns/10ps
module qmem_sram_tb();
//// parameters ////
parameter QAW = 32; // qmem adr width
parameter QDW = 32; // qmem dat width
parameter QSW = QDW/8; // qmem sel width
parameter AD = 10; // allowed delay for qmem slave
//// internal signals ////
reg clk50;
reg clk100;
reg rst;
wire mcs;
wire mwe;
wire [QSW-1:0] msel;
wire [QAW-1:0] madr;
wire [QDW-1:0] mdat_r;
wire [QDW-1:0] mdat_w;
wire mack;
wire merr;
wire error;
wire [ 18-1:0] SRAM_ADDR;
wire SRAM_CE_N;
wire SRAM_WE_N;
wire SRAM_UB_N;
wire SRAM_LB_N;
wire SRAM_OE_N;
wire [ 16-1:0] SRAM_DAT_W;
wire [ 16-1:0] SRAM_DAT_R;
wire [ 16-1:0] SRAM_DQ;
reg [QDW-1:0] q_dat;
reg [QAW-1:0] q_adr;
reg [QSW-1:0] q_sel;
//// bench ////
// clock & reset
initial begin
clk50 = 1;
forever #10 clk50 = ~clk50;
end
initial begin
clk100 = 1;
forever #5 clk100 = ~clk100;
end
initial begin
rst = 1;
#101;
rst = 0;
end
// bench
initial begin
$display("* BENCH : Starting ...");
#1;
wait(rst);
repeat (10) @ (posedge clk100);
#1;
// qmem master cycles
qmem_master.write(32'h00000000, 4'b1111, 32'h00000000);
qmem_master.read (32'h00000000, 4'b1111, q_dat);
qmem_master.write(32'h00000010, 4'b1111, 32'h00010001);
qmem_master.write(32'h00000014, 4'b1111, 32'h00010002);
qmem_master.write(32'h00000018, 4'b1111, 32'h00010003);
qmem_master.write(32'h0000001c, 4'b1111, 32'h00010004);
qmem_master.read (32'h00000010, 4'b1111, q_dat);
qmem_master.read (32'h00000014, 4'b1111, q_dat);
qmem_master.read (32'h00000018, 4'b1111, q_dat);
qmem_master.read (32'h0000001c, 4'b1111, q_dat);
qmem_master.read (32'h00000010, 4'b1111, q_dat);
qmem_master.write(32'h00000010, 4'b1111, 32'h00010001);
// read, write 0xdeadbeef to 0x0
q_dat = 32'hdeadbeef;
q_adr = 32'h00000000;
q_sel = 4'b1111;
qmem_master.write(q_adr, q_sel, q_dat);
q_dat = 32'h00000000;
qmem_master.read(q_adr, q_sel, q_dat);
if (q_dat != 32'hdeadbeef) begin
$display ("* BENCH : Error reading / writing 0x%08x to address 0x%08x !!!", q_dat, q_adr);
#100;
$finish(0);
end
// read, write 0x12345678 to 0x4
q_dat = 32'h12345678;
q_adr = 32'h00000004;
q_sel = 4'b0011;
qmem_master.write(q_adr, q_sel, q_dat);
q_dat = 32'h00000000;
qmem_master.read(q_adr, q_sel, q_dat);
if (q_dat != 32'h12zz5678) begin
$display ("* BENCH : Error reading / writing 0x%08x to address 0x%08x !!!", q_dat, q_adr);
#100;
$finish(0);
end
repeat (10) @ (posedge clk50);
$display("* BENCH : Done.");
$finish;
end
//// modules ////
// QMEM master
qmem_master #(
.QAW (QAW),
.QDW (QDW),
.QSW (QSW),
.AD (AD)
) qmem_master (
.clk (clk50 ),
.rst (rst ),
.cs (mcs ),
.we (mwe ),
.sel (msel ),
.adr (madr ),
.dat_o (mdat_w ),
.dat_i (mdat_r ),
.ack (mack ),
.err (merr ),
.error (error )
);
// QMEM SRAM bridge
qmem_sram #(
.AW (32),
.DW (32),
.SW (4)
) bridge (
// system signals
.clk50 (clk50 ),
.clk100 (clk100 ),
.rst (rst ),
// qmem bus
.adr (madr ),
.cs (mcs ),
.we (mwe ),
.sel (msel ),
.dat_w (mdat_w ),
.dat_r (mdat_r ),
.ack (mack ),
.err (merr ),
// SRAM interface
.sram_adr (SRAM_ADDR ),
.sram_ce_n (SRAM_CE_N ),
.sram_we_n (SRAM_WE_N ),
.sram_ub_n (SRAM_UB_N ),
.sram_lb_n (SRAM_LB_N ),
.sram_oe_n (SRAM_OE_N ),
.sram_dat_w (SRAM_DAT_W ),
.sram_dat_r (SRAM_DAT_R )
);
// SRAM data tristate drivers
assign SRAM_DQ = SRAM_OE_N ? SRAM_DAT_W : 16'bzzzzzzzzzzzzzzzz;
assign SRAM_DAT_R = SRAM_DQ;
// SRAM model
IS61LV6416L #(
.memdepth (262144),
.addbits (18)
) ram (
.A (SRAM_ADDR ),
.IO (SRAM_DQ ),
.CE_ (SRAM_CE_N ),
.OE_ (SRAM_OE_N ),
.WE_ (SRAM_WE_N ),
.LB_ (SRAM_LB_N ),
.UB_ (SRAM_UB_N )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int x, k, n, q, cnt; long long num[10]; int bel[1 << 10]; struct Square { long long num[75][75]; Square() { for (int i = 1; i <= 70; i++) { for (int j = 1; j <= 70; j++) num[i][j] = 1e18; num[i][i] = 0; } } Square operator*(const Square &a) const { Square tmp; for (int i = 1; i <= cnt; i++) tmp.num[i][i] = 1e18; for (int i = 1; i <= cnt; i++) for (int j = 1; j <= cnt; j++) for (int k = 1; k <= cnt; k++) tmp.num[i][j] = tmp.num[i][j] < (num[i][k] + a.num[k][j]) ? tmp.num[i][j] : (num[i][k] + a.num[k][j]); return tmp; } Square operator^(const int &x) { if (!x) return Square(); Square tmp, tmp1; int times = x; for (int i = 1; i <= cnt; i++) for (int j = 1; j <= cnt; j++) tmp1.num[i][j] = num[i][j]; while (times) { if (times & 1) tmp = tmp * tmp1; times >>= 1; tmp1 = tmp1 * tmp1; } return tmp; } } one; struct Stone { int place; long long val; } stone[30]; bool calc(int tmp) { int many = 0; for (int i = 1; i <= 8; i++) if (tmp & (1 << (i - 1))) many++; return many == x; } bool cmp(Stone a, Stone b) { return a.place < b.place; } int main() { scanf( %d%d%d%d , &x, &k, &n, &q); for (int i = 0; i <= (1 << k) - 1; i++) if (calc(i)) bel[i] = ++cnt; for (int i = 1; i <= k; i++) scanf( %lld , &num[i]); for (int i = 1; i <= q; i++) scanf( %d%lld , &stone[i].place, &stone[i].val); sort(stone + 1, stone + q + 1, cmp); for (int i = 1; i <= cnt; i++) one.num[i][i] = 1e18; for (int i = 1; i <= (1 << k) - 1; i++) { if (i & 1) { if (!bel[i]) continue; for (int j = 1; j <= k; j++) if (!((1 << j) & i)) one.num[bel[i]][bel[((1 << j) | i) >> 1]] = num[j]; } else if (bel[i]) one.num[bel[i]][bel[i >> 1]] = 0; } int now = 1; long long sum = 0; Square ans; for (int i = 1; i <= q; i++) { if (stone[i].place > n - x) { sum += stone[i].val; continue; } ans = ans * (one ^ (stone[i].place - now)), now = stone[i].place; for (int j = 1; j <= (1 << k) - 1; j += 2) if (bel[j]) for (int k = 1; k <= cnt; k++) ans.num[k][bel[j]] += stone[i].val; } ans = ans * (one ^ (n - x + 1 - now)); printf( %lld , ans.num[1][1] + sum); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFBBP_FUNCTIONAL_PP_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire SET ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; void start() {} int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long a, b; cin >> a >> b; if (a < b) swap(a, b); b = 2 * b; if (b >= a) cout << b * b << endl; else cout << a * a << endl; } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module ANN_ST_uOut_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./ANN_ST_uOut_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
q1 <= d1;
end
else
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module ANN_ST_uOut(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
output[DataWidth - 1:0] q1;
ANN_ST_uOut_ram ANN_ST_uOut_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ),
.q1( q1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int points(int p, int t) { int first = 75 * p; int second = 250 * p - p * t; return max(first, second); } int main() { int a, b, c, d; scanf( %d %d %d %d , &a, &b, &c, &d); int misha = points(a, c); int vasia = points(b, d); if (misha > vasia) { cout << Misha << endl; } else if (vasia > misha) { cout << Vasya << endl; } else { cout << Tie << endl; } return 0; } |
#include<bits/stdc++.h> using namespace std; int main(){ int t,n,x; set<int> notes; cin>>t; while(t--){ cin>>n; notes.clear(); for(int i=0;i<n;i++){ cin>>x; if(notes.find(x)==notes.end()){ notes.insert(x); }else{ notes.insert(x+1); } } cout<<notes.size()<<endl; } } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_FIFO_ADC_DATA (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 15: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 15: 0] data_out;
wire [ 15: 0] out_port;
wire [ 15: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[15 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int dis[40]; long long adj[40]; vector<long long> v1; vector<long long> v2; void bt(int l, int r, long long mask) { if (l == r) { v1.emplace_back(mask); return; } bt(l + 1, r, mask); if (adj[l] & mask) return; bt(l + 1, r, mask | (1ll << l)); } long long f[1 << 21]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int m; cin >> m; long long ans = 1; for (int i = 0; i < n; ++i) ans *= 2; for (int i = 0; i < m; ++i) { int x; cin >> x; --x; int y; cin >> y; --y; adj[x] |= (1ll << y); adj[y] |= (1ll << x); } long long cnt1 = 1; long long cnt01 = 1; long long cnt02 = 1; for (int j = 0; j < n; ++j) if (adj[j] == 0) cnt01 *= 2; fill(dis, dis + n, -1); for (int i = 0; i < n; ++i) if (dis[i] < 0) { cnt1 *= 2; cnt02 *= 2; int S = 0; queue<int> qu; qu.push(i); dis[i] = 0; while (qu.size()) { int u = qu.front(); qu.pop(); S++; for (int v = 0; v < n; ++v) if (adj[u] >> v & 1) { if (dis[v] < 0) dis[v] = dis[u] ^ 1, qu.push(v); if (dis[v] == dis[u]) cnt02 = 0; } } } if (ans == cnt1) ans = 0; ans -= cnt1; ans += cnt01 * 2; ans += cnt02; m = n / 2; bt(m, n, 0); v1.swap(v2); bt(0, m, 0); for (long long x : v2) { int M = 0; for (int i = 0; i < m; ++i) { if (adj[i] & x) continue; else M |= (1 << i); } f[M]++; } for (int i = 0; i < m; ++i) for (int j = 0; j < (1 << m); ++j) if (j >> i & 1) f[j ^ (1 << i)] += f[j]; for (long long x : v1) ans -= f[x], ans -= f[x]; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } vector<int> d(5000, 0); for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { ++d[abs(a[i] - a[j])]; } } vector<int> c(5000); c[4999] = 0; for (int i = 4998; i >= 0; --i) { c[i] = c[i + 1] + d[i + 1]; } long long good = 0; for (int d1 = 1; d1 < 5000; ++d1) { for (int d2 = 1; d2 < 5000 - d1; ++d2) { good += static_cast<long long>(d[d1]) * d[d2] * c[d1 + d2]; } } long long all = n * (n - 1) / 2; all = all * all * all; cout.precision(10); cout << fixed << static_cast<long double>(good) / static_cast<long double>(all); return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_wrlvl_off_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter nCK_PER_CLK = 2,
parameter CLK_PERIOD = 4,
parameter PO_INITIAL_DLY= 46,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter N_CTL_LANES = 3
)
(
input clk,
input rst,
input pi_fine_dly_dec_done,
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_s2_incdec_f,
output reg po_en_s2_f,
// Inc/dec Phaser_Out coarse delay line
output reg po_s2_incdec_c,
output reg po_en_s2_c,
// Completed adjusting delays for dq, dqs for tdqss
output po_ck_addr_cmd_delay_done,
// completed decrementing initialPO delays
output po_dec_done,
output phy_ctl_rdy_dly
);
localparam TAP_LIMIT = 63;
// PO fine delay tap resolution change by frequency. tCK > 2500, need
// twice the amount of taps
// localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY;
// coarse delay tap is added DQ/DQS to meet the TDQSS specification.
localparam TDQSS_DLY = (tCK > 2500 )? 2: 1;
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] po_delay_cnt_r;
reg po_cnt_inc;
reg cmd_delay_start_r1;
reg cmd_delay_start_r2;
reg cmd_delay_start_r3;
reg cmd_delay_start_r4;
reg cmd_delay_start_r5;
reg cmd_delay_start_r6;
reg po_delay_done;
reg po_delay_done_r1;
reg po_delay_done_r2;
reg po_delay_done_r3;
reg po_delay_done_r4;
reg pi_fine_dly_dec_done_r;
reg po_en_stg2_c;
reg po_en_stg2_f;
reg po_stg2_incdec_c;
reg po_stg2_f_incdec;
reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r;
reg [DQS_CNT_WIDTH:0] lane_cnt_po_r;
reg [5:0] delay_cnt_r;
always @(posedge clk) begin
cmd_delay_start_r1 <= #TCQ cmd_delay_start;
cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1;
cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2;
cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3;
cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4;
cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5;
pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done;
end
assign phy_ctl_rdy_dly = cmd_delay_start_r6;
// logic for decrementing initial fine delay taps for all PO
// Decrement done for add, ctrl and data phaser outs
assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4;
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 || po_delay_done) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end else if (po_delay_cnt_r > 6'd0) begin
po_en_stg2_f <= #TCQ ~po_en_stg2_f;
end
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0))
// set all the PO delays to 31. Decrement from 46 to 31.
// Requirement comes from dqs_found logic
po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31);
else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0))
po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1;
always @(posedge clk)
if (rst)
lane_cnt_po_r <= #TCQ 'd0;
else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1))
lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1;
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 )
po_delay_done <= #TCQ 1'b0;
else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0))
po_delay_done <= #TCQ 1'b1;
always @(posedge clk) begin
po_delay_done_r1 <= #TCQ po_delay_done;
po_delay_done_r2 <= #TCQ po_delay_done_r1;
po_delay_done_r3 <= #TCQ po_delay_done_r2;
po_delay_done_r4 <= #TCQ po_delay_done_r3;
end
// logic to select between all PO delays and data path delay.
always @(posedge clk) begin
po_s2_incdec_f <= #TCQ po_stg2_f_incdec;
po_en_s2_f <= #TCQ po_en_stg2_f;
end
// Logic to add 1/4 taps amount of delay to data path for tdqss.
// After all the initial PO delays are decremented the 1/4 delay will
// be added. Coarse delay taps will be added here .
// Delay added only to data path
assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r
: delay_done_r4;
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin
po_stg2_incdec_c <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b0;
end else if (delay_cnt_r > 6'd0) begin
po_en_stg2_c <= #TCQ ~po_en_stg2_c;
end
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0))
delay_cnt_r <= #TCQ TDQSS_DLY;
else if ( po_en_stg2_c && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
always @(posedge clk)
if (rst)
lane_cnt_dqs_c_r <= #TCQ 'd0;
else if ( po_en_stg2_c && (delay_cnt_r == 6'd1))
lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1;
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r)
delay_done <= #TCQ 1'b0;
else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0))
delay_done <= #TCQ 1'b1;
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
always @(posedge clk) begin
po_s2_incdec_c <= #TCQ po_stg2_incdec_c;
po_en_s2_c <= #TCQ po_en_stg2_c;
ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a, i, j, sum, k; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> a; sum += a; j += 1 - 2 * a; if (j < 0) j = 0; if (k < j) k = j; } if (!k) { cout << sum - 1; } else { cout << sum + k; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, t, k, x, d[200001] = {}, last_d = 1, last = 0, a; long long sum = 0; cin >> n; for (int i = 0; i < n; ++i) { cin >> t; if (1 == t) { cin >> a >> x; sum += a * x; if (last_d == 0) { last += x; } else if (last_d == a) { last += x; } else { d[a] -= x; } } else if (2 == t) { cin >> k; sum += k; d[last_d++] = k - last; last = k; } else { sum -= last; last -= d[--last_d]; } cout << setiosflags(ios::fixed) << setprecision(6) << ((double)sum) / ((double)last_d) << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << 3 * (n / 2); } |
#include <bits/stdc++.h> const int INF = 1e9; using namespace std; int dx[] = {-1, 1, 0, 0}; int dy[] = {0, 0, -1, 1}; bool vis[1005][1005], cvis[50]; vector<pair<int, int> > cc[50]; int m, n, k, a[1005][1005], D[45][1005][1005]; void DFS(int c) { memset(vis, 0, sizeof(vis)); memset(cvis, 0, sizeof(cvis)); for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) D[c][i][j] = 4000; queue<pair<int, int> > Q; for (int i = 0; i < cc[c].size(); i++) { Q.push(cc[c][i]); vis[cc[c][i].first][cc[c][i].second] = 1; D[c][cc[c][i].first][cc[c][i].second] = 0; } cvis[c] = 1; int first, second, xx, yy; while (!Q.empty()) { first = Q.front().first; second = Q.front().second; Q.pop(); for (int j = 0; j < 4; j++) { xx = first + dx[j]; yy = second + dy[j]; if (xx < 1 || yy < 1 || xx > m || yy > n) continue; if (!vis[xx][yy]) { vis[xx][yy] = 1; D[c][xx][yy] = D[c][first][second] + 1; Q.push(pair<int, int>(xx, yy)); } } if (!cvis[a[first][second]]) { cvis[a[first][second]] = 1; for (int i = 0; i < cc[a[first][second]].size(); i++) { xx = cc[a[first][second]][i].first; yy = cc[a[first][second]][i].second; if (!vis[xx][yy]) { vis[xx][yy] = 1; D[c][xx][yy] = D[c][first][second] + 1; Q.push(pair<int, int>(xx, yy)); } } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> m >> n >> k; for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) { cin >> a[i][j]; cc[a[i][j]].push_back(pair<int, int>(i, j)); } for (int i = 1; i <= k; i++) DFS(i); int ans = INF, q, r1, r2, c1, c2; cin >> q; while (q--) { cin >> r1 >> c1 >> r2 >> c2; ans = abs(r2 - r1) + abs(c1 - c2); for (int i = 1; i <= k; i++) { ans = min(ans, D[i][r1][c1] + D[i][r2][c2] + 1); } cout << ans << n ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:56:23 06/11/2014
// Design Name:
// Module Name: DasBlinkenLights
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DasBlinkenLights(
input clk,
input [3:0] btn,
input [7:0] sw,
output [7:0] led,
output [3:0] anode, // asserted low
output [7:0] cathode, // asserted low
input rx,
output tx
);
assign anode = 4'hF;
assign cathode = 8'hFF;
assign tx = rx;
wire [7:0] grayScramble;
assign led = {
grayScramble[6],
grayScramble[0],
grayScramble[5],
grayScramble[3],
grayScramble[1],
grayScramble[4],
grayScramble[2],
grayScramble[7]
};
GrayCounter gc (clk, sw[7], sw[6], btn[3], grayScramble);
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; long long ara[205]; long long dp[205][205][205]; int n, k, x; long long rec(int pos, int last, int left) { if (last > k) return -1e17; if (pos == n + 1) { if (!left) return 0; return (-1e17); } if (left < 0) return -1e17; long long& ret = dp[pos][last][left]; if (~ret) return ret; ret = -1e17; if (rec(pos + 1, 1, left - 1) >= 0) ret = max(ret, rec(pos + 1, 1, left - 1) + ara[pos]); if (rec(pos + 1, last + 1, left) >= 0) ret = max(ret, rec(pos + 1, last + 1, left)); return ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); scanf( %d %d %d , &n, &k, &x); for (int i = 1; i <= n; i++) scanf( %lld , &ara[i]); memset(dp, -1, sizeof dp); printf( %lld n , (rec(1, 1, x) <= 0 ? -1 : rec(1, 1, x))); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_lp/sky130_fd_sc_hd__udp_dlatch_lp.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputisolatch (
Q ,
D ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$lP dlatch0 (buf_Q , D, SLEEP_B );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V |
`include "Global_Macros.v"
module ALU(
operation_i,
status_i,
operand1_i,
operand2_i,
status_o,
result_o
);
//Input signals :
input wire [4:0] operation_i;
input wire [7:0] status_i;
input wire [15:0] operand1_i;
input wire [15:0] operand2_i;
//Output signals :
output wire [7:0] status_o;
output wire [15:0] result_o;
//Internal registers :
reg [15:0] result_reg;
reg cflag_reg;
reg vflag_reg;
//Assignments :
assign result_o = result_reg;
assign status_o[`N] = (operation_i == `ALU_ITF) ? operand1_i[`N] :
(operation_i == `ALU_BRK) ? status_i[`N] : result_reg[7];
assign status_o[`V] = (operation_i == `ALU_ITF) ? operand1_i[`V] :
(operation_i == `ALU_CLV) ? 1'h0 : vflag_reg;
assign status_o[`P] = (operation_i == `ALU_ITF) ? operand1_i[`P] : status_i[`P];
assign status_o[`B] = (operation_i == `ALU_ITF) ? operand1_i[`B] :
(operation_i == `ALU_BRK) ? 1'h1 : status_i[`B];
assign status_o[`D] = (operation_i == `ALU_ITF) ? operand1_i[`D] :
(operation_i == `ALU_CLD) ? 1'h0 :
(operation_i == `ALU_SED) ? 1'h1 : status_i[`D];
assign status_o[`I] = (operation_i == `ALU_ITF) ? operand1_i[`I] :
(operation_i == `ALU_CLI) ? 1'h0 :
(operation_i == `ALU_SEI) ? 1'h1 :
(operation_i == `ALU_BRK) ? 1'h1 : status_i[`I];
assign status_o[`Z] = (operation_i == `ALU_ITF) ? operand1_i[`Z] :
(operation_i == `ALU_BRK) ? status_i[`Z] :
(result_reg[7:0] == 8'h0) ? 1'h1 : 1'h0;
assign status_o[`C] = (operation_i == `ALU_ITF) ? operand1_i[`C] :
(operation_i == `ALU_CLC) ? 1'h0 :
(operation_i == `ALU_SEC) ? 1'h1 : cflag_reg;
//Blocks :
always @(operand1_i or operand2_i or operation_i or status_i[`C])
begin
case(operation_i)
`ALU_ADD : begin
result_reg = operand1_i + operand2_i + status_i[`C];
cflag_reg = result_reg[8];
vflag_reg = ( operand1_i[7] && operand2_i[7] && ~result_reg[7])||
(~operand1_i[7] && ~operand2_i[7] && result_reg[7]);
end
`ALU_AND : begin
result_reg = operand1_i & operand2_i;
end
`ALU_BRK : begin
result_reg = operand1_i;
end
`ALU_CMP : begin
result_reg = operand2_i - operand1_i;
cflag_reg = operand2_i < operand1_i ? 1'h1 : 1'h0;
end
`ALU_DEC : begin
result_reg = operand1_i - 16'h1;
end
`ALU_INC : begin
result_reg = operand1_i + 16'h1;
end
`ALU_ITO : begin
result_reg = operand1_i;
end
`ALU_ORA : begin
result_reg = operand1_i | operand2_i;
end
`ALU_ROL : begin
result_reg = operand1_i << 1;
result_reg[0] = cflag_reg;
cflag_reg = result_reg[8];
end
`ALU_ROR : begin
result_reg = operand1_i >> 1;
result_reg[7] = cflag_reg;
cflag_reg = operand1_i[0];
end
`ALU_SHL : begin
result_reg = operand1_i << 1;
cflag_reg = operand1_i[7];
end
`ALU_SHR : begin
result_reg = operand1_i >> 1;
cflag_reg = operand1_i[0];
end
`ALU_SUB : begin
result_reg = operand2_i - operand1_i - status_i[`C];
cflag_reg = operand2_i < (operand1_i + status_i[`C]) ? 1'h1 : 1'h0;
vflag_reg = ( operand1_i[7] && operand2_i[7] && ~result_reg[7]) ||
(~operand1_i[7] && ~operand2_i[7] && result_reg[7]);
end
`ALU_XOR : begin
result_reg = operand1_i ^ operand2_i;
end
default : begin
result_reg = result_reg;
cflag_reg = (operation_i == `ALU_CLC) ? 1'h0 :
(operation_i == `ALU_SEC) ? 1'h1 : status_i[`C];
vflag_reg = (operation_i == `ALU_CLV) ? 1'h0 : status_i[`V];
end
endcase
end
endmodule |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:60000000 ) using namespace std; const int MAXN = 10 + 100000; const int INF = int(1e9); const int m = 4; int k, t, d; int a[5][5], i, j, n; void nhap() { scanf( %d , &n); for (int i = (1), _b = (m); i <= m; ++i) scanf( %d%d%d%d , &a[i][1], &a[i][2], &a[i][3], &a[i][4]); } void xuli() {} int main() { nhap(); xuli(); for (int i = (1), _b = (m); i <= m; ++i) { t = min(a[i][1], a[i][2]); d = min(a[i][3], a[i][4]); if (n - t >= d) { cout << i << << t << << n - t; return 0; } } printf( -1 ); return 0; } |
#include <bits/stdc++.h> int main() { int n; int a[100000]; int l0, l1; int i, j; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &a[i]); } l0 = 0; l1 = 0; for (i = 1; i < n; i++) { if (a[i] >= a[i - 1]) { l1++; } if (a[i] < a[i - 1]) { if (l0 < l1) { l0 = l1; } l1 = 0; } } if (l0 < l1) { l0 = l1; } printf( %d , l0 + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; typedef long long ll; int get_next_state(bool s1, bool s2, bool b1, bool b2) { if (s1 && b1) { return -1; } if (s2 && b2) { return -1; } bool a1 = s1 | b1; bool a2 = s2 | b2; if ((a1 && a2) || (!a1 && !a2)) { return 0; } if (a1) { return 1; } return 2; } bool solve_dp(int n, const vector<pair<int, int>>& cr) { const bool S1[3] = {false, false, true}; const bool S2[3] = {false, true, false}; vector<vector<bool>> filled(2, vector<bool>(n, false)); int m = cr.size(); for (int i = 0; i < m; ++i) { filled[cr[i].second][cr[i].first] = true; } /* for (int r = 0; r < 2; ++r) { for (int i = 0; i < n; ++i) { if (filled[r][i]) { cout << # ; } else { cout << . ; } } cout << endl; } */ vector<uint8_t> dp(n+1); dp[n] = 1; for (int i = n-1; i >= 0; --i) { dp[i] = 0; for (int state = 0; state < 3; ++state) { int next_state = get_next_state(S1[state], S2[state], filled[0][i], filled[1][i]); //cout << next_state[ << i << ][ << state << ] = << next_state << endl; if (next_state >= 0) { dp[i] |= ((dp[i+1] >> next_state) & 1) << state; } } //cout << dp[i] << ; } //cout << endl; return (dp[0] & 1) == 1; } bool solve_dp2(int n, const vector<pair<int, int>>& cr) { int m = cr.size(); int prv_state = 0; int prv_posish = 0; int p = 0; while (p < m) { int posish = cr[p].first; int state = 0; if ((p < (m-1)) && (cr[p+1].first == posish)) { p += 2; } else { state = cr[p].second+1; p++; } if (state == 0) { if (prv_state != 0) { return false; } } else { if (prv_state == 0) { prv_state = 3-state; } else { if (((posish - prv_posish) % 2) == 1) { prv_state = 3-prv_state; } if (prv_state != state) { return false; } prv_state = 0; } } prv_posish = posish; } return (prv_state == 0); } bool solve(int n, const vector<int>& r, const vector<int>& c) { int m = r.size(); vector<pair<int, int>> cr(m); for (int i = 0; i < m; ++i) { cr[i] = make_pair(c[i], r[i]); } sort(cr.begin(), cr.end()); return solve_dp2(n, cr); vector<pair<int, int>> ccr(m); int prv_c = 0; int compress = 0; for (int i = 0; i < m; ++i) { if ((cr[i].first - prv_c) >= 2) { compress += ((cr[i].first - prv_c - 2) / 2) * 2; } prv_c = cr[i].first; ccr[i] = make_pair(cr[i].first-compress, cr[i].second); } return solve_dp(n-compress, ccr); } void test_case() { int n, m; cin >> n >> m; vector<int> r(m), c(m); for (int i = 0; i < m; ++i) { cin >> r[i] >> c[i]; --r[i]; --c[i]; } if (solve(n, r, c)) { cout << YES << endl; } else { cout << NO << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; for (int i = 0; i < t; ++i) { test_case(); } } |
module ALU (
input signed [15:0] DATA_A, DATA_B,
input [3:0] S_ALU,
output [15:0] ALU_OUT,
output [3:0] FLAG_OUT);
localparam IADD = 4'b0000;
localparam ISUB = 4'b0001;
localparam IAND = 4'b0010;
localparam IOR = 4'b0011;
localparam IXOR = 4'b0100;
localparam ISLL = 4'b1000;
localparam ISLR = 4'b1001;
localparam ISRL = 4'b1010;
localparam ISRA = 4'b1011;
localparam IIDT = 4'b1100;
localparam INON = 4'b1111;
wire S, Z, V;
function [16:0] amux(
input signed [15:0] A, B,
input [3:0] Selector);
case (Selector)
IADD : amux = {1'b0, A} + {1'b0, B};
ISUB : amux = {1'b0, A} - {1'b0, B};
IAND : amux = {1'b0, A & B};
IOR : amux = {1'b0, A | B};
IXOR : amux = {1'b0, A ^ B};
ISLL : amux = {1'b0, A} << B[3:0];
ISLR : amux = ({1'b0, A} << B[3:0]) | (A >> 16 - B[3:0]);
ISRL : amux = {B[3:0] > 0 ? A[B[3:0] - 1] : 1'b0, A >> B[3:0]};
ISRA : amux = {B[3:0] > 0 ? A[B[3:0] - 1] : 1'b0, A >>> B[3:0]};
IIDT : amux = {1'b0, B};
INON : amux = 17'b0;
default : amux = 17'b0;
endcase
endfunction
wire [16:0] result;
assign result = amux(DATA_A, DATA_B, S_ALU);
assign ALU_OUT = result[15:0];
assign S = result[15] == 1'b1 ? 1'b1 : 1'b0;
assign Z = result[15:0] == 16'b0 ? 1'b1 : 1'b0;
assign V = (((S_ALU == IADD) && (DATA_A[15] == DATA_B[15]) && (DATA_A[15] != result[15]))
|| ((S_ALU == ISUB) && (DATA_A[15] != DATA_B[15]) && (DATA_A[15] != result[15]))) ? 1'b1 : 1'b0;
assign FLAG_OUT = {S, Z, result[16], V};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_BLACKBOX_V
|
/**
1. нужно сделать шинным(временным будет массив)
2. и длиной 1-N ноль - соединение напрямую - лучще
вставлять в основной код
v_shift_registers #(
.DELAY(),
.WIDTH(`WIDTH)
)(
.clk(clk), .rst(rst), .clk_ena(clk_ena),
.si(), .so()
);
*/
`include "vconst_lib.v"
/**
abst. : сдвиговый регистр с паралл. загр (одной шиной)
парал. выходом разр. такта, загр, сбросом
conn. :
shift_reg_width
labdl_srwj(
.clk(clk), .rst(rst), .clk_ena(clk_ena),
// control
.load(load),
// datastream
.din(din),
.dfload(dfload), // для загрузки
// out. //
.dout(dout),
.doutbig(doutbig)); // выходные данные
*/
module shift_reg_width(
clk, rst, clk_ena,
// control
load,
// stream ///
din,
dfload,
// out. //
dout,
doutbig
);
parameter NUM_REG = 2; // число регистров
input clk, rst, clk_ena;
input load;
input [`G_WIDTH-1:0] din; // последовательные входные данные
output [`G_WIDTH-1:0] dout; // последовательные входные данные
//
input [`G_WIDTH*NUM_REG-1:0] dfload; // данные для загрузки
output [`G_WIDTH*NUM_REG-1:0] doutbig; // данные для счтитыания
// loc. ///
wire [`G_WIDTH-1:0] intconn [NUM_REG-1:0];
// conn. ///
// первый регистр
register_pe
label_pe0(
.clk(clk), .rst(rst), .clk_ena(clk_ena),
// control
.load(load),
// datastream
.datain(din),
.dforload(dfload[`G_WIDTH-1:0]), // под вопросом! т.к. вообще то он последний
// в модуле
.dataout(intconn[0])
);
assign doutbig[`G_WIDTH-1:0] = intconn[0];
// остальные
genvar g;
generate for(g = 1; g < NUM_REG; g = g+1) begin : label
register_pe
label_pej(
.clk(clk), .rst(rst), .clk_ena(clk_ena),
// control
.load(load),
// datastream
.datain(intconn[g-1]),
.dforload(dfload[(g+1)*(`G_WIDTH)-1:g*(`G_WIDTH)]), // inputs
.dataout(intconn[g])
);
assign doutbig[(g+1)*(`G_WIDTH)-1:g*(`G_WIDTH)] = intconn[g];
end endgenerate
// out. ///
assign dout = intconn[NUM_REG-1];
endmodule
module v_shift_registers(
clk, rst, clk_ena,
si, so
);
parameter DELAY = 1; // 1 - min! число тактов на которое можно сдвинуть
parameter WIDTH = 8;
input clk, rst, clk_ena;
input [WIDTH-1:0] si; // однобитный
output [WIDTH-1:0] so;
// local/
reg [DELAY+1-1:0] tmp [WIDTH-1:0]; //
integer i; // нужно для цикла
// logic
always @(posedge clk or posedge rst)
begin
if(rst) begin
for(i = 0; i < WIDTH; i = i+1) begin
tmp[i] = 'b0;
end
end
else if(clk_ena) begin
for(i = 0; i < WIDTH; i = i+1) begin
tmp[i] = {tmp[i][DELAY+1-2:0], si[i]};
end
end //
end
// out
genvar g;
generate for(g = 0; g < WIDTH; g = g+1) begin : asfas
assign so[g] = tmp[g][DELAY+1-1];
end endgenerate
endmodule
/*
// подстроечный регистр сдвига
// может лучше сдалать из станд см. альтеру
// сделать число регистров 0(!)-N
module shifter_buses(clk, rst, clk_ena, in, out);
parameter LEN_DELAY = 3; // сколько регистров !! может ругатсяна вложенность
input clk, rst, clk_ena;
input [`WIDTH-1:0] in;
output [`WIDTH-1:0] out;
//
wire [`WIDTH-1:0] connectors [0:LEN_DELAY-1-1];
// соединителей на один меньше чем задержек
a_dff #(`WIDTH) label_g1(clk, rst, clk_ena, in, connectors[0]);
genvar g;
generate for(g = 0; g < LEN_DELAY-1-1; g = g+1) begin : asdfasdf
a_dff #(`WIDTH) label_g(clk, rst, clk_ena, connectors[g], connectors[g+1]);
end endgenerate
// выходной регистр
a_dff #(`WIDTH) label_g2(clk, rst, clk_ena, connectors[LEN_DELAY-1-1], out);
endmodule*/
|
#include <bits/stdc++.h> using namespace std; bool binary(vector<int> v, int key) { int lo = 0, hi = v.size() - 1; while (lo <= hi) { int mid = (lo + hi) / 2; if (v[mid] == key) return true; else if (v[mid] < key) lo = mid + 1; else hi = mid - 1; } return false; } int main() { int n, ans = 0, l = 0, r = 0, u = 0, d = 0; cin >> n; vector<pair<int, int>> v; for (int i = 0; i < n; i++) { int t1, t2; cin >> t1 >> t2; v.push_back(make_pair(t1, t2)); } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (v[j].first == v[i].first && v[j].second < v[i].second) d++; if (v[j].first == v[i].first && v[j].second > v[i].second) u++; if (v[j].first < v[i].first && v[j].second == v[i].second) l++; if (v[j].first > v[i].first && v[j].second == v[i].second) r++; } if (d && r && l && u) ans++; d = 0, r = 0, l = 0, u = 0; } cout << ans; return 0; } |
module opc5cpu( input[15:0] datain, output [15:0] dataout, output[15:0] address, output rnw, input clk, input reset_b);
parameter FETCH0=3'h0, FETCH1=3'h1, EA_ED=3'h2, RDMEM=3'h3, EXEC=3'h4, WRMEM=3'h5;
parameter PRED_C=15, PRED_Z=14, PINVERT=13, FSM_MAP0=12, FSM_MAP1=11;
parameter LD=3'b000, ADD=3'b001, AND=3'b010, OR=3'b011, XOR=3'b100, ROR=3'b101, ADC=3'b110, STO=3'b111;
reg [15:0] OR_q, PC_q, IR_q, result, result_q ;
(* RAM_STYLE="DISTRIBUTED" *)
reg [15:0] GRF_q[15:0];
reg [2:0] FSM_q;
reg [3:0] grf_adr_q;
reg C_q, zero, carry;
wire predicate = (IR_q[PINVERT]^((IR_q[PRED_C]|C_q)&(IR_q[PRED_Z]|zero))); // For use once IR_q loaded (FETCH1,EA_ED)
wire predicate_datain = (datain[PINVERT]^((datain[PRED_C]|C_q)&(datain[PRED_Z]|zero))); // For use before IR_q loaded (FETCH0)
wire [15:0] grf_dout= (grf_adr_q==4'hF) ? PC_q: (GRF_q[grf_adr_q] & { 16{(grf_adr_q!=4'h0)}});
wire skip_eaed = !((grf_adr_q!=0) || (IR_q[FSM_MAP1]) || (IR_q[10:8]==STO));
assign rnw= ! (FSM_q==WRMEM);
assign dataout=grf_dout;
assign address=( FSM_q==WRMEM || FSM_q == RDMEM)? OR_q : PC_q;
always @( * )
begin
{ carry, result, zero} = { C_q, 16'bx, !(|result_q) } ;
case (IR_q[10:8])
LD : result=OR_q;
ADD, ADC : {carry, result}= grf_dout + OR_q + (!IR_q[8] & C_q); // IF ADC or ADD, IR_q[8] distinguishes between them
AND : result=(grf_dout & OR_q);
OR : result=(grf_dout | OR_q);
XOR : result=(grf_dout ^ OR_q);
ROR : {result,carry} = { carry, OR_q };
endcase // case ( IR_q )
end
always @(posedge clk or negedge reset_b )
if (!reset_b)
FSM_q <= FETCH0;
else
case (FSM_q)
FETCH0 : FSM_q <= (datain[FSM_MAP0])? FETCH1 : (!predicate_datain )? FETCH0: EA_ED;
FETCH1 : FSM_q <= (!predicate )? FETCH0: ( skip_eaed) ? EXEC : EA_ED; // Allow FETCH1 to skip through to EXEC
EA_ED : FSM_q <= (!predicate )? FETCH0: (IR_q[FSM_MAP1]) ? RDMEM : (IR_q[10:8]==STO) ? WRMEM : EXEC;
RDMEM : FSM_q <= EXEC;
EXEC : FSM_q <= (IR_q[3:0]==4'hF)? FETCH0: (datain[FSM_MAP0]) ? FETCH1 : EA_ED;
default: FSM_q <= FETCH0;
endcase // case (FSM_q)
always @(posedge clk)
case(FSM_q)
FETCH0, EXEC : {grf_adr_q, OR_q } <= {datain[7:4], 16'b0};
FETCH1 : {grf_adr_q, OR_q } <= {((skip_eaed)? IR_q[3:0] : IR_q[7:4]), datain};
RDMEM : {grf_adr_q, OR_q } <= {IR_q[3:0], datain};
EA_ED : {grf_adr_q, OR_q } <= {IR_q[3:0], grf_dout + OR_q};
default : {grf_adr_q, OR_q } <= {4'bx, 16'bx};
endcase
always @(posedge clk or negedge reset_b)
if ( !reset_b)
PC_q <= 16'b0;
else if ( FSM_q == FETCH0 || FSM_q == FETCH1 )
PC_q <= PC_q + 1;
else if ( FSM_q == EXEC )
PC_q <= (grf_adr_q==4'hF) ? result : PC_q + 1;
always @ (posedge clk)
if ( FSM_q == FETCH0 )
IR_q <= datain;
else if ( FSM_q == EXEC )
{ C_q, GRF_q[grf_adr_q], result_q, IR_q} <= { carry, result, result, datain};
endmodule
|
#include <bits/stdc++.h> using namespace std; long long m, n, q; long long X; long long f(long long a) { long long b = X - 2, c = X, k, ans = 1; while (b > 0) { long long p = 1, k = a; while (p * 2 <= b) { p *= 2; k = k * k % c; } ans = ans * k % c; b -= p; } return ans; } long long a[1005009], A; long long p[1000509]; int main() { cin >> n >> m >> A >> q; p[0] = 1; for (long long i = 1;; i++) { p[i] = p[i - 1] * A % q; if (p[i] == 1) { X = i; break; } } a[0] = 1; long long x = m, t = 1; for (long long i = 1; i <= n - 1; i++) { a[i] = (a[i - 1] * x * f(i)) % X; x--; } long long s = 0; for (long long i = 0; i <= n - 1; i++) { s += a[i]; a[i] = s; } for (long long i = n - 1; i >= 0; i--) cout << p[a[i] % X] << ; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
rst_sync_l, rst_both_l, rst_async_l, d, clk
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
sub2 sub2 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
endmodule
module sub1 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_sync_l, d
);
input clk;
input rst_both_l;
input rst_sync_l;
//input rst_async_l;
input d;
reg q1;
reg q2;
always @(posedge clk) begin
if (~rst_sync_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk) begin
q2 <= (rst_both_l) ? d : 1'b0;
if (0 && q1 && q2) ;
end
endmodule
module sub2 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_async_l, d
);
input clk;
input rst_both_l;
//input rst_sync_l;
input rst_async_l;
input d;
reg q1;
reg q2;
reg q3;
always @(posedge clk or negedge rst_async_l) begin
if (~rst_async_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk or negedge rst_both_l) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
end
// Make there be more async uses than sync uses
always @(posedge clk or negedge rst_both_l) begin
q3 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2 && q3) ;
end
endmodule
|
#include <bits/stdc++.h> char s[100], Ans[2000]; int n, m, ans, cnt, b[20], a[40][40], p[50], q[50], x[20][20]; void dfs(int c, int d) { if (d == 15) { memset(x, 0, sizeof(x)); for (int i = 1; i <= 28; i++) { if (x[b[p[i]]][b[q[i]]]) return; x[b[p[i]]][b[q[i]]] = x[b[q[i]]][b[p[i]]] = 1; } if (++ans == 1) { cnt = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) Ans[cnt++] = a[i][j] ? (b[a[i][j]] + 47) : . ; Ans[cnt++] = n ; } Ans[cnt] = 0 ; } } else { if (b[d]) { dfs(c, d + 1); return; } b[d] = c; for (int j = d + 1; j <= 14; j++) if (!b[j]) b[j] = c, dfs(c + 1, d + 1), b[j] = 0; b[d] = 0; } } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %s , &s); for (int j = 0; j < m; j++) { if (s[j] != . && !a[i][j]) a[i][j] = a[i + 1][j] = a[i][j + 1] = a[i + 1][j + 1] = ++cnt; if (s[j] != . ) { int t = s[j] <= B ? s[j] - 64 : s[j] - 94; if (!p[t]) p[t] = a[i][j]; else q[t] = a[i][j]; } } } dfs(1, 1); printf( %d n%s , ans * 5040, Ans); } |
#include <bits/stdc++.h> using namespace std; const int N = 5001; const int B = 27; int zhu[B], n, m; char s[N], t[N]; void solve() { memset(zhu, 0, sizeof(zhu)); n = strlen(s); m = strlen(t); for (int i = 0; i < n; ++i) zhu[s[i] - a ]++; int r = -1, p; if (n > m) p = m; else p = min(n, m) - 1; for (int i = t[0] - a + 1; i < 26; ++i) if (zhu[i]) r = 0; for (int i = 1; i <= p; ++i) { zhu[t[i - 1] - a ]--; if (zhu[t[i - 1] - a ] < 0) break; if (i == m) { r = m; continue; } for (int j = t[i] - a + 1; j < 26; ++j) if (zhu[j]) r = i; } if (r == -1) { printf( -1 n ); return; } else { memset(zhu, 0, sizeof(zhu)); for (int i = 0; i < n; ++i) zhu[s[i] - a ]++; for (int i = 0; i < r; ++i) { printf( %c , t[i]); zhu[t[i] - a ]--; } if (r < m) for (int i = t[r] - a + 1; i < 26; ++i) if (zhu[i]) { printf( %c , i + a ); zhu[i]--; break; } for (int i = 0; i < 26; ++i) while (zhu[i]--) printf( %c , i + a ); printf( n ); } } int main() { while (~scanf( %s%s , s, t)) solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_PP_BLACKBOX_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_PP_BLACKBOX_V
|
// DESCRIPTION: Verilog::PLI: Example Verilog code that will call perl
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module hello_top;
initial begin
// Set debug level
$pli_debug(0); // Set to 7 for more verbosity
// Setup the perl interpeter
$cmd_boot;
end
// invoke user-defined pli routine
initial $hello_verilog;
integer int;
reg w;
wire z = w;
initial begin
// You must wait some time (or #0) to make sure perl_boot is done!
# 10;
// $cmd can do any perl function
// Each argument is concated together,
// Numeric arguments (those <= 32 bits) are converted to numbers
$cmd ("print 'This is inside perl, called on ', `date`, \"\\n\";");
# 10;
// $cmdv will return a value
$display (" 1 + 2 = %x\n", $cmdval("1+2"));
# 10;
// Need a sparse array? (Slow, so don't use in place of sparse C code!)
$cmd ("$Sparse{", 230000, "}", "=", 32'hfeed);
# 10;
$display (" Sparse array [230000] = %x\n", $cmdval("$Sparse{230000}"));
# 100;
w = 1;
$display ("waited 100 and then printed");
$display ("z is %d", z);
$display ("setting w = 0 using perl");
$cmd ("$NET{w} = 0;");
# 1; // Need transport delay from w to z
$display ("z is %d", z);
end
endmodule
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module counter_neg(
input negedge_clk,
input rx_resetn,
input rx_din,
output reg is_control,
output reg [5:0] counter_neg
);
reg control_bit_found;
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
is_control <= 1'b0;
control_bit_found <= 1'b0;
counter_neg <= 6'd1;
end
else
begin
control_bit_found <= rx_din;
case(counter_neg)
6'd1:
begin
counter_neg <= 6'd2;
end
6'd2:
begin
if(control_bit_found)
begin
is_control <= 1'b1;
end
else
begin
is_control <= 1'b0;
end
counter_neg <= 6'd4;
end
6'd4:
begin
is_control <= 1'b0;
if(is_control)
begin
counter_neg <= 6'd2;
end
else
begin
counter_neg <= 6'd8;
end
end
6'd8:
begin
is_control <= 1'b0;
counter_neg <= 6'd16;
end
6'd16:
begin
is_control <= 1'b0;
counter_neg <= 6'd32;
end
6'd32:
begin
is_control <= 1'b0;
counter_neg <= 6'd2;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f3f3f3f3f; int32_t main() { long long n; cin >> n; vector<long long> v1, v2; long long i, j, ans = 0; for (i = 0; i < n; i++) { long long len; cin >> len; bool fg = true; long long mi = INT_MAX, mx = INT_MIN; for (j = 0; j < len; j++) { long long x; cin >> x; if (x > mi) { fg = false; } mi = min(mi, x); mx = max(mx, x); } if (fg) { v1.push_back(mi); v2.push_back(mx); } } sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); long long c = 0; for (auto x : v1) { auto p = upper_bound(v2.begin(), v2.end(), x) - v2.begin(); c += p; } ans = n * n - c; cout << ans << n ; } |
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
`timescale 1ns/1ps
module hififo_fetch_descriptor
(
input clock,
input reset,
output [AMSB:0] request_addr,
output request_valid,
input request_ack,
input [DMSB:0] wdata,
input wvalid,
output [SMSB:0] status,
output interrupt
);
parameter BS = 0; // bit shift, number of LSBs to ignore in address
parameter AMSB = 63; // address MSB
parameter DMSB = 63; // data MSB
parameter SMSB = 31; // status MSB
parameter CBITS = 22; // count bits
parameter CMSB = CBITS - 1; // count MSB
reg [CMSB-BS:0] p_current = 0, p_interrupt = 0, p_stop = 0;
reg reset_or_abort;
reg abort = 1;
reg [AMSB-CBITS:0] addr_high;
wire write_interrupt = wvalid && (wdata[2:0] == 1);
wire write_stop = wvalid && (wdata[2:0] == 2);
wire write_addr_high = wvalid && (wdata[2:0] == 3);
wire write_abort = wvalid && (wdata[2:0] == 4);
assign request_addr = {addr_high,p_current,{BS{1'b0}}};
assign request_valid = (p_current != p_stop) && ~request_ack;
assign status = {p_current, {BS{1'b0}}};
always @ (posedge clock)
begin
reset_or_abort <= reset | abort;
if(write_abort)
abort <= wdata[8];
if(write_addr_high)
addr_high <= wdata[AMSB:CBITS];
p_stop <= reset_or_abort ? 1'b0 :
write_stop ? wdata[CMSB:BS] : p_stop;
if(write_interrupt)
p_interrupt <= wdata[CMSB:BS];
p_current <= reset_or_abort ? 1'b0 : p_current + request_ack;
end
one_shot one_shot_i0
(.clock(clock),
.in(p_current == p_interrupt),
.out(interrupt));
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Lisa Liu
//
// Create Date: 06/30/2014 03:42:37 PM
// Design Name:
// Module Name: rx_isolation
// Project Name:
// Target Devices:
// Tool Versions:
// Description: read back presure signal (tready) from 8K byte FIFO and drop packets from xgmac whenever the empty space in the FIFO is less than 5K.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rx_isolation #(
FIFO_FULL_THRESHOLD = 11'd256
)
(
input [63:0] axi_str_tdata_from_xgmac,
input [7:0] axi_str_tkeep_from_xgmac,
input axi_str_tvalid_from_xgmac,
input axi_str_tlast_from_xgmac,
//input axi_str_tuser_from_xgmac,
input axi_str_tready_from_fifo,
output [63:0] axi_str_tdata_to_fifo,
output [7:0] axi_str_tkeep_to_fifo,
output axi_str_tvalid_to_fifo,
output axi_str_tlast_to_fifo,
input user_clk,
input reset
);
reg [63:0] axi_str_tdata_from_xgmac_r;
reg [7:0] axi_str_tkeep_from_xgmac_r;
reg axi_str_tvalid_from_xgmac_r;
reg axi_str_tlast_from_xgmac_r;
wire[10:0] fifo_occupacy_count;
wire s_axis_tvalid;
reg [10:0] wcount_r; //number of words in the current xgmac packet
wire fifo_has_space;
localparam IDLE = 1'd0,
STREAMING = 1'd1;
reg curr_state_r;
rx_fifo rx_fifo_inst (
.s_aclk(user_clk), // input wire s_aclk
.s_aresetn(~reset), // input wire s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(), // output wire s_axis_tready
.s_axis_tdata(axi_str_tdata_from_xgmac_r), // input wire [63 : 0] s_axis_tdata
.s_axis_tkeep(axi_str_tkeep_from_xgmac_r), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast(axi_str_tlast_from_xgmac_r), // input wire s_axis_tlast
.m_axis_tvalid(axi_str_tvalid_to_fifo), // output wire m_axis_tvalid
.m_axis_tready(axi_str_tready_from_fifo), // input wire m_axis_tready
.m_axis_tdata(axi_str_tdata_to_fifo), // output wire [63 : 0] m_axis_tdata
.m_axis_tkeep(axi_str_tkeep_to_fifo), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast(axi_str_tlast_to_fifo), // output wire m_axis_tlast
.axis_data_count(fifo_occupacy_count) // output wire [10 : 0] axis_data_count
);
assign fifo_has_space = (fifo_occupacy_count < FIFO_FULL_THRESHOLD);
assign s_axis_tvalid = axi_str_tvalid_from_xgmac_r & (((wcount_r == 0) & fifo_has_space) | (curr_state_r == STREAMING));
always @(posedge user_clk) begin
axi_str_tdata_from_xgmac_r <= axi_str_tdata_from_xgmac;
axi_str_tkeep_from_xgmac_r <= axi_str_tkeep_from_xgmac;
axi_str_tvalid_from_xgmac_r <= axi_str_tvalid_from_xgmac;
axi_str_tlast_from_xgmac_r <= axi_str_tlast_from_xgmac;
end
always @(posedge user_clk)
if (reset)
wcount_r <= 0;
else if (axi_str_tvalid_from_xgmac_r & ~axi_str_tlast_from_xgmac_r)
wcount_r <= wcount_r + 1;
else if (axi_str_tvalid_from_xgmac_r & axi_str_tlast_from_xgmac_r)
wcount_r <= 0;
always @(posedge user_clk)
if (reset)
curr_state_r <= IDLE;
else
case (curr_state_r)
IDLE: if ((wcount_r == 0) & fifo_has_space & axi_str_tvalid_from_xgmac_r)
curr_state_r <= STREAMING;
STREAMING: if (axi_str_tvalid_from_xgmac_r & axi_str_tlast_from_xgmac_r)
curr_state_r <= IDLE;
endcase
/* always @(posedge user_clk) begin
data [63:0] <= axi_str_tdata_from_xgmac_r;
data [71:64] <= axi_str_tkeep_from_xgmac_r;
data[72] <= axi_str_tvalid_from_xgmac_r;
data[73] <= axi_str_tlast_from_xgmac_r;
data[74] <= axi_str_tready_from_fifo;
data[138:75] <= axi_str_tdata_to_fifo;
data[146:139] <= axi_str_tkeep_to_fifo;
data[147] <= axi_str_tvalid_to_fifo;
data[148] <= axi_str_tlast_to_fifo;
data[159:149] <= wcount_r;
data[160] <= curr_state_r;
data[171:161] <= fifo_occupacy_count;
trig0[10:0] <= wcount_r;
trig0[11] <= axi_str_tvalid_to_fifo;
trig0[12] <= axi_str_tready_from_fifo;
end*/
endmodule |
#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; const int MOD = 1e9 + 7; int n; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout << fixed; cin >> n; int dp[] = {1, 0}; for (int i = 1; i < n; i++) dp[i % 2] = (dp[i % 2] + dp[1 - i % 2] + 1) % MOD; cout << (dp[0] + dp[1]) % MOD << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const double inf = 1.0 / 0.0; const double pi = 2 * acos(0.0); map<char, int> tab, tab1; char x; int main() { tab1[ Q ] = 9; tab[ q ] = 9; tab1[ R ] = 5; tab[ r ] = 5; tab1[ B ] = 3; tab[ b ] = 3; tab1[ P ] = 1; tab[ p ] = 1; tab1[ N ] = 3; tab[ n ] = 3; tab1[ K ] = 0; tab[ k ] = 0; ios_base::sync_with_stdio(false); int b = 0, w = 0; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { x = getchar(); if (tab.count(x) != 0) { b += tab[x]; } else if (tab1.count(x) != 0) { w += tab1[x]; } } getchar(); } if (b > w) cout << Black n ; else if (w > b) cout << White n ; else cout << Draw n ; return 0; } |
#include <bits/stdc++.h> using namespace ::std; const long long maxn = 400; const long long mod = 1e9 + 7; const long long inf = 1e17 + 500; string s[maxn]; long long a[maxn]; string t; long long n; long long ger[maxn][maxn]; long long tvi[maxn][maxn]; long long sav[maxn][maxn]; long long tyu[maxn][maxn]; long long star[maxn]; long long m; long long f(string h) { long long ans = 0; for (long long i = 0; i < n; i++) { if (h.size() >= s[i].size()) { bool good = 1; for (long long j = 0; j < s[i].size(); j++) { if (h[j] != s[i][j]) { good = 0; } } if (good) { ans += a[i]; } } } return ans; } void tavtosav() { for (long long i = 0; i < m; i++) { for (long long j = 0; j < m; j++) { sav[i][j] = tvi[i][j]; } } } void jelosav() { for (long long i = 0; i < m; i++) { for (long long j = 0; j < m; j++) { long long v = -inf; for (long long z = 0; z < m; z++) { v = max(v, sav[i][z] + ger[z][j]); } tyu[i][j] = v; } } for (long long i = 0; i < m; i++) { for (long long j = 0; j < m; j++) { sav[i][j] = tyu[i][j]; } } } void tavbasavtotav() { for (long long i = 0; i < m; i++) { for (long long j = 0; j < m; j++) { long long v = -inf; for (long long z = 0; z < m; z++) { v = max(v, sav[i][z] + tvi[z][j]); } tyu[i][j] = v; } } for (long long i = 0; i < m; i++) { for (long long j = 0; j < m; j++) { tvi[i][j] = tyu[i][j]; } } } void tav(long long l) { if (l == 0) { for (long long i = 0; i < m; i++) { for (long long j = 0; j < m; j++) { tvi[i][j] = -inf; } tvi[i][i] = 0; } return; } tav(l / 2); tavtosav(); if (l & 1) { jelosav(); } tavbasavtotav(); } bool sub(string a, string b) { for (long long i = 0; i < a.size(); i++) { if (a[i] != b[i]) { return 0; } } return 1; } map<string, int> ml; int main() { long long l; cin >> n >> l; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { cin >> s[i]; ml[s[i]] += a[i]; } long long np = 0; for (long long i = 0; i < n; i++) { long long v = ml[s[i]]; if (v != 0) { a[np] = v; s[np] = s[i]; np++; ml[s[i]] = 0; } } n = np; for (long long i = 0; i < n; i++) { star[i] = t.size(); t += s[i]; t += # ; } m = t.size(); for (long long i = 0; i < maxn; i++) { for (long long j = 0; j < maxn; j++) { ger[i][j] = -inf; } } for (int i = 0; i < t.size(); i++) { if (t[i] == # ) { ger[i][i] = 0; } else { string h; for (int j = i + 1; t[j] != # ; j++) { h += t[j]; } ger[i][i + 1] = f(t[i] + h); for (int j = 0; j < n; j++) { if (h.size() < s[j].size() && sub(h, s[j])) { ger[i][star[j]] = f(t[i] + s[j]); } } } } tav(l); long long ans = 0; for (int i = 0; i < m; i++) { if (t[i] == # ) { for (int j = 0; j < m; j++) { ans = max(ans, tvi[j][i]); } } } cout << ans; } |
/*
########################################################################
Generic small FIFO using distributed memory
Caution: There is no protection against overflow or underflow,
driving logic should avoid wen on full or ren on empty.
########################################################################
*/
module fifo_sync
#(
// Address width (must be 5 => 32-deep FIFO)
parameter AW = 5,
// Data width
parameter DW = 16
)
(
input clk,
input reset,
input [DW-1:0] wr_data,
input wr_en,
input rd_en,
output wire [DW-1:0] rd_data,
output reg rd_empty,
output reg wr_full
);
reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr;
reg [AW-1:0] count;
always @ ( posedge clk ) begin
if( reset )
begin
wr_addr[AW-1:0] <= 'd0;
rd_addr[AW-1:0] <= 'b0;
count[AW-1:0] <= 'b0;
rd_empty <= 1'b1;
wr_full <= 1'b0;
end else
begin
if( wr_en & rd_en )
begin
wr_addr <= wr_addr + 'd1;
rd_addr <= rd_addr + 'd1;
end
else if( wr_en )
begin
wr_addr <= wr_addr + 'd1;
count <= count + 'd1;
rd_empty <= 1'b0;
if( & count )
wr_full <= 1'b1;
end
else if( rd_en )
begin
rd_addr <= rd_addr + 'd1;
count <= count - 'd1;
wr_full <= 1'b0;
if( count == 'd1 )
rd_empty <= 1'b1;
end
end // else: !if( reset )
end // always @ ( posedge clk )
`ifdef TARGET_XILINX
genvar dn;
generate for(dn=0; dn<DW; dn=dn+1)
begin : genbits
RAM32X1D RAM32X1D_inst
(
.DPO(rd_data[dn] ), // Read-only 1-bit data output
.SPO(), // Rw/ 1-bit data output
.A0(wr_addr[0]), // Rw/ address[0] input bit
.A1(wr_addr[1]), // Rw/ address[1] input bit
.A2(wr_addr[2]), // Rw/ address[2] input bit
.A3(wr_addr[3]), // Rw/ address[3] input bit
.A4(wr_addr[4]), // Rw/ address[4] input bit
.D(wr_data[dn]), // Write 1-bit data input
.DPRA0(rd_addr[0]), // Read-only address[0] input bit
.DPRA1(rd_addr[1]), // Read-only address[1] input bit
.DPRA2(rd_addr[2]), // Read-only address[2] input bit
.DPRA3(rd_addr[3]), // Read-only address[3] input bit
.DPRA4(rd_addr[4]), // Read-only address[4] input bit
.WCLK(clk), // Write clock input
.WE(wr_en) // Write enable input
);
end
endgenerate
`elsif TARGET_CLEAN
defparam mem.DW=DW;
defparam mem.AW=AW;
memory_dp mem (
// Outputs
.rd_data (rd_data[DW-1:0]),
// Inputs
.wr_clk (clk),
.wr_en ({(DW/8){wr_en}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_data (wr_data[DW-1:0]),
.rd_clk (clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]));
`endif
endmodule // fifo_sync
// Local Variables:
// verilog-library-directories:(".")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; vector<int> v[maxn]; int vos[maxn]; int ans; void dfs(int now, int pre) { if (vos[now]) { ans = 0; return; } vos[now] = 1; for (int i = 0; i < v[now].size(); i++) { if (v[now][i] != pre) { dfs(v[now][i], now); } } } int main() { int n, m; scanf( %d%d , &n, &m); int a, b; for (int i = 0; i < m; i++) { scanf( %d%d , &a, &b); v[a].push_back(b); v[b].push_back(a); } memset(vos, 0, sizeof(vos)); int sum = 0; for (int i = 1; i <= n; i++) { if (vos[i]) continue; ans = 1; dfs(i, 0); sum += ans; } printf( %d n , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k, w, nm; char ls[1000][10][10]; int _d[1000][1000]; int used[1000], res[1000], sz = 0, c = 0; int main() { cin >> n >> m >> k >> w; nm = n * m; c = nm; for (int i = 0; i < k; i++) for (int y = 0; y < n; y++) for (int x = 0; x < m; x++) cin >> ls[i][y][x]; for (int a = 0; a < k; a++) for (int b = 0; b < k; b++) { int res = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (ls[a][i][j] != ls[b][i][j]) res++; _d[a][b] = res; } res[0] = 0; used[0] = 1; sz = 1; stringstream ss; ss << 1 0 << endl; while (sz < k) { int mini = -1, minval = -1, minj = -1, type = 0; for (int j = 0; j < sz; j++) { for (int i = 0; i < k; i++) { if (used[i]) continue; int a = _d[res[j]][i] * w, t = min(a, nm); if (t < minval || mini < 0) { mini = i; minval = t; minj = -1; if (a < nm) { minj = res[j]; type = 1; } } } } res[sz++] = mini; used[mini] = 1; ss << mini + 1 << << minj + 1 << endl; c += minval; } cout << c << endl << ss.str(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long gcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long x1, y1; long long g = gcd(b, a % b, x1, y1); x = y1; y1 = x1 - y1 * (a / b); return g; } long long qpow(long long a, long long n) { long long res = 1; while (n) { if (n % 2) { res = (res * a) % MOD; n--; } else { n = n / 2; a = (a * a) % MOD; } } return res; } long long inv(long long a) { return qpow(a, MOD - 2); } bool cmp(pair<long long, long long> &p1, pair<long long, long long> &p2) { if (p1.first != p2.first) return p1.first < p2.first; return p1.second < p2.second; } bool prime(long long n) { for (long long i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } long long sum(long long n) { long long second = 0; while (n) { second += n % 10; n /= 10; } return second; } void solve() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long second, x; cin >> second >> x; long long c = 0; vector<long long> a; for (int i = 0; i < 42; i++) { if (x & (1LL << i)) { c++; second -= (1LL << i); } else a.push_back(1LL << (i + 1)); } if (second < 0) { cout << 0 << n ; return; } sort(a.begin(), a.end(), greater<long long>()); bool ok = false; for (int i = 0; i < a.size(); i++) { if (a[i] <= second) { ok = true; second -= a[i]; } } if (second == 0) { if (ok) cout << (1LL << c) << n ; else { cout << max(0LL, (1LL << c) - 2) << n ; } } else cout << 0 << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t = 1; while (t--) { solve(); } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_jbi_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: JBus Interface CMP clk cluster header
*/
module bw_clk_cl_jbi_cmp(so,dbginit_l ,cluster_grst_l ,rclk ,si ,se ,
adbginit_l ,gdbginit_l ,arst_l ,grst_l ,cluster_cken ,gclk );
output so ;
output dbginit_l ;
output cluster_grst_l ;
output rclk ;
input si ;
input se ;
input adbginit_l ;
input gdbginit_l ;
input arst_l ;
input grst_l ;
input cluster_cken ;
input gclk ;
cluster_header I0 (
.rclk (rclk ),
.so (so ),
.dbginit_l (dbginit_l ),
.cluster_grst_l (cluster_grst_l ),
.si (si ),
.se (se ),
.adbginit_l (adbginit_l ),
.gdbginit_l (gdbginit_l ),
.arst_l (arst_l ),
.grst_l (grst_l ),
.cluster_cken (cluster_cken ),
.gclk (gclk ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 10; int par[maxn], sub[maxn], col[maxn]; vector<pair<int, int>> parHis, colHis, subHis; bool bad[maxn]; int c[maxn]; int root(int x) { while (x != par[x]) { x = par[x]; } return x; } int getCol(int x) { int res = 0; while (x != par[x]) { res ^= col[x]; x = par[x]; } return res; } void save(int x, int y) { parHis.emplace_back(x, par[x]); subHis.emplace_back(y, sub[y]); colHis.emplace_back(x, col[x]); } void join(int x, int y, bool rollback = false) { int rx = root(x); int ry = root(y); int dif = (getCol(x) == getCol(y)); if (sub[rx] > sub[ry]) swap(rx, ry); if (rollback) save(rx, ry); par[rx] = ry; sub[ry] += sub[rx]; col[rx] = dif; } bool check(int p, int q) { if (root(p) == root(q) && getCol(p) == getCol(q)) return false; return true; } int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) { scanf( %d , &c[i]); } map<pair<int, int>, vector<pair<int, int>>> cont; for (int i = 1; i <= m; i++) { int p, q; scanf( %d %d , &p, &q); if (c[p] > c[q]) swap(p, q); cont[make_pair(c[p], c[q])].emplace_back(p, q); } for (int i = 1; i <= n; i++) { par[i] = i; col[i] = 0; sub[i] = 1; } int active = k; for (int i = 1; i <= k; i++) { auto v = cont[make_pair(i, i)]; for (auto j : v) { int p = j.first; int q = j.second; if (check(p, q)) { join(p, q); } else { bad[i] = true; active -= 1; break; } } } long long ans = (1LL * active * (active - 1)) / 2; for (auto i : cont) { if (i.first.first == i.first.second) continue; if (bad[i.first.first] || bad[i.first.second]) continue; auto v = i.second; for (auto j : v) { int p = j.first; int q = j.second; if (check(p, q)) { join(p, q, true); } else { ans -= 1; break; } } while (not parHis.empty()) { auto ph = parHis.back(); auto ch = colHis.back(); auto sh = subHis.back(); parHis.pop_back(); colHis.pop_back(); subHis.pop_back(); par[ph.first] = ph.second; col[ch.first] = ch.second; sub[sh.first] = sh.second; } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 220000; vector<int> e1[M], e2[M]; int p[M], dis[M]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; e1[u].push_back(v); e2[v].push_back(u); } int k; cin >> k; for (int i = 0; i < k; i++) cin >> p[i]; queue<int> q; q.push(p[k - 1]); dis[p[k - 1]] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (int v : e2[u]) { if (dis[v] == 0) { dis[v] = dis[u] + 1; q.push(v); } } } int mi = 0, mx = 0; for (int i = 0; i < k - 1; i++) { if (dis[p[i]] != dis[p[i + 1]] + 1) ++mi; for (int v : e1[p[i]]) { if (v != p[i + 1] && dis[v] == dis[p[i]] - 1) { ++mx; break; } } } cout << mi << << mx << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; int s; struct DSU { int p[505]; void init() { for (int i = 1; i <= n; i++) p[i] = i; } int find(int x) { return p[x] == x ? x : p[x] = find(p[x]); } int count() { int count = 0; for (int i = 1; i <= n; i++) if (p[i] == i) count++; return count; } void link(int a, int b) { p[find(a)] = find(b); } } L[10050], R[10050]; DSU hebing(DSU L, DSU R) { DSU a = L; for (int i = 1; i <= n; i++) a.link(i, R.find(i)); return a; } int l[10050], r[10050]; int main() { cin >> n >> m; L[0].init(); for (int i = 1; i <= m; i++) { cin >> l[i]; cin >> r[i]; L[i] = L[i - 1]; L[i].link(l[i], r[i]); } R[m + 1].init(); for (int i = m; i >= 1; i--) { R[i] = R[i + 1]; R[i].link(l[i], r[i]); } cin >> k; while (k--) { int x1, y1; cin >> x1 >> y1; DSU h = hebing(L[x1 - 1], R[y1 + 1]); cout << h.count() << endl; } } |
// mmio_if_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2017.05.28.12:10:00
`timescale 1 ps / 1 ps
module mmio_if_hps_0 #(
parameter F2S_Width = 0,
parameter S2F_Width = 0
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
mmio_if_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY) // .rready
);
mmio_if_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18 + 7; long long f[53], fac[53]; long long add(long long a, long long b) { return min(INF, a + b); } long long mul(long long a, long long b) { if (INF / a < b) return INF; return a * b; } const int N = 50; long long g(int n) { if (n == 1) return 1; return fac[n - 2]; } void init() { fac[0] = 1; for (int i = 1; i <= N; i++) fac[i] = mul(fac[i - 1], i); f[0] = 1; for (int i = 1; i <= N; i++) for (int j = 1; j <= i; j++) f[i] = add(f[i], mul(f[i - j], g(j))); return; } int p[53]; int q[53]; bool vis[53]; int find(int x) { while (q[x]) x = q[x]; return x; } void getq(int n, long long k) { if (n == 1) { q[1] = 1; return; } for (int i = 1; i <= n; i++) q[i] = vis[i] = 0; q[1] = n; vis[n] = 1; for (int i = 2; i < n; i++) { long long num = fac[n - i - 1]; for (int j = 1; j <= n; j++) if (j != i && !vis[j] && find(j) != i) { if (k <= num) { q[i] = j; vis[j] = true; break; } k -= num; } } for (int i = 1; i <= n; i++) if (!vis[i]) q[n] = i; return; } void getp(int n, long long k) { if (!n) return; int len = 0; for (int i = 1; i <= n; i++) { long long num = mul(g(i), f[n - i]); if (k <= num) { len = i; break; } k -= num; } long long num = f[n - len]; long long need = (k - 1) / num + 1; getp(n - len, k - (need - 1) * num); for (int i = n; i > len; i--) p[i] = p[i - len] + len; getq(len, need); for (int i = 1; i <= len; i++) p[i] = q[i]; return; } int main() { init(); int t; scanf( %d , &t); while (t--) { int n; long long k; scanf( %d %lld , &n, &k); if (f[n] < k) printf( -1 n ); else { getp(n, k); for (int i = 1; i <= n; i++) printf( %d , p[i]); printf( n ); } } return 0; } |
#include <bits/stdc++.h> const int inf = 0x3f3f3f; const long long INF = 1ll << 61; using namespace std; int n, x; typedef struct Node { int t, h, m; }; Node aa[2000 + 55], bb[2000 + 55]; void init() { memset(aa, 0, sizeof(aa)); memset(bb, 0, sizeof(bb)); } int cnt1, cnt2; bool input() { while (cin >> n >> x) { cnt1 = cnt2 = 0; for (int i = 0; i < n; i++) { int t; scanf( %d , &aa[i].t); scanf( %d %d , &aa[i].h, &aa[i].m); bb[i].t = aa[i].t, bb[i].h = aa[i].h, bb[i].m = aa[i].m; } return false; } return true; } bool cmp1(Node x, Node y) { return x.m > y.m; } void cal() { sort(aa, aa + n, cmp1); sort(bb, bb + n, cmp1); int ans1 = 0; int now = 0; int tx = x; for (int i = 0; i < n; i++) { if (aa[i].t == now && tx >= aa[i].h) { now = 1 - now; tx += aa[i].m; ans1++; aa[i].t = -1; i = -1; } } int ans2 = 0; now = 1; for (int i = 0; i < n; i++) { if (bb[i].t == now && x >= bb[i].h) { now = 1 - now; x += bb[i].m; ans2++; bb[i].t = -1; i = -1; } } int ans = max(ans1, ans2); cout << ans << endl; } void output() {} int main() { while (true) { init(); if (input()) return 0; cal(); output(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1010; const int MOD = 1e9 + 7; int dp[MAXN][MAXN][2]; int Steps[MAXN]; int add(int a, int b) { return ((a + b) >= MOD ? a + b - MOD : a + b); } void PreproccessSteps() { Steps[1] = 1; for (int i = (2); i < (1010); i++) Steps[i] = Steps[__builtin_popcount(i)] + 1; } int Ones(int N, string s) { int cnt = 0; for (int i = (1); i < (N); i++) if (s[i] == 1 ) cnt++; return cnt; } void FillDP(int N, string s) { for (int j = (0); j < (N + 1); j++) dp[0][j][0] = dp[0][j][1] = 1; for (int i = (1); i < (N + 1); i++) for (int j = (1); j < (N + 1); j++) { if (s[j - 1] == 1 ) dp[i][j][0] = add(dp[i - 1][j - 1][0], dp[i][j - 1][1]); if (s[j - 1] == 0 ) dp[i][j][0] = dp[i][j - 1][0]; dp[i][j][1] = add(dp[i - 1][j - 1][1], dp[i][j - 1][1]); } } int main() { int N, k, sum = 0; string s; cin >> s >> k; reverse(s.begin(), s.end()); PreproccessSteps(); N = (int)s.size(); FillDP(N, s); for (int i = (1); i < (N + 1); i++) if (Steps[i] == k) sum = add(sum, dp[i][N][0]); if (k == 1) { cout << dp[1][N][0] - 1; return 0; } if (!k) sum++; cout << sum; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int t, n, a[N]; int main() { ios::sync_with_stdio(false); for (cin >> t; t; t--) { cin >> n; long long l = 0, r = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; l += a[i]; r ^= a[i]; } cout << 2 << n << r << << (l + r) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; int a[maxn], cnt[maxn], n, q; long long ans = 0; map<pair<long long, long long>, int> mp; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; ans += a[i]; } cin >> q; long long s, t, u; while (q--) { cin >> s >> t >> u; if (mp.find(pair<long long, long long>(s, t)) != mp.end()) { int c = mp[pair<long long, long long>(s, t)]; if (cnt[c] <= a[c]) ans++; cnt[c]--; mp.erase(pair<long long, long long>(s, t)); } if (u != 0) { mp[pair<long long, long long>(s, t)] = u; if (cnt[u] < a[u]) ans--; cnt[u]++; } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int MAX = 1e9 + 5; long long i, j, k, n, m, RIGHT[N], LEFT[N], ans, a[N]; long long _RIGHT[N], _LEFT[N]; int main() { scanf( %lld , &n); for (int i = 1; i <= n - 1; i++) scanf( %lld , &a[i]); for (int i = n; i >= 1; i--) { if (a[i] != 1) RIGHT[i] = RIGHT[i + 1] + a[i] - (a[i] & 1); _RIGHT[i] = max(RIGHT[i + 1], _RIGHT[i + 1]) + a[i] - (!(a[i] & 1)); } for (int i = 1; i <= n; i++) { if (a[i - 1] != 1) LEFT[i] = LEFT[i - 1] + a[i - 1] - (a[i - 1] & 1); _LEFT[i] = max((a[i] != 1) * LEFT[i - 1], (_LEFT[i - 1])) + a[i - 1] - (!(a[i - 1] & 1)); } for (int i = 1; i <= n; i++) { ans = max(ans, max(_LEFT[i], LEFT[i]) + RIGHT[i]); ans = max(ans, max(_RIGHT[i], RIGHT[i]) + LEFT[i]); } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = ((res % p) * (x % p)) % p; y = y >> 1; x = ((x % p) * (x % p)) % p; } return res; } long long raichu(long long x, long long y) { long long res = 1; while (y > 0) { if (y & 1) res = ((res) * (x)); y = y >> 1; x = ((x) * (x)); } return res; } bool isprime(long long n) { if (n < 2) return false; else if (n == 2) return true; else if (n % 2 == 0) return false; else { long long z = sqrt(n); for (int i = 0; i < z - 1; i++) if (n % (i + 2) == 0) return false; return true; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1, T; T = t; while (t--) { int n; cin >> n; vector<pair<int, int> > kb(n); vector<pair<pair<long double, int>, int> > v; vector<pair<long double, int> > minus, plus; vector<pair<long long, long long> > lines; long long K = 0, B = 0; for (int i = 0; i < n; i++) { cin >> kb[i].first >> kb[i].second; if (kb[i].first == 0 && kb[i].second == 0) continue; else if (kb[i].first == 0) { if (kb[i].second > 0) B += kb[i].second; else continue; } else if (kb[i].second == 0) { if (kb[i].first > 0) v.push_back(make_pair(make_pair(0, 1), i)); else v.push_back(make_pair(make_pair(0, -1), i)); } else { if (kb[i].first > 0) v.push_back( make_pair(make_pair((-1.0 * kb[i].second) / kb[i].first, 1), i)); else v.push_back( make_pair(make_pair((-1.0 * kb[i].second) / kb[i].first, -1), i)); } } n = (int)v.size(); int ans = 0; sort(v.begin(), v.end()); for (int i = 0; i < n; i++) { if (v[i].first.second == -1) { K += kb[v[i].second].first; B += kb[v[i].second].second; } } lines.push_back(make_pair(K, B)); for (int i = 0; i < n; i++) { long double x = v[i].first.first; while (i < n && v[i].first.first == x) { if (v[i].first.second == 1) { K += kb[v[i].second].first; B += kb[v[i].second].second; } else { K -= kb[v[i].second].first; B -= kb[v[i].second].second; } i++; } i--; lines.push_back(make_pair(K, B)); } for (int i = 0; i < (int)lines.size() - 1; i++) { if (lines[i].first != lines[i + 1].first) ans++; } cout << ans; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<vector<long long>> matrixMul(vector<vector<long long>> lft, vector<vector<long long>> rit, long long mod = 1e9 + 7) { int n = lft.size(), s = rit.size(), m = rit.back().size(); vector<vector<long long>> res(n, vector<long long>(m, 0)); for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) for (int k = 0; k < s; ++k) res[i][j] = (res[i][j] + lft[i][k] * rit[k][j]) % mod; return res; } vector<vector<long long>> matrixPow(vector<vector<long long>> base, long long exp, long long mod = 1e9 + 7) { int n = base.size(); vector<vector<long long>> res(n, vector<long long>(n, 0)); for (int i = 0; i < n; ++i) res[i][i] = 1; for (; exp; exp >>= 1, base = matrixMul(base, base, mod)) if (exp & 1) res = matrixMul(res, base, mod); return res; } int main() { long long n, m; cin >> n >> m; vector<vector<long long>> mat; mat.resize(m); for (int i = 0; i < m; ++i) mat[i].resize(m); for (int i = 0; i < m; ++i) for (int j = 0; j < m; ++j) { mat[i][j] = 0; } for (int i = 1; i < m; ++i) mat[i][i - 1] = 1; mat[0][0] = 1; mat[0][m - 1] = 1; cout << matrixPow(mat, n)[0][0]; } |
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