name string | code string | asm string | file string |
|---|---|---|---|
(anonymous namespace)::SplitModuleLogger& (anonymous namespace)::operator<<<llvm::StringRef>((anonymous namespace)::SplitModuleLogger&, llvm::StringRef const&) | static SplitModuleLogger &operator<<(SplitModuleLogger &SML, const Ty &Val) {
static_assert(
!std::is_same_v<Ty, Value>,
"do not print values to logs directly, use handleName instead!");
LLVM_DEBUG(dbgs() << Val);
if (SML.hasLogFile())
SML.logfile() << Val;
return SML;
} | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
jmp 0x1168390
movq 0x20(%rsp), %rdi
callq 0x116a940
testb $0x1, %al
jne 0x11683a0
jmp 0x11683d2
movq 0x20(%rsp), %rdi
callq 0x116a960
movq %rax, %rdi
movq 0x18(%rsp), %rax
movq (%rax), %rcx
movq %rcx, 0x8(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0x10(%rsp)
movq ... | /Target/AMDGPU/AMDGPUSplitModule.cpp |
(anonymous namespace)::externalize(llvm::GlobalValue&) | static void externalize(GlobalValue &GV) {
if (GV.hasLocalLinkage()) {
GV.setLinkage(GlobalValue::ExternalLinkage);
GV.setVisibility(GlobalValue::HiddenVisibility);
}
// Unnamed entities must be named consistently between modules. setName will
// give a distinct name to each such entity.
if (!GV.hasN... | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq 0x30(%rsp), %rdi
callq 0x7278a0
testb $0x1, %al
jne 0x1168449
jmp 0x1168464
movq 0x30(%rsp), %rdi
xorl %esi, %esi
callq 0xb1e8b0
movq 0x30(%rsp), %rdi
movl $0x1, %esi
callq 0xb479f0
movq 0x30(%rsp), %rdi
callq 0x78bd50
testb $0x1, %al
jne 0x116849a
movq 0x30(%rsp), %rax
movq ... | /Target/AMDGPU/AMDGPUSplitModule.cpp |
(anonymous namespace)::SplitModuleLogger& (anonymous namespace)::operator<<<char [3]>((anonymous namespace)::SplitModuleLogger&, char const (&) [3]) | static SplitModuleLogger &operator<<(SplitModuleLogger &SML, const Ty &Val) {
static_assert(
!std::is_same_v<Ty, Value>,
"do not print values to logs directly, use handleName instead!");
LLVM_DEBUG(dbgs() << Val);
if (SML.hasLogFile())
SML.logfile() << Val;
return SML;
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
jmp 0x1168f30
movq 0x10(%rsp), %rdi
callq 0x116a940
testb $0x1, %al
jne 0x1168f40
jmp 0x1168f57
movq 0x10(%rsp), %rdi
callq 0x116a960
movq %rax, %rdi
movq 0x8(%rsp), %rsi
callq 0x41be30
movq 0x10(%rsp), %rax
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nopl (%ra... | /Target/AMDGPU/AMDGPUSplitModule.cpp |
(anonymous namespace)::SplitModuleLogger& (anonymous namespace)::operator<<<char [23]>((anonymous namespace)::SplitModuleLogger&, char const (&) [23]) | static SplitModuleLogger &operator<<(SplitModuleLogger &SML, const Ty &Val) {
static_assert(
!std::is_same_v<Ty, Value>,
"do not print values to logs directly, use handleName instead!");
LLVM_DEBUG(dbgs() << Val);
if (SML.hasLogFile())
SML.logfile() << Val;
return SML;
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
jmp 0x116a070
movq 0x10(%rsp), %rdi
callq 0x116a940
testb $0x1, %al
jne 0x116a080
jmp 0x116a097
movq 0x10(%rsp), %rdi
callq 0x116a960
movq %rax, %rdi
movq 0x8(%rsp), %rsi
callq 0x41be30
movq 0x10(%rsp), %rax
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nopl (%ra... | /Target/AMDGPU/AMDGPUSplitModule.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::Function const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseSetPair<llvm::Function const*>>, llvm::Function const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseSetPair<llvm:... | iterator makeIterator(BucketT *P, BucketT *E,
DebugEpochBase &Epoch,
bool NoAdvance=false) {
if (shouldReverseIterate<KeyT>()) {
BucketT *B = P == getBucketsEnd() ? getBuckets() : P + 1;
return iterator(B, E, Epoch, NoAdvance);
}
return iterator(P,... | subq $0x58, %rsp
movb %r8b, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0xbdf5c0
testb $0x1, %al
jne 0x116d616
jmp 0x116d682
movq 0x10(%rsp), %rdi
movq 0x38(%rsp), %rax
movq %rax, 0x8(%r... | /llvm/ADT/DenseMap.h |
llvm::DenseMapIterator<llvm::Function const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseSetPair<llvm::Function const*>, true>::RetreatPastEmptyBuckets() | void RetreatPastEmptyBuckets() {
assert(Ptr >= End);
const KeyT Empty = KeyInfoT::getEmptyKey();
const KeyT Tombstone = KeyInfoT::getTombstoneKey();
while (Ptr != End && (KeyInfoT::isEqual(Ptr[-1].getFirst(), Empty) ||
KeyInfoT::isEqual(Ptr[-1].getFirst(), Tombstone)))
-... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq 0x20(%rsp), %rax
movq %rax, 0x8(%rsp)
callq 0xbdf710
movq %rax, 0x18(%rsp)
callq 0xbdf730
movq %rax, 0x10(%rsp)
movq 0x8(%rsp), %rdx
movq (%rdx), %rcx
xorl %eax, %eax
cmpq 0x8(%rdx), %rcx
movb %al, 0x7(%rsp)
je 0x116ed50
movq 0x8(%rsp), %rax
movq (%rax), %rdi
addq $-0x8, %rdi... | /llvm/ADT/DenseMap.h |
void llvm::sort<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>*>(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>*) | inline void sort(IteratorTy Start, IteratorTy End) {
if constexpr (detail::sort_trivially_copyable<IteratorTy>::value) {
// Forward trivially copyable types to array_pod_sort. This avoids a large
// amount of code bloat for a minor performance hit.
array_pod_sort(Start, End);
} else {
#ifdef EXPENSIVE_C... | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rdi
movq 0x8(%rsp), %rsi
callq 0x1170b90
addq $0x18, %rsp
retq
nopw %cs:(%rax,%rax)
nopl (%rax)
| /llvm/ADT/STLExtras.h |
void llvm::DenseMapBase<llvm::DenseMap<llvm::Function const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseSetPair<llvm::Function const*>>, llvm::Function const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseSetPair<... | void copyFrom(
const DenseMapBase<OtherBaseT, KeyT, ValueT, KeyInfoT, BucketT> &other) {
assert(&other != this);
assert(getNumBuckets() == other.getNumBuckets());
setNumEntries(other.getNumEntries());
setNumTombstones(other.getNumTombstones());
if (std::is_trivially_copyable<KeyT>::value &&
... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x20(%rsp), %rax
movq %rax, (%rsp)
movq 0x18(%rsp), %rdi
callq 0x116dc90
movq (%rsp), %rdi
movl %eax, %esi
callq 0x116c030
movq 0x18(%rsp), %rdi
callq 0x116dcc0
movq (%rsp), %rdi
movl %eax, %esi
callq 0x116c050
movq (%rsp), %rdi
callq 0x116c080
movq %rax... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::Function const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseSetPair<llvm::Function const*>>, llvm::Function const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Function const*, void>, llvm::detail::DenseSetPair<llvm:... | const_iterator find(const_arg_type_t<KeyT> Val) const {
const BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeConstIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(... | subq $0x48, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, 0x18(%rsp)
leaq 0x28(%rsp), %rsi
leaq 0x20(%rsp), %rdx
callq 0x116d730
testb $0x1, %al
jne 0x117658d
jmp 0x11765eb
movq 0x20(%rsp), %rax
movq %rax, 0x10(%rsp)
callq 0xbdf5c0
testb $0x1, %al
jne 0x11765a2
jmp 0x11765b3
movq 0x1... | /llvm/ADT/DenseMap.h |
llvm::scc_iterator<llvm::MachineFunction*, llvm::GraphTraits<llvm::MachineFunction*>>::DFSVisitOne(llvm::MachineBasicBlock*) | void scc_iterator<GraphT, GT>::DFSVisitOne(NodeRef N) {
++visitNum;
nodeVisitNumbers[N] = visitNum;
SCCNodeStack.push_back(N);
VisitStack.push_back(StackElement(N, GT::child_begin(N), visitNum));
#if 0 // Enable if needed when debugging.
dbgs() << "TarjanSCC: Node " << N <<
" : visitNum = " << visitNu... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movl (%rdi), %eax
addl $0x1, %eax
movl %eax, (%rdi)
movl (%rdi), %eax
movl %eax, 0xc(%rsp)
addq $0x8, %rdi
leaq 0x48(%rsp), %rsi
callq 0xe5d050
movl 0xc(%rsp), %ecx
movq 0x18(%rsp), %rdi
movl %ecx, (%rax)
addq $0x20... | /llvm/ADT/SCCIterator.h |
llvm::GCNHazardRecognizer::fixWMMAHazards(llvm::MachineInstr*) | bool GCNHazardRecognizer::fixWMMAHazards(MachineInstr *MI) {
if (!SIInstrInfo::isWMMA(*MI) && !SIInstrInfo::isSWMMAC(*MI))
return false;
const SIInstrInfo *TII = ST.getInstrInfo();
const SIRegisterInfo *TRI = ST.getRegisterInfo();
auto IsHazardFn = [MI, TII, TRI, this](const MachineInstr &I) {
if (!SI... | subq $0xc8, %rsp
movq %rdi, 0xb8(%rsp)
movq %rsi, 0xb0(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0xb0(%rsp), %rdi
callq 0xd8a9d0
testb $0x1, %al
jne 0x11892a3
movq 0xb0(%rsp), %rdi
callq 0x10b4db0
testb $0x1, %al
jne 0x11892a3
movb $0x0, 0xc7(%rsp)
jmp 0x118942c
movq 0x20(%rsp), %rax
movq 0x38(%rax), %rdi
... | /Target/AMDGPU/GCNHazardRecognizer.cpp |
llvm::SmallDenseMap<llvm::Register, int, 4u, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, int>>::deallocateBuckets() | void deallocateBuckets() {
if (Small)
return;
deallocate_buffer(getLargeRep()->Buckets,
sizeof(BucketT) * getLargeRep()->NumBuckets,
alignof(BucketT));
getLargeRep()->~LargeRep();
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rax
movq %rax, 0x8(%rsp)
movl (%rax), %eax
andl $0x1, %eax
cmpl $0x0, %eax
je 0x118e81f
jmp 0x118e85b
movq 0x8(%rsp), %rdi
callq 0x118e3a0
movq 0x8(%rsp), %rdi
movq (%rax), %rax
movq %rax, (%rsp)
callq 0x118e3a0
movq (%rsp), %rdi
movl 0x8(%rax), %eax
movl %eax, %... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::R600DAGToDAGISel::Select(llvm::SDNode*) | void R600DAGToDAGISel::Select(SDNode *N) {
unsigned int Opc = N->getOpcode();
if (N->isMachineOpcode()) {
N->setNodeId(-1);
return; // Already selected.
}
switch (Opc) {
default:
break;
case AMDGPUISD::BUILD_VERTICAL_VECTOR:
case ISD::SCALAR_TO_VECTOR:
case ISD::BUILD_VECTOR: {
EVT VT =... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x38(%rsp), %rdi
callq 0x97c400
movl %eax, 0x34(%rsp)
movq 0x38(%rsp), %rdi
callq 0x97c390
testb $0x1, %al
jne 0x11992e6
jmp 0x11992fa
movq 0x38(%rsp), %rdi
movl $0xffffffff, %esi # imm = 0xFFFFFFFF
callq... | /Target/AMDGPU/R600ISelDAGToDAG.cpp |
isFPExtFromF16OrConst(llvm::MachineRegisterInfo const&, llvm::Register) | static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
Register Reg) {
const MachineInstr *Def = MRI.getVRegDef(Reg);
if (Def->getOpcode() == TargetOpcode::G_FPEXT) {
Register SrcReg = Def->getOperand(1).getReg();
return MRI.getType(SrcReg) == LLT::scalar(16);
... | subq $0x68, %rsp
movl %esi, 0x60(%rsp)
movq %rdi, 0x58(%rsp)
movq 0x58(%rsp), %rdi
movl 0x60(%rsp), %eax
movl %eax, 0x4c(%rsp)
movl 0x4c(%rsp), %esi
callq 0x34bc760
movq %rax, 0x50(%rsp)
movq 0x50(%rsp), %rdi
callq 0x72bbb0
cmpl $0xbe, %eax
jne 0x11a01a5
movq 0x50(%rsp), %rdi
movl $0x1, %esi
callq 0x72c4d0
movq %rax, %... | /Target/AMDGPU/AMDGPUCombinerHelper.cpp |
llvm::R600TargetLowering::LowerImplicitParameter(llvm::SelectionDAG&, llvm::EVT, llvm::SDLoc const&, unsigned int) const | SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
const SDLoc &DL,
unsigned DwordOffset) const {
unsigned ByteOffset = DwordOffset * 4;
PointerType * PtrType = PointerType::get(VT.getTyp... | pushq %rbx
subq $0x190, %rsp # imm = 0x190
movb %dl, %al
movb %al, 0x170(%rsp)
movq %rcx, 0x178(%rsp)
movq %rdi, 0x168(%rsp)
movq %rsi, 0x160(%rsp)
movq %r8, 0x158(%rsp)
movl %r9d, 0x154(%rsp)
movl 0x154(%rsp), %eax
shll $0x2, %eax
movl %eax, 0x150(%rsp)
movq 0x160(%rsp), %rdi
callq 0x995030
movq %rax, %rsi
... | /Target/AMDGPU/R600ISelLowering.cpp |
llvm::ARMAsmPrinter::PrintAsmOperand(llvm::MachineInstr const*, unsigned int, char const*, llvm::raw_ostream&) | bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
const char *ExtraCode, raw_ostream &O) {
// Does this asm operand have a single letter operand modifier?
if (ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0) return true; // Unknown modifier.
... | subq $0x278, %rsp # imm = 0x278
movq %rdi, 0x268(%rsp)
movq %rsi, 0x260(%rsp)
movl %edx, 0x25c(%rsp)
movq %rcx, 0x250(%rsp)
movq %r8, 0x248(%rsp)
movq 0x268(%rsp), %rax
movq %rax, 0xa0(%rsp)
cmpq $0x0, 0x250(%rsp)
je 0x11b7fcb
movq 0x250(%rsp), %rax
cmpb $0x0, (%rax)
je 0x11b7fcb
movq 0x250(%rsp), %rax
movsb... | /Target/ARM/ARMAsmPrinter.cpp |
getArgumentStackToRestore(llvm::MachineFunction&, llvm::MachineBasicBlock&) | static int getArgumentStackToRestore(MachineFunction &MF,
MachineBasicBlock &MBB) {
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
bool IsTailCallReturn = false;
if (MBB.end() != MBBI) {
unsigned RetOpcode = MBBI->getOpcode();
IsTailCallReturn = RetOpco... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq 0x48(%rsp), %rdi
movl $0x1, %esi
callq 0x33703f0
movq %rax, 0x40(%rsp)
movb $0x0, 0x3f(%rsp)
movq 0x48(%rsp), %rdi
callq 0x73fef0
movq %rax, 0x30(%rsp)
leaq 0x30(%rsp), %rdi
leaq 0x40(%rsp), %rsi
callq 0x73fec0
testb $0x1, %al
jne 0x11d5fab
jmp 0x11d5ffa... | /Target/ARM/ARMFrameLowering.cpp |
llvm::isARMArea1Register(unsigned int, bool) | static inline bool isARMArea1Register(unsigned Reg, bool SplitFramePushPop) {
using namespace ARM;
switch (Reg) {
case R0: case R1: case R2: case R3:
case R4: case R5: case R6: case R7:
case LR: case SP: case PC:
return true;
case R8: case R9: case R10: case R11: case R12:
// ... | movb %sil, %al
movl %edi, -0x8(%rsp)
andb $0x1, %al
movb %al, -0x9(%rsp)
movl -0x8(%rsp), %eax
addl $-0xd, %eax
movl %eax, %ecx
movq %rcx, -0x18(%rsp)
subl $0x48, %eax
ja 0x11d840a
movq -0x18(%rsp), %rax
leaq 0x57147d8(%rip), %rcx # 0x68ecbc4
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movb $0x1, -0x1(%rsp)... | /Target/ARM/ARMBaseRegisterInfo.h |
llvm::isARMArea2Register(unsigned int, bool) | static inline bool isARMArea2Register(unsigned Reg, bool SplitFramePushPop) {
using namespace ARM;
switch (Reg) {
case R8: case R9: case R10: case R11: case R12:
// iOS has this second area.
return SplitFramePushPop;
default:
return false;
}
} | movb %sil, %al
movl %edi, -0x8(%rsp)
andb $0x1, %al
movb %al, -0x9(%rsp)
movl -0x8(%rsp), %eax
addl $-0x51, %eax
subl $0x4, %eax
ja 0x11d8447
jmp 0x11d843b
movb -0x9(%rsp), %al
andb $0x1, %al
movb %al, -0x1(%rsp)
jmp 0x11d844c
movb $0x0, -0x1(%rsp)
movb -0x1(%rsp), %al
andb $0x1, %al
retq
nopw %cs:(%rax,%rax)
nopl (%ra... | /Target/ARM/ARMBaseRegisterInfo.h |
llvm::BasicTTIImplBase<llvm::ARMTTIImpl>::getInterleavedMemoryOpCost(unsigned int, llvm::Type*, unsigned int, llvm::ArrayRef<unsigned int>, llvm::Align, unsigned int, llvm::TargetTransformInfo::TargetCostKind, bool, bool) | InstructionCost getInterleavedMemoryOpCost(
unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
bool UseMaskForCond = false, bool UseMaskForGaps = false) {
// We cannot scalarize scalable vectors, so retu... | subq $0x428, %rsp # imm = 0x428
movq %r9, %r10
movq %r8, %r11
movl %ecx, 0x94(%rsp)
movq %rdx, %rax
movl 0x94(%rsp), %edx
movq %rax, 0x98(%rsp)
movl %esi, %eax
movq 0x98(%rsp), %rsi
movl %eax, 0xa4(%rsp)
movq %rdi, %r8
movl 0xa4(%rsp), %edi
movb 0x450(%rsp), %al
movb 0x448(%rsp), %cl
movl 0x440(%rsp), %r9d
m... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::SmallVectorImpl<llvm::Instruction*>::operator=(llvm::SmallVectorImpl<llvm::Instruction*>&&) | SmallVectorImpl<T> &SmallVectorImpl<T>::operator=(SmallVectorImpl<T> &&RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If the RHS isn't small, clear this vector and then steal its buffer.
if (!RHS.isSmall()) {
this->assignRemote(std::move(RHS));
return *this;
}
// If we already... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x30(%rsp)
cmpq 0x50(%rsp), %rax
jne 0x122e38e
movq 0x30(%rsp), %rax
movq %rax, 0x60(%rsp)
jmp 0x122e570
movq 0x50(%rsp), %rdi
callq 0x7beb40
testb $0x1, %al
jne 0x122e3ba
movq 0x30(%rsp), %rdi
movq 0x50(%rsp), %rsi
callq 0x12... | /llvm/ADT/SmallVector.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Value*, llvm::SCEVWrapPredicate::IncrementWrapFlags, llvm::ValueMapConfig<llvm::Value*, llvm::sys::SmartMutex<false>>>, llvm::SCEVWrapPredicate::IncrementWrapFlags, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Value*, llvm::SCEVWrapPredicate::Increme... | bool erase(const KeyT &Val) {
BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket))
return false; // not in map.
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
return true;
} | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq 0x48(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movq 0x40(%rsp), %rsi
leaq 0x38(%rsp), %rdx
callq 0x122fa10
testb $0x1, %al
jne 0x122f9b2
movb $0x0, 0x57(%rsp)
jmp 0x122fa00
movq 0x38(%rsp), %rdi
callq 0x122f5b0
leaq 0x10(%rsp), %rdi
callq 0x122f4f0
movq 0x38(%rsp... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::Use*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Use*, void>, llvm::detail::DenseSetPair<llvm::Use*>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
movl 0xc(%rsp), %esi
callq 0x12444a0
movq (%rsp), %rdi
movl %eax, 0x8(%rsp)
movl 0x8(%rsp), %esi
callq 0x12444f0
testb $0x1, %al
jne 0x1244476
jmp 0x1244481
movq (%rsp), %rdi
callq 0x1244560
jmp 0x1244493
movq (%rsp), %r... | /llvm/ADT/DenseMap.h |
initializeMVEVPTBlockPassOnce(llvm::PassRegistry&) | static MachineInstr *findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,
const TargetRegisterInfo *TRI,
unsigned &NewOpcode) {
// Search backwards to the instruction that defines VPR. This may or not
// be a VCMP, we check th... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movl $0x50, %edi
callq 0x349070
movq %rax, 0x20(%rsp)
leaq 0x38(%rsp), %rdi
leaq 0x56a3bb4(%rip), %rsi # 0x68f07e8
callq 0x3ee9c0
leaq 0x28(%rsp), %rdi
leaq 0x56a3bba(%rip), %rsi # 0x68f07ff
callq 0x3ee9c0
movq 0x20(%rsp), %rdi
movq 0x38(%rsp), %rsi
movq 0x40(%rsp), %rdx
movq ... | /Target/ARM/MVEVPTBlockPass.cpp |
(anonymous namespace)::MVETPAndVPTOptimisations::LowerWhileLoopStart(llvm::MachineLoop*) | bool MVETPAndVPTOptimisations::LowerWhileLoopStart(MachineLoop *ML) {
LLVM_DEBUG(dbgs() << "LowerWhileLoopStart on loop "
<< ML->getHeader()->getName() << "\n");
MachineInstr *LoopEnd, *LoopPhi, *LoopStart, *LoopDec;
if (!findLoopComponents(ML, MRI, LoopStart, LoopPhi, LoopDec, LoopEnd))
... | subq $0xd8, %rsp
movq %rdi, 0xc8(%rsp)
movq %rsi, 0xc0(%rsp)
movq 0xc8(%rsp), %rax
movq %rax, 0x20(%rsp)
jmp 0x124e4a6
movq 0x20(%rsp), %rax
movq 0xc0(%rsp), %rdi
movq 0x40(%rax), %rsi
leaq 0xa8(%rsp), %rdx
leaq 0xb0(%rsp), %rcx
leaq 0xa0(%rsp), %r8
leaq 0xb8(%rsp), %r9
callq 0x1251250
testb $0x1, %al
jne 0x124e4ed
mov... | /Target/ARM/MVETPAndVPTOptimisationsPass.cpp |
llvm::Thumb1FrameLowering::emitPopSpecialFixUp(llvm::MachineBasicBlock&, bool) const | bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
bool DoIt) const {
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
const TargetInstrInfo &TII = ... | subq $0x8d8, %rsp # imm = 0x8D8
movb %dl, %al
movq %rdi, 0x8c8(%rsp)
movq %rsi, 0x8c0(%rsp)
andb $0x1, %al
movb %al, 0x8bf(%rsp)
movq 0x8c8(%rsp), %rax
movq %rax, 0x108(%rsp)
movq 0x8c0(%rsp), %rdi
callq 0x73fb50
movq %rax, 0x8b0(%rsp)
movq 0x8b0(%rsp), %rdi
callq 0x11b6910
movq %rax, 0x8a8(%rsp)
movq 0x8a8(... | /Target/ARM/Thumb1FrameLowering.cpp |
llvm::Thumb2InstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::MCRegister, llvm::MCRegister, bool) const | void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
// Handle SPR, DPR, and QPR copies.
if (!ARM... | subq $0x118, %rsp # imm = 0x118
movb 0x120(%rsp), %al
movq %rdx, 0x110(%rsp)
movl %r8d, 0x10c(%rsp)
movl %r9d, 0x108(%rsp)
movq %rdi, 0x100(%rsp)
movq %rsi, 0xf8(%rsp)
movq %rcx, 0xf0(%rsp)
andb $0x1, %al
movb %al, 0xef(%rsp)
movq 0x100(%rsp), %rax
movq %rax, 0x28(%rsp)
movl 0x10c(%rsp), %eax
movl %eax, 0xe4... | /Target/ARM/Thumb2InstrInfo.cpp |
llvm::ARMBaseInstrInfo::loadRegFromStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, llvm::Register) const | void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register DestReg, int FI,
const TargetRegisterClass *RC,
... | subq $0xae8, %rsp # imm = 0xAE8
movl 0xaf8(%rsp), %eax
movq 0xaf0(%rsp), %r10
movq %rdx, 0xae0(%rsp)
movl %ecx, 0xadc(%rsp)
movl %eax, 0xad8(%rsp)
movq %rdi, 0xad0(%rsp)
movq %rsi, 0xac8(%rsp)
movl %r8d, 0xac4(%rsp)
movq %r9, 0xab8(%rsp)
movq 0xad0(%rsp), %rax
movq %rax, 0x158(%rsp)
leaq 0xab0(%rsp), %rdi
ca... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::getLDMDefCycle(llvm::InstrItineraryData const*, llvm::MCInstrDesc const&, unsigned int, unsigned int, unsigned int) const | std::optional<unsigned>
ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
const MCInstrDesc &DefMCID, unsigned DefClass,
unsigned DefIdx, unsigned DefAlign) const {
int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
if (Re... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq %rdx, 0x28(%rsp)
movl %ecx, 0x24(%rsp)
movl %r8d, 0x20(%rsp)
movl %r9d, 0x1c(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x20(%rsp), %eax
addl $0x1, %eax
movl %eax, 0x10(%rsp)
movq 0x28(%rsp), %rdi
callq 0x5beba0
movl %eax, %ecx
movl 0x10(%rsp)... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::getOperandLatency(llvm::InstrItineraryData const*, llvm::MachineInstr const&, unsigned int, llvm::MachineInstr const&, unsigned int) const | std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency(
const InstrItineraryData *ItinData, const MachineInstr &DefMI,
unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
// No operand latency. The caller may fall back to getInstrLatency.
if (!ItinData || ItinData->isEmpty())
retur... | pushq %rbp
pushq %r14
pushq %rbx
subq $0xf0, %rsp
movq %rdi, 0xe0(%rsp)
movq %rsi, 0xd8(%rsp)
movq %rdx, 0xd0(%rsp)
movl %ecx, 0xcc(%rsp)
movq %r8, 0xc0(%rsp)
movl %r9d, 0xbc(%rsp)
movq 0xe0(%rsp), %rax
movq %rax, 0x80(%rsp)
cmpq $0x0, 0xd8(%rsp)
je 0x1288848
movq 0xd8(%rsp), %rdi
callq 0xcfa880
testb $0x1, %al
jne 0x1... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::InstrItineraryData::getStageLatency(unsigned int) const | unsigned getStageLatency(unsigned ItinClassIndx) const {
// If the target doesn't provide itinerary information, use a simple
// non-zero default value for all instructions.
if (isEmpty())
return 1;
// Calculate the maximum completion time for any stage.
unsigned Latency = 0, StartCycle = 0;
... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movl %esi, 0x34(%rsp)
movq 0x38(%rsp), %rdi
movq %rdi, 0x8(%rsp)
callq 0xcfa880
testb $0x1, %al
jne 0x128a172
jmp 0x128a17f
movl $0x1, 0x44(%rsp)
jmp 0x128a21e
movq 0x8(%rsp), %rdi
movl $0x0, 0x30(%rsp)
movl $0x0, 0x2c(%rsp)
movl 0x34(%rsp), %esi
callq 0x1293f00
movq 0x8(%rsp), %r... | /llvm/MC/MCInstrItineraries.h |
llvm::ARMBaseInstrInfo::hasLowDefLatency(llvm::TargetSchedModel const&, llvm::MachineInstr const&, unsigned int) const | bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
const MachineInstr &DefMI,
unsigned DefIdx) const {
const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
if (!ItinData || ItinData->isEmpty())... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq %rdx, 0x28(%rsp)
movl %ecx, 0x24(%rsp)
movq 0x30(%rsp), %rdi
callq 0x128a530
movq %rax, 0x18(%rsp)
cmpq $0x0, 0x18(%rsp)
je 0x128a47e
movq 0x18(%rsp), %rdi
callq 0xcfa880
testb $0x1, %al
jne 0x128a47e
jmp 0x128a488
movb $0x0, 0x47(%rsp)
jmp 0x128a519
mov... | /Target/ARM/ARMBaseInstrInfo.cpp |
getCorrespondingDRegAndLane(llvm::TargetRegisterInfo const*, unsigned int, unsigned int&) | static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
unsigned SReg, unsigned &Lane) {
unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
Lane = 0;
if (DReg != ARM::NoRegister)
return DReg;
Lane = 1;
DReg = TRI-... | subq $0x48, %rsp
movq %rdi, 0x38(%rsp)
movl %esi, 0x34(%rsp)
movq %rdx, 0x28(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x34(%rsp), %esi
leaq 0x1c(%rsp), %rdi
callq 0x40c480
movq 0x8(%rsp), %rdi
movl 0x1c(%rsp), %esi
movl $0x11, %edx
leaq 0x8358551(%rip), %rcx # 0x95e5590
callq 0xae4700
movl %eax, 0x20(%rs... | /Target/ARM/ARMBaseInstrInfo.cpp |
(anonymous namespace)::ARMIncomingValueHandler::assignCustomValue(llvm::CallLowering::ArgInfo&, llvm::ArrayRef<llvm::CCValAssign>, std::function<void ()>*) | unsigned assignCustomValue(ARMCallLowering::ArgInfo &Arg,
ArrayRef<CCValAssign> VAs,
std::function<void()> *Thunk) override {
assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
const CCValAssign &VA = VAs[0];
assert(VA.needsCustom() &&... | subq $0xf8, %rsp
movq %rdx, 0xe0(%rsp)
movq %rcx, 0xe8(%rsp)
movq %rdi, 0xd8(%rsp)
movq %rsi, 0xd0(%rsp)
movq %r8, 0xc8(%rsp)
movq 0xd8(%rsp), %rax
movq %rax, 0x20(%rsp)
leaq 0xe0(%rsp), %rdi
xorl %eax, %eax
movl %eax, %esi
callq 0x12a1fa0
movq %rax, 0xc0(%rsp)
movq 0xc0(%rsp), %rdi
callq 0x7fe9d0
movb %al, 0xbf(%rsp)
... | /Target/ARM/ARMCallLowering.cpp |
llvm::DenseMap<int, int, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, int>>::allocateBuckets(unsigned int) | bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = nullptr;
return false;
}
Buckets = static_cast<BucketT *>(
allocate_buffer(sizeof(BucketT) * NumBuckets, alignof(BucketT)));
return true;
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movl %esi, 0x14(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x8(%rsp)
movl 0x14(%rsp), %ecx
movl %ecx, 0x10(%rax)
cmpl $0x0, 0x10(%rax)
jne 0x12a41b7
movq 0x8(%rsp), %rax
movq $0x0, (%rax)
movb $0x0, 0x27(%rsp)
jmp 0x12a41df
movq 0x8(%rsp), %rax
movl 0x10(%rax), %eax
movl %eax, %edi
sh... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::ARMConstantIslands::getUserOffset((anonymous namespace)::ARMConstantIslands::CPUser&) const | unsigned ARMConstantIslands::getUserOffset(CPUser &U) const {
unsigned UserOffset = BBUtils->getOffsetOf(U.MI);
SmallVectorImpl<BasicBlockInfo> &BBInfo = BBUtils->getBBInfo();
const BasicBlockInfo &BBI = BBInfo[U.MI->getParent()->getNumber()];
unsigned KnownBits = BBI.internalKnownBits();
// The value read ... | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x10(%rsp)
addq $0x38, %rdi
callq 0x12a9620
movq %rax, %rdi
movq 0x38(%rsp), %rax
movq (%rax), %rsi
callq 0x14260e0
movq 0x10(%rsp), %rdi
movl %eax, 0x34(%rsp)
addq $0x38, %rdi
callq 0x12a9620
movq %rax, %rdi
callq 0x12ad330
m... | /Target/ARM/ARMConstantIslandPass.cpp |
llvm::BasicBlockInfo::postOffset(llvm::Align) const | unsigned postOffset(Align Alignment = Align(1)) const {
unsigned PO = Offset + Size;
const Align PA = std::max(PostAlign, Alignment);
if (PA == Align(1))
return PO;
// Add alignment padding from the terminator.
return PO + UnknownPadding(PA, internalKnownBits());
} | subq $0x28, %rsp
movb %sil, %al
movb %al, 0x23(%rsp)
movq %rdi, 0x18(%rsp)
movq 0x18(%rsp), %rdi
movq %rdi, 0x8(%rsp)
movl (%rdi), %eax
addl 0x4(%rdi), %eax
movl %eax, 0x14(%rsp)
addq $0xa, %rdi
leaq 0x23(%rsp), %rsi
callq 0x868d00
movb (%rax), %al
movb %al, 0x13(%rsp)
movb 0x13(%rsp), %al
movb %al, 0x12(%rsp)
leaq 0x1... | /Target/ARM/ARMBasicBlockInfo.h |
llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes) | inline static CondCodes getOppositeCondition(CondCodes CC) {
switch (CC) {
default: llvm_unreachable("Unknown condition code");
case EQ: return NE;
case NE: return EQ;
case HS: return LO;
case LO: return HS;
case MI: return PL;
case PL: return MI;
case VS: return VC;
case VC: return VS;
case HI: r... | movl %edi, -0x8(%rsp)
movl -0x8(%rsp), %eax
movq %rax, -0x10(%rsp)
movq -0x10(%rsp), %rax
leaq 0x563ed87(%rip), %rcx # 0x68f28f0
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl $0x1, -0x4(%rsp)
jmp 0x12b3bff
movl $0x0, -0x4(%rsp)
jmp 0x12b3bff
movl $0x3, -0x4(%rsp)
jmp 0x12b3bff
movl $0x2, -0x4(%rsp)
jmp 0... | /Target/ARM/Utils/ARMBaseInfo.h |
(anonymous namespace)::ARMExpandPseudo::CMSEClearFPRegsV81(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::BitVector const&) | MachineBasicBlock &
ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const BitVector &ClearRegs) {
auto &RetI = *MBBI;
// Emit a sequence of VSCCLRM <sreglist> instructions, one instruction for
//... | subq $0x198, %rsp # imm = 0x198
movq %rdx, 0x190(%rsp)
movq %rdi, 0x188(%rsp)
movq %rsi, 0x180(%rsp)
movq %rcx, 0x178(%rsp)
movq 0x188(%rsp), %rax
movq %rax, 0x18(%rsp)
leaq 0x190(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x170(%rsp)
movl $0xffffffff, 0x16c(%rsp) # imm = 0xFFFFFFFF
movl $0xffffffff, 0x168(%rsp) ... | /Target/ARM/ARMExpandPseudoInsts.cpp |
(anonymous namespace)::ARMExpandPseudo::CMSEClearFPRegsV8(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::BitVector const&) | MachineBasicBlock &
ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const BitVector &ClearRegs) {
if (!STI->hasFPRegs())
return MBB;
auto &RetI = *MBBI;
const DebugLoc &DL = RetI.getDebugLoc();
... | subq $0x848, %rsp # imm = 0x848
movq %rdx, 0x838(%rsp)
movq %rdi, 0x830(%rsp)
movq %rsi, 0x828(%rsp)
movq %rcx, 0x820(%rsp)
movq 0x830(%rsp), %rax
movq %rax, 0x180(%rsp)
movq 0x48(%rax), %rdi
callq 0x12c6500
testb $0x1, %al
jne 0x12c51f9
movq 0x828(%rsp), %rax
movq %rax, 0x840(%rsp)
jmp 0x12c64e2
leaq 0x838(... | /Target/ARM/ARMExpandPseudoInsts.cpp |
(anonymous namespace)::ARMExpandPseudo::CMSESaveClearFPRegsV81(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc&, llvm::LivePhysRegs const&) | void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
DebugLoc &DL,
const LivePhysRegs &LiveRegs) {
BitVector ClearRegs(32, true);
b... | subq $0x398, %rsp # imm = 0x398
movq %rdx, 0x390(%rsp)
movq %rdi, 0x388(%rsp)
movq %rsi, 0x380(%rsp)
movq %rcx, 0x378(%rsp)
movq %r8, 0x370(%rsp)
movq 0x388(%rsp), %rax
movq %rax, 0x70(%rsp)
leaq 0x328(%rsp), %rdi
movl $0x20, %esi
movl $0x1, %edx
callq 0x5303b0
leaq 0x390(%rsp), %rdi
callq 0x7410f0
movq %rax... | /Target/ARM/ARMExpandPseudoInsts.cpp |
getBaseOffset(llvm::MachineInstr const&, llvm::MachineOperand const*&, long&) | static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp,
int64_t &Offset) {
uint64_t TSFlags = MI.getDesc().TSFlags;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
unsigned IndexMode =
(TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
// A... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq %rdx, 0x48(%rsp)
movq 0x58(%rsp), %rdi
callq 0x7349e0
movq 0x18(%rax), %rax
movq %rax, 0x40(%rsp)
movl 0x40(%rsp), %eax
andl $0x1f, %eax
movl %eax, 0x3c(%rsp)
movl 0x40(%rsp), %eax
andl $0x60, %eax
shrl $0x5, %eax
movl %eax, 0x38(%rsp)
movl 0x3c(%rsp), %... | /Target/ARM/ARMHazardRecognizer.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectVLDSTLane(llvm::SDNode*, bool, bool, unsigned int, unsigned short const*, unsigned short const*) | void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
unsigned NumVecs,
const uint16_t *DOpcodes,
const uint16_t *QOpcodes) {
assert(Subtarget->hasNEON());
assert(NumVecs >=2 &&... | subq $0x648, %rsp # imm = 0x648
movb %cl, %al
movb %dl, %cl
movq 0x650(%rsp), %rdx
movq %rdi, 0x640(%rsp)
movq %rsi, 0x638(%rsp)
andb $0x1, %cl
movb %cl, 0x637(%rsp)
andb $0x1, %al
movb %al, 0x636(%rsp)
movl %r8d, 0x630(%rsp)
movq %r9, 0x628(%rsp)
movq 0x640(%rsp), %rax
movq %rax, 0xa0(%rsp)
movq 0x638(%rsp)... | /Target/ARM/ARMISelDAGToDAG.cpp |
llvm::ARMTargetLowering::setAllExpand(llvm::MVT) | void ARMTargetLowering::setAllExpand(MVT VT) {
for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
setOperationAction(Opc, VT, Expand);
// We support these really simple operations even on types where all
// the actual arithmetic has to be broken down into simpler
// operations or turned into library ... | subq $0x28, %rsp
movb %sil, %al
movb %al, 0x27(%rsp)
movq %rdi, 0x18(%rsp)
movq 0x18(%rsp), %rax
movq %rax, (%rsp)
movl $0x0, 0x14(%rsp)
cmpl $0x1e5, 0x14(%rsp) # imm = 0x1E5
jae 0x13146f7
movq (%rsp), %rdi
movl 0x14(%rsp), %esi
movb 0x27(%rsp), %al
movb %al, 0x13(%rsp)
movl $0x2, %ecx
movzbl 0x13(%rsp), %edx
call... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::MoveToHPR(llvm::SDLoc const&, llvm::SelectionDAG&, llvm::MVT, llvm::MVT, llvm::SDValue) const | SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
MVT LocVT, MVT ValVT, SDValue Val) const {
Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
Val);
if (Subtarget->hasFullFP16()) {
Val = DAG.getNode(ARMIS... | subq $0x228, %rsp # imm = 0x228
movb %r8b, %al
leaq 0x230(%rsp), %r8
movq %r8, 0x58(%rsp)
movb %cl, 0x20f(%rsp)
movb %al, 0x20e(%rsp)
movq %rdi, 0x200(%rsp)
movq %rsi, 0x1f8(%rsp)
movq %rdx, 0x1f0(%rsp)
movq 0x200(%rsp), %rax
movq %rax, 0x60(%rsp)
movq 0x1f0(%rsp), %rax
movq %rax, 0x48(%rsp)
movq 0x1f8(%rsp)... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::MoveFromHPR(llvm::SDLoc const&, llvm::SelectionDAG&, llvm::MVT, llvm::MVT, llvm::SDValue) const | SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
MVT LocVT, MVT ValVT,
SDValue Val) const {
if (Subtarget->hasFullFP16()) {
Val = DAG.getNode(ARMISD::VMOVrh, dl,
MVT::getIntegerVT(LocVT.ge... | subq $0x218, %rsp # imm = 0x218
movb %r8b, %al
leaq 0x220(%rsp), %r8
movq %r8, 0x58(%rsp)
movb %cl, 0x207(%rsp)
movb %al, 0x206(%rsp)
movq %rdi, 0x1f8(%rsp)
movq %rsi, 0x1f0(%rsp)
movq %rdx, 0x1e8(%rsp)
movq 0x1f8(%rsp), %rax
movq 0x4e0f8(%rax), %rdi
callq 0x1225a10
testb $0x1, %al
jne 0x131f62a
jmp 0x131f73... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerCallResult(llvm::SDValue, llvm::SDValue, unsigned int, bool, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::SmallVectorImpl<llvm::SDValue>&, bool, llvm::SDValue, bool) const | SDValue ARMTargetLowering::LowerCallResult(
SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
SDValue ThisVal, bool isCmseNSCall) const {
// Assign ... | subq $0xba8, %rsp # imm = 0xBA8
movq %rcx, 0x1d8(%rsp)
movl %edx, %r10d
movq %rsi, %r11
movq 0x1d8(%rsp), %rsi
movb 0xbf0(%rsp), %al
leaq 0xbe0(%rsp), %rcx
movq %rcx, 0x1e0(%rsp)
movb 0xbd8(%rsp), %cl
movq 0xbd0(%rsp), %rdx
movq 0xbc8(%rsp), %rdx
movq 0xbc0(%rsp), %rdx
movq 0xbb8(%rsp), %rdx
movb 0xbb0(%rsp)... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerConstantPool(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
SelectionDAG &DAG) const {
EVT PtrVT = Op.getValueType();
// FIXME there is no actual debug info here
SDLoc dl(Op);
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
SDValue Res;
// When generating ex... | subq $0x408, %rsp # imm = 0x408
movq %rsi, 0x3e8(%rsp)
movl %edx, 0x3f0(%rsp)
movq %rdi, 0x3e0(%rsp)
movq %rcx, 0x3d8(%rsp)
movq 0x3e0(%rsp), %rax
movq %rax, 0xc8(%rsp)
leaq 0x3e8(%rsp), %rdi
callq 0x98a410
movb %al, 0x3c8(%rsp)
movq %rdx, 0x3d0(%rsp)
movq 0x3e8(%rsp), %rax
movq %rax, 0x3a8(%rsp)
movq 0x3f0(... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::getJumpTableEncoding() const | unsigned ARMTargetLowering::getJumpTableEncoding() const {
// If we don't have a 32-bit pc-relative branch instruction then the jump
// table consists of block addresses. Usually this is inline, but for
// execute-only it must be placed out-of-line.
if (Subtarget->genExecuteOnly() && !Subtarget->hasV8MBaselineO... | subq $0x18, %rsp
movq %rdi, 0x8(%rsp)
movq 0x8(%rsp), %rax
movq %rax, (%rsp)
movq 0x4e0f8(%rax), %rdi
callq 0x11b6d90
testb $0x1, %al
jne 0x132c5f4
jmp 0x132c612
movq (%rsp), %rax
movq 0x4e0f8(%rax), %rdi
callq 0x1204d30
testb $0x1, %al
jne 0x132c612
movl $0x0, 0x14(%rsp)
jmp 0x132c61a
movl $0x5, 0x14(%rsp)
movl 0x14(%... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::isReadOnly(llvm::GlobalValue const*) const | bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
if (!(GV = GA->getAliaseeObject()))
return false;
if (const auto *V = dyn_cast<GlobalVariable>(GV))
return V->isConstant();
return isa<Function>(GV);
} | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
callq 0x1330100
movq %rax, 0x8(%rsp)
cmpq $0x0, 0x8(%rsp)
je 0x13300b3
movq 0x8(%rsp), %rdi
callq 0x3061160
movq %rax, 0x10(%rsp)
cmpq $0x0, %rax
jne 0x13300b1
movb $0x0, 0x27(%rsp)
jmp 0x13300e9
jmp 0x13300b3
movq 0x10(%rsp), %rdi
callq... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerINTRINSIC_VOID(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) const | SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
unsigned IntNo =
Op.getConstantOperandVal(Op.getOperand(0).getValueType() == MVT::Other);
switch (IntNo) {
default:
return SDValue(); // Don't custom lower most intrinsics.
... | subq $0x348, %rsp # imm = 0x348
movq %rsi, 0x328(%rsp)
movl %edx, 0x330(%rsp)
movq %rdi, 0x320(%rsp)
movq %rcx, 0x318(%rsp)
movq %r8, 0x310(%rsp)
movq 0x320(%rsp), %rax
movq %rax, 0x58(%rsp)
leaq 0x328(%rsp), %rdi
movq %rdi, 0x60(%rsp)
xorl %esi, %esi
callq 0x98cd00
movq %rax, %rdi
callq 0x98a410
movb %al, 0... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::VarArgStyleRegisters(llvm::CCState&, llvm::SelectionDAG&, llvm::SDLoc const&, llvm::SDValue&, unsigned int, unsigned int, bool) const | void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
const SDLoc &dl, SDValue &Chain,
unsigned ArgOffset,
unsigned TotalArgRegsSaveSize,
... | subq $0x98, %rsp
movb 0xa8(%rsp), %al
movl 0xa0(%rsp), %r10d
movq %rdi, 0x90(%rsp)
movq %rsi, 0x88(%rsp)
movq %rdx, 0x80(%rsp)
movq %rcx, 0x78(%rsp)
movq %r8, 0x70(%rsp)
movl %r9d, 0x6c(%rsp)
andb $0x1, %al
movb %al, 0x6b(%rsp)
movq 0x90(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x80(%rsp), %rdi
callq 0x985ce0
movq %rax, ... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::isUnsupportedFloatingType(llvm::EVT) const | bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
if (VT == MVT::f32)
return !Subtarget->hasVFP2Base();
if (VT == MVT::f64)
return !Subtarget->hasFP64();
if (VT == MVT::f16)
return !Subtarget->hasFullFP16();
return false;
} | subq $0x58, %rsp
movb %sil, %al
movb %al, 0x40(%rsp)
movq %rdx, 0x48(%rsp)
movq %rdi, 0x38(%rsp)
movq 0x38(%rsp), %rax
movq %rax, (%rsp)
leaq 0x28(%rsp), %rdi
movl $0xc, %esi
callq 0x793360
movb 0x28(%rsp), %al
movq 0x30(%rsp), %rdx
leaq 0x40(%rsp), %rdi
movzbl %al, %esi
callq 0x793470
testb $0x1, %al
jne 0x133dda9
jmp... | /Target/ARM/ARMISelLowering.cpp |
expandf64Toi32(llvm::SDValue, llvm::SelectionDAG&, llvm::SDValue&, llvm::SDValue&) | static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
SDValue &RetVal1, SDValue &RetVal2) {
SDLoc dl(Op);
if (isFloatingPointZero(Op)) {
RetVal1 = DAG.getConstant(0, dl, MVT::i32);
RetVal2 = DAG.getConstant(0, dl, MVT::i32);
return;
}
if (LoadSDNode *Ld = dyn_cast<Lo... | pushq %r14
pushq %rbx
subq $0x368, %rsp # imm = 0x368
movq %rdi, 0x358(%rsp)
movl %esi, 0x360(%rsp)
movq %rdx, 0x350(%rsp)
movq %rcx, 0x348(%rsp)
movq %r8, 0x340(%rsp)
movq 0x358(%rsp), %rax
movq %rax, 0x320(%rsp)
movq 0x360(%rsp), %rax
movq %rax, 0x328(%rsp)
movq 0x320(%rsp), %rsi
movl 0x328(%rsp), %edx
lea... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerBRCOND(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDValue Cond = Op.getOperand(1);
SDValue Dest = Op.getOperand(2);
SDLoc dl(Op);
// Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
// instruction.
unsigned Opc = Cond.getOpcode(... | subq $0x2d8, %rsp # imm = 0x2D8
movq %rsi, 0x2b8(%rsp)
movl %edx, 0x2c0(%rsp)
movq %rdi, 0x2b0(%rsp)
movq %rcx, 0x2a8(%rsp)
movq 0x2b0(%rsp), %rax
movq %rax, 0xb8(%rsp)
leaq 0x2b8(%rsp), %rdi
xorl %esi, %esi
callq 0x98cd00
movq (%rax), %rcx
movq %rcx, 0x298(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0x2a0(%rsp)
l... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerBR_CC(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDValue LHS = Op.getOperand(2);
SDValue RHS = Op.getOperand(3);
SDValue Dest = Op.getOperand(4);
SDLoc dl(Op);
if (isUnsupported... | pushq %rbx
subq $0x760, %rsp # imm = 0x760
movq %rsi, 0x740(%rsp)
movl %edx, 0x748(%rsp)
movq %rdi, 0x738(%rsp)
movq %rcx, 0x730(%rsp)
movq 0x738(%rsp), %rax
movq %rax, 0x128(%rsp)
leaq 0x740(%rsp), %rdi
xorl %esi, %esi
callq 0x98cd00
movq (%rax), %rcx
movq %rcx, 0x720(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0... | /Target/ARM/ARMISelLowering.cpp |
isVEXTMask(llvm::ArrayRef<int>, llvm::EVT, bool&, unsigned int&) | static bool isVEXTMask(ArrayRef<int> M, EVT VT,
bool &ReverseVEXT, unsigned &Imm) {
unsigned NumElts = VT.getVectorNumElements();
ReverseVEXT = false;
// Assume that the first shuffle index is not UNDEF. Fail if it is.
if (M[0] < 0)
return false;
Imm = M[0];
// If this is a VE... | subq $0x48, %rsp
movb %dl, %al
movq %rdi, 0x30(%rsp)
movq %rsi, 0x38(%rsp)
movb %al, 0x20(%rsp)
movq %rcx, 0x28(%rsp)
movq %r8, 0x18(%rsp)
movq %r9, 0x10(%rsp)
leaq 0x20(%rsp), %rdi
callq 0x7abb40
movl %eax, 0xc(%rsp)
movq 0x18(%rsp), %rax
movb $0x0, (%rax)
leaq 0x30(%rsp), %rdi
xorl %eax, %eax
movl %eax, %esi
callq 0x... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerFSETCC(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerFSETCC(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
EVT VT = Op.getValueType();
SDValue Chain = Op.getOperand(0);
SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
bool IsSignaling = Op.... | pushq %r15
pushq %r14
pushq %rbx
subq $0x570, %rsp # imm = 0x570
movq %rsi, 0x550(%rsp)
movl %edx, 0x558(%rsp)
movq %rdi, 0x548(%rsp)
movq %rcx, 0x540(%rsp)
movq 0x548(%rsp), %rax
movq %rax, 0xc8(%rsp)
movq 0x550(%rsp), %rax
movq %rax, 0x520(%rsp)
movq 0x558(%rsp), %rax
movq %rax, 0x528(%rsp)
movq 0x520(%rsp... | /Target/ARM/ARMISelLowering.cpp |
LowerEXTRACT_SUBVECTOR(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) | static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
SDLoc dl(Op);
EVT VT = Op.getValueType();
EVT Op1VT = V1.getValueType();
unsigned NumElts = VT.getVectorNumElemen... | subq $0x638, %rsp # imm = 0x638
movq %rdi, 0x618(%rsp)
movl %esi, 0x620(%rsp)
movq %rdx, 0x610(%rsp)
movq %rcx, 0x608(%rsp)
leaq 0x618(%rsp), %rdi
movq %rdi, 0xf8(%rsp)
xorl %esi, %esi
callq 0x98cd00
movq 0xf8(%rsp), %rdi
movups (%rax), %xmm0
movaps %xmm0, 0x5f0(%rsp)
movl $0x1, %esi
callq 0x98cd00
movups (%... | /Target/ARM/ARMISelLowering.cpp |
LowerSDIV(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) | static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
EVT VT = Op.getValueType();
assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
"unexpected type for custom-lowering ISD::SDIV");
SDLoc dl(Op);
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOpe... | subq $0x4d8, %rsp # imm = 0x4D8
movq %rdi, 0x4b8(%rsp)
movl %esi, 0x4c0(%rsp)
movq %rdx, 0x4b0(%rsp)
movq %rcx, 0x4a8(%rsp)
leaq 0x4b8(%rsp), %rdi
callq 0x98a410
movb %al, 0x498(%rsp)
movq %rdx, 0x4a0(%rsp)
movq 0x4b8(%rsp), %rax
movq %rax, 0x478(%rsp)
movq 0x4c0(%rsp), %rax
movq %rax, 0x480(%rsp)
movq 0x478... | /Target/ARM/ARMISelLowering.cpp |
LowerSTORE(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) | static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) {
StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
EVT MemVT = ST->getMemoryVT();
assert(ST->isUnindexed() && "Stores should be unindexed at this point.");
if (MemVT == MVT::i64 && Subtarget->has... | subq $0x2d8, %rsp # imm = 0x2D8
movq %rdi, 0x2b8(%rsp)
movl %esi, 0x2c0(%rsp)
movq %rdx, 0x2b0(%rsp)
movq %rcx, 0x2a8(%rsp)
leaq 0x2b8(%rsp), %rdi
callq 0x981890
movq %rax, %rdi
callq 0x997b90
movq %rax, 0x2a0(%rsp)
movq 0x2a0(%rsp), %rdi
callq 0x98ac30
movb %al, 0x290(%rsp)
movq %rdx, 0x298(%rsp)
leaq 0x280... | /Target/ARM/ARMISelLowering.cpp |
Expand64BitShift(llvm::SDNode*, llvm::SelectionDAG&, llvm::ARMSubtarget const*) | static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *ST) {
EVT VT = N->getValueType(0);
SDLoc dl(N);
// We can get here for a node like i32 = ISD::SHL i32, i64
if (VT != MVT::i64)
return SDValue();
assert((N->getOpcode() == ISD::SRL || N->getO... | subq $0x588, %rsp # imm = 0x588
movq %rdi, 0x570(%rsp)
movq %rsi, 0x568(%rsp)
movq %rdx, 0x560(%rsp)
movq 0x570(%rsp), %rdi
xorl %esi, %esi
callq 0x97c3d0
movb %al, 0x550(%rsp)
movq %rdx, 0x558(%rsp)
movq 0x570(%rsp), %rsi
leaq 0x540(%rsp), %rdi
callq 0x9817d0
leaq 0x530(%rsp), %rdi
movl $0x8, %esi
callq 0x7... | /Target/ARM/ARMISelLowering.cpp |
PerformInsertEltCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) | static SDValue PerformInsertEltCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
// Bitcast an i64 load inserted into a vector to f64.
// Otherwise, the i64 value will be legalized to a pair of i32 values.
EVT VT = N->getValueType(0);
SDNode *Elt = N->getOperand(1... | subq $0x238, %rsp # imm = 0x238
movq %rdi, 0x220(%rsp)
movq %rsi, 0x218(%rsp)
movq 0x220(%rsp), %rdi
xorl %esi, %esi
callq 0x97c3d0
movb %al, 0x208(%rsp)
movq %rdx, 0x210(%rsp)
movq 0x220(%rsp), %rdi
movl $0x1, %esi
callq 0x981ab0
movq %rax, %rdi
callq 0x981890
movq %rax, 0x200(%rsp)
leaq 0x208(%rsp), %rdi
c... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::isLegalAddressingMode(llvm::DataLayout const&, llvm::TargetLoweringBase::AddrMode const&, llvm::Type*, unsigned int, llvm::Instruction*) const | bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, Type *Ty,
unsigned AS, Instruction *I) const {
EVT VT = getValueType(DL, Ty, true);
if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtar... | subq $0x98, %rsp
movq %rdi, 0x88(%rsp)
movq %rsi, 0x80(%rsp)
movq %rdx, 0x78(%rsp)
movq %rcx, 0x70(%rsp)
movl %r8d, 0x6c(%rsp)
movq %r9, 0x60(%rsp)
movq 0x88(%rsp), %rdi
movq %rdi, 0x10(%rsp)
movq 0x80(%rsp), %rsi
movq 0x70(%rsp), %rdx
movl $0x1, %ecx
callq 0x791230
movb %al, %cl
movq 0x10(%rsp), %rax
movb %cl, 0x50(%r... | /Target/ARM/ARMISelLowering.cpp |
isVUZPMask(llvm::ArrayRef<int>, llvm::EVT, unsigned int&) | static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
unsigned EltSz = VT.getScalarSizeInBits();
if (EltSz == 64)
return false;
unsigned NumElts = VT.getVectorNumElements();
if (M.size() != NumElts && M.size() != NumElts*2)
return false;
for (unsigned i = 0; i < M.size(); i += Num... | subq $0x68, %rsp
movb %dl, %al
movq %rdi, 0x50(%rsp)
movq %rsi, 0x58(%rsp)
movb %al, 0x40(%rsp)
movq %rcx, 0x48(%rsp)
movq %r8, 0x38(%rsp)
leaq 0x40(%rsp), %rdi
callq 0x79e260
movl %eax, 0x34(%rsp)
cmpl $0x40, 0x34(%rsp)
jne 0x13b36bd
movb $0x0, 0x67(%rsp)
jmp 0x13b3823
leaq 0x40(%rsp), %rdi
callq 0x7abb40
movl %eax, 0... | /Target/ARM/ARMISelLowering.cpp |
PerformExtractFpToIntStores(llvm::StoreSDNode*, llvm::SelectionDAG&) | static SDValue PerformExtractFpToIntStores(StoreSDNode *St, SelectionDAG &DAG) {
if (!St->isSimple() || St->isTruncatingStore() || !St->isUnindexed())
return SDValue();
SDValue Extract = St->getValue();
EVT VT = Extract.getValueType();
// For now only uses f16. This may be useful for f32 too, but that will
... | pushq %r14
pushq %rbx
subq $0x248, %rsp # imm = 0x248
movq %rdi, 0x230(%rsp)
movq %rsi, 0x228(%rsp)
movq 0x230(%rsp), %rdi
callq 0xaa0a20
testb $0x1, %al
jne 0x13cd21d
jmp 0x13cd23f
movq 0x230(%rsp), %rdi
callq 0x997ba0
testb $0x1, %al
jne 0x13cd23f
movq 0x230(%rsp), %rdi
callq 0x98b750
testb $0x1, %al
jne 0... | /Target/ARM/ARMISelLowering.cpp |
PerformShuffleVMOVNCombine(llvm::ShuffleVectorSDNode*, llvm::SelectionDAG&) | static SDValue PerformShuffleVMOVNCombine(ShuffleVectorSDNode *N,
SelectionDAG &DAG) {
SDValue Trunc = N->getOperand(0);
EVT VT = Trunc.getValueType();
if (Trunc.getOpcode() != ARMISD::MVETRUNC || !N->getOperand(1).isUndef())
return SDValue();
SDLoc DL(Trunc);
if... | subq $0x308, %rsp # imm = 0x308
movq %rdi, 0x2f0(%rsp)
movq %rsi, 0x2e8(%rsp)
movq 0x2f0(%rsp), %rdi
xorl %esi, %esi
callq 0x981ab0
movq (%rax), %rcx
movq %rcx, 0x2d8(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0x2e0(%rsp)
leaq 0x2d8(%rsp), %rdi
callq 0x98a410
movb %al, 0x2c8(%rsp)
movq %rdx, 0x2d0(%rsp)
leaq 0x2d... | /Target/ARM/ARMISelLowering.cpp |
PerformFADDVCMLACombine(llvm::SDNode*, llvm::SelectionDAG&) | static SDValue PerformFADDVCMLACombine(SDNode *N, SelectionDAG &DAG) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
EVT VT = N->getValueType(0);
SDLoc DL(N);
if (!N->getFlags().hasAllowReassociation())
return SDValue();
// Combine fadd(a, vcmla(b, c, d)) -> vcmla(fadd(a, b), b, c)
... | subq $0xe8, %rsp
movq %rdi, 0xd0(%rsp)
movq %rsi, 0xc8(%rsp)
movq 0xd0(%rsp), %rdi
xorl %esi, %esi
callq 0x981ab0
movq (%rax), %rcx
movq %rcx, 0xb8(%rsp)
movq 0x8(%rax), %rax
movq %rax, 0xc0(%rsp)
movq 0xd0(%rsp), %rdi
movl $0x1, %esi
callq 0x981ab0
movq (%rax), %rcx
movq %rcx, 0xa8(%rsp)
movq 0x8(%rax), %rax
movq %rax... | /Target/ARM/ARMISelLowering.cpp |
llvm::DenseMap<unsigned int, llvm::SmallVector<llvm::MachineBasicBlock*, 2u>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::SmallVector<llvm::MachineBasicBlock*, 2u>>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | subq $0x28, %rsp
movq %rdi, 0x20(%rsp)
movl %esi, 0x1c(%rsp)
movq 0x20(%rsp), %rax
movq %rax, (%rsp)
movl 0x10(%rax), %ecx
movl %ecx, 0x18(%rsp)
movq (%rax), %rax
movq %rax, 0x10(%rsp)
movl $0x40, 0xc(%rsp)
movl 0x1c(%rsp), %eax
subl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x8(%rsp)
leaq 0x... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, bool, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, bool>>, unsigned int, bool, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, bool>>::moveFromOldBuckets(llvm::detail::DenseMapPair<unsigned int, bool>*, ... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdx, 0x40(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x10(%rsp)
callq 0x13dcec0
callq 0x13dcf80
movl %eax, 0x3c(%rsp)
callq 0x13dd120
movl %eax, 0x38(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x30(%rs... | /llvm/ADT/DenseMap.h |
llvm::SmallVector<llvm::ARMLegalizerInfo::FCmpLibcallInfo, 2u> const* llvm::SmallVectorTemplateCommon<llvm::SmallVector<llvm::ARMLegalizerInfo::FCmpLibcallInfo, 2u>, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<llvm::SmallVector<llvm::ARMLegalizerInfo::FCmpLibcallInfo, 2u>, false>>(llvm::SmallV... | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | subq $0x58, %rsp
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq %rdx, 0x38(%rsp)
movq 0x48(%rsp), %rdi
callq 0x3a8dca0
addq 0x38(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x48(%rsp), %rdi
callq 0x3a8dab0
movq %rax, %rcx
movq 0x18(%rsp), %rax
cmpq %rcx, %rax
ja 0x13e5607
movq 0... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::ARMParallelDSP::RecordMemoryOps(llvm::BasicBlock*) | bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) {
SmallVector<LoadInst*, 8> Loads;
SmallVector<Instruction*, 8> Writes;
LoadPairs.clear();
WideLoads.clear();
// Collect loads and instruction that may write to memory. For now we only
// record loads which are simple, sign-extended and have a single use... | subq $0x2d8, %rsp # imm = 0x2D8
movq %rdi, 0x2c8(%rsp)
movq %rsi, 0x2c0(%rsp)
movq 0x2c8(%rsp), %rax
movq %rax, 0x30(%rsp)
leaq 0x270(%rsp), %rdi
callq 0x13e8f90
leaq 0x220(%rsp), %rdi
callq 0xb530c0
movq 0x30(%rsp), %rdi
addq $0x50, %rdi
callq 0x13e8fb0
movq 0x30(%rsp), %rdi
addq $0xc0, %rdi
callq 0x13e8fc0... | /Target/ARM/ARMParallelDSP.cpp |
(anonymous namespace)::Reduction::InsertMuls()::'lambda'(llvm::Value*)::operator()(llvm::Value*) const | void InsertMuls() {
auto GetMulOperand = [](Value *V) -> Instruction* {
if (auto *SExt = dyn_cast<SExtInst>(V)) {
if (auto *I = dyn_cast<Instruction>(SExt->getOperand(0)))
if (I->getOpcode() == Instruction::Mul)
return I;
} else if (auto *I = dyn_cast<Instructio... | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x20(%rsp), %rdi
callq 0xacb2b0
movq %rax, 0x18(%rsp)
cmpq $0x0, 0x18(%rsp)
je 0x13ecca5
movq 0x18(%rsp), %rdi
xorl %esi, %esi
callq 0x78d180
movq %rax, %rdi
callq 0x7d5b40
movq %rax, 0x10(%rsp)
cmpq $0x0, 0x10(%rsp)
je 0x13ecca3
movq 0x10(%rsp), %rdi
ca... | /Target/ARM/ARMParallelDSP.cpp |
(anonymous namespace)::ARMParallelDSP::AreSequentialLoads(llvm::LoadInst*, llvm::LoadInst*, llvm::SmallVectorImpl<llvm::LoadInst*>&) | bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1,
MemInstList &VecMem) {
if (!Ld0 || !Ld1)
return false;
if (!LoadPairs.count(Ld0) || LoadPairs[Ld0] != Ld1)
return false;
LLVM_DEBUG(dbgs() << "Loads are sequential and valid:\n";
dbgs() << "... | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq %rdx, 0x18(%rsp)
movq %rcx, 0x10(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x8(%rsp)
cmpq $0x0, 0x20(%rsp)
je 0x13edd02
cmpq $0x0, 0x18(%rsp)
jne 0x13edd09
movb $0x0, 0x37(%rsp)
jmp 0x13edd77
movq 0x8(%rsp), %rdi
addq $0x50, %rdi
leaq 0x20(%rsp), %rsi
callq... | /Target/ARM/ARMParallelDSP.cpp |
(anonymous namespace)::Reduction::AddMulPair((anonymous namespace)::MulCandidate*, (anonymous namespace)::MulCandidate*, bool) | void AddMulPair(MulCandidate *Mul0, MulCandidate *Mul1,
bool Exchange = false) {
LLVM_DEBUG(dbgs() << "Pairing:\n"
<< *Mul0->Root << "\n"
<< *Mul1->Root << "\n");
Mul0->Paired = true;
Mul1->Paired = true;
if (Exchange)
Mul1->Exchange ... | subq $0x48, %rsp
movb %cl, %al
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
andb $0x1, %al
movb %al, 0x2f(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x10(%rsp)
jmp 0x13eddb7
movq 0x38(%rsp), %rax
movb $0x1, 0x19(%rax)
movq 0x30(%rsp), %rax
movb $0x1, 0x19(%rax)
testb $0x1, 0x2f(%rsp)
je 0x13eddd9
movq ... | /Target/ARM/ARMParallelDSP.cpp |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [33], llvm::cl::OptionHidden, llvm::cl::initializer<bool>, llvm::cl::desc>(char const (&) [33], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x38, %rsp
movq %rdi, 0x30(%rsp)
movq %rsi, 0x28(%rsp)
movq %rdx, 0x20(%rsp)
movq %rcx, 0x18(%rsp)
movq %r8, 0x10(%rsp)
movq 0x30(%rsp), %rdi
movq %rdi, (%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq (%rsp), %rdi
addq $0x80, %rdi
callq 0x3f7700
movq (%rsp), %rsi
leaq 0x82ec616(%rip), %rax # 0x96df18... | /llvm/Support/CommandLine.h |
initializeARMLoadStoreOptPassOnce(llvm::PassRegistry&) | static bool definesCPSR(const MachineInstr &MI) {
for (const auto &MO : MI.operands()) {
if (!MO.isReg())
continue;
if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
// If the instruction has live CPSR def, then it's not safe to fold it
// into load / store.
return true;
}
... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movl $0x50, %edi
callq 0x349070
movq %rax, 0x20(%rsp)
leaq 0x38(%rsp), %rdi
leaq 0x55580a7(%rip), %rsi # 0x694accb
callq 0x3ee9c0
leaq 0x28(%rsp), %rdi
leaq 0x5557db7(%rip), %rsi # 0x694a9ec
callq 0x3ee9c0
movq 0x20(%rsp), %rdi
movq 0x38(%rsp), %rsi
movq 0x40(%rsp), %rdx
movq ... | /Target/ARM/ARMLoadStoreOptimizer.cpp |
getPostIndexedLoadStoreOpcode(unsigned int, llvm::ARM_AM::AddrOpc) | static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc,
ARM_AM::AddrOpc Mode) {
switch (Opc) {
case ARM::LDRi12:
return ARM::LDR_POST_IMM;
case ARM::STRi12:
return ARM::STR_POST_IMM;
case ARM::VLDRS:
return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : AR... | movl %edi, -0x8(%rsp)
movl %esi, -0xc(%rsp)
movl -0x8(%rsp), %eax
movl %eax, -0x10(%rsp)
subl $0x3bf, %eax # imm = 0x3BF
je 0x13f5392
jmp 0x13f51ad
movl -0x10(%rsp), %eax
subl $0x4cb, %eax # imm = 0x4CB
je 0x13f5488
jmp 0x13f51be
movl -0x10(%rsp), %eax
subl $0x4cf, %eax # imm = 0x4CF
je... | /Target/ARM/ARMLoadStoreOptimizer.cpp |
IsSafeAndProfitableToMove(bool, unsigned int, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::SmallPtrSetImpl<llvm::MachineInstr*>&, llvm::SmallSet<unsigned int, 4u, std::less<unsigned int>>&, llvm::TargetRegisterInfo const*, llvm::AAResult... | static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
MachineBasicBlock::iterator I,
MachineBasicBlock::iterator E,
SmallPtrSetImpl<MachineInstr*> &MemOps,
Sm... | subq $0x128, %rsp # imm = 0x128
movb %dil, %al
movq 0x138(%rsp), %rdi
movq 0x130(%rsp), %rdi
movq %rdx, 0x118(%rsp)
movq %rcx, 0x110(%rsp)
andb $0x1, %al
movb %al, 0x10f(%rsp)
movl %esi, 0x108(%rsp)
movq %r8, 0x100(%rsp)
movq %r9, 0xf8(%rsp)
leaq 0xa8(%rsp), %rdi
callq 0xa19200
leaq 0x118(%rsp), %rdi
callq 0... | /Target/ARM/ARMLoadStoreOptimizer.cpp |
llvm::SmallDenseMap<llvm::MachineInstr*, llvm::SmallVector<llvm::Register, 12u>, 8u, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, llvm::SmallVector<llvm::Register, 12u>>>::grow(unsigned int) | void grow(unsigned AtLeast) {
if (AtLeast > InlineBuckets)
AtLeast = std::max<unsigned>(64, NextPowerOf2(AtLeast-1));
if (Small) {
// First move the inline buckets into a temporary storage.
AlignedCharArrayUnion<BucketT[InlineBuckets]> TmpStorage;
BucketT *TmpBegin = reinterpret_cast<Bu... | subq $0x2c8, %rsp # imm = 0x2C8
movq %rdi, 0x2c0(%rsp)
movl %esi, 0x2bc(%rsp)
movq 0x2c0(%rsp), %rax
movq %rax, 0x28(%rsp)
cmpl $0x8, 0x2bc(%rsp)
jbe 0x13fc060
movl $0x40, 0x2b8(%rsp)
movl 0x2bc(%rsp), %eax
subl $0x1, %eax
movl %eax, %eax
movl %eax, %edi
callq 0x5487c0
movl %eax, 0x2b4(%rsp)
leaq 0x2b8(%rsp)... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorImpl<llvm::MachineInstr*>::erase(llvm::MachineInstr* const*, llvm::MachineInstr* const*) | iterator erase(const_iterator CS, const_iterator CE) {
// Just cast away constness because this is a non-const member function.
iterator S = const_cast<iterator>(CS);
iterator E = const_cast<iterator>(CE);
assert(this->isRangeInStorage(S, E) && "Range to erase is out of bounds.");
iterator N = S;
... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdx, 0x40(%rsp)
movq 0x50(%rsp), %rdi
movq %rdi, 0x18(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0x40(%rsp), %rax
movq %rax, 0x30(%rsp)
movq 0x38(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x30(%rsp), %rax
movq %rax, (%rsp)
callq 0x7f0490
movq (... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::ARMLoadStoreOpt::CombineMovBx(llvm::MachineBasicBlock&) | bool ARMLoadStoreOpt::CombineMovBx(MachineBasicBlock &MBB) {
MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
if (MBBI == MBB.begin() || MBBI == MBB.end() ||
MBBI->getOpcode() != ARM::tBX_RET)
return false;
MachineBasicBlock::iterator Prev = MBBI;
--Prev;
if (Prev->getOpcode() != ARM::t... | subq $0x168, %rsp # imm = 0x168
movq %rdi, 0x158(%rsp)
movq %rsi, 0x150(%rsp)
movq 0x158(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x150(%rsp), %rdi
callq 0x33700d0
movq %rax, 0x148(%rsp)
movq 0x150(%rsp), %rdi
callq 0x73fe80
movq %rax, 0x140(%rsp)
leaq 0x148(%rsp), %rdi
leaq 0x140(%rsp), %rsi
callq 0x745400
mo... | /Target/ARM/ARMLoadStoreOptimizer.cpp |
initializeARMLowOverheadLoopsPassOnce(llvm::PassRegistry&) | static bool TryRemove(MachineInstr *MI, ReachingDefAnalysis &RDA,
InstSet &ToRemove, InstSet &Ignore) {
// Check that we can remove all of Killed without having to modify any IT
// blocks.
auto WontCorruptITs = [](InstSet &Killed, ReachingDefAnalysis &RDA) {
// Collect the dead code and... | subq $0x58, %rsp
movq %rdi, 0x50(%rsp)
movl $0x50, %edi
callq 0x349070
movq %rax, 0x20(%rsp)
leaq 0x38(%rsp), %rdi
leaq 0x553f81a(%rip), %rsi # 0x694aeae
callq 0x3ee9c0
leaq 0x28(%rsp), %rdi
leaq 0x553f825(%rip), %rsi # 0x694aeca
callq 0x3ee9c0
movq 0x20(%rsp), %rdi
movq 0x38(%rsp), %rsi
movq 0x40(%rsp), %rdx
movq ... | /Target/ARM/ARMLowOverheadLoops.cpp |
(anonymous namespace)::ARMLowOverheadLoops::ARMLowOverheadLoops() | ARMLowOverheadLoops() : MachineFunctionPass(ID) { } | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, 0x8(%rsp)
leaq 0x8358052(%rip), %rsi # 0x97637ac
callq 0x7ec2f0
movq 0x8(%rsp), %rdi
leaq 0x81e286d(%rip), %rax # 0x95edfd8
addq $0x10, %rax
movq %rax, (%rdi)
movq $0x0, 0x38(%rdi)
movq $0x0, 0x40(%rdi)
movq $0x0, 0x48(%rdi)
movq $0x0, 0x50(%rd... | /Target/ARM/ARMLowOverheadLoops.cpp |
(anonymous namespace)::ARMLowOverheadLoops::runOnMachineFunction(llvm::MachineFunction&) | bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
const ARMSubtarget &ST = mf.getSubtarget<ARMSubtarget>();
if (!ST.hasLOB())
return false;
MF = &mf;
LLVM_DEBUG(dbgs() << "ARM Loops on " << MF->getName() << " ------------- \n");
MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI(... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x50(%rsp), %rdi
callq 0x11b6920
movq %rax, 0x48(%rsp)
movq 0x48(%rsp), %rdi
callq 0x122b580
testb $0x1, %al
jne 0x140b90f
movb $0x0, 0x67(%rsp)
jmp 0x140baf2
movq 0x10(%rsp), %rax
movq 0x50(%rsp), %rcx
movq %r... | /Target/ARM/ARMLowOverheadLoops.cpp |
auto llvm::enumerate<llvm::iterator_range<std::reverse_iterator<llvm::MCOperandInfo const*>>>(llvm::iterator_range<std::reverse_iterator<llvm::MCOperandInfo const*>>&&) | auto enumerate(FirstRange &&First, RestRanges &&...Rest) {
if constexpr (sizeof...(Rest) != 0) {
#ifndef NDEBUG
// Note: Create an array instead of an initializer list to work around an
// Apple clang 14 compiler bug.
size_t sizes[] = {range_size(First), range_size(Rest)...};
assert(all_equal(sizes) &... | subq $0x28, %rsp
movq %rdi, %rax
movq %rax, 0x8(%rsp)
movq %rdi, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
movq 0x18(%rsp), %rdx
leaq 0x17(%rsp), %rsi
callq 0x140eb20
movq 0x8(%rsp), %rax
addq $0x28, %rsp
retq
nop
| /llvm/ADT/STLExtras.h |
llvm::VCTPOpcodeToLSTP(unsigned int, bool) | static inline unsigned VCTPOpcodeToLSTP(unsigned Opcode, bool IsDoLoop) {
switch (Opcode) {
default:
llvm_unreachable("unhandled vctp opcode");
break;
case ARM::MVE_VCTP8:
return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8;
case ARM::MVE_VCTP16:
return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_... | movb %sil, %al
movl %edi, -0x8(%rsp)
andb $0x1, %al
movb %al, -0x9(%rsp)
movl -0x8(%rsp), %eax
addl $0xfffffbb4, %eax # imm = 0xFFFFFBB4
movq %rax, -0x18(%rsp)
movq -0x18(%rsp), %rax
leaq 0x5531e99(%rip), %rcx # 0x694ad90
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movb -0x9(%rsp), %dl
movl $0x722, %e... | /Target/ARM/MVETailPredUtils.h |
llvm::DenseMap<llvm::MachineBasicBlock const*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, unsigned int>>::copyFrom(llvm::DenseMap<llvm::MachineBasicBlock const*, unsigned int, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>... | void copyFrom(const DenseMap& other) {
this->destroyAll();
deallocate_buffer(Buckets, sizeof(BucketT) * NumBuckets, alignof(BucketT));
if (allocateBuckets(other.NumBuckets)) {
this->BaseT::copyFrom(other);
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | subq $0x18, %rsp
movq %rdi, 0x10(%rsp)
movq %rsi, 0x8(%rsp)
movq 0x10(%rsp), %rdi
movq %rdi, (%rsp)
callq 0x141c130
movq (%rsp), %rax
movq (%rax), %rdi
movl 0x10(%rax), %eax
movl %eax, %esi
shlq $0x4, %rsi
movl $0x8, %edx
callq 0x3a79dc0
movq (%rsp), %rdi
movq 0x8(%rsp), %rax
movl 0x10(%rax), %esi
callq 0x11cdaa0
testb... | /llvm/ADT/DenseMap.h |
llvm::isAESPair(llvm::MachineInstr const*, llvm::MachineInstr const&) | static bool isAESPair(const MachineInstr *FirstMI,
const MachineInstr &SecondMI) {
// Assume the 1st instr to be a wildcard if it is unspecified.
switch(SecondMI.getOpcode()) {
// AES encode.
case ARM::AESMC :
return FirstMI == nullptr || FirstMI->getOpcode() == ARM::AESE;
// AES dec... | subq $0x28, %rsp
movq %rdi, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq 0x10(%rsp), %rdi
callq 0x72bbb0
movl %eax, %ecx
movl %ecx, 0xc(%rsp)
subl $0x314, %eax # imm = 0x314
je 0x141c844
jmp 0x141c807
movl 0xc(%rsp), %eax
subl $0x315, %eax # imm = 0x315
jne 0x141c874
jmp 0x141c814
movb $0x1, %al
cmpq $0x... | /Target/ARM/ARMMacroFusion.cpp |
llvm::cl::opt<llvm::TPLoop::MemTransfer, false, llvm::cl::parser<llvm::TPLoop::MemTransfer>>::opt<char [23], llvm::cl::OptionHidden, llvm::cl::desc, llvm::cl::initializer<llvm::TPLoop::MemTransfer>, llvm::cl::ValuesClass>(char const (&) [23], llvm::cl::OptionHidden const&, llvm::cl::desc const&, llvm::cl::initializer<l... | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | subq $0x48, %rsp
movq %rdi, 0x40(%rsp)
movq %rsi, 0x38(%rsp)
movq %rdx, 0x30(%rsp)
movq %rcx, 0x28(%rsp)
movq %r8, 0x20(%rsp)
movq %r9, 0x18(%rsp)
movq 0x40(%rsp), %rdi
movq %rdi, 0x8(%rsp)
xorl %edx, %edx
movl %edx, %esi
callq 0x3f6a60
movq 0x8(%rsp), %rdi
addq $0x80, %rdi
callq 0x14222d0
movq 0x8(%rsp), %rsi
leaq 0x8... | /llvm/Support/CommandLine.h |
llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(llvm::SelectionDAG&, llvm::SDLoc const&, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::Align, bool, bool, llvm::MachinePointerInfo, llvm::MachinePointerInfo) const | SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
const ARMSubtarget &Subtarget =
... | pushq %rbx
subq $0x8a0, %rsp # imm = 0x8A0
movl %r9d, %eax
movl %r8d, %r9d
movq %rcx, %r10
movb %al, %r8b
leaq 0x908(%rsp), %rax
movq %rax, 0x1b0(%rsp)
leaq 0x8f0(%rsp), %rax
movq %rax, 0x1b8(%rsp)
movb 0x8e8(%rsp), %al
movb 0x8e0(%rsp), %cl
leaq 0x8d0(%rsp), %r11
movq %r11, 0x1d8(%rsp)
leaq 0x8c0(%rsp), %r1... | /Target/ARM/ARMSelectionDAGInfo.cpp |
shouldGenerateInlineTPLoop(llvm::ARMSubtarget const&, llvm::SelectionDAG const&, llvm::ConstantSDNode*, llvm::Align, bool) | static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget,
const SelectionDAG &DAG,
ConstantSDNode *ConstantSize,
Align Alignment, bool IsMemcpy) {
auto &F = DAG.getMachineFunction().getFunc... | subq $0x48, %rsp
movb %r8b, %al
movb %cl, 0x46(%rsp)
movq %rdi, 0x38(%rsp)
movq %rsi, 0x30(%rsp)
movq %rdx, 0x28(%rsp)
andb $0x1, %al
movb %al, 0x27(%rsp)
movq 0x30(%rsp), %rdi
callq 0x985ce0
movq %rax, %rdi
callq 0x727890
movq %rax, 0x18(%rsp)
leaq 0x8342962(%rip), %rdi # 0x97637d0
addq $0x80, %rdi
callq 0x1422290
c... | /Target/ARM/ARMSelectionDAGInfo.cpp |
(anonymous namespace)::ARMFastISel::fastSelectInstruction(llvm::Instruction const*) | bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
switch (I->getOpcode()) {
case Instruction::Load:
return SelectLoad(I);
case Instruction::Store:
return SelectStore(I);
case Instruction::Br:
return SelectBranch(I);
case Instruction::IndirectBr:
return SelectIndir... | subq $0x38, %rsp
movq %rdi, 0x28(%rsp)
movq %rsi, 0x20(%rsp)
movq 0x28(%rsp), %rax
movq %rax, 0x8(%rsp)
movq 0x20(%rsp), %rdi
callq 0x785480
decl %eax
movl %eax, %ecx
movq %rcx, 0x10(%rsp)
subl $0x38, %eax
ja 0x142f10a
movq 0x10(%rsp), %rax
leaq 0x551ce08(%rip), %rcx # 0x694bba8
movslq (%rcx,%rax,4), %rax
addq %rcx, ... | /Target/ARM/ARMFastISel.cpp |
(anonymous namespace)::ARMFastISel::fastMaterializeAlloca(llvm::AllocaInst const*) | unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
// Don't handle dynamic allocas.
if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
MVT VT;
if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
DenseMap<const AllocaInst*, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
// This... | subq $0x98, %rsp
movq %rdi, 0x88(%rsp)
movq %rsi, 0x80(%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0x20(%rax), %rdi
addq $0xb0, %rdi
movq 0x80(%rsp), %rsi
callq 0xb8e550
cmpl $0x0, %eax
jne 0x1432411
movl $0x0, 0x94(%rsp)
jmp 0x143260c
leaq 0x7f(%rsp), %rdi
callq 0xa1fa70
movq 0x80(%rsp), %rdi
callq 0xb52ad0... | /Target/ARM/ARMFastISel.cpp |
(anonymous namespace)::ARMFastISel::SelectFPExt(llvm::Instruction const*) | bool ARMFastISel::SelectFPExt(const Instruction *I) {
// Make sure we have VFP and that we're extending float to double.
if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false;
Value *V = I->getOperand(0);
if (!I->getType()->isDoubleTy() ||
!V->getType()->isFloatTy()) return false;
Regis... | subq $0x68, %rsp
movq %rdi, 0x58(%rsp)
movq %rsi, 0x50(%rsp)
movq 0x58(%rsp), %rax
movq %rax, 0x10(%rsp)
movq 0xb0(%rax), %rdi
callq 0x11b9970
testb $0x1, %al
jne 0x14357ba
jmp 0x14357cf
movq 0x10(%rsp), %rax
movq 0xb0(%rax), %rdi
callq 0x12259f0
testb $0x1, %al
jne 0x14357d9
movb $0x0, 0x67(%rsp)
jmp 0x1435926
movq 0x... | /Target/ARM/ARMFastISel.cpp |
(anonymous namespace)::ARMFastISel::ARMMoveToFPReg(llvm::MVT, unsigned int) | unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
if (VT == MVT::f64) return 0;
Register MoveReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(ARM::VMOVSR), MoveReg)
.addReg(SrcReg));
... | subq $0x58, %rsp
movb %sil, %al
movb %al, 0x53(%rsp)
movq %rdi, 0x48(%rsp)
movl %edx, 0x44(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x10(%rsp)
leaq 0x43(%rsp), %rdi
movl $0xd, %esi
callq 0x5345c0
leaq 0x53(%rsp), %rdi
leaq 0x43(%rsp), %rsi
callq 0x534c90
testb $0x1, %al
jne 0x143ba52
jmp 0x143ba5f
movl $0x0, 0x54(%rsp)
j... | /Target/ARM/ARMFastISel.cpp |
(anonymous namespace)::ARMFastISel::ARMMaterializeGV(llvm::GlobalValue const*, llvm::MVT) | unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
// For now 32-bit only.
if (VT != MVT::i32 || GV->isThreadLocal()) return 0;
// ROPI/RWPI not currently supported.
if (Subtarget->isROPI() || Subtarget->isRWPI())
return 0;
bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
cons... | subq $0x1f8, %rsp # imm = 0x1F8
movb %dl, %al
movb %al, 0x1f3(%rsp)
movq %rdi, 0x1e8(%rsp)
movq %rsi, 0x1e0(%rsp)
movq 0x1e8(%rsp), %rax
movq %rax, 0x78(%rsp)
leaq 0x1df(%rsp), %rdi
movl $0x7, %esi
callq 0x5345c0
leaq 0x1f3(%rsp), %rdi
leaq 0x1df(%rsp), %rsi
callq 0x7ad500
movb %al, %cl
movb $0x1, %al
testb ... | /Target/ARM/ARMFastISel.cpp |
(anonymous namespace)::ARMFastISel::ARMMaterializeFP(llvm::ConstantFP const*, llvm::MVT) | unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
const APFloat Val = CFP->getValueAPF();
bool is64bit = VT == MVT::f64;
// This checks to see if we can use VFP3 instructions to materialize
// a constant, otherwise we have to go through the constant pool.
if (TLI.isFPImmLegal(Val, VT)) ... | subq $0x108, %rsp # imm = 0x108
movb %dl, %al
movb %al, 0x103(%rsp)
movq %rdi, 0xf8(%rsp)
movq %rsi, 0xf0(%rsp)
movq 0xf8(%rsp), %rax
movq %rax, 0x38(%rsp)
movq 0xf0(%rsp), %rdi
callq 0x8207f0
movq %rax, %rsi
leaq 0xd0(%rsp), %rdi
callq 0x42e360
leaq 0xce(%rsp), %rdi
movl $0xd, %esi
callq 0x5345c0
leaq 0x103... | /Target/ARM/ARMFastISel.cpp |
bool (anonymous namespace)::AVRExpandPseudo::expand<379u>(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) | bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
Register DstReg = MI.getOperand(0).getReg();
bool DstIsKill = MI.getOperand(0).isKill();
unsigned Imm = MI.getOperand(1).getImm();
Reg... | subq $0x1e8, %rsp # imm = 0x1E8
movq %rdx, 0x1e0(%rsp)
movq %rdi, 0x1d8(%rsp)
movq %rsi, 0x1d0(%rsp)
movq 0x1d8(%rsp), %rax
movq %rax, 0x58(%rsp)
leaq 0x1e0(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x1c8(%rsp)
movq 0x1d0(%rsp), %rdi
callq 0x73fb50
movq %rax, %rdi
callq 0x1465ed0
movq %rax, 0x1c0(%rsp)
movq 0x1c... | /Target/AVR/AVRExpandPseudoInsts.cpp |
bool (anonymous namespace)::AVRExpandPseudo::expand<380u>(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) | bool AVRExpandPseudo::expand<AVR::STDWSPQRr>(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
const MachineFunction &MF = *MBB.getParent();
const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
assert(MI.getOperand(0).getReg() == AVR::SP &&
"SP is expected as base pointer");
assert(STI.ge... | subq $0x58, %rsp
movq %rdx, 0x50(%rsp)
movq %rdi, 0x48(%rsp)
movq %rsi, 0x40(%rsp)
movq 0x48(%rsp), %rax
movq %rax, 0x8(%rsp)
leaq 0x50(%rsp), %rdi
callq 0x7410f0
movq %rax, 0x38(%rsp)
movq 0x40(%rsp), %rdi
callq 0x73fb50
movq %rax, 0x30(%rsp)
movq 0x30(%rsp), %rdi
callq 0x1465ed0
movq %rax, %rcx
movq 0x8(%rsp), %rax
m... | /Target/AVR/AVRExpandPseudoInsts.cpp |
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