name string | code string | asm string | file string |
|---|---|---|---|
llvm::ThumbRegisterInfo::resolveFrameIndex(llvm::MachineInstr&, llvm::Register, long) const | void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
int64_t Offset) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
if (!STI.isThumb1Only())
return ARMBaseRegisterIn... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r12
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
movq 0x18(%rsi), %rax
movq 0x20(%rax), %rax
movq 0x10(%rax), %rdi
cmpb $0x1, 0x192(%rdi)
jne 0xd2bd24
testb $0x1, 0x161(%rdi)
jne 0xd2bd24
movq (%rdi), %rax
callq *0x80(%rax)
movl %r12d, 0x4(%rsp)
movq... | /Target/ARM/ThumbRegisterInfo.cpp |
llvm::Thumb2InstrInfo::expandLoadStackGuard(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | void Thumb2InstrInfo::expandLoadStackGuard(
MachineBasicBlock::iterator MI) const {
MachineFunction &MF = *MI->getParent()->getParent();
Module &M = *MF.getFunction().getParent();
if (M.getStackProtectorGuard() == "tls") {
expandLoadStackGuardBase(MI, ARM::t2MRC, ARM::t2LDRi12);
return;
}
const ... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
movq 0x18(%rsi), %rax
movq 0x20(%rax), %r15
movq (%r15), %rax
movq 0x28(%rax), %rdi
callq 0x1a743ea
cmpq $0x3, %rdx
jne 0xd2e0f8
leaq 0x41928f0(%rip), %rsi # 0x4ec09dc
movq %rax, %rdi
callq 0x751d10
testl %eax, %eax
je 0xd2e158
movq 0x30(%rbx), %rax
tes... | /Target/ARM/Thumb2InstrInfo.cpp |
(anonymous namespace)::A15SDOptimizer::runOnMachineFunction(llvm::MachineFunction&) | bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
if (skipFunction(Fn.getFunction()))
return false;
const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
// Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
// enabled when NEON is available.
if (!(STI.useSplat... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x188, %rsp # imm = 0x188
movq %rsi, %r15
movq %rdi, %rbx
movq (%rsi), %rsi
callq 0x1a7c502
testb %al, %al
jne 0xd33577
movq 0x10(%r15), %r14
cmpb $0x1, 0x1a4(%r14)
jne 0xd33577
cmpb $0x1, 0x155(%r14)
jne 0xd33577
movq (%r14), %rax
movq ... | /Target/ARM/A15SDOptimizer.cpp |
(anonymous namespace)::A15SDOptimizer::elideCopies(llvm::MachineInstr*) | MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
if (!MI->isFullCopy())
return MI;
if (!MI->getOperand(1).getReg().isVirtual())
return nullptr;
MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
if (!Def)
return nullptr;
return elideCopies(Def);
} | pushq %rbx
movq %rsi, %rax
movq %rdi, %rbx
cmpw $0x13, 0x44(%rax)
jne 0xd33e53
movq 0x20(%rax), %rcx
movzwl 0x1(%rcx), %edx
testl $0xfff, %edx # imm = 0xFFF
jne 0xd33e53
movzwl 0x21(%rcx), %ecx
testl $0xfff, %ecx # imm = 0xFFF
jne 0xd33e53
movq 0x20(%rax), %rax
movl 0x24(%rax), %esi
testl %esi, %e... | /Target/ARM/A15SDOptimizer.cpp |
llvm::ARMBaseInstrInfo::SubsumesPredicate(llvm::ArrayRef<llvm::MachineOperand>, llvm::ArrayRef<llvm::MachineOperand>) const | bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
ArrayRef<MachineOperand> Pred2) const {
if (Pred1.size() > 2 || Pred2.size() > 2)
return false;
ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
ARMCC::CondCodes CC2 = (ARMCC::CondCode... | cmpq $0x3, %rdx
setae %al
cmpq $0x3, %r8
setae %dl
orb %al, %dl
je 0xd3728f
xorl %eax, %eax
retq
movl 0x10(%rsi), %edx
movl 0x10(%rcx), %ecx
movb $0x1, %al
cmpl %ecx, %edx
je 0xd3728e
xorl %eax, %eax
leal -0x9(%rdx), %esi
cmpl $0x5, %esi
ja 0xd372c3
leaq 0x2a71dc4(%rip), %rdx # 0x37a9070
movslq (%rdx,%rsi,4), %rsi
ad... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::addUnpredicatedMveVpredNOp(llvm::MachineInstrBuilder&) | void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB) {
MIB.addImm(ARMVCC::None);
MIB.addReg(0);
MIB.addReg(0); // tp_reg
} | pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rdi, %rbx
movq (%rdi), %rsi
movq 0x8(%rdi), %rdi
movl $0xfff00000, %eax # imm = 0xFFF00000
movq %rsp, %r14
andl (%r14), %eax
incl %eax
movl %eax, (%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x8(%r14)
movq %r14, %rdx
callq 0x1791f06
movq (%rbx), %rsi
movq 0x8(%rbx), %rdi
xo... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::isCopyInstrImpl(llvm::MachineInstr const&) const | std::optional<DestSourcePair>
ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
// VMOVRRD is also a copy instruction but it requires
// special way of handling. It is more complex copy version
// and since that we are not considering it. For recognition
// of such instruction isExtractSubregLik... | movq %rdi, %rax
movq 0x10(%rdx), %rcx
testb $0x40, 0x11(%rcx)
jne 0xd38cf7
xorl %ecx, %ecx
jmp 0xd38d1c
cmpw $0xc2d, 0x44(%rdx) # imm = 0xC2D
jne 0xd38d0b
movq 0x20(%rdx), %rcx
movl 0x24(%rcx), %esi
cmpl 0x44(%rcx), %esi
jne 0xd38cf3
movq 0x20(%rdx), %rcx
movq %rcx, (%rax)
addq $0x20, %rcx
movq %rcx, 0x8(%rax)
mov... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::isStoreToStackSlotPostFE(llvm::MachineInstr const&, int&) const | Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
SmallVector<const MachineMemOperand *, 1> Accesses;
if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses) &&
Accesses.size() == 1) {
FrameIndex =
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x18(%rsp), %r12
movq %r12, -0x10(%r12)
movabsq $0x100000000, %rax # imm = 0x100000000
movq %rax, -0x8(%r12)
movq %rsi, %rdi
movl $0x1, %esi
callq 0x8e0a86
xorl %ebp, %ebp
testb %al, %al
je ... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::tryFoldSPUpdateIntoPushPop(llvm::ARMSubtarget const&, llvm::MachineFunction&, llvm::MachineInstr*, unsigned int) | bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
MachineFunction &MF, MachineInstr *MI,
unsigned NumBytes) {
// This optimisation potentially adds lots of load and store
// micro-operations, it's only really a great bene... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
cmpb $0x1, 0x1f8(%rdi)
jne 0xd3e89f
movl %ecx, %r8d
movq %rdx, %rbx
movzwl 0x44(%rdx), %eax
movb $0x1, %dl
cmpl $0x396, %eax # imm = 0x396
jle 0xd3e80c
cmpl $0x100c, %eax # imm = 0x100C
jg 0xd3e823
cmpl $0x397, %eax ... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARM_AM::isT2SOImmTwoPartVal(unsigned int) | inline int getT2SOImmValSplatVal(unsigned V) {
unsigned u, Vs, Imm;
// control = 0
if ((V & 0xffffff00) == 0)
return V;
// If the value is zeroes in the first byte, just shift those off
Vs = ((V & 0xff) == 0) ? V >> 8 : V;
// Any passing value only has 8 bits of payload, splatted across t... | cmpl $0x100, %edi # imm = 0x100
jae 0xd4059a
xorl %eax, %eax
retq
movl %edi, %ecx
shrl $0x8, %ecx
testb %dil, %dil
cmovnel %edi, %ecx
movzbl %cl, %edx
movl %edx, %esi
shll $0x10, %esi
orl %edx, %esi
xorl %eax, %eax
cmpl %esi, %ecx
je 0xd40599
imull $0x1010101, %edx, %edx # imm = 0x1010101
cmpl %edx, %ecx
je... | /Target/ARM/MCTargetDesc/ARMAddressingModes.h |
llvm::ARMBaseInstrInfo::getLDMDefCycle(llvm::InstrItineraryData const*, llvm::MCInstrDesc const&, unsigned int, unsigned int, unsigned int) const | unsigned getNumOperands() const { return NumOperands; } | movzwl 0x2(%rdx), %eax
movl %r8d, %edx
subl %eax, %edx
leal 0x1(%rdx), %eax
cmpl $0x7fffffff, %eax # imm = 0x7FFFFFFF
jb 0xd41074
movq 0x60(%rsi), %rdx
testq %rdx, %rdx
je 0xd410b7
movl %ecx, %eax
leaq (%rax,%rax,4), %rcx
movzwl 0x6(%rdx,%rcx,2), %eax
movzwl 0x8(%rdx,%rcx,2), %ecx
addl %r8d, %eax
cmpl %ecx, %eax
... | /llvm/MC/MCInstrDesc.h |
llvm::ARMBaseInstrInfo::getVSTMUseCycle(llvm::InstrItineraryData const*, llvm::MCInstrDesc const&, unsigned int, unsigned int, unsigned int) const | unsigned getNumOperands() const { return NumOperands; } | movzwl 0x2(%rdx), %r10d
movl %r8d, %eax
subl %r10d, %eax
leal 0x1(%rax), %r10d
cmpl $0x7fffffff, %r10d # imm = 0x7FFFFFFF
jb 0xd41148
movq 0x60(%rsi), %rdx
testq %rdx, %rdx
je 0xd4118c
movl %ecx, %eax
leaq (%rax,%rax,4), %rcx
movzwl 0x6(%rdx,%rcx,2), %eax
movzwl 0x8(%rdx,%rcx,2), %ecx
addl %r8d, %eax
cmpl %ecx, %e... | /llvm/MC/MCInstrDesc.h |
getCorrespondingDRegAndLane(llvm::TargetRegisterInfo const*, unsigned int, unsigned int&) | static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
unsigned SReg, unsigned &Lane) {
unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
Lane = 0;
if (DReg != ARM::NoRegister)
return DReg;
Lane = 1;
DReg = TRI-... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movl %esi, %ebx
movq %rdi, %r14
addq $0x8, %r14
leaq 0x49dc630(%rip), %r12 # 0x5720850
movq (%r12), %rcx
movq %r14, %rdi
movl $0x11, %edx
callq 0x1b0147e
movl $0x0, (%r15)
testl %eax, %eax
je 0xd44248
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(llvm::MachineInstr const&, unsigned int, llvm::TargetRegisterInfo const*) const | unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
const MachineInstr &MI, unsigned OpNum,
const TargetRegisterInfo *TRI) const {
auto PartialUpdateClearance = Subtarget.getPartialUpdateClearance();
if (!PartialUpdateClearance)
return 0;
assert(TRI && "Need TRI instance");
const MachineOpera... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq 0x50(%rdi), %rax
movl 0x1e4(%rax), %ebp
xorl %ebx, %ebx
testl %ebp, %ebp
je 0xd444a2
movq %rcx, %r15
movq %rsi, %r14
movq 0x20(%rsi), %r13
movl %edx, %eax
shlq $0x5, %rax
movl (%r13,%rax), %ecx
testl $0x30000000, %ecx # imm = 0x3000... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::breakPartialRegDependency(llvm::MachineInstr&, unsigned int, llvm::TargetRegisterInfo const*) const | void ARMBaseInstrInfo::breakPartialRegDependency(
MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
assert(TRI && "Need TRI instance");
const MachineOperand &MO = MI.getOperand(OpNum);
Register Reg = MO.getReg();
as... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rcx, 0x30(%rsp)
movq %rsi, %r14
movq %rdi, %r12
movq 0x20(%rsi), %rax
movl %edx, %ecx
shlq $0x5, %rcx
movl 0x4(%rax,%rcx), %ebx
leal -0x1(%rbx), %eax
cmpl $0x3ffffffe, %eax # imm = 0x3FFFFFFE
ja 0xd44516
leaq 0x49dab1c(%rip),... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::getOutliningCandidateInfo(std::vector<llvm::outliner::Candidate, std::allocator<llvm::outliner::Candidate>>&) const | std::optional<outliner::OutlinedFunction>
ARMBaseInstrInfo::getOutliningCandidateInfo(
std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
unsigned SequenceSize = 0;
for (auto &MI : RepeatedSequenceLocs[0])
SequenceSize += getInstSizeInBytes(MI);
// Properties about candidate MBBs that hold f... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq (%rdx), %rdi
movq 0x8(%rdi), %rbx
callq 0xa44038
cmpq %rax, %rbx
je 0xd45071
movq %rax, %r14
xorl %ebp, %ebp
movq (%r12), %rax
movq %r12, %rdi
movq %rbx, %rsi
callq *0x98(%rax)
testq %... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::emitCFIForLRSaveToReg(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register) const | void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator It,
Register Reg) const {
MachineFunction &MF = *MBB.getParent();
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
unsi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movl %ecx, %ebp
movq %rdx, 0x8(%rsp)
movq %rsi, %r14
movq %rdi, %r15
movq 0x20(%rsi), %r12
movq 0x50(%rdi), %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
leaq 0x8(%rax), %r13
testq %rax, %rax
cmoveq %rax, %r13
movq %r13, %rdi
movl $0xd, %esi
... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMBaseInstrInfo::isReallyTriviallyReMaterializable(llvm::MachineInstr const&) const | bool ARMBaseInstrInfo::isReallyTriviallyReMaterializable(
const MachineInstr &MI) const {
// Try hard to rematerialize any VCTPs because if we spill P0, it will block
// the tail predication conversion. This means that the element count
// register has to be live for longer, but that has to be better than
/... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movzwl 0x44(%rsi), %eax
andl $-0x4, %eax
cmpl $0x44c, %eax # imm = 0x44C
jne 0xd47dff
movq (%r14), %rax
movq %r14, %rdi
movq %rbx, %rsi
callq *0x340(%rax)
testb %al, %al
je 0xd47e11
movq %r14, %rdi
movq %rbx, %rsi
addq $0x8, %rsp
popq %rbx
popq... | /Target/ARM/ARMBaseInstrInfo.cpp |
llvm::ARMCallLowering::lowerReturn(llvm::MachineIRBuilder&, llvm::Value const*, llvm::ArrayRef<llvm::Register>, llvm::FunctionLoweringInfo&) const | bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val, ArrayRef<Register> VRegs,
FunctionLoweringInfo &FLI) const {
assert(!Val == VRegs.empty() && "Return value without a vreg");
auto const &ST = MIRBuilder.getMF().getS... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %r8, 0x10(%rsp)
movq %rcx, 0x8(%rsp)
movq %rdx, %r12
movq %rsi, %rbx
movq 0x8(%rsi), %rax
movq 0x10(%rax), %rax
testb $0x1, 0x163(%rax)
movl $0x32f, %ecx # imm = 0x32F
movl $0x3c7, %edx # imm = 0x3C7
cmovnel %e... | /Target/ARM/ARMCallLowering.cpp |
(anonymous namespace)::ARMIncomingValueHandler::buildLoad(llvm::DstOp const&, llvm::Register, llvm::LLT, llvm::MachinePointerInfo const&) | MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, LLT MemTy,
const MachinePointerInfo &MPO) {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtr... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rcx, %r15
movl %edx, %ebp
movq %rsi, 0x38(%rsp)
movq %rdi, %r14
movq 0x8(%rdi), %rax
movq 0x8(%rax), %r12
movq 0x10(%r8), %rax
movq %rax, 0x50(%rsp)
movups (%r8), %xmm0
movaps %xmm0, 0x40(%rsp)
movq %r12, %rdi
movq %r8, %rsi
callq ... | /Target/ARM/ARMCallLowering.cpp |
llvm::DenseMapBase<llvm::DenseMap<int, int, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, int>>, int, int, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, int>>::clear() | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %eax
testl %eax, %eax
jne 0xd52591
cmpl $0x0, 0xc(%rdi)
je 0xd526c5
shll $0x2, %eax
movl 0x10(%rdi), %ecx
cmpl %ecx, %eax
setae %al
cmpl $0x41, %ecx
setb %dl
orb %al, %dl
je 0xd540dc
testq %rcx, %rcx
je 0xd526bd
movq (%rdi), %rax
movabsq $0x1fffffffffffffff, %rdx # imm = 0x1FFFFFFFFFFFFFFF
addq %rdx, %r... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineBasicBlock const*, int, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, int>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<int, int, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, int>>, int, int, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, int>>::LookupBucketFor<int>(int const&, llvm::detail::DenseMapPair<int, int> const*&) const | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xd53082
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %esi
leal (%rsi,%rsi,8), %eax
leal (%rsi,%rax,4), %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
leaq (%rdi,%r11,8), %r11
movl (%r11), %ebx
cmpl %ebx, %esi
jne 0xd5304b
movq %r11, (%rdx)
movb $... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<int, int, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, int>>, int, int, llvm::DenseMapInfo<int, void>, llvm::detail::DenseMapPair<int, int>>::FindAndConstruct(int&&) | value_type& FindAndConstruct(KeyT &&Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, std::move(Key));
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0xd5300c
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0xd53763
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0xd5308e
movl (%rbx), %ecx
movl %ecx, (%rax)
movl $0x0... | /llvm/ADT/DenseMap.h |
llvm::cl::opt<int, false, llvm::cl::parser<int>>::opt<char [19], llvm::cl::initializer<int>, llvm::cl::OptionHidden>(char const (&) [19], llvm::cl::initializer<int> const&, llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movl $0x0, 0x80(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%rbx)
movb $0x0, 0x94(%rbx)
leaq 0x498d8dd(%rip), %rax # 0x56f2650
movq %rax, 0x88(%rbx)
lea... | /llvm/Support/CommandLine.h |
(anonymous namespace)::ARMDAGToDAGISel::SelectRegShifterOperand(llvm::SDValue, llvm::SDValue&, llvm::SDValue&, llvm::SDValue&, bool) | bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
SDValue &BaseReg,
SDValue &ShReg,
SDValue &Opc,
bool CheckProfitability) {
if... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x30, %rsp
movq %rsi, 0x20(%rsp)
movl %edx, 0x28(%rsp)
xorl %ebp, %ebp
cmpb $0x0, 0x4b2f190(%rip) # 0x58a7590
movl $0x0, %r12d
jne 0xd78526
movq %r9, %rbx
movq %rsi, %r14
movq %rdi, %r15
movb $0x1, %al
movl $0xffffff43, %edx # imm = 0xFFFFFF43
addl 0x... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::is_t2_so_imm(unsigned int) const | inline bool is_t2_so_imm(unsigned Imm) const {
return ARM_AM::getT2SOImmVal(Imm) != -1;
} | movb $0x1, %al
cmpl $0x100, %edi # imm = 0x100
jb 0xd7bd64
movl %edi, %ecx
shrl $0x8, %ecx
testb %dil, %dil
cmovnel %edi, %ecx
movzbl %cl, %edx
movl %edx, %esi
shll $0x10, %esi
orl %edx, %esi
cmpl %esi, %ecx
je 0xd7bd64
cmpl $0x100, %edi # imm = 0x100
setb %sil
imull $0x1010101, %edx, %eax # imm ... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectCMPZ(llvm::SDNode*, bool&) | void ARMDAGToDAGISel::SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI) {
assert(N->getOpcode() == ARMISD::CMPZ);
SwitchEQNEToPLMI = false;
if (!Subtarget->isThumb())
// FIXME: Work out whether it is profitable to do this in A32 mode - LSL and
// LSR don't exist as standalone instructions - they need the bar... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movb $0x0, (%rdx)
movq 0x108(%rdi), %rax
cmpb $0x1, 0x192(%rax)
jne 0xd7d68b
movq %rsi, %r12
movq 0x28(%rsi), %rax
movq (%rax), %r14
movq 0x38(%r14), %rcx
testq %rcx, %rcx
je 0xd7d68b
cmpq $0x0, 0x20(%rcx)
jne 0xd7d68b
movq %rdx, %r15
mo... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectVLD(llvm::SDNode*, bool, unsigned int, unsigned short const*, unsigned short const*, unsigned short const*) | void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
const uint16_t *DOpcodes,
const uint16_t *QOpcodes0,
const uint16_t *QOpcodes1) {
assert(Subtarget->hasNEON());
assert(NumVecs >= 1 && NumVecs... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x258, %rsp # imm = 0x258
movq %r9, 0xc8(%rsp)
movq %r8, 0xa0(%rsp)
movl %ecx, 0x38(%rsp)
movl %edx, 0x3c(%rsp)
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x90(%rsp)
testq %rsi, %rsi
je 0xd7e476
leaq 0x90(%rsp), %rd... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectVLDSTLane(llvm::SDNode*, bool, bool, unsigned int, unsigned short const*, unsigned short const*) | void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
unsigned NumVecs,
const uint16_t *DOpcodes,
const uint16_t *QOpcodes) {
assert(Subtarget->hasNEON());
assert(NumVecs >=2 &&... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1e8, %rsp # imm = 0x1E8
movq %r9, 0xc8(%rsp)
movl %r8d, %r13d
movl %ecx, 0x34(%rsp)
movl %edx, 0x64(%rsp)
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x78(%rsp)
testq %rsi, %rsi
je 0xd7f205
leaq 0x78(%rsp), %rdi
mo... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(llvm::SDNode*, llvm::SDValue, llvm::SDValue&) | bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
SDValue &OffImm){
unsigned Opcode = Op->getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
: cast<StoreSDNode>(Op)->getAddressingMode(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rcx, %rbx
movq %rdx, %r14
movl 0x18(%rdx), %eax
cmpl $0x23, %eax
je 0xd822e3
cmpl $0xb, %eax
jne 0xd822e8
movq %r14, %rax
jmp 0xd822ea
xorl %eax, %eax
testq %rax, %rax
je 0xd822ff
movq 0x58(%rax), %rax
cmpl $0x41, 0x20(%rax)
jb 0xd... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(llvm::SDNode*, llvm::SDValue, llvm::SDValue&, llvm::SDValue&) | bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Opc) {
unsigned Opcode = Op->getOpcode();
ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
? cast<LoadSDNode>(Op)->getAddressingMode()
: cast<StoreSDNode>(Op)->getAddr... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %rbx
movq %rcx, %r15
movq %rsi, %r14
movq %rdi, %r12
movl 0x18(%rdx), %eax
cmpl $0x23, %eax
je 0xd8241f
cmpl $0xb, %eax
je 0xd8241f
xorl %edx, %edx
testq %rdx, %rdx
je 0xd82434
movq 0x58(%rdx), %rax
cmpl $0x41, 0x20(%rax)
jb 0x... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::SelectAddrMode6(llvm::SDNode*, llvm::SDValue, llvm::SDValue&, llvm::SDValue&) | bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
SDValue &Align) {
Addr = N;
unsigned Alignment = 0;
MemSDNode *MemN = cast<MemSDNode>(Parent);
if (isa<LSBaseSDNode>(MemN) ||
((MemN->getOpcode() == ARMISD::VST1_UPD ||
MemN->ge... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x30, %rsp
movq %r9, %rbx
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %r15
movq %rdx, (%r8)
movl %ecx, 0x8(%r8)
movl 0x18(%rsi), %eax
leal -0x121(%rax), %ecx
cmpl $0x2, %ecx
jb 0xd82b9e
cmpl $0x3eb, %eax # imm = 0x3EB
je 0xd82b6f
cmpl $0x3dd, %eax ... | /Target/ARM/ARMISelDAGToDAG.cpp |
(anonymous namespace)::ARMDAGToDAGISel::createQuadQRegsNode(llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue) | SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
SDValue V2, SDValue V3) {
SDLoc dl(V0.getNode());
SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl,
MVT::i32);
SDValue SubReg0 = CurD... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movl %r8d, 0x28(%rsp)
movq %rcx, %r13
movq %rdx, 0x48(%rsp)
movl %esi, 0x2c(%rsp)
movq %rdi, %r14
movq 0x48(%rcx), %rsi
movq %rsi, 0x50(%rsp)
testq %rsi, %rsi
je 0xd839f0
leaq 0x50(%rsp), %rdi
movl $0x1, %edx
ca... | /Target/ARM/ARMISelDAGToDAG.cpp |
llvm::ARMTargetLowering::getTargetNodeName(unsigned int) const | const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
#define MAKE_CASE(V) \
case V: \
return #V;
switch ((ARMISD::NodeType)Opcode) {
case ARMISD::FIRST_NUMBER:
... | leal -0x1e6(%rsi), %eax
cmpl $0xab, %eax
ja 0xd86eab
leaq 0x2a6ef7a(%rip), %rcx # 0x37f5e14
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
leaq 0x2a7049b(%rip), %rax # 0x37f7345
retq
addl $0xfffffc27, %esi # imm = 0xFFFFFC27
cmpl $0x1d, %esi
ja 0xd871ca
leaq 0x2a6f203(%rip), %rax # 0x37f60c4
movslq (... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::shouldAlignPointerArgs(llvm::CallInst*, unsigned int&, llvm::Align&) const | bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
Align &PrefAlign) const {
if (!isa<MemIntrinsic>(CI))
return false;
MinSize = 8;
// On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
// cycle faster than 4-byt... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rdi, %r15
cmpb $0x55, (%rsi)
jne 0xd8767d
movq %rsi, %r12
movq %rsi, %rdi
callq 0x8f16ea
testb %al, %al
je 0xd8767d
movq -0x20(%r12), %rax
movl $0xffffff19, %ecx # imm = 0xFFFFFF19
addl 0x24(%rax), %ecx
cmpl $0x7, %ecx
ja... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::PassF64ArgInRegs(llvm::SDLoc const&, llvm::SelectionDAG&, llvm::SDValue, llvm::SDValue&, llvm::SmallVector<std::pair<unsigned int, llvm::SDValue>, 8u>&, llvm::CCValAssign&, llvm::CCValAssign&, llvm::SDValue&, llvm::SmallVectorImpl<llvm::SDValue>&, bool, int) const | void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
SDValue Chain, SDValue &Arg,
RegsToPassVector &RegsToPass,
CCValAssign &VA, CCValAssign &NextVA,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %r9, %r15
movl %r8d, 0x4c(%rsp)
movq %rcx, 0x50(%rsp)
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq 0x108(%rsp), %r14
movq %rdx, %rdi
movl $0x7, %esi
xorl %edx, %edx
movl $0x7, %ecx
xorl %r8d, %r8d
callq 0x1f2df6c
movl %edx, ... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerConstantFP(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) const | SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) const {
EVT VT = Op.getValueType();
bool IsDouble = (VT == MVT::f64);
ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
const APFloat &FPVal = CFP->getValueAPF();
// ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x198, %rsp # imm = 0x198
movq %rcx, 0x48(%rsp)
movl %edx, %r15d
movq %rsi, %r14
movl %edx, %eax
shlq $0x4, %rax
movq 0x30(%rsi), %rcx
movq 0x58(%rsi), %r13
movb (%rcx,%rax), %r12b
movq 0x8(%rcx,%rax), %rcx
addq $0x18, %r13
cmpb $0x1, 0x... | /Target/ARM/ARMISelLowering.cpp |
bool llvm::all_of<llvm::iterator_range<llvm::SDNode::use_iterator>, llvm::ARMTargetLowering::LowerBUILD_VECTOR(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) const::$_0>(llvm::iterator_range<llvm::SDNode::use_iterator>&&, llvm::ARMTargetLowering::LowerBUILD_VECTOR(llvm::SDValue, llvm::SelectionDAG&, llv... | IteratorT begin() const { return begin_iterator; } | movq (%rdi), %rax
movq 0x8(%rdi), %rcx
cmpq %rcx, %rax
je 0xd9c6fa
pushq %r14
pushq %rbx
movabsq $0x3000001400, %rdx # imm = 0x3000001400
movabsq $0xc000000800, %rdi # imm = 0xC000000800
movabsq $0x103800000001, %r8 # imm = 0x103800000001
movabsq $0xb00200001001, %r9 # imm = 0xB00200001001
movabsq $0x8010... | /llvm/ADT/iterator_range.h |
llvm::ARMTargetLowering::LowerDIV_Windows(llvm::SDValue, llvm::SelectionDAG&, bool) const | SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
bool Signed) const {
assert(Op.getValueType() == MVT::i32 &&
"unexpected type for custom lowering DIV");
SDLoc dl(Op);
SDValue DBZCHK = DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %r8d, %r14d
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %r12
movq 0x48(%rsi), %rsi
movq %rsi, 0x28(%rsp)
testq %rsi, %rsi
je 0xd9fbdb
leaq 0x28(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r15), %eax
leaq 0x... | /Target/ARM/ARMISelLowering.cpp |
LowerMLOAD(llvm::SDValue, llvm::SelectionDAG&) | static SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) {
MaskedLoadSDNode *N = cast<MaskedLoadSDNode>(Op.getNode());
MVT VT = Op.getSimpleValueType();
SDValue Mask = N->getMask();
SDValue PassThru = N->getPassThru();
SDLoc dl(Op);
if (isZeroVector(PassThru))
return Op;
// MVE Masked loads use zero... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r15
movq 0x30(%rdi), %rax
movl %esi, %ecx
shlq $0x4, %rcx
movb (%rax,%rcx), %r13b
movq 0x28(%rdi), %rax
movups 0x78(%rax), %xmm0
movaps %xmm0, 0x80(%rsp)
movq 0xa0(%ra... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::LowerFP_ROUND(llvm::SDValue, llvm::SelectionDAG&) const | SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
bool IsStrict = Op->isStrictFPOpcode();
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
EVT SrcVT = SrcVal.getValueType();
EVT DstVT = Op.getValueType();
const unsigned DstSz = Op.getValueType().getSizeInBits();
const unsigne... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %rcx, 0x60(%rsp)
movl %edx, %r12d
movq %rsi, %r14
movq %rdi, 0x68(%rsp)
movq %rsi, %rdi
callq 0x9c288e
movl %eax, %ebp
movq 0x28(%r14), %rax
movzbl %bpl, %ecx
leaq (%rcx,%rcx,4), %rcx
movups (%rax,%rcx,8), %xmm0
movaps %xmm0, 0x80(%... | /Target/ARM/ARMISelLowering.cpp |
isPowerOf2Constant(llvm::SDValue) | unsigned getOpcode() const { return (unsigned)NodeType; } | movl 0x18(%rdi), %eax
cmpl $0x23, %eax
je 0xdb93a0
cmpl $0xb, %eax
je 0xdb93a0
xorl %edi, %edi
testq %rdi, %rdi
je 0xdb93c5
pushq %rbx
movq 0x58(%rdi), %rax
leaq 0x18(%rax), %rbx
cmpl $0x40, 0x20(%rax)
ja 0xdb93c8
movq (%rbx), %rax
testq %rax, %rax
je 0xdb93e0
leaq -0x1(%rax), %rcx
testq %rcx, %rax
jmp 0xdb93d3
xorl %e... | /llvm/CodeGen/SelectionDAGNodes.h |
llvm::ARMTargetLowering::PerformMVETruncCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const | SDValue ARMTargetLowering::PerformMVETruncCombine(
SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
EVT VT = N->getValueType(0);
SDLoc DL(N);
// MVETrunc(Undef, Undef) -> Undef
if (all_of(N->ops(), [](SDValue Op) { return Op.isUndef(); }))
return DAG.getUNDEF(VT);... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x278, %rsp # imm = 0x278
movq %rdx, %r15
movq %rsi, %r14
movq 0x10(%rdx), %rbx
movq 0x30(%rsi), %rax
movb (%rax), %cl
movq 0x8(%rax), %rax
movb %cl, 0x58(%rsp)
movq %rax, 0x60(%rsp)
movq 0x48(%rsi), %rsi
movq %rsi, 0x78(%rsp)
testq %rsi... | /Target/ARM/ARMISelLowering.cpp |
PerformVSetCCToVCTPCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&, llvm::ARMSubtarget const*) | static SDValue PerformVSetCCToVCTPCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const ARMSubtarget *Subtarget) {
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(N-... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rdi), %rax
movq (%rax), %rcx
movl 0x8(%rax), %ebp
movq 0x28(%rax), %r12
movl 0x30(%rax), %esi
movq 0x50(%rax), %rax
movl 0x58(%rax), %eax
movq 0x30(%rdi), %r8
movzbl (%r8), %edi
movq 0x8(%r8), %... | /Target/ARM/ARMISelLowering.cpp |
PerformSUBCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&, llvm::ARMSubtarget const*) | static SDValue PerformSUBCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const ARMSubtarget *Subtarget) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
// fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
if... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq 0x28(%rdi), %rax
movq 0x28(%rax), %rsi
movq 0x38(%rsi), %rcx
testq %rcx, %rcx
je 0xdc0603
cmpq $0x0, 0x20(%rcx)
je 0xdc07b5
movq 0x30(%rbx), %rax
cmpb $0x7, (%rax)
jne 0xdc0778
movq 0x... | /Target/ARM/ARMISelLowering.cpp |
PerformHWLoopCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&, llvm::ARMSubtarget const*) | static SDValue PerformHWLoopCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const ARMSubtarget *ST) {
// The hwloop intrinsics that we're interested are used for control-flow,
// either for entering or exiting the loop:
// - test.st... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x178, %rsp # imm = 0x178
movq %rsi, %rbx
movq %rdi, %r15
movl $0x1, 0x34(%rsp)
movb $0x0, 0x2f(%rsp)
movq 0x28(%rdi), %rax
movq (%rax), %r13
movsd 0x8(%rax), %xmm0
movaps %xmm0, 0xb0(%rsp)
cmpl $0x128, 0x18(%rdi) # imm = 0x128
jne ... | /Target/ARM/ARMISelLowering.cpp |
PerformVECTOR_SHUFFLECombine(llvm::SDNode*, llvm::SelectionDAG&) | static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
if (SDValue R = PerformShuffleVMOVNCombine(cast<ShuffleVectorSDNode>(N), DAG))
return R;
// The LLVM shufflevector instruction does not require the shuffle mask
// length to match the operand vector length, but ISD::VECTOR_SHUFFLE do... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %rsi, %r13
movq %rdi, %r14
movq 0x28(%rdi), %rax
movq (%rax), %rbx
cmpl $0x222, 0x18(%rbx) # imm = 0x222
jne 0xdc7bcd
movq 0x28(%rax), %rcx
cmpl $0x33, 0x18(%rcx)
jne 0xdc7bcd
movq %r13, 0x40(%rsp)
movl 0x8(%rax), %eax
movq 0x3... | /Target/ARM/ARMISelLowering.cpp |
PerformMVEVLDCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) | bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } | cmpl $0x0, 0x8(%rsi)
je 0xdcc08e
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x398, %rsp # imm = 0x398
movq %rsi, %rbx
cmpb $0x0, 0xc(%rsi)
jne 0xdcc07d
movq %rdi, %r14
movq 0x10(%rbx), %rax
movq %rax, 0x60(%rsp)
movq 0x28(%rdi), %rax
movq 0x50(%rax), %rcx
movq %rcx, 0x30(%rsp)
mo... | /llvm/CodeGen/TargetLowering.h |
llvm::ARMTargetLowering::isTruncateFree(llvm::EVT, llvm::EVT) const | bool ARMTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() ||
!DstVT.isInteger())
return false;
unsigned SrcBits = SrcVT.getSizeInBits();
unsigned DestBits = DstVT.getSizeInBits();
return (SrcBits == 64 && DestBits == 32);
} | pushq %rbx
subq $0x30, %rsp
movl %ecx, %ebx
movb %sil, 0x10(%rsp)
movq %rdx, 0x18(%rsp)
movb %bl, (%rsp)
movq %r8, 0x8(%rsp)
testb %sil, %sil
je 0xdcc397
addb $-0x11, %sil
cmpb $-0x53, %sil
setb %al
jmp 0xdcc3a1
leaq 0x10(%rsp), %rdi
callq 0x18dde12
testb %al, %al
jne 0xdcc3f9
testb %bl, %bl
je 0xdcc3b4
addb $-0x11, %b... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::computeKnownBitsForTargetNode(llvm::SDValue, llvm::KnownBits&, llvm::APInt const&, llvm::SelectionDAG const&, unsigned int) const | void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
KnownBits &Known,
const APInt &DemandedElts,
const SelectionDAG &DAG,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %r9, %r15
movq %rcx, %rbx
movl %edx, %r12d
movq %rsi, %r14
movl 0xd0(%rsp), %ebp
movl 0x8(%rcx), %r13d
movq %rcx, %rdi
callq 0xb7f33a
movl 0x18(%r14), %eax
cmpl $0x238, %eax # imm = 0x238
jle 0xdce2cd
cmpl $0x28e, %eax ... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::getSingleConstraintMatchWeight(llvm::TargetLowering::AsmOperandInfo&, char const*) const | TargetLowering::ConstraintWeight
ARMTargetLowering::getSingleConstraintMatchWeight(
AsmOperandInfo &info, const char *constraint) const {
ConstraintWeight weight = CW_Invalid;
Value *CallOperandVal = info.CallOperandVal;
// If we don't have a value, we can't do a match,
// but allow it at the lowest wei... | movq 0x78(%rsi), %rax
testq %rax, %rax
je 0xdcf640
movq 0x8(%rax), %rcx
movzbl (%rdx), %eax
cmpl $0x6c, %eax
je 0xdcf643
cmpl $0x77, %eax
jne 0xdcf660
movl 0x8(%rcx), %ecx
cmpb $0x6, %cl
jae 0xdcf62a
movl $0x1, %eax
movzbl %cl, %edx
movl $0x2f, %esi
btl %edx, %esi
jb 0xdcf665
andl $0xfd, %ecx
xorl %eax, %eax
cmpl $0x4,... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::canCombineStoreAndExtract(llvm::Type*, llvm::Value*, unsigned int&) const | bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
unsigned &Cost) const {
// If we do not have NEON, vector types are not natively supported.
if (!Subtarget->hasNEON())
return false;
// Floating point values and vector values map t... | pushq %rbx
movq 0x4e0f8(%rdi), %rax
cmpb $0x1, 0x155(%rax)
jne 0xdd10ad
movq %rcx, %rbx
movl $0xfe, %ecx
andl 0x8(%rsi), %ecx
movq %rsi, %rax
cmpl $0x12, %ecx
jne 0xdd104f
movq 0x10(%rsi), %rax
movq (%rax), %rax
movl 0x8(%rax), %ecx
cmpb $0x6, %cl
jae 0xdd106c
movb $0x2f, %al
shrb %cl, %al
xorb $0x1, %al
andl $0x5, %ec... | /Target/ARM/ARMISelLowering.cpp |
llvm::ARMTargetLowering::getABIAlignmentForCallingConv(llvm::Type*, llvm::DataLayout const&) const | Align ARMTargetLowering::getABIAlignmentForCallingConv(
Type *ArgTy, const DataLayout &DL) const {
const Align ABITypeAlign = DL.getABITypeAlign(ArgTy);
if (!ArgTy->isVectorTy())
return ABITypeAlign;
// Avoid over-aligning vector parameters. It would require realigning the
// stack and waste space for ... | pushq %r14
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdx, %rdi
callq 0x19e803a
movl $0xfe, %edx
andl 0x8(%r14), %edx
movl 0x8(%rbx), %ecx
cmpb %al, %cl
movzbl %al, %eax
cmovael %eax, %ecx
cmpl $0x12, %edx
cmovnel %eax, %ecx
movl %ecx, %eax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
| /Target/ARM/ARMISelLowering.cpp |
void llvm::SmallVectorImpl<unsigned char>::resizeImpl<false>(unsigned long) | void resizeImpl(size_type N) {
if (N == this->size())
return;
if (N < this->size()) {
this->truncate(N);
return;
}
this->reserve(N);
for (auto I = this->end(), E = this->begin() + N; I != E; ++I)
if (ForOverwrite)
new (&*I) T;
else
new (&*I) T();
t... | cmpq %rsi, 0x8(%rdi)
je 0xdd3553
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
ja 0xdd3548
cmpq %rbx, 0x10(%r14)
jae 0xdd3532
leaq 0x18(%r14), %rsi
movl $0x1, %ecx
movq %r14, %rdi
movq %rbx, %rdx
callq 0x1cba770
movq 0x8(%r14), %rdi
movq %rbx, %rdx
subq %rdi, %rdx
je 0xdd3548
addq (%r14), %rdi
xorl %... | /llvm/ADT/SmallVector.h |
combineSelectAndUse(llvm::SDNode*, llvm::SDValue, llvm::SDValue, llvm::TargetLowering::DAGCombinerInfo&, bool) | static
SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
TargetLowering::DAGCombinerInfo &DCI,
bool AllOnes = false) {
SelectionDAG &DAG = DCI.DAG;
EVT VT = N->getValueType(0);
SDValue NonConstantVal;
SDValue CCOp;
bool SwapSelectOps;... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %r9d, %r15d
movl %ecx, %ebp
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, 0x68(%rsp)
movq 0x10(%r8), %rax
movq %rax, 0x50(%rsp)
movq 0x30(%rdi), %rax
movb (%rax), %cl
movb %cl, 0x4c(%rsp)
movq 0x8(%rax), %r14
movl 0x18(%rsi), %eax
cmpl... | /Target/ARM/ARMISelLowering.cpp |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::SmallVector<llvm::MachineBasicBlock*, 2u>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::SmallVector<llvm::MachineBasicBlock*, 2u>>>, unsigned int, llvm::SmallVector<llvm::MachineBasicBlock*, 2u>, llvm::DenseMapInfo<unsigned ... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %eax
testq %rax, %rax
je 0xddd934
pushq %r14
pushq %rbx
pushq %rax
movq (%rdi), %rbx
shlq $0x3, %rax
leaq (%rax,%rax,4), %r14
addq $0x18, %rbx
cmpl $-0x3, -0x18(%rbx)
ja 0xddd923
movq -0x10(%rbx), %rdi
cmpq %rdi, %rbx
je 0xddd923
callq 0x751980
addq $0x28, %rbx
addq $-0x28, %r14
jne 0xddd90f
addq $0x8,... | /llvm/ADT/DenseMap.h |
llvm::createARMParallelDSPPass() | Pass *llvm::createARMParallelDSPPass() {
return new ARMParallelDSP();
} | pushq %rax
movl $0xf0, %edi
callq 0x751940
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x4ac6130(%rip), %rdx # 0x58a7b1c
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
leaq 0x4946fea(%rip), %rdx # 0x57289e8
movq %rdx, (%rax)
leaq 0x58(%rax), %rdx
movl %ecx, 0x58(%rax)
movq %rcx, 0x60(%rax)
movq %rdx, 0x68(%rax)
movq %rd... | /Target/ARM/ARMParallelDSP.cpp |
bool (anonymous namespace)::ARMParallelDSP::IsNarrowSequence<16u>(llvm::Value*) | bool ARMParallelDSP::IsNarrowSequence(Value *V) {
if (auto *SExt = dyn_cast<SExtInst>(V)) {
if (SExt->getSrcTy()->getIntegerBitWidth() != MaxBitWidth)
return false;
if (auto *Ld = dyn_cast<LoadInst>(SExt->getOperand(0))) {
// Check that this load could be paired.
return LoadPairs.count(Ld) ... | cmpb $0x45, (%rsi)
jne 0xde3a15
pushq %rbx
movq -0x20(%rsi), %rsi
movq 0x8(%rsi), %rax
movl $0xffffff00, %ecx # imm = 0xFFFFFF00
andl 0x8(%rax), %ecx
cmpl $0x1000, %ecx # imm = 0x1000
jne 0xde3a18
cmpb $0x3d, (%rsi)
jne 0xde3a18
movq %rdi, %rbx
movq 0x60(%rdi), %rdx
leaq 0x58(%rdi), %rcx
movq %rcx, %rax... | /Target/ARM/ARMParallelDSP.cpp |
llvm::IRBuilder<llvm::NoFolder, llvm::IRBuilderDefaultInserter>::IRBuilder(llvm::BasicBlock*, llvm::ilist_iterator_w_bits<llvm::ilist_detail::node_options<llvm::Instruction, false, false, void, true, llvm::BasicBlock>, false, false>, llvm::MDNode*, llvm::ArrayRef<llvm::OperandBundleDefT<llvm::Value*>>) | IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP,
MDNode *FPMathTag = nullptr,
ArrayRef<OperandBundleDef> OpBundles = std::nullopt)
: IRBuilderBase(TheBB->getContext(), this->Folder, this->Inserter,
FPMathTag, OpBundles) {
SetInsertPoint(TheBB, IP);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r13
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x19b8816
leaq 0x80(%r12), %rcx
leaq 0x88(%r12), %rdx
leaq 0x10(%r12), %rsi
movq %rsi, (%r12)
movabsq $0x200000000, %rsi # imm = 0x200000000
movq %rsi, 0x8(%r1... | /llvm/IR/IRBuilder.h |
llvm::LoadInst** llvm::SmallVectorImpl<llvm::LoadInst*>::insert<llvm::LoadInst**, void>(llvm::LoadInst**, llvm::LoadInst**, llvm::LoadInst**) | iterator insert(iterator I, ItTy From, ItTy To) {
// Convert iterator to elt# to avoid invalidating iterator when we reserve()
size_t InsertElt = I - this->begin();
if (I == this->end()) { // Important special case for empty vector.
append(From, To);
return this->begin()+InsertElt;
}
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
movq %rdi, %r13
movq (%rdi), %rax
movq %rsi, %r12
subq %rax, %r12
movl 0x8(%rdi), %edx
leaq (%rax,%rdx,8), %rax
cmpq %rsi, %rax
je 0xde4a76
movq %rcx, 0x8(%rsp)
movq %rcx, %rbp
subq %rbx, %rbp
movq %rbp, 0x10(%rsp)
sarq $... | /llvm/ADT/SmallVector.h |
llvm::createARMLoadStoreOptimizationPass(bool) | FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) {
if (PreAlloc)
return new ARMPreAllocLoadStoreOpt();
return new ARMLoadStoreOpt();
} | pushq %rbx
testl %edi, %edi
je 0xde4f0e
movl $0x78, %edi
callq 0x751940
movq %rax, %rbx
xorl %eax, %eax
movq %rax, 0x8(%rbx)
leaq 0x4ac2dbd(%rip), %rcx # 0x58a7ca9
movq %rcx, 0x10(%rbx)
movl $0x2, 0x18(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rbx)
movq %rax, 0x30(%rbx)
leaq 0x4943b7f(%rip), %rax # 0x5728a88
mov... | /Target/ARM/ARMLoadStoreOptimizer.cpp |
getMemoryOpOffset(llvm::MachineInstr const&) | unsigned getOpcode() const { return Opcode; } | movzwl 0x44(%rdi), %ecx
movq 0x10(%rdi), %rax
movq 0x20(%rdi), %rdx
movzwl 0x2(%rax), %eax
addl $-0x3, %eax
shlq $0x5, %rax
movq 0x10(%rdx,%rax), %rax
cmpl $0x10e9, %ecx # imm = 0x10E9
jg 0xde74aa
cmpl $0x7e0, %ecx # imm = 0x7E0
jle 0xde74de
leal -0x1017(%rcx), %edx
cmpl $0x1e, %edx
ja 0xde74fb
mov... | /llvm/CodeGen/MachineInstr.h |
llvm::cl::parser<llvm::TPLoop::MemTransfer>::OptionInfo const* llvm::SmallVectorTemplateCommon<llvm::cl::parser<llvm::TPLoop::MemTransfer>::OptionInfo, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<llvm::cl::parser<llvm::TPLoop::MemTransfer>::OptionInfo, false>>(llvm::SmallVectorTemplateBase<llv... | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movl 0x8(%rdi), %ecx
movl 0xc(%rdi), %eax
addq %rcx, %rdx
cmpq %rax, %rdx
ja 0xdfa030
movq %rbx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
movq %rdi, %r14
movq (%rdi), %rax
leaq (%rcx,%rcx,2), %rcx
shlq $0x4, %rcx
addq %rax, ... | /llvm/ADT/SmallVector.h |
llvm::ARMBasicBlockUtils::isBBInRange(llvm::MachineInstr*, llvm::MachineBasicBlock*, unsigned int) const | bool ARMBasicBlockUtils::isBBInRange(MachineInstr *MI,
MachineBasicBlock *DestBB,
unsigned MaxDisp) const {
unsigned PCAdj = isThumb ? 4 : 8;
unsigned BrOffset = getOffsetOf(MI) + PCAdj;
unsigned DestOffset = BBInfo[DestBB->getNumber... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movl %ecx, %ebx
movq %rdx, %r14
movq %rdi, %r15
movzbl 0x8(%rdi), %r12d
xorl $0x1, %r12d
callq 0xdfb51c
leal (%rax,%r12,4), %eax
addl $0x4, %eax
movslq 0x18(%r14), %rcx
movq 0x18(%r15), %rdx
leaq (%rcx,%rcx,2), %rcx
movl (%rdx,%rcx,4), %ecx
movl %eax, %edx
subl %ec... | /Target/ARM/ARMBasicBlockInfo.cpp |
(anonymous namespace)::ARMFastISel::ARMEmitLoad(llvm::MVT, llvm::Register&, (anonymous namespace)::Address&, llvm::MaybeAlign, bool, bool) | bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
MaybeAlign Alignment, bool isZExt,
bool allocReg) {
unsigned Opc;
bool useAM3 = false;
bool needVMOV = false;
const TargetRegisterClass *RC;
switch (VT.SimpleTy) {
// This ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %esi, %r15d
movq %rdi, %r14
movzbl %r15b, %esi
xorl %eax, %eax
leal -0x2(%rsi), %edi
cmpl $0xb, %edi
ja 0xe05432
movl %r8d, %ebx
movzbl %bh, %ebp
leaq 0x29fb2e9(%rip), %r8 # 0x3800338
movslq (%r8,%rdi,4), %rdi
addq %r8, %rdi
jmpq... | /Target/ARM/ARMFastISel.cpp |
getComparePred(llvm::CmpInst::Predicate) | static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
switch (Pred) {
// Needs two compares...
case CmpInst::FCMP_ONE:
case CmpInst::FCMP_UEQ:
default:
// AL is our "false" for now. The other two need more compares.
return ARMCC::AL;
case CmpInst::ICMP_EQ:
case CmpInst:... | decl %edi
movl $0xe, %eax
cmpl $0x28, %edi
ja 0xe07ae9
movl %edi, %eax
leaq 0x29f8a86(%rip), %rcx # 0x380056c
movl (%rcx,%rax,4), %eax
retq
| /Target/ARM/ARMFastISel.cpp |
(anonymous namespace)::ARMFastISel::ARMEmitIntExt(llvm::MVT, unsigned int, llvm::MVT, bool) | unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
bool isZExt) {
if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
return 0;
if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
return 0;
// Table of which combinatio... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movl %ecx, %r15d
leal -0x5(%r15), %ecx
xorl %eax, %eax
cmpb $0x2, %cl
ja 0xe083d8
cmpb $0x6, %sil
ja 0xe083d8
movl %edx, %ebp
movzbl %sil, %edx
movl $0x64, %ecx
btl %edx, %ecx
jae 0xe083d8
movq %rdi, %rbx
shll $0x4, %edx
leaq 0x2384d7e(%... | /Target/ARM/ARMFastISel.cpp |
llvm::AVRAsmPrinter::AVRAsmPrinter(llvm::TargetMachine&, std::unique_ptr<llvm::MCStreamer, std::default_delete<llvm::MCStreamer>>) | AVRAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)), MRI(*TM.getMCRegisterInfo()) {} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdx), %rax
leaq 0x8(%rsp), %r15
movq %rax, (%r15)
movq $0x0, (%rdx)
movq %r15, %rdx
callq 0x1dd6584
movq (%r15), %rdi
testq %rdi, %rdi
je 0xe10fd1
movq (%rdi), %rax
callq *0x38(%rax)
movq $0x0, 0x8(%rsp)
leaq 0x491893f(%rip), %rax ... | /Target/AVR/AVRAsmPrinter.cpp |
llvm::AVRTargetMachine::AVRTargetMachine(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, std::optional<llvm::Reloc::Model>, std::optional<llvm::CodeModel::Model>, llvm::CodeGenOptLevel, bool) | AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeM... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %r9, 0x38(%rsp)
movq %r8, %r15
movq %rcx, %r12
movq %rdx, 0x40(%rsp)
movq %rsi, %rbp
movq %rdi, %rbx
movq 0xe8(%rsp), %r14
movq 0xe0(%rsp), %r13
movq %rcx, %rdi
movq %r8, %rsi
callq 0xe11488
movq %rax, 0x48(%rsp)
movq %rdx, 0x50(%rs... | /Target/AVR/AVRTargetMachine.cpp |
llvm::AVRTargetObjectFile::SelectSectionForGlobal(llvm::GlobalObject const*, llvm::SectionKind, llvm::TargetMachine const&) const | MCSection *AVRTargetObjectFile::SelectSectionForGlobal(
const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
// Global values in flash memory are placed in the progmem*.data section
// unless they already have a user assigned section.
const auto &AVRTM = static_cast<const AVRTargetMachin... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rcx, %r15
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %rbx
movq 0x8(%rsi), %rax
movl 0x8(%rax), %eax
shrl $0x8, %eax
decl %eax
cmpl $0x5, %eax
ja 0xe11d2c
testb $0x4, 0x23(%r14)
jne 0xe11d2c
movl %ebp, %eax
andb $-0x4, %al
cmpb $0x8, %al
je 0xe11cbf
movz... | /Target/AVR/AVRTargetObjectFile.cpp |
(anonymous namespace)::AVRExpandPseudo::expandArith(unsigned int, unsigned int, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) | bool AVRExpandPseudo::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB,
BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(2).getReg();
bool DstIsDead = MI... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %r8, 0x30(%rsp)
movq %rcx, 0x20(%rsp)
movl %edx, 0x10(%rsp)
movl %esi, 0xc(%rsp)
movq %rdi, %rbp
xorl %eax, %eax
leaq 0x1c(%rsp), %rcx
movl %eax, (%rcx)
movq %rcx, %rdx
leaq 0x18(%rsp), %rcx
movl %eax, (%rcx)
leaq 0x14(%rsp), %rsi
m... | /Target/AVR/AVRExpandPseudoInsts.cpp |
(anonymous namespace)::AVRExpandPseudo::expandLogic(unsigned int, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) | bool AVRExpandPseudo::expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(2).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
bool DstIsKill = MI.getO... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rcx, %r8
movq %rcx, 0x18(%rsp)
movq %rdx, 0x20(%rsp)
movl %esi, 0x4(%rsp)
movq %rdi, %r13
xorl %eax, %eax
leaq 0x14(%rsp), %rcx
movl %eax, (%rcx)
movq %rcx, %rdx
leaq 0x10(%rsp), %rcx
movl %eax, (%rcx)
leaq 0x34(%rsp), %r15
movl %e... | /Target/AVR/AVRExpandPseudoInsts.cpp |
llvm::AVRInstrInfo::loadRegFromStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, llvm::Register) const | void AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %r9, 0x60(%rsp)
movl %r8d, %ebx
movl %ecx, 0x38(%rsp)
movq %rdx, 0x50(%rsp)
movq %rdi, 0x40(%rsp)
movq 0x100(%rsp), %r12
movq %rsi, 0x48(%rsp)
movq 0x20(%rsi), %r13
movq 0x38(%r13), %rbp
xorl %r15d, %r15d
leaq 0xb0(%rsp), %r14
movq ... | /Target/AVR/AVRInstrInfo.cpp |
llvm::AVRInstrInfo::removeBranch(llvm::MachineBasicBlock&, int*) const | unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;
while (I != MBB.begin()) {
--I;
if (I->isDebugInstr()) {
continue;
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
testq %rdx, %rdx
je 0xe1d5d5
movl $0x0, (%rbx)
leaq 0x30(%r14), %r13
movq %rsp, %r12
movq %r13, (%r12)
xorl %ebp, %ebp
movq (%rsp), %rax
cmpq 0x38(%r14), %rax
je 0xe1d63b
movq %r12, %rdi
callq 0x... | /Target/AVR/AVRInstrInfo.cpp |
llvm::AVRTargetLowering::getTargetNodeName(unsigned int) const | const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
#define NODE(name) \
case AVRISD::name: \
return #name
switch (Opcode) {
default:
return nullptr;
NODE(RET_GL... | addl $0xfffffe1a, %esi # imm = 0xFFFFFE1A
cmpl $0x1f, %esi
ja 0xe21b15
movl %esi, %eax
leaq 0x490ab68(%rip), %rcx # 0x572c678
movq (%rcx,%rax,8), %rax
retq
xorl %eax, %eax
retq
| /Target/AVR/AVRISelLowering.cpp |
llvm::AVRTargetLowering::ReplaceNodeResults(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const | void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const {
SDLoc DL(N);
switch (N->getOpcode()) {
case ISD::ADD: {
// Convert add (x, imm) into sub (x, -imm).
if ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rcx, %r14
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movq 0x48(%rsi), %rsi
movq %rsi, 0x38(%rsp)
testq %rsi, %rsi
je 0xe25a5c
leaq 0x38(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r15), %eax
movl %eax, 0x40(%rsp)
cm... | /Target/AVR/AVRISelLowering.cpp |
llvm::AVRTargetLowering::CanLowerReturn(unsigned int, llvm::MachineFunction&, bool, llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, llvm::LLVMContext&) const | bool AVRTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
if (CallConv == CallingConv::AVR_BUILTIN) {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, MF, RVLoc... | pushq %r15
pushq %r14
pushq %rbx
subq $0x320, %rsp # imm = 0x320
movq %r8, %rbx
cmpl $0x56, %esi
jne 0xe27d86
movq %rdx, %rax
leaq 0x1a0(%rsp), %r15
movq %r15, -0x10(%r15)
movabsq $0x1000000000, %rdx # imm = 0x1000000000
movq %rdx, -0x8(%r15)
movl $0x0, (%rsp)
movzbl %cl, %edx
leaq 0x8(%rsp), %r14
leaq 0... | /Target/AVR/AVRISelLowering.cpp |
llvm::AVRTargetLowering::insertShift(llvm::MachineInstr&, llvm::MachineBasicBlock*, bool) const | MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
MachineBasicBlock *BB,
bool Tiny) const {
unsigned Opc;
const TargetRegisterClass *RC;
bool HasRepeatedOperand = false;
MachineFunction *F = BB-... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movl %ecx, %ebx
movq %rsi, %r12
movq %rdx, 0x18(%rsp)
movq 0x20(%rdx), %r15
movq 0x28(%r15), %r13
movq 0x4e0f8(%rdi), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, %r14
movq 0x38(%r12), %rsi
movq %rsi, 0x20(%rsp)
testq %rsi, %rsi
j... | /Target/AVR/AVRISelLowering.cpp |
(anonymous namespace)::BPFAsmPrinter::doInitialization(llvm::Module&) | bool BPFAsmPrinter::doInitialization(Module &M) {
AsmPrinter::doInitialization(M);
// Only emit BTF when debuginfo available.
if (MAI->doesSupportDebugInformation() && !M.debug_compile_units().empty()) {
BTF = new BTFDebug(this);
DebugHandlers.push_back(std::unique_ptr<BTFDebug>(BTF));
}
return fals... | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rsi, %r14
movq %rdi, %rbx
callq 0x1dd6b46
movq 0x40(%rbx), %rax
cmpb $0x1, 0x1a0(%rax)
jne 0xe2ccce
movq %rsp, %r15
movq %r15, %rdi
movq %r14, %rsi
callq 0xe2cf4a
movl 0x8(%r15), %eax
cmpl 0x18(%r15), %eax
je 0xe2ccce
movl $0x418, %edi # imm = 0x418
cal... | /Target/BPF/BPFAsmPrinter.cpp |
std::enable_if<!std::is_same_v<llvm::BPFAbstractMemberAccessPass, llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>>, void>::type llvm::PassManager<llvm::Function, llvm::AnalysisManager<llvm::Function>>::addPass<llvm::BPFAbstractMemberAccessPass>(llvm::BPFAbstractMemberAccessPass&&) | LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v<PassT, PassManager>>
addPass(PassT &&Pass) {
using PassModelT =
detail::PassModel<IRUnitT, PassT, AnalysisManagerT, ExtraArgTs...>;
// Do not use make_unique or emplace_back, they cause too many template
// instantiations, causing terrible co... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
pushq $0x10
popq %rdi
callq 0x751940
movq (%rbx), %rcx
leaq 0x48fe452(%rip), %rdx # 0x572cd88
movq %rdx, (%rax)
movq %rcx, 0x8(%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
movq %r14, %rdi
movq %rbx, %rsi
callq 0xab2b52
movq (%rbx), %rdi
testq %rdi, %rdi
je 0... | /llvm/IR/PassManager.h |
llvm::TargetTransformInfo::Model<llvm::BPFTTIImpl>::simplifyDemandedUseBitsIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&, llvm::APInt, llvm::KnownBits&, bool&) | std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) override {
return Impl.simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r9, %rbx
movq %r8, %rbp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
addq $0x8, %r13
movl 0x8(%rcx), %eax
movl %eax, 0x10(%rsp)
cmpl $0x40, %eax
ja 0xe2f005
movq (%rcx), %rax
movq %rax, 0x8(%rsp)
jmp 0xe2f012
leaq 0x8(%rsp), %rd... | /llvm/Analysis/TargetTransformInfo.h |
llvm::TargetTransformInfoImplCRTPBase<llvm::BPFTTIImpl>::getPointersChainCost(llvm::ArrayRef<llvm::Value const*>, llvm::Value const*, llvm::TargetTransformInfo::PointersChainInfo const&, llvm::Type*, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getPointersChainCost(ArrayRef<const Value *> Ptrs,
const Value *Base,
const TTI::PointersChainInfo &Info,
Type *AccessTy,
TTI::TargetCostKind CostKi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r9, 0x38(%rsp)
movq %r8, 0x40(%rsp)
movq %rcx, 0x48(%rsp)
testq %rdx, %rdx
je 0xe2fd7e
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, 0x30(%rsp)
leaq -0x8(%rdi), %rax
movq %rax, 0x28(%rsp)
shlq $0x3, %r12
xorl %r15d, %r15d
movl $0x0, 0... | /llvm/Analysis/TargetTransformInfoImpl.h |
llvm::TargetTransformInfoImplCRTPBase<llvm::BPFTTIImpl>::getInstructionCost(llvm::User const*, llvm::ArrayRef<llvm::Value const*>, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getInstructionCost(const User *U,
ArrayRef<const Value *> Operands,
TTI::TargetCostKind CostKind) {
using namespace llvm::PatternMatch;
auto *TargetTTI = static_cast<T *>(this);
// Handle non-intrinsic calls, invokes,... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x248, %rsp # imm = 0x248
movl %r8d, %ebp
movq %rcx, %r13
movq %rsi, %r14
movq %rdi, %rbx
movzbl (%rsi), %eax
cmpl $0x1d, %eax
jb 0xe30b3e
leal -0x22(%rax), %ecx
cmpl $0x33, %ecx
ja 0xe30b3e
movabsq $0x8000000000041, %rsi # imm = 0x8000... | /llvm/Analysis/TargetTransformInfoImpl.h |
llvm::BasicTTIImplBase<llvm::BPFTTIImpl>::simplifyDemandedVectorEltsIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&, llvm::APInt, llvm::APInt&, llvm::APInt&, llvm::APInt&, std::function<void (llvm::Instruction*, unsigned int, llvm::APInt, llvm::APInt&)>) | std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) {
return BaseT::simplifyDemandedVect... | pushq %r14
pushq %rbx
subq $0x38, %rsp
movq 0x58(%rsp), %rbx
movl 0x8(%rcx), %eax
movl %eax, 0x8(%rsp)
cmpl $0x40, %eax
ja 0xe36f9d
movq (%rcx), %rax
movq %rax, (%rsp)
jmp 0xe36fa8
movq %rsp, %rdi
movq %rcx, %rsi
callq 0x1c8174e
xorps %xmm0, %xmm0
movaps %xmm0, 0x20(%rsp)
movaps %xmm0, 0x10(%rsp)
movq 0x10(%rbx), %rax
... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::BPFTTIImpl>::preferToKeepConstantsAttached(llvm::Instruction const&, llvm::Function const&) const | unsigned getValueID() const {
return SubclassID;
} | movzbl (%rsi), %ecx
xorl %eax, %eax
cmpq $0x34, %rcx
ja 0xe37356
pushq %r14
pushq %rbx
pushq %rax
movq %rdx, %rbx
movabsq $0x1b000000000000, %rdx # imm = 0x1B000000000000
btq %rcx, %rdx
jae 0xe3734f
movq %rdi, %r14
movl 0x4(%rsi), %eax
btl $0x1e, %eax
jb 0xe37311
shll $0x5, %eax
movq %rsi, %rcx
subq %rax, %rcx
jmp 0xe3... | /llvm/IR/Value.h |
llvm::BasicTTIImplBase<llvm::BPFTTIImpl>::isIndexedLoadLegal(llvm::TargetTransformInfo::MemIndexedMode, llvm::Type*, llvm::DataLayout const&) const | bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty,
const DataLayout &DL) const {
EVT VT = getTLI()->getValueType(DL, Ty);
return getTLI()->isIndexedLoadLegal(getISDIndexedMode(M), VT);
} | pushq %rbp
pushq %r14
pushq %rbx
movl %esi, %ebx
movq %rdi, %r14
movq 0x18(%rdi), %rdi
xorl %ebp, %ebp
movq %rcx, %rsi
xorl %ecx, %ecx
callq 0x8f1f84
testb %al, %al
je 0xe37d24
movzbl %al, %eax
leaq (%rax,%rax,4), %rax
addq %rax, %rax
addq 0x18(%r14), %rax
movl %ebx, %ecx
movb 0x4a2ce(%rax,%rcx,2), %al
cmpb $0x10, %al
... | /llvm/CodeGen/BasicTTIImpl.h |
(anonymous namespace)::BPFMIPeephole::BPFMIPeephole() | BPFMIPeephole() : MachineFunctionPass(ID) {
initializeBPFMIPeepholePass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4a703aa(%rip), %rcx # 0x58a8258
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x48f5595(%rip), %rcx # 0x572d460
movq %rcx, (%rdi)
leaq 0x58(%rdi), %rcx
movl $0x0, 0x58(%rdi)
movq %rax, 0x60(%r... | /Target/BPF/BPFMIPeephole.cpp |
(anonymous namespace)::BPFMIPeephole::isMovFrom32Def(llvm::MachineInstr*) | bool BPFMIPeephole::isMovFrom32Def(MachineInstr *MovMI)
{
MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg());
LLVM_DEBUG(dbgs() << " Def of Mov Src:");
LLVM_DEBUG(DefInsn->dump());
PhiInsns.clear();
if (!isInsnFrom32Def(DefInsn))
return false;
LLVM_DEBUG(dbgs() << " One ZExt eli... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq 0x48(%rdi), %rdi
movq 0x20(%rsi), %rax
movl 0x24(%rax), %esi
callq 0x17dae6c
movq %rax, %r14
leaq 0x50(%rbx), %rdi
movq 0x60(%rbx), %rsi
callq 0x96b954
leaq 0x58(%rbx), %rax
xorl %ecx, %ecx
movq %rcx, 0x60(%rbx)
movq %rax, 0x68(%rbx)
movq %rax, 0x70(%rbx)
movq %rcx,... | /Target/BPF/BPFMIPeephole.cpp |
(anonymous namespace)::BPFMIPeephole::isInsnFrom32Def(llvm::MachineInstr*) | bool BPFMIPeephole::isInsnFrom32Def(MachineInstr *DefInsn)
{
if (!DefInsn)
return false;
if (DefInsn->isPHI()) {
if (!PhiInsns.insert(DefInsn).second)
return false;
if (!isPhiFrom32Def(DefInsn))
return false;
} else if (DefInsn->getOpcode() == BPF::COPY) {
if (!isCopyFrom32Def(DefInsn... | pushq %rbx
subq $0x10, %rsp
movq %rsi, 0x8(%rsp)
testq %rsi, %rsi
je 0xe3862b
movq %rdi, %rbx
movzwl 0x44(%rsi), %eax
testl $0xffbf, %eax # imm = 0xFFBF
je 0xe38603
cmpw $0x13, %ax
jne 0xe38627
movq %rbx, %rdi
callq 0xe38718
jmp 0xe38623
leaq 0x50(%rbx), %rdi
leaq 0x8(%rsp), %rsi
callq 0x96b7dc
testb $0x1, %d... | /Target/BPF/BPFMIPeephole.cpp |
(anonymous namespace)::BPFMISimplifyPatchable::BPFMISimplifyPatchable() | BPFMISimplifyPatchable() : MachineFunctionPass(ID) {
initializeBPFMISimplifyPatchablePass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4a6dd78(%rip), %rcx # 0x58a8268
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x48f3193(%rip), %rcx # 0x572d6a0
movq %rcx, (%rdi)
leaq 0x50(%rdi), %rcx
movl $0x0, 0x50(%rdi)
movq %rax, 0x58(%r... | /Target/BPF/BPFMISimplifyPatchable.cpp |
llvm::BTFDebug::populateFileContent[abi:cxx11](llvm::DIFile const*) | std::string BTFDebug::populateFileContent(const DIFile *File) {
std::string FileName;
if (!File->getFilename().starts_with("/") && File->getDirectory().size())
FileName = File->getDirectory().str() + "/" + File->getFilename().str();
else
FileName = std::string(File->getFilename());
// No need to popul... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movq $0x0, 0x8(%rdi)
movb $0x0, 0x10(%rdi)
movq %rdx, %rdi
xorl %esi, %esi
callq 0x8dd0dc
testq %rdx, %rdx
je 0xe3dced
cmpb $0x2f, (%rax)
je 0xe3dd2a... | /Target/BPF/BTFDebug.cpp |
llvm::BTFDebug::emitBTFSection() | void BTFDebug::emitBTFSection() {
// Do not emit section if no types and only "" string.
if (!TypeEntries.size() && StringTable.getSize() == 1)
return;
MCContext &Ctx = OS.getContext();
MCSectionELF *Sec = Ctx.getELFSection(".BTF", ELF::SHT_PROGBITS, 0);
Sec->setAlignment(Align(4));
OS.switchSection(Se... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rdi, %rbx
movq 0x250(%rdi), %rax
cmpq 0x248(%rdi), %rax
jne 0xe3e56a
cmpl $0x1, 0x1f8(%rbx)
je 0xe3e84c
movq 0x1e0(%rbx), %rax
movq 0x8(%rax), %rdi
leaq 0x29c4865(%rip), %rax # 0x3802de1
leaq 0x28(%rsp), %rsi
movq %rax, (%rsi)
mo... | /Target/BPF/BTFDebug.cpp |
llvm::BPFAdjustOptPass::run(llvm::Module&, llvm::AnalysisManager<llvm::Module>&) | PreservedAnalyses BPFAdjustOptPass::run(Module &M, ModuleAnalysisManager &AM) {
return BPFAdjustOptImpl(&M).run() ? PreservedAnalyses::none()
: PreservedAnalyses::all();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x288, %rsp # imm = 0x288
movq %rdi, 0x68(%rsp)
leaq 0x108(%rsp), %rcx
movq %rdx, -0x18(%rcx)
movq %rcx, -0x10(%rcx)
movabsq $0x1000000000, %rax # imm = 0x1000000000
movq %rax, -0x8(%rcx)
movq 0x20(%rdx), %rax
addq $0x18, %rdx
movq %... | /Target/BPF/BPFAdjustOpt.cpp |
bool llvm::PatternMatch::LogicalOp_match<llvm::PatternMatch::bind_ty<llvm::Value>, llvm::PatternMatch::bind_ty<llvm::Value>, 29u, false>::match<llvm::Instruction>(llvm::Instruction*) | bool match(T *V) {
auto *I = dyn_cast<Instruction>(V);
if (!I || !I->getType()->isIntOrIntVectorTy(1))
return false;
if (I->getOpcode() == Opcode) {
auto *Op0 = I->getOperand(0);
auto *Op1 = I->getOperand(1);
return (L.match(Op0) && R.match(Op1)) ||
(Commutable && L.mat... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
testq %rsi, %rsi
je 0xe49c3b
movq %rsi, %r14
movq %rdi, %rbx
movq 0x8(%rsi), %rdi
movl $0xfe, %eax
andl 0x8(%rdi), %eax
cmpl $0x12, %eax
jne 0xe49bb6
movq 0x10(%rdi), %rax
movq (%rax), %rdi
movl $0x1, %esi
callq 0x1a89852
testb %al, %al
je 0xe49c3b
movzbl (%r14), %... | /llvm/IR/PatternMatch.h |
llvm::BPFASpaceCastSimplifyPass::run(llvm::Function&, llvm::AnalysisManager<llvm::Function>&) | PreservedAnalyses BPFASpaceCastSimplifyPass::run(Function &F,
FunctionAnalysisManager &AM) {
SmallVector<CastGEPCast, 16> WorkList;
bool Changed = false;
for (BasicBlock &BB : F) {
for (Instruction &I : BB)
if (auto It = CastGEPCast::match(&I))
Wo... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rdi, %rbx
leaq 0x58(%rsp), %r14
movq %r14, -0x10(%r14)
movabsq $0x1000000000, %rax # imm = 0x1000000000
movq %rax, -0x8(%r14)
movq 0x50(%rdx), %rax
addq $0x48, %rdx
movq %rdx, 0x10(%rsp)
cmpq %rdx, %rax
je 0xe49ef4
movq %rbx, 0... | /Target/BPF/BPFASpaceCastSimplifyPass.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::Value*, llvm::Value*, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseMapPair<llvm::Value*, llvm::Value*>>, llvm::Value*, llvm::Value*, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseMapPair<llvm::Value*, llvm::Value*>>::find(llvm::Value const*) | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rax
movq %rsi, (%rax)
leaq 0x10(%rsp), %r14
movq %rax, %rsi
movq %r14, %rdx
callq 0xe4b7be
movl 0x10(%rbx), %edx
shlq $0x4, %rdx
addq (%rbx), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x18, %rsp
popq %rbx
popq %r14
retq
nop
| /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<llvm::Value*, llvm::Value*>* llvm::DenseMapBase<llvm::DenseMap<llvm::Value*, llvm::Value*, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseMapPair<llvm::Value*, llvm::Value*>>, llvm::Value*, llvm::Value*, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseMapPair<llvm::Valu... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0xe4b97f
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x... | /llvm/ADT/DenseMap.h |
llvm::createBPFISelDag(llvm::BPFTargetMachine&) | FunctionPass *llvm::createBPFISelDag(BPFTargetMachine &TM) {
return new BPFDAGToDAGISelLegacy(TM);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdi, %r14
movl $0x40, %edi
callq 0x751940
movq %rax, %rbx
movl $0x140, %edi # imm = 0x140
callq 0x751940
movq %rax, %r15
movq %rax, %rdi
movq %r14, %rsi
movl $0x2, %edx
callq 0x1f6bf6a
leaq 0x48e0da9(%rip), %rax # 0x572e1c8
movq %rax, (%r15)
xorl %eax... | /Target/BPF/BPFISelDAGToDAG.cpp |
(anonymous namespace)::BPFDAGToDAGISel::SelectInlineAsmMemoryOperand(llvm::SDValue const&, llvm::InlineAsm::ConstraintCode, std::vector<llvm::SDValue, std::allocator<llvm::SDValue>>&) | bool BPFDAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintCode) {
default:
return true;
case InlineAsm::ConstraintCode::m: // memory
if (!SelectAddr(Op, Op0, Op1))
ret... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x48, %rsp
xorl %eax, %eax
movq %rax, 0x28(%rsp)
movl %eax, 0x30(%rsp)
movq %rax, 0x18(%rsp)
movl %eax, 0x20(%rsp)
movb $0x1, %bpl
cmpl $0x4, %edx
jne 0xe4dd71
movq %rcx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movq (%rsi), %rsi
movl 0x8(%r15), %edx
leaq 0x28(%rsp), %rcx
l... | /Target/BPF/BPFISelDAGToDAG.cpp |
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